Method for constructing general test system

Abstract

The invention discloses a general test system and a test method. The general test system is characterized in that an upper computer is connected with a plurality of data acquisition devices through a data transmission external bus; each data acquisition device comprises a microcontroller which is connected with and controls a plurality of parameter measurement units through a data transmission external bus; the upper computer receives a test requirement of the to-be-tested equipment, generates a test model, makes software data containing the test model into test model data packets, and respectively issues the test model data packets to the data acquisition devices; a microcontroller of the data acquisition device receives and analyzes the test model data packet and the test algorithm data packet, the microcontroller generates a plurality of control models, and each control model is associated with one parameter measurement unit; and the microcontroller tests the equipment to be tested according to the control model and the test algorithm. The method can well adapt to the requirements of different equipment and different test scenes.

Description

Technical Field

[0001] The present invention relates to the technical field of product measurement equipment for flexible production lines, and particularly to a method for constructing a general test system. Background Art

[0002] In industrialized assembly line production, performance testing of products is an important link to examine whether the product quality is qualified. In order to improve the debugging efficiency of product development and batch production, generally a number of test devices are equipped. Different test devices can be configured respectively according to different control device functions, uses and interfaces. Common product test devices are all special test devices designed and produced specifically with reference to product functions, in accordance with the requirements of the product test task book, according to the required test items, test functions and test interfaces. The special test devices completed according to this production procedure can better meet the simultaneous testing of multiple functions of the product, but such special test devices do not have universality and can only perform tests on one product or similar products. This leads to repeated research and development and production of test devices, occupying funds and space, and the use efficiency of such special test devices is not high. It results in low use efficiency of the test device, occupying resources and space. Multifunctional test devices that can test multiple product performances generally have a large volume, are inconvenient to use, and have a high cost.

[0003] There is an urgent need for a general test device that can adapt to multiple products, and adjust the test means and test functions through software, so as to solve the problems of low use efficiency of common test devices and repeated occupation of scientific research funds, and further improve the effective utilization rate of test devices, improve the utilization rate of funds, and reduce the occupied space of redundant devices. Summary of the Invention

[0004] A first aspect of the present invention provides a general test system, and the general test system includes: a host computer and a plurality of data acquisition devices, and the host computer is connected to the plurality of data acquisition devices through a data transmission external bus;

[0005] Each of the data acquisition devices includes a microcontroller and a plurality of parameter measurement units, and the microcontroller is connected to and controls the plurality of parameter measurement units through a data transmission external bus;

[0006] The host computer receives the test requirements of the device under test, generates test models and test algorithms for the plurality of data acquisition devices, and makes software data including the test models and test algorithms into a test model data packet and a test algorithm data packet; the host computer respectively issues the test model data packet and the test algorithm data packet to the plurality of data acquisition devices through the data transmission external bus;

[0007] The microcontroller of each of the data acquisition devices receives and parses the test model data packet and the test algorithm data packet associated with this data acquisition device. The microcontroller decomposes and transforms the parsed test model data packet into multiple control models, and each control model is directly associated with the measurement function of a parameter measurement unit connected to the data acquisition device.

[0008] The microcontroller runs the control module according to the control model and the test algorithm to test the device under test, and stores the test results in the memory and / or uploads them to the upper computer via the data transmission external bus.

[0009] Furthermore, the microcontroller of each of the data acquisition devices is connected to and controls the multiple parameter measurement units through an independent data transmission internal bus.

[0010] Each of the parameter measurement units includes: a sensor module, an audio signal interface module, a video signal interface module, and a bus-type data interface module.

[0011] The sensors include: natural environment sensors, speed sensors, electrical signal sensors, and electromagnetic radiation signal sensors.

[0012] Furthermore, the natural environment sensors include: wind speed and direction sensors, temperature sensors, humidity sensors, and rainfall sensors.

[0013] The audio signal interface module is connected to the audio signal output port of the device under test; the video signal interface module is used to connect to the video signal output port of the device under test.

[0014] The bus-type data interface module is used to connect to the bus output port of the various parameter data of the device under test.

[0015] Furthermore, the microcontroller of the data acquisition device includes a microprocessor or DSP, a data and program memory, an upstream bus interface module, a downstream bus interface module, and an analog-to-digital converter.

[0016] The upstream bus interface module is connected to the data transmission external bus.

[0017] The downstream bus interface module is connected to the data transmission internal bus.

[0018] The analog-to-digital converter is used to transform the output signals of the sensor module, the audio signal interface module, and the video signal interface module into digital signals and provide them to the microcontroller.

[0019] Furthermore, the upper computer includes a central processing unit, an input device, an output device, a display device, and a storage device.

[0020] The output device is connected to a printing device and a display device through a data transmission external bus;

[0021] The input device is used to receive the test requirements of the device under test; the input device also queries the number and functions of the parameter measurement units connected to each data acquisition device through the data transmission external bus;

[0022] The central processing unit analyzes the test requirements and generates a test model data packet and a test algorithm data packet according to various signal processing algorithms pre-stored in the storage device.

[0023] The present invention also provides a method for constructing a general test system, and the method includes the following steps;

[0024] Step 1, the host computer receives the test requirements of the device under test input, and analyzes the test requirements into multiple test tasks according to the signal processing algorithm;

[0025] Step 2, the host computer queries the number and functions of the parameter measurement units of each data acquisition device through the data transmission external bus;

[0026] Step 3, the host computer generates a test model data packet and a test algorithm data packet according to the functions of the parameter measurement units for the multiple test tasks, and sends the test model data packet and the test algorithm data packet through the data transmission external bus;

[0027] Step 4, the microcontroller of the data acquisition device receives and analyzes the test model data packet and the test algorithm data packet of the data acquisition device, and the microcontroller decomposes and transforms the parsed test model data packet into multiple control models, and each control model or test algorithm is directly associated with the measurement function of a parameter measurement unit connected to the data acquisition device; the microcontroller optimally configures the test resources, and the microcontroller controls the multiple parameter measurement units connected to the data acquisition device to perform test work according to the control model and the test algorithm;

[0028] Step 5, the data acquisition device uploads various test result data of the device under test to the host computer through the data transmission external bus;

[0029] Step 6, the host computer evaluates various test results and generates a device function test result of the device under test.

[0030] Further, step 1 further includes: the host computer receives the test requirements of the device under test input, analyzes the test requirements into a test software model for multiple signals in the form of a parameter model of a stochastic process according to a signal processing algorithm, and performs spectral estimation based on the parameter model; the spectral estimation based on the parameter model includes the following sub-steps:

[0031] Step 1.1, determine or select a reasonable parameter model to be estimated for the stochastic process;

[0032] Step 1.2, estimate the parameters of the parameter model according to the relevant data of the known device under test;

[0033] Step 1.3, calculate the power spectrum using the parameters of the estimated parameter model.

[0034] Further, in step 4, the microcontroller's optimal configuration of test resources includes:

[0035] Step 4.1, use the firefly optimization algorithm to optimize the configuration of multi-model general test resources; the firefly optimization algorithm includes the following sub-steps:

[0036] Step 4.11, population initialization: take the firefly population size as N, with an optimization variable as a firefly individual, and limit the value range of each element of the individual within (0, δ), where δ is the upper limit of the test resource quantity value, and initialize the following parameters: the current iteration number, the maximum iteration number, the initial step size, and the initial attractiveness;

[0037] Step 4.12, preprocessing of firefly individuals: after calculating the absolute value of each element of the initialized individual, perform a rounding operation;

[0038] Step 4.13, calculate the individual brightness: perform a dimensionless processing on the objective function and combine it through a weighting coefficient as the fitness of the individual at the current position;

[0039] Step 4.14, calculate the individual attractiveness: calculate the attractiveness between two individuals according to the distance between two firefly individuals;

[0040] Step 4.15, update the firefly position: further calculate a new position according to the current position of the individual and the attractiveness between individuals;

[0041] Step 4.16, output of the optimal solution: if the iteration number reaches the maximum value, stop the search and output the position information of the individual with the highest current brightness; otherwise, return to step 4.12; output the information of the brightest individual obtained at the end of the search as the optimal solution for the test resource configuration.

[0042] Further, in step 4, the microcontroller controls multiple parameter measurement units connected to the data acquisition device to perform test work according to the test algorithm, including the following sub-steps:

[0043] Step 4.21: The host computer identifies the corresponding relationship between the type of the device under test, the transmitter model, and the signal collector interface number according to the matching information of the two-dimensional barcode, establishes a test algorithm data packet, and sends the test algorithm data packet to the microprocessor of the corresponding signal collector.

[0044] Step 4.22: The microprocessor analyzes the test algorithm data packet to obtain the test algorithm, and uses the analog-to-digital converter to collect and test the electrical signals of one or more sensors corresponding to a certain signal collector interface in the chip by switching the collected signals.

[0045] Step 4.23: The microprocessor calculates the physical quantity based on the electrical signal and displays the relevant performance parameters of the device under test.

[0046] Step 4.24: The test algorithm for each sensor includes: setting the signal preprocessing operation process, which includes designing the gain coefficient of the programmable gain amplifier to amplify the input signal to meet the dynamic measurement range requirements of the signal under test, setting the anti-aliasing filter to filter out the out-of-band interference, and using the analog-to-digital converter to perform analog-to-digital conversion on the input data.

[0047] Step 4.25: The waveform after analog-to-digital conversion is shaped to meet the signal input requirements of the microprocessor, and the microprocessor processes the input signal, executes the test algorithm operation, and outputs the operation result.

[0048] Further, step 6 includes the following sub-steps:

[0049] Step 6.1: The host computer receives multiple test result data packets, unpacks them, and classifies and stores the test data in the storage device.

[0050] Step 6.2: The host computer extracts the design parameters of the device under test pre-stored in the storage device, compares the test data with the design parameters, and generates a comparison result between the test data and the design parameters.

[0051] Step 6.3: The host computer generates an evaluation report for the device under test based on multiple comparison results and outputs the evaluation report.

[0052] The method of the present invention has the following advantages: The general equipment test system of the present invention uses multiple data acquisition devices to form an overall test capability. The test tasks are assigned to each test unit of the test system through the service decision layer of the upper computer. The adjustable equipment flexible test function is jointly realized through the service decision layer, the data acquisition layer, and the signal layer. Through the methods of standardizing interfaces, configuring drivers, and bus interconnection, the function recombination and flexible expansion test function based on the acquisition device are realized. Any test equipment that follows the interface specifications can be connected, and the test function can be further expanded after connection. By virtue of the ability to re-determine the test mode through software definition, a test method for various types of equipment independent of equipment categories, test tasks, and data sources is provided, which can well meet the requirements of different equipment and different test scenarios.

[0053] The above description is only an overview of the technical solution of the present invention. In order to be able to understand the technical means of the present invention more clearly, it can be implemented according to the content of the description. And in order to make the above and other purposes, features, and advantages of the present invention more obvious and understandable, the following specific preferred embodiments are given, and detailed descriptions are provided in conjunction with the accompanying drawings as follows. Brief Description of the Drawings

[0054] Figure 1 Principle block diagram of the general equipment test system of the present invention;

[0055] Figure 2 Schematic diagram of the overall composition of the test system of the present invention;

[0056] Figure 3 Flowchart of the general equipment test method of the present invention;

[0057] Figure 4 Flowchart for parsing test data packets of the present invention. Detailed Embodiments

[0058] The present invention provides a flexible and software-changeable general test system. It selects test functions according to test algorithms, highlighting the plasticity, wide applicability, and agile development of test data acquisition devices. Through the software control around the upper computer and the combination of multiple single-function test function devices, the independence or low coupling with equipment categories, test tasks, and data sources is achieved. Furthermore, a general equipment test system convenient to use in test and evaluation is developed. This general equipment solves the problems of standardization, normalization, and agile development in the top-level architecture design of the data test acquisition system, promotes the development of the systematic construction of data acquisition devices, provides support for equipment transformation and the research and development of new equipment projects, and also provides support for the design and implementation of other test systems.

[0059] The general test system of the present invention includes a service decision-making layer, a data acquisition layer, and a signal layer, realizing the decoupling of test functions and the basic composition, logical structure, and mutual relationship of the general test system architecture.

[0060] The preferred embodiments of the present invention will be described in detail below in conjunction with the embodiments. It should be understood that the following embodiments are given only for the purpose of illustration and are not used to limit the protection scope of the present invention. Those skilled in the art can make various modifications and substitutions to the present invention without departing from the purpose and spirit of the present invention, and all such modifications and substitutions fall within the scope of the claims of the present invention.

[0061] Appendix Figure 1 is the principle block diagram of the general device test system of the present invention.

[0062] In a first aspect of the present invention, a general test system is provided, characterized in that the general test system includes: a host computer and a plurality of data acquisition devices, and the host computer is connected to the plurality of data acquisition devices through an external data transmission bus.

[0063] Each data acquisition device includes a microcontroller and a plurality of parameter measurement units, and the microcontroller is connected to and controls the plurality of parameter measurement units through an external data transmission bus.

[0064] The host computer receives the test requirements of the device under test, generates test models for the plurality of data acquisition devices, and makes the software data including the test models into test model data packets; the host computer distributes them to the plurality of data acquisition devices respectively through the external data transmission bus.

[0065] The microcontroller of each data acquisition device receives and parses the test model data packet and the test algorithm data packet associated with this data acquisition device, and the microcontroller decomposes and transforms the parsed test model data packet into a plurality of control models, and each control model is directly associated with the measurement function of a parameter measurement unit connected to the data acquisition device.

[0066] The microcontroller runs the control module to test the device under test according to the control model and the test algorithm, and stores the test results in the memory and / or uploads them to the host computer through the external data transmission bus.

[0067] Appendix Figure 2 is the overall composition schematic diagram of the test system of the present invention.

[0068] As in the general test system of the first aspect of the present invention, the microcontroller of each data acquisition device is connected to and controls the plurality of parameter measurement units through an independent internal data transmission bus.

[0069] The parameter measurement unit includes: a sensor module, an audio signal interface module, a video signal interface module, and a bus-type data interface module;

[0070] The sensors include: a natural environment sensor, a speed sensor, an electrical signal sensor, and an electromagnetic radiation signal sensor.

[0071] Embodiment 1

[0072] The general test system of the present invention takes a data acquisition device as the main body and a parameter measurement unit connected to the data acquisition device as the smallest entity to form a distributed test system. As shown in the attached Figure 1 figure, the host computer is connected to multiple data acquisition devices through a flexible topology of a data transmission external bus to meet the needs of different test scenarios. The host computer and the data acquisition devices are connected by a data transmission external bus. Between the data acquisition device, which includes a microcontroller and a data acquisition module (i.e., the parameter measurement unit), an independent data transmission internal bus is used to form a dual-transmission bus mode of the general test system architecture, meeting the needs of flexible combination and expansion. The host computer system decomposes the input device test requirements, generates specific test configurations, and software-selects and configures the test functions of each data acquisition device. The test functions are generated through signal test algorithms preset in the storage device and the functions of the existing parameter test units. The generated test data packets are sent step by step to the data acquisition devices and their parameter measurement units through the internal and external buses. The data acquisition devices and the included parameter measurement units perform data acquisition work. The data collected by the data acquisition module is converged in the reverse direction to the host computer system to complete data acquisition and management work.

[0073] The data acquisition device is composed of a microcontroller and a data acquisition module, and completes functions such as test configuration, data acquisition, and storage and convergence of data; the host computer management system is the user interaction and carrier for the realization of test functions, manages the data acquisition devices, and completes functions such as test task decomposition, test configuration distribution, test data convergence and collation, and test data visualization analysis. Through the cooperation and function integration of multiple acquisition devices, complex test requirements are solved, the coupling of system design is reduced, and the openness, combinability, and reconfigurability of the system are improved, adapting to diverse test scenarios.

[0074] To ensure the continuous and reliable operation of a test system composed of multiple acquisition units, for a test task, using 3 to 5 data acquisition units can basically meet most test task scenarios. Therefore, for the accuracy and reliability of testing, in addition to the address of the currently used main acquisition unit, at least 5 available backup acquisition unit addresses are designed. These backup acquisition unit addresses are designed according to the priority order of the working intensity of specific acquisition units, the convenience of maintenance operations, etc. The acquisition units with low working intensity and high convenience of maintenance operations are placed first. If the current main acquisition unit fails, the backup acquisition unit can be automatically called to replace the main acquisition unit.

[0075] The general test system architecture of the present invention includes: based on a data transmission bus, through test configuration, several data acquisition devices with "function definition and flexible combination" are formed into a test system, and relying on the test configuration to drive different acquisition devices and their internal modules to complete the specified functions, forming the test system capabilities.

[0076] The test configuration is the mapping relationship between "test requirements - test tasks - test functions" in the entire test system architecture. In the test configuration, the test system topology structure, the number of data acquisition devices, the composition of each data acquisition device, the robustness strategy, the bus protocol table, and test parameters, etc. that meet the current test task requirements are described.

[0077] For the general test system as described in the first aspect of the present invention, the microcontroller of each data acquisition device is connected to and controls the multiple parameter measurement units through an independent internal data transmission bus;

[0078] The parameter measurement unit includes: a sensor module, an audio signal interface module, a video signal interface module, and a bus-type data interface module;

[0079] The sensors include: natural environment sensors, speed sensors, electrical signal sensors, and electromagnetic radiation signal sensors.

[0080] The natural environment sensors include: wind speed and direction sensors, temperature sensors, humidity sensors, and rainfall sensors;

[0081] The audio signal interface module is connected to the audio signal output port of the device under test; the video signal interface module is used to connect to the video signal output port of the device under test;

[0082] The bus-type data interface module is used to connect to the bus output ports of various parameter data of the device under test; the buses connected by the bus-type data interface module include: serial buses, CAN buses, MIC buses, FlexRay buses, or FC buses.

[0083] The internal and external data transmission bus is a path that connects multiple acquisition units that make up the test system and the functional modules that make up the acquisition unit into an organic whole, directly affecting the integrity, economy, coordination, and effectiveness of the entire acquisition system. The selection and design of the data transmission bus need to effectively reduce the transmission delay caused by assembling multiple acquisition units to form a test system on the one hand. On the other hand, the internal data transmission bus serves the communication needs between multiple acquisition units and multiple functional modules. Its transmission distance is short, and it is easy to meet the requirements of the data transmission volume and quality between the acquisition unit and the functional module. Therefore, higher requirements are placed on the economy of the selected internal data transmission bus. Therefore, when selecting a data transmission bus, the following aspects need to be considered.

[0084] (1) Bus transmission bandwidth. The transmission bandwidth determines the capacity and real-time performance of data transmission and is the primary factor to be considered in the construction of a test system. The transmission distance, topology method, etc. of the bus type used also need to be considered.

[0085] (2) Bus topology. Currently, data transmission buses have topology methods such as bus type, star type, and hybrid type. For example, the CAN bus supports the bus type topology, and the Flexray bus supports the bus and star type topologies. When actually constructing a test system, due to restrictions in aspects such as the defined functions and placement positions of different data acquisition units and functional modules, different topology methods need to be adopted to comprehensively balance the requirements of various aspects and determine the data transmission bus.

[0086] (3) Bus protocol configuration and development. As a general test system architecture, data acquisition units and functional modules should have the ability to be connected as long as they meet the interface requirements.

[0087] (4) The environmental adaptability of the bus. As a test system that meets the test of general equipment, the harsh environment brought about by factors such as temperature, humidity, shock, vibration, dust, and electromagnetism requires the selected bus to have good environmental adaptability. It is required that the data transmission bus meets the application scenario requirements in terms of protocol chips, bus cables, etc.

[0088] For the general test system described in the first aspect of the present invention, the microcontroller of the data acquisition device includes a microprocessor or DSP, a data and program memory, an upstream bus interface module, a downstream bus interface module, and an analog-to-digital converter;

[0089] The upstream bus interface module is connected to the external data transmission bus;

[0090] The downstream bus interface module is connected to the internal data transmission bus;

[0091] The analog-to-digital converter is used to convert the output signals of the sensor module, audio signal interface module, and video signal interface module into digital signals and provide them to the microcontroller.

[0092] For the general test system described in the first aspect of the present invention, the upper computer includes a central processing unit, an input device, an output device, a display device, and a storage device;

[0093] The output device is connected to a data transmission external bus, a printing device, and a display device;

[0094] The input device is used to receive the test requirements of the device under test; it also queries the number and functions of the parameter measurement units connected to each of the data acquisition devices through the data transmission external bus;

[0095] The central processing unit analyzes the test requirements and generates a test model data packet according to various signal processing algorithms pre-stored in the storage device.

[0096] Appendix Figure 3 is the flowchart of the general device test method of the present invention.

[0097] Embodiment 2

[0098] The second aspect of the present invention provides the general test system as described above. The second aspect of the present invention provides a method for constructing the general test system described in any one of the foregoing, and the method includes the following steps;

[0099] Step 1, the upper computer receives the test requirements of the device under test input, and parses the test requirements into multiple test tasks according to the signal processing algorithm;

[0100] Step 2, the upper computer queries the number and functions of the parameter measurement units of each data acquisition device through the data transmission external bus;

[0101] Step 3, the upper computer generates a test model data packet according to the functions of the parameter measurement units for the multiple test tasks, and sends the test model data packet and the test algorithm data packet through the data transmission external bus;

[0102] Step 4, the microcontroller of the data acquisition device receives and parses the test model data packet and the test algorithm data packet of the present data acquisition device. The microcontroller decomposes and transforms the parsed test model data packet into multiple control models, and each control model is directly associated with the measurement function of a parameter measurement unit connected to the data acquisition device. The microcontroller optimally configures the test resources and controls the multiple parameter measurement units connected to the present data acquisition device to perform test work according to the control model and the test algorithm;

[0103] Step 5: The data acquisition device uploads various test result data of the device under test to the host computer via the external data transmission bus.

[0104] Step 6: The host computer evaluates various test results and generates the device function test result of the device under test.

[0105] The optimization configuration of the test resources by the microcontroller includes:

[0106] The firefly optimization algorithm is used to optimize the configuration of multi-model general test resources. Its core lies in simulating the flashing behavior of fireflies, establishing the concept of brightness to represent the fitness value of the solution, and using the position as the problem solution. This process is iterated repeatedly to search for the optimal solution. The firefly optimization algorithm includes the following steps:

[0107] Step 4.11: Population initialization: Take the firefly population size as N, with one optimization variable as one firefly individual, and limit the value range of each element of the individual within (0, δ), where δ is the upper limit of the value of the test resource quantity. Initialize the following parameters: the current iteration number t, the maximum iteration number tmax, the light absorption coefficient γ of the medium, the initial step size α, and the initial attractiveness β0;

[0108] Step 4.12: Preprocessing of firefly individuals: Since the configured quantity of test resources must be a non-negative integer, after calculating the absolute value of each element of the initialized individual, a rounding operation is performed; thus, the position Xi of the i-th firefly is obtained as:

[0109] Xi = round(|Xi,1|, |Xi,2|,..., |Xi,I|

[0110] where Xi,I is the configured quantity of the I-th test resource of the i-th firefly individual, and round(X) represents rounding X.

[0111] Step 4.13: Calculate the individual brightness: The objective function is made dimensionless and combined into a single objective value θ through a weighting coefficient, which is used as the fitness of the individual at the current position:

[0112] θ = λEa + (1 - λ)Ha

[0113] Among them, θ is the objective value obtained by dimensionless processing the objective function and merged by the weighting coefficient. λ is the weighting coefficient. Ea represents the brightness part related to the "energy" or "fitness" of the firefly individual. It is directly related to the quality of the solution represented by the firefly. The higher the quality of the solution (i.e., the better the objective function value), the larger Ea usually is; Ha represents the brightness part related to a certain "heuristic" or "prior knowledge" of the firefly individual. It is based on the specific nature or structure of the problem or some external information knowledge. In some cases, if there is a lack of clear heuristic information, Ha may be simplified to a constant or calculated dynamically according to a certain rule. Further, the reciprocal of the fitness can be calculated as the brightness Ii of the firefly individual, and the calculation method is:

[0114]

[0115] Among them, θi is the fitness of the firefly individual. Set the brightness value of the individual that does not meet the model constraint conditions to 0, and sort the brightness values of all individuals. The individual with low brightness moves towards the brightest individual Xj, and the brightest individual Xj keeps its position unchanged;

[0116] Step 4.14, calculate the individual attraction: Calculate the attraction βi,j between two individuals according to the distance between two firefly individuals, which is:

[0117]

[0118] Among them, βi,j is the attraction between two individuals, β0 is the initial attraction, γ is the absorption coefficient of the medium to light, and ri,j2 is the square of the Euclidean distance between two firefly individuals, that is:

[0119]

[0120] Among them, Xi and Xj are any two firefly individuals, and k is a counting symbol.

[0121] Step 4.15, update the firefly position: Further, according to the current position Xi of the individual and the attraction βi,j between individuals, calculate the new position as:

[0122]

[0123] Among them, α is the initial step size of the algorithm iteration, t is the current iteration number, and arand is a random number obeying the normal distribution (0, 1).

[0124] Step 4.16, output the optimal solution: If the iteration number reaches the maximum value tmax, stop the search and output the position information of the currently brightest individual, otherwise return to step S2; Take the information of the brightest individual obtained at the end of the search as the optimal solution for testing resource allocation.

[0125] The microprocessor tests by switching the electrical signals in the chip using the signals collected by the ADC (Analog-to-Digital Converter) according to the corresponding test algorithms of the device under test, and displays the physical quantities by back-calculating from the electrical signals; specifically including: The host computer identifies the correspondence between the type of the device under test, the transmitter model, and the signal collector interface number according to the matching information of the two-dimensional barcode, analyzes the test algorithm data packet to be used, and sends a command to the microprocessor of the corresponding signal collector; The microprocessor tests by switching the electrical signals of one or several channels of the corresponding signal collector interface in the chip using the signals collected by the ADC according to the test algorithms in the test algorithm data packet, and back-calculates the physical quantities from the electrical signals to display each performance parameter of the device under test.

[0126] The microcontroller of the data acquisition device receives and parses the test model data packet and the test algorithm data packet of this data acquisition device. The algorithm data packet performs specific design for a specific test item to generate an optimized data processing method. The parameter measurement unit of the present invention includes: a sensor module, an audio signal interface module, a video signal interface module, and a bus-type data interface module;

[0127] The sensors include: natural environment sensors, speed sensors, electrical signal sensors, and electromagnetic radiation signal sensors; The natural environment sensors include: wind speed and direction sensors, temperature sensors, humidity sensors, and rainfall sensors.

[0128] Each of the above sensors has a test algorithm. Taking the test algorithms of audio or electrical signal sensors as an example, first set the signal preprocessing operation process, and the signal preprocessing operation process includes: designing the gain coefficient of the programmable gain amplifier to amplify the input signal to meet the dynamic measurement range requirements of the signal to be measured, setting an anti-aliasing filter to filter out out-of-band interference, and using an A / D converter to perform analog-to-digital conversion of the input data. Then shape the waveform to meet the requirements of the microprocessor. The microprocessor performs preprocessing, algorithm operations, and input / output device responses on the audio or electrical signal.

[0129] When performing Fourier transform analysis on the sampled audio signal, try to make the analysis spectral lines fall on the frequency of the signal to avoid the fence effect. Assume that the audio signal is x(t), the frequency is f0, the sampling frequency is fs, the number of sampling points is N, the time length is T, and the frequency sampling interval is Δf. According to the Fourier transform principle, the relationship between T and Δf is as follows

[0130] Δf = fs / N = 1 / T

[0131] In order to make the analysis signal fall at f0, f0 and Δf must satisfy:

[0132] Z = f0 / Δf (2)

[0133] Wherein: Z is a positive integer.

[0134] Assume that the period of the audio signal x(t) is T0, then the time length T and T0 have the following relationship:

[0135]

[0136] Only when the time length T of the number of sampling points N is an integer multiple of the period T0 of the audio signal x(t) can the analysis spectral line fall on the frequency of the signal to obtain an accurate spectrum. Therefore, with the frequency f of the signal to be measured as a reference, the sampling frequency dynamically and real-time tracks the signal frequency:

[0137] fs = n * f,

[0138] n is an integer. Oversampling technology is adopted during the sampling process to reduce the quantization noise of A / D and the design index of the anti-aliasing filter.

[0139] In the signal preprocessing algorithm, audio data is sampled for a period of time for signal preprocessing. In the time domain, the center frequency point of the signal to be measured is used as a reference point for multi-period synchronous averaging. According to the data after synchronous averaging, the frequency range and stability of the audio signal are judged, and then reasonable data acquisition time and algorithm processing time are allocated to the subsequent processing algorithms. The audio signal is synchronously averaged every 4 frequency periods to make the final signal tend to an ideal synchronous average signal. Using the above method, the audio signal is subjected to STFT every 4 periods, and then each parameter of the STFT measurement results of each time is removed of gross errors and averaged to obtain the amplitude and phase of the required frequency, and then the amplitude and phase are corrected to obtain the final result, thereby determining the frequency range and stability of the audio signal. The audio signal can be an engine vibration signal or a vibration frequency emitted during the operation of the equipment.

[0140] As described in the second aspect of the present invention, the test method, step 1 includes: the upper computer receives the test requirements of the device to be tested input, and parses the test requirements into a test software model for various signals in the form of a parameter model of a random process according to the signal processing algorithm; the spectral estimation step based on the parameter model includes the following sub-steps:

[0141] Step 1.1, determine or select a reasonable parameter model to be measured for the random process to be estimated;

[0142] Step 1.2, estimate the parameters of the parameter model according to the relevant data of the known device to be tested;

[0143] Step 1.3, calculate the power spectrum using the parameters of the estimated parameter model.

[0144] The testing method as described in the second aspect of the present invention, step 3 includes the following sub-steps:

[0145] Step 3.1, the host computer stores the number of parameter measurement units connected to each data acquisition device and the function data of each parameter measurement unit obtained from step 2 into a predetermined module of the storage device;

[0146] Step 3.2, the host computer extracts the relevant data of a predetermined data acquisition device, determines the test data that the predetermined data acquisition device can complete, and generates a test model data packet for the predetermined data acquisition device according to the test data;

[0147] Step 3.3, the host computer distributes multiple test model data packets to the associated data acquisition devices respectively through the data transmission external bus. Attached Figure 4 is the flowchart for parsing the test data packet of the present invention.

[0148] The testing method as described in the second aspect of the present invention, step 4 includes the sampling sub-step 4.3, which contains the following sub-steps:

[0149] Step 4.31, the microcontroller of the data acquisition device receives and parses the test model data packet distributed to this data acquisition device, and distributes the parsed single test function to the corresponding parameter measurement unit through the data transmission internal bus;

[0150] Step 4.32, the microcontroller of the data acquisition device receives the test results of the parameter measurement unit through the data transmission internal bus, and the test results include analog test signal data and digital test signal data;

[0151] Step 4.33, the microcontroller of the data acquisition device performs analog-to-digital conversion on the analog test signal in the test results to data signals;

[0152] Step 4.34, the microcontroller of the data acquisition device edits the digital test signal data and the analog-to-digital converted data signals into a test result data packet.

[0153] The testing method as described in the second aspect of the present invention, step 6 includes the following sub-steps:

[0154] Step 6.1, the host computer receives multiple test result data packets, unpacks them and classifies and stores the test data in the storage device;

[0155] Step 6.2, the host computer extracts the design parameters of the device under test pre-stored in the storage device, compares the test data with the design parameters, and generates a comparison result between the test data and the design parameters

[0156] Step 6.3: The host computer generates an evaluation report for the device under test based on multiple comparison results and outputs the evaluation report.

[0157] The data acquisition device consists of one or more acquisition devices that can undertake independent test tasks. Each acquisition device is composed of independently encapsulated parameter measurement units that can independently complete specified functions. The acquisition devices and the internal parameter measurement units are interconnected through a standardized data transmission bus interface. The acquisition devices and specific parameter measurement units are selected as needed according to the test requirements. The functions of the specific parameter measurement units are defined according to the test configuration description. Under a unified management mechanism and clock, the combined and extended test devices and parameter measurement units are driven to specifically implement and complete the test tasks.

[0158] The service decision-making layer is mainly composed of a management software system, which generates a test configuration description according to the test requirements, realizes software-defined systems, and functions such as data fusion processing, management, and visual display.

[0159] Standardization means that the data transmission bus interface specifications, test task descriptions, collaborative management mechanisms, data arrangement and storage formats, etc. adopt unified standards to ensure the combinability, extensibility, and reconfigurability of the data acquisition device, meeting the needs of different test purposes and different test scenarios.

[0160] Based on standardization, combinability realizes the combination of acquisition devices and internal modules through the data transmission bus and test task descriptions based on test configurations. In essence, it aims to achieve "flexible deployment and logical integration". Thus, the versatility of the general test system architecture is realized, so as to achieve the purpose that the test system constructed based on the general test system architecture is independent of the equipment, independent of the test task, and independent of the signal source.

[0161] Modularization refers to the modular design of software and hardware in the system architecture. By reasonably dividing the functional interfaces and adopting a modular approach, a loose coupling relationship between modules and within modules is established, so that all connections between modules are realized through standardized information interaction protocols and data transmission bus interfaces, achieving the independence of modules and laying the foundation for combinability. At the same time, the independent design of the internal functional devices of the modules also lays the foundation for module expansion and improvement of reliability and maintainability.

[0162] Embodiment 3

[0163] The tasks of the host computer are as follows:

[0164] 1) Use the Flexray external bus to schedule the data interaction of each acquisition device;

[0165] 2) Use the internal Flexray bus to distribute the instructions sent by the upper computer to the corresponding parameter measurement units;

[0166] 3) Use the internal Flexray bus, the external Flexray bus, and the TCP network protocol to conduct two-way interaction with the upper computer;

[0167] 4) Collect and analyze various signals according to the configured parameters. Analyze, packetize, and aggregate the data and then transmit it to the upper computer for final processing on the upper computer.

[0168] The first-level network: This layer of network is the TCP connection between the upper computer and the core module. The core module will automatically detect the connection status with the upper computer. If a reliable connection is detected by TCP, all the data received by the internal and external buses will be uploaded through TCP. If a reliable TCP connection is not detected, the data will be transmitted to the external bus. Any core module connected to the upper computer in the external bus network will assist the unconnected core module in uploading data.

[0169] The TCP protocol, i.e., the Transmission Control Protocol, is a very important communication protocol. It is connection-oriented and needs to establish a connection before data transmission to ensure the reliability and stability of communication. It has high reliability and guarantees the accurate transmission of data through mechanisms such as acknowledgment, retransmission, and sequencing. At the same time, it has a flow control function. The receiving party controls the sending party's speed by notifying the window size to prevent data loss due to insufficient processing capacity of the receiving party. In addition, it can also perform congestion control and adjust the speed of sending data according to the network congestion situation.

[0170] The second-level network: This layer of network is the Flexray bus connection between each core module. If only one acquisition device is working, the external bus network will not work. If there are multiple acquisition devices, the external bus network will be automatically activated.

[0171] When the external bus network is working, the core modules will be divided into two working conditions: the connected modules that have established a reliable connection with the upper computer and the unconnected modules that have not established a reliable connection with the upper computer. During operation, the connected modules will receive the instructions sent by the upper computer and convey the instructions sent by the upper computer to the unconnected modules through the external bus network. When the unconnected modules upload data, they will also first convey the data to the connected modules through the external bus, and then the connected modules will upload the data.

[0172] Third-level network: This layer is the Flexray bus within each acquisition device, with the core module as the master and the parameter measurement units as slaves. When the core module of the acquisition device receives a command from the host computer, regardless of whether the command originates from the host computer or is forwarded by a connected module via the external bus network, the core module sends the command to the corresponding parameter measurement unit according to the address. The parameter measurement unit then changes its status or performs the corresponding operation according to the command.

[0173] When the parameter measurement unit in the acquisition device collects the configured acquisition signal, the parameter measurement unit will parse the collected signal according to the analysis configuration, package it, and then upload it. Then the core module will forward the data uploaded by the parameter measurement unit to the host computer.

[0174] The software design follows the principle of maximizing the use of MCU resources. Here we introduce the MCU model and characteristics selected for this project, which are closely related to the principles of software design.

[0175] The acquisition function area is responsible for collecting signals according to instructions, then packaging the data to the encoding and decoding function area, and finally handing it over to the communication function area for uploading the data. The communication function area receives instructions from the upper computer at any time. The program mechanism of the acquisition function of the acquisition function area is divided into two acquisition modes according to different types of acquisition objects:

[0176] Passive acquisition, such as various buses, involves data being transmitted by an external device under test. Each time data is received from the device under test, the program checks whether the frame matches the configuration information. If the received data matches the data required by the parsing configuration, the message is sent to the codec program for initial parsing and initial packetization. Therefore, the upload rate of this type of signal is consistent with the transmission rate of the device under test.

[0177] Active acquisition, such as voltage and switch signals. Even if there is no external signal source, the floating voltage of the wiring harness can be collected and uploaded as the collected data. The microprocessor collects the voltage and switch information connected to the wiring harness, and transmits the collected data to the encoding and decoding function area for packaging.

[0178] (2) Codec Function Area

[0179] After the acquisition function area collects the data, the collected and parsed data will be sent to the encoding and decoding function area, where it will be stored in the FIFO according to a specific format.

[0180] The packetized data packets stored in the FIFO will be uploaded according to this data stream: first sent from the acquisition module to the core module through the internal bus Flexray, and then the data is shared among the core modules through the external bus Flexray. Therefore, all the data collected by all the acquisition devices can be stored equally in each core module. The core module set as the main acquisition module will be connected to the upper computer, and upload this data to the upper computer in the first-in-first-out order through Ethernet. The upper computer then unpacks and encapsulates it into a database format according to the packetized format.

[0181] The encoding and decoding functional area is also responsible for parsing the instructions sent by the upper computer, and the parsing process is as shown in the appendix Figure 4 as follows.

[0182] The evaluation of the test results by the upper computer includes two types of evaluation methods. One is quantitative evaluation. This evaluation is usually for certain performances of the device under test that have been determined, such as the driving speed of a vehicle, acceleration or deceleration performance, maximum driving distance, noise intensity, etc.

[0183] The other evaluation is for the specific performances of new devices. These performances may still be in the condition domain with fuzzy indicators. The evaluation method proposed in the present invention can use the known indicators for deep learning training to obtain parameter data that optimizes the fuzzy indicators, and use the optimized parameter data as the test standard to detect the test results of the device. The present invention applies deep learning to the selection process of fuzzy testing, and intelligently selects different algorithms for different test cases. The test results are effectively evaluated based on the deep learning algorithm.

[0184] Although the present invention has been described in detail with general descriptions and specific embodiments above, based on the present invention, some modifications or improvements can be made, which are obvious to those skilled in the art. Therefore, these modifications or improvements made without departing from the spirit of the present invention all fall within the scope of protection required by the present invention.

Claims

1. A general test system, characterized in that, The described general test system includes: a host computer and multiple data acquisition devices, and the host computer is connected to the multiple data acquisition devices through a data transmission external bus; Each of the data acquisition devices includes a microcontroller and multiple parameter measurement units, and the microcontroller is connected to and controls the multiple parameter measurement units through a data transmission external bus; The host computer receives the test requirements of the device under test, generates test models and test algorithms for the multiple data acquisition devices, and makes software data including the test models and test algorithms into test model data packets and test algorithm data packets; the host computer respectively sends the test model data packets and test algorithm data packets to the multiple data acquisition devices through the data transmission external bus; The microcontroller of each data acquisition device receives and parses the test model data packet and the test algorithm data packet associated with this data acquisition device, and the microcontroller decomposes and transforms the parsed test model data packet into multiple control models, and each control model is directly associated with the measurement function of a parameter measurement unit connected to the data acquisition device; The microcontroller tests the device under test according to the control models and test algorithms by operating the control module, and stores the test results in the memory and / or uploads them to the host computer through the data transmission external bus.

2. The general test system according to claim 1, characterized in that, The microcontroller of each data acquisition device is connected to and controls the multiple parameter measurement units through an independent data transmission internal bus; Each of the parameter measurement units includes: a sensor module, an audio signal interface module, a video signal interface module, and a bus-type data interface module; The sensors include: natural environment sensors, speed sensors, electrical signal sensors, and electromagnetic radiation signal sensors.

3. The general test system according to claim 2, wherein The natural environment sensors include: wind speed and direction sensors, temperature sensors, humidity sensors, and rainfall sensors; The audio signal interface module is connected to the audio signal output port of the device under test; the video signal interface module is used to connect to the video signal output port of the device under test; The bus-type data interface module is used to connect to the bus output port of the various parameter data of the device under test.

4. The general test system according to claim 2, wherein The microcontroller of the data acquisition device includes a microprocessor or DSP, data and program memories, an upstream bus interface module, a downstream bus interface module, and an analog-to-digital converter; The upstream bus interface module is connected to the data transmission external bus; The downstream bus interface module is connected to the data transmission internal bus; The analog-to-digital converter is used to transform the output signals of the sensor module, the audio signal interface module, and the video signal interface module into digital signals and provide them to the microcontroller.

5. The general test system according to claim 1, wherein The host computer includes a central processing unit, an input device, an output device, a display device, and a storage device; The output device is connected to a printing device and a display device through a data transmission external bus; The input device is used to receive the test requirements of the device under test; the input device also queries the number and functions of the parameter measurement units connected to each data acquisition device through the data transmission external bus; The central processor analyzes the test requirements and generates a test model data packet and a test algorithm data packet according to a variety of signal processing algorithms pre-stored in the storage device.

6. A method for constructing a general test system for the general test system according to any one of claims 1-5, characterized in that, The method includes the following steps; Step 1, the host computer receives the test requirements of the device under test input, and resolves the test requirements into multiple test tasks according to the signal processing algorithm; Step 2, the host computer queries the number and functions of the parameter measurement units of each data acquisition device through the data transmission external bus; Step 3, the host computer generates a test model data packet and a test algorithm data packet according to the functions of the parameter measurement units for the multiple test tasks, and sends the test model data packet and the test algorithm data packet through the data transmission external bus; Step 4, the microcontroller of the data acquisition device receives and analyzes the test model data packet and the test algorithm data packet of this data acquisition device. The microcontroller decomposes and transforms the analyzed test model data packet into multiple control models. Each control model or test algorithm is directly associated with the measurement function of a parameter measurement unit connected to the data acquisition device; the microcontroller optimally configures the test resources, and the microcontroller controls multiple parameter measurement units connected to this data acquisition device to perform test work according to the control model and the test algorithm; Step 5, the data acquisition device uploads various test result data of the device under test to the host computer through the data transmission external bus; Step 6, the host computer evaluates various test results and generates the device function test result of the device under test.

7. The method for constructing a general test system according to claim 6, wherein The further steps of Step 1 include: the host computer receives the test requirements of the device under test input, resolves the test requirements into a test software model of a parameter model of a random process for multiple signals according to the signal processing algorithm, and performs spectral estimation based on the parameter model; the spectral estimation based on the parameter model includes the following sub-steps: Step 1.1, determine or select a reasonable parameter model to be estimated for the random process; Step 1.2, estimate the parameters of the parameter model according to the relevant data of the known device under test; Step 1.3, calculate the power spectrum with the parameters of the estimated parameter model.

8. The method for constructing a general test system according to claim 6, wherein The optimization configuration of the test resources by the microcontroller in Step 4 includes: Step 4.1, adopt the firefly optimization algorithm to optimize the configuration of multi-model general test resources; the firefly optimization algorithm includes the following sub-steps: Step 4.11, population initialization: take the firefly population number as N, take an optimization variable as a firefly individual, and limit the value range of each element of the individual within (0, δ), where δ is the upper limit of the test resource quantity value, and initialize the following parameters: the current iteration number, the maximum iteration number, the initial step size, and the initial attractiveness; Step 4.12, Firefly individual preprocessing: After calculating the absolute value of each element of the initialized individual, perform a rounding operation. Step 4.13, Calculate individual brightness: Nondimensionalize the objective function and combine it through a weighting coefficient as the fitness of the individual at the current position. Step 4.14, Calculate individual attractiveness: Calculate the attractiveness between two individuals according to the distance between the two firefly individuals. Step 4.15, Firefly position update: Further calculate the new position according to the current position of the individual and the attractiveness between individuals. Step 4.16, Optimal solution output: If the number of iterations reaches the maximum value, stop the search and output the position information of the individual with the highest current brightness; otherwise, return to Step 4.12; Output the information of the brightest individual obtained at the end of the search as the optimal solution for test resource allocation.

9. The method for constructing a general test system according to claim 6, characterized in that, In Step 4, the microcontroller controls multiple parameter measurement units connected to the data acquisition device to perform test work according to the test algorithm, including the following sub-steps: Step 4.21, The host computer identifies the corresponding relationship between the type of device under test, the transmitter model, and the signal collector interface number according to the matching information of the two-dimensional barcode, establishes a test algorithm data packet, and sends the test algorithm data packet to the microprocessor of the corresponding signal collector. Step 4.22, The microprocessor parses the test algorithm data packet to obtain the test algorithm, and uses the analog-to-digital converter to collect and test the electrical signals of one or more sensors corresponding to a certain signal collector interface in the chip by switching the collected signals. Step 4.23, The microprocessor calculates the physical quantity based on the electrical signal and displays the relevant performance parameters of the device under test. Step 4.24, The test algorithm for each sensor includes: setting the signal preprocessing operation process, and the signal preprocessing operation process includes designing the gain coefficient of the programmable gain amplifier to amplify the input signal to meet the dynamic measurement range requirements of the signal under test, setting an anti-aliasing filter to filter out out-of-band interference, and using an analog-to-digital converter to perform analog-to-digital conversion of the input data. Step 4.25, Shape the waveform after analog-to-digital conversion to meet the signal input requirements of the microprocessor, and the microprocessor processes the input signal, executes the test algorithm operation, and outputs the operation result.

10. The method for constructing a general test system according to claim 6, wherein Step 6 includes the following sub-steps: Step 6.1, The host computer receives multiple test result data packets, unpacks them, and stores the test data in a classified manner in a storage device. Step 6.2, The host computer extracts the design parameters of the device under test pre-stored in the storage device, compares the test data with the design parameters, and generates a comparison result between the test data and the design parameters. Step 6.3, The host computer generates an evaluation report for the device under test based on multiple comparison results and outputs the evaluation report.

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