Chip, equipment and data processing method

Abstract

The invention discloses a chip, equipment and a data processing method, and belongs to the technical field of computers. A reservation station table, a selection unit and a mask unit in the chip are connected in pairs, the selection unit is connected with a first assembly line, the mask unit is connected with a first comparison unit, and the first comparison unit is connected with a second assembly line; the selection unit is used for determining a first loading instruction from a reservation station table, and the reservation station table is used for storing at least two candidate loading instructions to be executed; the mask unit is used for determining a mask vector according to the first loading instruction and other loading instructions, and the mask vector is used for indicating whether a first storage area of the first loading instruction in the data cache is the same as a target storage area of other loading instructions in the data cache; the first comparison unit is used for determining a second loading instruction according to the mask vector; the first assembly line is used for accessing data in the data cache according to the first loading instruction; the second assembly line is used for accessing the data in the data cache according to the second loading instruction.

Description

Technical Field

[0001] This application relates to the field of computer technologies, and in particular, to a chip, a device, and a data processing method. Background Art

[0002] A Load instruction is used to access data for an electronic device to perform processing such as editing, moving, and deleting the data.

[0003] In related technologies, parallel execution of Load instructions means that multiple Load instructions are executed simultaneously in terms of timing to achieve parallel access to multiple data in a data cache. When multiple data correspond to the same storage area, only one Load instruction can be executed, and the remaining Load instructions need to be re-executed.

[0004] How to improve the efficiency of parallel execution of Load instructions is an urgent problem to be solved. Summary of the Invention

[0005] This application provides a chip, a device, and a data processing method, and the technical solutions are as follows:

[0006] According to one aspect of this application, a chip is provided. The chip includes: a reservation station table, a selection unit, a mask unit, a first comparison unit, a first pipeline, and a second pipeline; the reservation station table, the selection unit, and the mask unit are pairwise connected; the selection unit is connected to the first pipeline; the mask unit is connected to the first comparison unit; and the first comparison unit is connected to the second pipeline;

[0007] The selection unit is configured to determine a first Load instruction from the reservation station table, where the reservation station table is used to store at least two candidate Load instructions to be executed, and the candidate Load instructions are used to access data in a data cache;

[0008] The mask unit is configured to determine a mask vector according to the first Load instruction and other Load instructions stored in the reservation station table, where the mask vector is used to indicate whether a first storage area of the first Load instruction in the data cache is the same as a target storage area of the other Load instructions in the data cache, and the other Load instructions are instructions in the reservation station table except the first Load instruction;

[0009] The first comparison unit is configured to determine a second Load instruction from the reservation station table according to the mask vector, where the first storage area corresponding to the first Load instruction is different from a second storage area corresponding to the second Load instruction;

[0010] The first pipeline is configured to access data in the data cache according to the first Load instruction;

[0011] The second pipeline is used to access data in the data cache according to the second load instruction, and the first pipeline and the second pipeline access data in parallel.

[0012] According to another aspect of the present application, a computer device is provided, and the computer device includes a chip as described in the above aspect.

[0013] According to another aspect of the present application, a data processing method is provided. The method is applied to a chip, and the chip includes: a reservation station table, a selection unit, a mask unit, a first comparison unit, a first pipeline, and a second pipeline; the reservation station table, the selection unit, and the mask unit are pairwise connected, the selection unit is connected to the first pipeline, the mask unit is connected to the first comparison unit, and the first comparison unit is connected to the second pipeline; the method includes:

[0014] The selection unit determines a first load instruction from the reservation station table, and the reservation station table is used to store at least two candidate load instructions to be executed, and the candidate load instructions are used to access data in the data cache;

[0015] The mask unit determines a mask vector according to the first load instruction and other load instructions stored in the reservation station table. The mask vector is used to indicate whether the first storage area of the first load instruction in the data cache is the same as the target storage area of the other load instructions in the data cache, and the other load instructions are instructions other than the first load instruction in the reservation station table;

[0016] The first comparison unit determines a second load instruction from the reservation station table according to the mask vector, and the first storage area corresponding to the first load instruction is different from the second storage area corresponding to the second load instruction;

[0017] The first pipeline accesses data in the data cache according to the first load instruction;

[0018] The second pipeline accesses data in the data cache according to the second load instruction, and the first pipeline and the second pipeline access data in parallel.

[0019] The beneficial effects brought by the technical solution provided by the present application at least include:

[0020] It is indicated by a mask vector whether the first storage area corresponding to the first load instruction is the same as the target storage areas corresponding to other load instructions. The second pipeline accesses data in the data cache based on the second load instruction. Since the first storage area is different from the second storage area corresponding to the second load instruction, it is ensured that there will be no storage area conflict; it avoids the problem that when load instructions are executed in parallel, due to the limitation of storage area conflict, only one load instruction can be executed, and improves the processing efficiency of parallel execution of load instructions. Description of the Drawings

[0021] To more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0022] Figure 1 It is a block diagram of an electronic device provided by an exemplary embodiment of the present application;

[0023] Figure 2 It is a flowchart of a data processing method provided by an exemplary embodiment of the present application;

[0024] Figure 3 It is a flowchart of a data processing method provided by an exemplary embodiment of the present application;

[0025] Figure 4 It is a schematic diagram of an offset field provided by an exemplary embodiment of the present application;

[0026] Figure 5 It is a block diagram of an electronic device provided by an exemplary embodiment of the present application;

[0027] Figure 6 It is a flowchart of a data processing method provided by an exemplary embodiment of the present application;

[0028] Figure 7 It is a schematic diagram of a data cache provided by an exemplary embodiment of the present application;

[0029] Figure 8 It is a flowchart of a data processing method provided by an exemplary embodiment of the present application;

[0030] Figure 9 It is a schematic diagram of a data processing method provided by an exemplary embodiment of the present application.

[0031] The drawings here are incorporated into the specification and constitute a part of this specification, showing the embodiments in line with the present application, and are used together with the specification to explain the principles of the present application. Detailed implementation manners

[0032] To make the objectives, technical solutions and advantages of the present application clearer, the following will further describe the implementation manners of the present application in detail with reference to the accompanying drawings.

[0033] Here, the exemplary embodiments will be described in detail, and the examples are shown in the accompanying drawings. When the following description refers to the accompanying drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The implementation manners described in the following exemplary embodiments do not represent all implementation manners consistent with the present application. On the contrary, they are merely examples of devices and methods consistent with some aspects of the present application as detailed in the appended claims.

[0034] The terms used in the present disclosure are only for the purpose of describing specific embodiments and are not intended to limit the present disclosure. The singular forms "a", "the" and "said" used in the present disclosure and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term "and / or" as used herein refers to and includes any or all possible combinations of one or more of the associated listed items.

[0035] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data for analysis, stored data, displayed data, etc.) involved in the present application are all information and data that have been authorized by the user or fully authorized by all parties, and the collection, use and processing of the relevant data need to comply with the relevant laws, regulations and standards of the relevant countries and regions. For example, the candidate loading instructions, description information, etc. involved in the present application are all obtained under full authorization.

[0036] It should be understood that although the terms first, second, etc. may be used in the present disclosure to describe various information, these information should not be limited to these terms. These terms are only used to distinguish the same type of information from each other. For example, without departing from the scope of the present disclosure, the first parameter may also be referred to as the second parameter, and similarly, the second parameter may also be referred to as the first parameter. Depending on the context, the word "if" as used herein may be interpreted as "when" or "while" or "in response to determining".

[0037] Figure 1The structural block diagram of an electronic device provided by an embodiment of the present application is shown. The electronic device 100 can be implemented as the system architecture of a data processing method. The electronic device 100 in this embodiment is a device with data processing capabilities. Exemplarily, the electronic device 100 is a chip including one or more processing cores, such as a 4-core processor, an 8-core processor, etc. The processor can be implemented in at least one hardware form of Digital Signal Processing (DSP), Field-Programmable Gate Array (FPGA), and Programmable Logic Array (PLA). Exemplarily, the above-mentioned processor can be at least one of a Central Processing Unit (CPU), a Graphics Processing Unit (GPU), and an Artificial Intelligence (AI) processor, or can also be other devices with data processing capabilities, which are not limited in this application.

[0038] The reservation station table 110 is a hardware component in the electronic device 100 for storing Load instructions. The reservation station table 110 is respectively connected to the selection unit 120 and the mask unit 130. The mask unit 130 is connected to the first comparison unit 140, and the selection unit 120 is connected to the mask unit 130. The selection unit 120, the mask unit 130, and the first comparison unit 140 in the electronic device 100 are devices with data processing capabilities, such as one or more processing cores in a processor.

[0039] Furthermore, the reservation station table 110 can store Load instructions in the data structure of an array. Each entry in the reservation station table 110 corresponds to a Load instruction. The entries in the reservation station table 110 contain some fields for the relevant information of the Load instruction, such as at least one of the address information of the Load instruction, whether the Load instruction is valid, and the storage time of the Load instruction in the reservation station table 110.

[0040] The selection unit 120 is connected to the first pipeline 210, and the first pipeline 210 has the ability to access data in the data cache 250. The first comparison unit 140 is connected to the second pipeline 220; similarly, the second pipeline 220 has the ability to access data in the data cache 250. Exemplarily, the second pipeline 220 can directly or indirectly obtain the data processing result output by the first comparison unit 140, and there is no limitation that other hardware components are connected between the mask unit 130 and the second pipeline 220.

[0041] The data cache (D-cache) 250 is a high-speed cache inside the electronic device 100 and is used to store data. The data cache 250 is usually composed of a Static Random Access Memory (SRAM).

[0042] Figure 2 The flowchart of the data processing method provided by an exemplary embodiment of the present application is shown. This method can be applied to a chip. The method includes:

[0043] Step 510: The selection unit determines a first load instruction from the reservation station table;

[0044] The reservation station table is used to store at least two candidate load instructions to be executed, and the candidate load instructions are used to access data in the data cache. Exemplarily, the ways to access data in the data cache include but are not limited to at least one of the following: reading, editing, and moving the data position.

[0045] Exemplarily, the selection unit can determine the first load instruction in the reservation station table in a random manner; it can also determine the first load instruction according to at least one of the information such as the address information of the candidate load instructions recorded in the reservation station table, whether the candidate load instructions are valid, and the storage time of the candidate load instructions in the reservation station table; this embodiment does not limit this.

[0046] In an optional implementation, the first load instruction is an instruction in an effective state, and the above effective state is used to indicate at least one of the following: the first load instruction has no instruction syntax error, the data position indicated by the first load instruction is an actual existing data position, and the instruction source of the first load instruction is a trusted source.

[0047] Step 520: The mask unit determines a mask vector according to the first load instruction and other load instructions stored in the reservation station table;

[0048] The mask vector is used to indicate whether the first storage area of the first load instruction in the data cache is the same as the target storage area of other load instructions in the data cache, and the other load instructions are the instructions in the reservation station table except the first load instruction.

[0049] Exemplarily, there are multiple storage areas in the data cache for storing service data, and one or more service data can be stored in one storage area. Further, the storage area in the data cache is a data storage unit (Bank). The first storage area is the storage area in the data cache of the data that the first load instruction indicates to access. Similarly, the target storage area is the storage area in the data cache of the data that the corresponding other load instruction indicates to access.

[0050] Step 530: The first comparison unit determines a second load instruction in the reservation station table according to the mask vector;

[0051] Exemplarily, the second load instruction is a load instruction determined from other load instructions, and the first storage area corresponding to the first load instruction is different from the second storage area corresponding to the second load instruction.

[0052] Exemplarily, the elements in the mask vector indicate whether the target storage area corresponding to other load instructions is the same as the first storage area. In one example, the target storage areas corresponding to some or all of the other load instructions are different from the first storage area, and the instructions meeting the above conditions are also called filtered load instructions. This embodiment does not limit the manner of determining the second load instruction from the filtered load instructions; the first comparison unit can determine the second load instruction randomly, or can determine the second load instruction according to the address information of the filtered load instructions recorded in the reservation station table, etc.

[0053] Step 540: The first pipeline accesses data in the data cache according to the first load instruction;

[0054] Exemplarily, the first pipeline accesses data in the data cache according to the access type and / or access address corresponding to the first load instruction.

[0055] This application does not limit whether step 540 can be executed before, after, or simultaneously with any step in the first step group. The first step group includes step 520, step 530, and step 550.

[0056] Step 550: The second pipeline accesses data in the data cache according to the second load instruction;

[0057] Exemplarily, the second pipeline accesses data in the data cache according to the access type and / or access address corresponding to the second load instruction.

[0058] Exemplarily, the first pipeline and the second pipeline access data in parallel. Since the first storage area corresponding to the first load instruction is different from the second storage area corresponding to the second load instruction, the data accessed by the first pipeline and the second pipeline in the data cache is different.

[0059] In summary, for the method provided in this embodiment, the mask vector indicates whether the first storage area corresponding to the first load instruction is the same as the target storage areas corresponding to other load instructions. The second pipeline accesses data in the data cache based on the second load instruction. Since the first storage area is different from the second storage area corresponding to the second load instruction, it is ensured that there will be no storage area conflict; the problem that when load instructions are executed in parallel, they are restricted by storage area conflicts and only one load instruction can be executed is avoided, and the processing efficiency of parallel execution of load instructions is improved.

[0060] Figure 3 The flowchart of a data processing method provided by an exemplary embodiment of the present application is shown. This method can be applied to a chip. That is, in Figure 2 In the illustrated embodiment, step 520 can be implemented as step 522, step 524, and step 526:

[0061] Step 522: The acquisition subunit acquires the storage area corresponding to each candidate load instruction stored in the reservation station table one by one;

[0062] Exemplarily, the reservation station table stores the storage areas of candidate load instructions. The storage areas acquired from the reservation station table include the first storage area of the first load instruction in the data cache and the target storage areas of other load instructions in the data cache.

[0063] In an optional example, step 522 can be implemented as the following two sub-steps:

[0064] The acquisition subunit acquires the address information of each candidate load instruction stored in the reservation station table;

[0065] The processing subunit determines the storage area corresponding to each candidate load instruction one by one according to the binary information recorded in the offset field in the address information.

[0066] Exemplarily, the reservation station table stores the address information (Addr) of each candidate load instruction, and the address information corresponds to the identification information of the candidate load instruction (such as the name or identity representation of the candidate load instruction) one by one. The address information (Addr) carries an offset (Offset) field; the offset field records binary information. It can be understood that the offset field includes one or more bits.

[0067] In an example, Figure 4A schematic diagram of an offset field provided by an exemplary embodiment of the present application is shown. Exemplarily, there are 8 storage areas provided in the data cache, denoted as bank0 to bank7. The offset field 612 is 3 bits in the address information 610. The binary information recorded in the offset field 612 is used to indicate the storage area in the data cache of the data to be accessed by the corresponding candidate record instruction. Exemplarily, the three-bit binary information in the offset field 612 is converted into a decimal number, and this decimal number is the sequence number of the storage area in the data cache of the data to be accessed by the corresponding candidate record instruction. For example: the three-bit binary information in the offset field 612 is 010, the obtained decimal number is 2, and the corresponding storage area is bank2.

[0068] Step 524: When the i-th storage area corresponding to the i-th other load instruction is the same as the first storage area, the processing subunit determines the i-th element of the mask vector as the first value;

[0069] Exemplarily, when the i-th storage area is the same as the first storage area, parallel execution of the first load instruction and the i-th other load instruction will cause the two load instructions to access the same storage area simultaneously, resulting in a storage area conflict. Determining the i-th element of the mask vector as the first value indicates to the second pipeline the risk of a storage area conflict.

[0070] Exemplarily, the elements in the mask vector correspond one-to-one with the other load instructions, but it does not exclude the case that there are other elements in the mask vector.

[0071] In an alternative example, step 524 may be implemented as:

[0072] The acquisition subunit acquires the first description information stored in the reservation station table;

[0073] When the i-th storage area corresponding to the i-th other load instruction is the same as the first storage area, the processing subunit corrects the i-th element of the first description information to the first value to obtain the mask vector.

[0074] Exemplarily, the first description information is used to indicate whether the other load instructions stored in the reservation station table are valid. Exemplarily, the first description information is information stored in a vector manner.

[0075] In an optional example, the first description information indicates whether each candidate load instruction is valid in a vector manner, and the number of elements in the first description information is the same as the number of candidate load instructions. Exemplarily, in the first description information, the first value is used to indicate that the corresponding candidate load instruction is in an invalid state, and the second value is used to indicate that the corresponding candidate load instruction is in a valid state. The valid state is used to indicate at least one of the following: the candidate load instruction has no instruction syntax error, the data location indicated by the candidate load instruction is an actual existing data location, and the instruction source of the candidate load instruction is a trusted source.

[0076] Exemplarily, based on the first description information, a mask vector is corrected. It can be seen that the mask vector not only indicates whether the target storage area corresponding to other load instructions is the same as the first storage area, but also indicates whether the candidate load instruction takes effect.

[0077] Step 526: When the j-th storage area corresponding to the j-th other load instruction is different from the first storage area, the processing subunit determines the j-th element of the mask vector as the second value;

[0078] Exemplarily, when the j-th storage area is the same as the first storage area, the first load instruction and the j-th other load instruction are executed in parallel. The storage areas simultaneously accessed by the two load instructions are different, and there will be no storage area conflict. The j-th element of the mask vector is determined as the second value, indicating to the second pipeline that there is no risk of storage area conflict.

[0079] In this embodiment, both i and j are positive integers, i and j are different, and the first value and the second value are different. In an example, the first value is 0 and the second value is 1.

[0080] It should be noted that this embodiment only shows the case where steps 524 and 526 are executed together, but does not exclude the case where steps 524 and 526 are executed alternatively. In this embodiment, the execution timing between steps 524 and 526 is not limited. Step 524 can be executed before, after, or simultaneously with step 526.

[0081] In summary, the method provided in this embodiment stores the storage areas corresponding to the candidate load instructions one by one in the reservation station table, determines one by one whether the target storage area corresponding to other load instructions is the same as the first storage area corresponding to the first load instruction, and constructs a mask vector; the second pipeline accesses the data in the data cache based on the second load instruction. Based on the difference between the first storage area and the second storage area corresponding to the second load instruction, it is ensured that there will be no storage area conflict; it avoids the problem that when load instructions are executed in parallel, due to the storage area conflict, only one load instruction can be executed alternatively, and improves the processing efficiency of parallel execution of load instructions.

[0082] Figure 5 The block diagram of the electronic device provided by an embodiment of the present application is shown. The electronic device 100 can be implemented as the system architecture of the data processing method. The electronic device 100 in this embodiment is a device with data processing capabilities. Exemplarily, the electronic device 100 is a chip including one or more processing cores, such as a 4-core processor, an 8-core processor, etc.

[0083] The electronic device 100 includes: a reservation station table 110, a selection unit 120, a mask unit 130, a first comparison unit 140, a first pipeline 210, a second pipeline 220, and a data cache 250; the connection relationships and introductions of the above hardware components can be referred to the introductions and Figure 1 the connection methods in Figure 5 above, which will not be elaborated here.

[0084] The electronic device 100 further includes the following devices with data processing capabilities: a shielding unit 150, a second comparison unit 160, a discrimination unit 175, and a multiplexer 170. For example, it is implemented as one or more processing cores in a processor.

[0085] Exemplarily, the reservation station table 110 is connected to the shielding unit 150, and the shielding unit 150 is connected to the second comparison unit 160;

[0086] For the multiplexer 170, the multiplexer 170 is deployed between the first comparison unit 140 and the second pipeline 220; specifically, the data output terminal of the multiplexer 170 is connected to the second pipeline 220, and the data output terminal of the multiplexer 170 provides a way to access data in the data cache 250 to the second pipeline 220.

[0087] The first data input terminal of the multiplexer 170 is connected to the first comparison unit 140, and the second data input terminal of the multiplexer 170 is connected to the second comparison unit 160; the first data input terminal and the second data input terminal of the multiplexer 170 receive two kinds of load instructions to be processed.

[0088] The address code port of the multiplexer 170 is connected to the discrimination unit 175, and the discrimination unit 175 is connected to the mask unit 130; the address code port of the multiplexer 170 indicates the way for the multiplexer 170 to select one load instruction from the two kinds of load instructions to be processed.

[0089] Figure 6 The flowchart of the data processing method provided by an exemplary embodiment of the present application is shown. This method can be applied to a kind of chip. That is, in Figure 2Based on the illustrated embodiments, it further includes step 515, step 516, step 532, step 535, step 536; step 550 can be implemented as step 552:

[0090] Step 515: The masking unit determines a masking vector according to at least two candidate load instructions stored in the reservation station table;

[0091] The masking vector is used to distinguish the first load instruction from other load instructions in the reservation station table; Exemplarily, the values of the elements corresponding to the first load instruction and the elements corresponding to other load instructions in the masking vector are different.

[0092] Exemplarily, the masking vector can be constructed or corrected based on the information stored in the reservation station table. In an alternative example, step 515 can be implemented as the following steps:

[0093] The masking unit obtains the second description information stored in the reservation station table;

[0094] The masking unit corrects the k-th element of the second description information to a third value to obtain the masking vector;

[0095] Exemplarily, the second description information is used to indicate whether at least two candidate load instructions in the reservation station table are valid. Exemplarily, the second description information is information stored in a vector manner, and each element in the second description information has a corresponding candidate load instruction. Among them, the k-th candidate load instruction corresponding to the k-th element is the first load instruction.

[0096] Exemplarily, in the second description information, the third value is used to indicate that the candidate load instruction corresponding to the element is invalid. It should be noted that the first load instruction is determined by step 510 in this embodiment and is a valid load instruction, that is, the value of the element corresponding to the first load instruction in the second description information is different from the third value.

[0097] In an example, the value of the element corresponding to the first load instruction in the second description information is 1, which is used to indicate that the first load instruction is a valid load instruction. By correcting the element corresponding to the first load instruction to the third value (for example, the value is 0), the masking vector is obtained.

[0098] Step 516: The second comparison unit determines a third load instruction in the reservation station table according to the masking vector;

[0099] Exemplarily, the third load instruction determined by the second comparison unit is different from the first load instruction; that is to say, the third load instruction is determined from the other load instructions except the first load instruction among at least two candidate load instructions.

[0100] Exemplarily, according to the values of the elements in the shielding vector, a third load instruction different from the first load instruction is determined. In one example, the element corresponding to the first load instruction takes a third value (for example, the value is 0), and the third load instruction is determined from the candidate load instructions where the values of the corresponding elements are not equal to 0. Similar to step 530, the present embodiment does not limit the manner of determining the third load instruction.

[0101] Step 532: The discrimination unit determines the address code according to the mask vector;

[0102] The address code is used to indicate whether the target storage areas corresponding to other load instructions are all the same as the first storage area corresponding to the first load instruction.

[0103] In one example, the values of the elements in the mask vector indicate whether the target storage areas corresponding to the corresponding other load instructions are the same as the first storage area.

[0104] Referring to the corresponding embodiments in the above text Figure 3 Taking the first value indicating that the target storage area is the same as the first storage area as an example; when all the elements in the mask vector are the first value, the discrimination unit determines the first address code (for example, the value of the first address code is 0), which is used to indicate that the target storage areas corresponding to other load instructions are all the same as the first storage area corresponding to the first load instruction. When all the elements in the mask vector are not the first value, the discrimination unit determines the second address code (for example, the value of the second address code is 1), which is used to indicate that the target storage areas corresponding to other load instructions are not all the same as the first storage area corresponding to the first load instruction.

[0105] Step 535: When the address code indicates that the target storage area is not the same as the first storage area, the multiplexer determines the second load instruction as the output load instruction;

[0106] Exemplarily, the address code port of the multiplexer is connected to the discrimination unit to obtain the address code obtained by the discrimination unit, and the address code indicates the manner in which the multiplexer determines the information output by the data output terminal among the two data input terminals. Further, the address code indicates that the information output by the data output terminal of the multiplexer is selected from one of the two data input terminals.

[0107] Exemplarily, when the address code indicates that the target storage area is not the same as the first storage area, the storage areas accessed by the second load instruction and the first load instruction are different, and there will be no storage area conflict.

[0108] Step 536: When the address code indicates that the target storage areas are all the same as the first storage area, the multiplexer determines the third load instruction as the output load instruction;

[0109] Exemplarily, when the address code indicates that the target storage areas are all the same as the first storage area, among other load instructions, the target storage areas corresponding to the load instructions in the valid state are all the same as the first storage area; that is, if any load instruction in the valid state is selected, the corresponding target storage area is the same as the first storage area. The second load instruction determined by the first comparison unit is empty.

[0110] The third load instruction is determined by the second comparison unit. The third load instruction is different from the first load instruction, ensuring that the first pipeline and the second pipeline do not execute the same load instruction in parallel.

[0111] Step 552: The second pipeline accesses data in the data cache according to the output load instruction provided by the multiplexer;

[0112] The multiplexer determines the output load instruction provided to the second pipeline at the data output end based on the discriminator unit connected to the address code port. The second pipeline accesses data in the data cache according to the access type and / or access address corresponding to the output load instruction. Exemplarily, the first pipeline and the second pipeline access data in parallel.

[0113] In summary, the method provided in this embodiment avoids two pipelines from executing the same load instruction in parallel by masking the vectors indicating instructions different from the first load instruction; the multiplexer determines the output load instruction based on the mask vector, providing a technical solution for determining the output load instruction in both cases where the target storage areas are all the same as the first storage area or not; reducing the risk that when executing load instructions in parallel, being restricted by conflicts in the storage area and only being able to execute one load instruction at a time, and improving the processing efficiency of executing load instructions in parallel.

[0114] Next, the data cache will be introduced. Figure 7 FIG. shows a schematic diagram of a data cache provided by an exemplary embodiment of the present application. In one example, the data cache 250 includes 4 ways (also referred to as 4-way data arrays); denoted as way0 to way3, and each way is divided into 8 data storage units (banks), denoted as bank0 to bank7.

[0115] In one example, there are two load instructions. One load instruction corresponds to the first data storage unit (bank0) of the first data group (way0); further, the field where the above load instruction is located in the data storage unit is denoted as instr0. The other load instruction corresponds to the first data storage unit (bank0) of the second data group (way1); further, the field where the above load instruction is located in the data storage unit is denoted as instr1.

[0116] It should be noted that even though the data storage units corresponding to the above two load instructions are both the first data storage unit (bank0), but the corresponding data groups are different (one load instruction corresponds to the first data group way0, and the other load instruction corresponds to the second data group way1), there will be no storage area conflict.

[0117] Next, the construction method of the masking vector will be further introduced:

[0118] As Figure 6 described in step 515, in an optional example, the masking vector is corrected based on the second description information. On the basis of the above description, it also includes:

[0119] · The masking unit obtains the first attribute information corresponding to at least two candidate load instructions in the reservation station table;

[0120] Exemplarily, the first attribute information carries at least one of the following: the storage time of the candidate load instruction in the reservation station table, the type information of the candidate load instruction, the application program to which the candidate load instruction belongs;

[0121] Exemplarily, the reservation station table stores the first attribute information of each candidate load instruction, and the first attribute information corresponds one-to-one to the identification information of the candidate load instruction (such as the name or identity representation of the candidate load instruction).

[0122] As introduced above, even if the storage areas corresponding to two parallel load instructions are the same, there will be no storage area conflict when the corresponding ways (ways) of the storage areas are different. It can be seen that if two parallel load instructions access the same data, due to the same storage area and the same corresponding way (way) of the storage area, a storage area conflict will occur. To reduce the risk of storage area conflict, it is necessary to avoid parallel load instructions from accessing the same data.

[0123] Correspondingly, the construction of the masking vector also includes at least one of the following steps:

[0124] · When the difference between the storage time of the x-th candidate load instruction and the storage time of the first load instruction by the shielding unit is greater than a preset time difference, the x-th element of the second description information is corrected to a third value;

[0125] This step is executed when the first attribute information carries the storage time of the candidate load instruction in the reservation station table.

[0126] The storage time of the x-th candidate load instruction indicates the time when the x-th candidate load instruction establishes a cache in the reservation station table. When the difference between the storage time of the x-th candidate load instruction and the storage time of the first load instruction is greater than a preset time difference, the time interval between the x-th candidate load instruction and the first load instruction is large. The x-th element of the second description information is corrected to a third value; this avoids determining the x-th candidate load instruction as the third load instruction.

[0127] On the one hand, repeated access to the same data usually occurs in periodically executed services or during the repeated execution of the same or similar services; when the above difference is greater than the preset time difference, the x-th element of the second description information is corrected to the third value; this excludes the influence caused by periodically executed services or repeatedly executed services and reduces the risk that the parallel executed load instructions access the same data.

[0128] On the other hand, from the perspective of the timing when the candidate load instruction is added to the reservation station table; in one example, the storage time of the first load instruction is earlier than the storage times of other load instructions, and it is the load instruction with the longest storage time in the reservation station table. The load instruction with a storage time close to the time when the first load instruction is added to the reservation station table is preferentially executed, which realizes the preferential execution of candidate load instructions with a longer storage time and avoids the problem that the candidate load instruction is not executed for a long time, resulting in poor timeliness of the service processing corresponding to the candidate load instruction.

[0129] · When the type of the y-th candidate load instruction is the same as the type of the first load instruction by the shielding unit, the y-th element of the second description information is corrected to a third value;

[0130] Exemplarily, the types of candidate load instructions include at least one of types such as reading data, editing data, moving data, etc., which respectively correspond to different data access methods. The above different types of candidate load instructions usually need to be combined to complete a service; for example, first read data, and when the data volume exceeds a preset limit size, move the data to other storage locations, and the candidate load instructions of the two types of reading data and moving data need to be combined. The later executed load instruction takes effect after the previously executed load instruction is completed.

[0131] It can be seen that two load instructions in the effective state and of different types correspond to different services, and the two services are often in different execution stages. For example, for two parallel services of first reading data and then moving data; the first service is in the first stage of reading data, and the load instruction corresponding to moving data is in the ineffective state. If there is a load instruction of the moving data type in the effective state, then this load instruction belongs to the second stage of moving data of the second service. The above two services are different and in different stages; since the electronic device needs to process numerous services, the data corresponding to different services is often different. Further, the two services being in different stages further ensures that the data corresponding to different services is different. Specifically, if the data corresponding to the two services is the same, an error will occur in the executed stage of the service, such as an incorrect data address. The load instructions of the two services are both in the effective state, which ensures that no error occurs in the executed stage of the two services, and further reduces the risk of the load instructions executed in parallel accessing the same data.

[0132] · When the application program to which the z-th candidate load instruction belongs is the same as the application program to which the first load instruction belongs, the shielding unit corrects the z-th element of the second description information to the third value;

[0133] Exemplarily, the candidate load instruction corresponds to an application program, and the application program is installed on a computer device including the above chip.

[0134] On the one hand, the data corresponding to the same application program is often continuous in the data cache, that is, in adjacent positions. Correcting the z-th element to the third value avoids the parallel execution of the z-th candidate load instruction and the first load instruction belonging to the same application program.

[0135] On the other hand, the services in the same application program are similar, and the possibility of accessing the same data is high. Correcting the z-th element to the third value reduces the risk of the load instructions executed in parallel accessing the same data.

[0136] It should be noted that x, y, and z are all positive integers, and this embodiment does not limit whether any two of x, y, and z are the same.

[0137] In summary, the method provided in this embodiment corrects the shielding vector based on the second description information, fully considering the characteristics of different load instructions accessing data in the data cache; uses the shielding vector to indicate instructions different from the first load instruction to avoid two pipelines from executing the same load instruction in parallel; the multiplexer determines the output load instruction based on the mask vector, providing a technical solution for determining the output load instruction in both cases where the target storage area is the same as the first storage area or not; reducing the risk of being restricted by storage area conflicts when executing load instructions in parallel and only being able to execute one load instruction at a time, and improving the processing efficiency of executing load instructions in parallel.

[0138] Figure 8 FIG. shows a flowchart of a data processing method provided by an exemplary embodiment of the present application. This method can be applied to a chip. That is, in Figure 2 In the illustrated embodiment, step 510 can be implemented as step 512:

[0139] Step 512: The selection unit determines a first load instruction from the reservation station table based on the storage times of at least two candidate load instructions.

[0140] The storage time is used to indicate the time when the reservation station table stores the corresponding candidate load instruction. Exemplarily, the storage time can be recorded and provided in the reservation station table, or provided by the application program described by the candidate load instruction.

[0141] The storage time of the first load instruction is earlier than the storage times of other load instructions, and the first load instruction is the load instruction with the earliest storage time among all candidate load instructions in the reservation station table.

[0142] In an optional example, before step 512, it further includes:

[0143] The selection unit obtains the second attribute information corresponding to at least two candidate load instructions in the reservation station table;

[0144] The second attribute information carries the storage time of the corresponding candidate load instruction in the reservation station table. Exemplarily, the reservation station table stores the second attribute information of each candidate load instruction, and the second attribute information corresponds to the identification information of the candidate load instruction (such as the name or identity representation of the candidate load instruction) one by one.

[0145] In summary, in the method provided in this embodiment, the loading instruction with the earliest storage time in the reservation station table is determined by the selection unit, and the candidate loading instruction with a longer storage time is preferentially executed, so as to avoid the problem that the candidate loading instruction is not executed for a long time, resulting in poor timeliness of the service processing corresponding to the candidate loading instruction; the mask vector indicates whether the first storage area corresponding to the first loading instruction is the same as the target storage areas corresponding to other loading instructions, and the second pipeline accesses the data in the data cache based on the second loading instruction. Based on the difference between the first storage area and the second storage area corresponding to the second loading instruction, it is ensured that there will be no storage area conflict; the problem that when loading instructions are executed in parallel, due to the restriction of storage area conflict, only one loading instruction can be selected for execution is avoided, and the processing efficiency of parallel execution of loading instructions is improved.

[0146] Figure 9 FIG. shows a schematic diagram of a data processing method provided by an exemplary embodiment of the present application. This method can be applied to an electronic device.

[0147] In this embodiment, the introduction and connection relationships of the hardware components such as the reservation station table 110, selection unit 120, mask unit 130, first comparison unit 140, shielding unit 150, second comparison unit 160, discrimination unit 175, multiplexer 170, first pipeline 210, second pipeline 220, and data cache 250 included in the electronic device can be referred to in the above Figure 1 、 Figure 5 、 Figure 7 and will not be repeated here one by one.

[0148] In one example, the combination of the hardware components of the reservation station table 110, selection unit 120, mask unit 130, first comparison unit 140, shielding unit 150, second comparison unit 160, discrimination unit 175, and multiplexer 170 is also referred to as a reservation station (RS).

[0149] The reservation station table 110 is used to store at least two candidate loading instructions to be executed; the selection unit 120 obtains the attribute information corresponding to at least two candidate loading instructions in the reservation station table 110, and the attribute information carries the storage time of the corresponding candidate loading instruction in the reservation station table 110;

[0150] The selection unit 120 determines the first loading instruction 302 from the reservation station table 110 based on the storage times of at least two candidate loading instructions. The storage time is used to indicate the time when the reservation station table 110 stores the corresponding candidate loading instruction. The storage time of the first loading instruction 302 is earlier than the storage times of other loading instructions, and other loading instructions are the instructions in the reservation station table 110 except the first loading instruction 302.

[0151] The mask unit 130 determines a mask vector 312 according to the first load instruction 302 and other load instructions stored in the reservation station table 110. The mask vector 312 is used to indicate whether the first storage area of the first load instruction 302 in the data cache 250 is the same as the target storage areas of other load instructions in the data cache 250;

[0152] In one example, each element in the mask vector 312 corresponds to an other load instruction one by one, and the mask vector 312 is obtained by modifying based on the first description information stored in the reservation station table 110. The first description information is used to indicate whether the other load instructions stored in the reservation station table 110 are valid;

[0153] Furthermore, the first description information is information stored in vector form. When the element of the first description information is a second value (such as 1), the corresponding other load instruction is in a valid state; when the element of the first description information is a first value (such as 0), the corresponding other load instruction is in an invalid state;

[0154] Based on the first description information, the mask vector 312 is obtained by modification. Specifically, when the i-th storage area corresponding to the i-th other load instruction is the same as the first storage area, the i-th element of the first description information is modified to the first value (such as 0) to construct the mask vector 312.

[0155] The first comparison unit 140 determines a second load instruction 304 in the reservation station table 110 according to the mask vector 312. The first storage area corresponding to the first load instruction 302 is different from the second storage area corresponding to the second load instruction 304; Exemplarily, the value of the element corresponding to the second load instruction 304 in the mask vector 312 is the second value (such as 1).

[0156] Exemplarily, the first comparison unit 140 uses the leading one detect (LOD) method to determine the first binary bit with a value of 1 in the binary number composed of each element of the mask vector 312, and determines the other load instruction corresponding to this binary bit as the second load instruction 304.

[0157] The masking unit 150 determines a masking vector 314 according to at least two candidate load instructions stored in the reservation station table 110. The masking vector 314 is used to distinguish the first load instruction 302 from other load instructions in the reservation station table 110;

[0158] In one example, each element in the mask vector 314 corresponds one-to-one with at least two candidate load instructions stored in the reservation station table 110, and the mask vector 314 is corrected based on the second description information stored in the reservation station table 110; similar to the introduction above, the second description information is used to indicate whether at least two candidate load instructions stored in the reservation station table 110 are valid.

[0159] Based on the second description information, the mask vector 314 is corrected. Specifically, the masking unit 150 corrects the k-th element of the second description information to a third value (for example, 0) to obtain the mask vector 314; the k-th candidate load instruction corresponding to the k-th element is the first load instruction 302.

[0160] The second comparison unit 160 determines a third load instruction 306 in the reservation station table 110 according to the mask vector 314, and the first load instruction 302 is different from the third load instruction 306; similar to the first comparison unit 140, the second comparison unit 160 can determine the third load instruction 306 in a leading-one manner.

[0161] The second load instruction 304 determined by the first comparison unit 140 and the third load instruction 306 determined by the second comparison unit 160 are both information input to the multiplexer 170. The multiplexer 170 is used to select one of the above two input information as the output load instruction 310 as the output information of the multiplexer 170.

[0162] Exemplarily, the address code port of the multiplexer 170 indicates the manner in which the multiplexer 170 selects one load instruction from two load instructions to be processed.

[0163] Specifically, the address code port of the path selector is connected to the discrimination unit 175, and the discrimination unit 175 determines the address code 308 according to the mask vector 312. The address code 308 is used to indicate whether the target storage areas corresponding to other load instructions are all the same as the first storage area corresponding to the first load instruction 302;

[0164] In one example, when all elements in the mask vector 312 are the first value, the discrimination unit 175 determines a first address code (for example, the value of the first address code is 0) to indicate that the target storage areas corresponding to other load instructions are all the same as the first storage area corresponding to the first load instruction 302. When all elements in the mask vector 312 are not the first value, the discrimination unit 175 determines a second address code (for example, the value of the second address code is 1) to indicate that the target storage areas corresponding to other load instructions are not all the same as the first storage area corresponding to the first load instruction 302.

[0165] The first address code is used to instruct the multiplexer 170 to determine the third load instruction 306 as the output load instruction 310; the second address code is used to instruct the multiplexer 170 to determine the second load instruction 304 as the output load instruction 310.

[0166] The first pipeline 210 accesses data in the data cache 250 according to the first load instruction 302;

[0167] The second pipeline 220 accesses data in the data cache 250 according to the output load instruction 310 provided by the multiplexer 170; the first pipeline 210 and the second pipeline 220 access data in parallel.

[0168] In summary, in the method provided in this embodiment, the mask vector indicates whether the first storage area corresponding to the first load instruction is the same as the target storage areas corresponding to other load instructions. The second pipeline accesses data in the data cache based on the second load instruction. Since the first storage area is different from the second storage area corresponding to the second load instruction, it is ensured that there will be no storage area conflicts; the problem that when load instructions are executed in parallel, due to storage area conflicts, only one load instruction can be selected for execution is avoided, and the processing efficiency of parallel execution of load instructions is improved.

[0169] Those of ordinary skill in the art can understand that the above embodiments can be implemented independently, or the above embodiments can be freely combined to form new embodiments to implement the data processing method of the present application.

[0170] In an embodiment of the present application, a chip is provided. The chip includes: a reservation station table, a selection unit, a mask unit, a first comparison unit, a first pipeline, and a second pipeline; the reservation station table, the selection unit, and the mask unit are connected to each other in pairs, the selection unit is connected to the first pipeline, the mask unit is connected to the first comparison unit, and the first comparison unit is connected to the second pipeline;

[0171] The selection unit is used to determine a first load instruction from the reservation station table, and the reservation station table is used to store at least two candidate load instructions to be executed, and the candidate load instructions are used to access data in the data cache;

[0172] The mask unit is used to determine a mask vector according to the first load instruction and other load instructions stored in the reservation station table. The mask vector is used to indicate whether the first storage area of the first load instruction in the data cache is the same as the target storage areas of the other load instructions in the data cache, and the other load instructions are instructions in the reservation station table other than the first load instruction;

[0173] The first comparison unit is configured to determine a second load instruction in the reservation station table according to the mask vector, where a first storage area corresponding to the first load instruction is different from a second storage area corresponding to the second load instruction;

[0174] The first pipeline is configured to access data in the data cache according to the first load instruction;

[0175] The second pipeline is configured to access data in the data cache according to the second load instruction, and the first pipeline and the second pipeline access data in parallel.

[0176] In an optional implementation manner of this embodiment, the mask unit includes an acquisition subunit and a processing subunit;

[0177] The acquisition subunit is configured to acquire a storage area corresponding to each candidate load instruction stored in the reservation station table, where the storage area includes a first storage area of the first load instruction in the data cache and a target storage area of other load instructions in the data cache;

[0178] The processing subunit is configured to determine a first value of the i-th element of the mask vector when a i-th storage area corresponding to the i-th other load instruction is the same as the first storage area;

[0179] And / or, determine a second value of the j-th element of the mask vector when a j-th storage area corresponding to the j-th other load instruction is different from the first storage area, where both i and j are positive integers and i is different from j.

[0180] In an optional implementation manner of this embodiment, the acquisition subunit is further configured to acquire first description information stored in the reservation station table, where the first description information is used to indicate whether the other load instructions stored in the reservation station table are valid;

[0181] The processing subunit is further configured to correct the i-th element of the first description information to a first value to obtain the mask vector when the i-th storage area corresponding to the i-th other load instruction is the same as the first storage area.

[0182] In an optional implementation manner of this embodiment, the acquisition subunit is further configured to acquire address information of each candidate load instruction stored in the reservation station table;

[0183] The processing subunit is further configured to determine a storage area corresponding to each candidate load instruction according to binary information recorded in an offset field in the address information.

[0184] In an alternative implementation of this embodiment, the chip further includes: a shielding unit, a second comparison unit, a discrimination unit, and a multiplexer; the reservation station table is connected to the shielding unit, the shielding unit is connected to the second comparison unit, the multiplexer is deployed between the first comparison unit and the second pipeline, the data output terminal of the multiplexer is connected to the second pipeline, the first data input terminal of the multiplexer is connected to the first comparison unit, the second data input terminal of the multiplexer is connected to the second comparison unit, the address code port of the multiplexer is connected to the discrimination unit, and the discrimination unit is connected to the mask unit;

[0185] The shielding unit is configured to determine a shielding vector according to the at least two candidate load instructions stored in the reservation station table, and the shielding vector is used to distinguish the first load instruction from the other load instructions in the reservation station table;

[0186] The second comparison unit is configured to determine a third load instruction in the reservation station table according to the shielding vector, and the first load instruction is different from the third load instruction;

[0187] The discrimination unit is configured to determine an address code according to the mask vector, and the address code is used to indicate whether the target storage areas corresponding to the other load instructions are all the same as the first storage area corresponding to the first load instruction;

[0188] The multiplexer is configured to determine the second load instruction as the output load instruction when the address code indicates that the target storage area is not the same as the first storage area;

[0189] The multiplexer is further configured to determine the third load instruction as the output load instruction when the address code indicates that the target storage areas are all the same as the first storage area;

[0190] The second pipeline is configured to access data in the data cache according to the output load instruction provided by the multiplexer.

[0191] In an alternative implementation of this embodiment, the shielding unit is further configured to obtain second description information stored in the reservation station table, and the second description information is used to indicate whether the at least two candidate load instructions in the reservation station table are valid;

[0192] The shielding unit is further configured to correct the k-th element of the second description information to a third value to obtain the shielding vector;

[0193] Wherein, the k-th candidate load instruction corresponding to the k-th element is the first load instruction.

[0194] In an alternative implementation of this embodiment, the shielding unit is further configured to obtain first attribute information corresponding to at least two candidate load instructions in the reservation station table, where the first attribute information carries at least one of the following: the storage time of the candidate load instruction in the reservation station table, the type information of the candidate load instruction, and the application program to which the candidate load instruction belongs;

[0195] The shielding unit is further configured to perform at least one of the following:

[0196] In a case where the difference between the storage time of the x-th candidate load instruction and the storage time of the first load instruction is greater than a preset time difference, correcting the x-th element of the second description information to the third value;

[0197] In a case where the type of the y-th candidate load instruction is the same as the type of the first load instruction, correcting the y-th element of the second description information to the third value;

[0198] In a case where the application program to which the z-th candidate load instruction belongs is the same as the application program to which the first load instruction belongs, correcting the z-th element of the second description information to the third value;

[0199] Where x, y, and z are all positive integers.

[0200] In an alternative implementation of this embodiment, the selection unit is further configured to:

[0201] Based on the storage times of the at least two candidate load instructions, determine a first load instruction from the reservation station table, where the storage time is used to indicate the time when the reservation station table stores the corresponding candidate load instruction, and the storage time of the first load instruction is earlier than the storage times of the other load instructions.

[0202] In an alternative implementation of this embodiment, the selection unit is further configured to:

[0203] Obtain second attribute information corresponding to at least two candidate load instructions one by one in the reservation station table, where the second attribute information carries the storage time of the corresponding candidate load instruction in the reservation station table.

[0204] It should be noted that when the chip provided in the above embodiment implements its functions, only the division of the above-mentioned various devices is used for illustration. In actual applications, the above functions can be allocated to different functional devices according to actual needs, that is, the internal structure of the device is divided into different functional devices to complete all or part of the functions described above.

[0205] Regarding the chip in the above embodiments, the specific manner in which each device performs operations has been described in detail in the embodiments of the related data processing method; the technical effects achieved by each device performing operations are the same as those in the embodiments of the related data processing method, and will not be elaborated here.

[0206] An embodiment of the present application further provides a computer device, which includes the chip described in the above aspect. Exemplarily, the computer device in this embodiment includes: a processor and a memory, and a computer program is stored in the memory; the processor is the chip described in the above aspect.

[0207] In one example, the processor may include one or more processing cores, such as a 4-core processor, an 8-core processor, etc. The processor may be implemented in at least one hardware form of digital signal processing (DSP), field-programmable gate array (FPGA), and programmable logic array (PLA). The processor may also include a main processor and a coprocessor. The main processor is a processor for processing data in the wake state, also known as the central processing unit (CPU); the coprocessor is a low-power processor for processing data in the standby state. In some embodiments, the processor may be integrated with a graphics processing unit (GPU), and the GPU is responsible for rendering and drawing the content to be displayed on the display screen. In some embodiments, the processor may further include an artificial intelligence (AI) processor, and the AI processor is used to process computational operations related to machine learning.

[0208] The memory may include one or more computer-readable storage media, and the computer-readable storage media may be non-transitory. The memory may also include high-speed random access memory and non-volatile memory, such as one or more disk storage devices and flash storage devices. In some embodiments, the non-transitory computer-readable storage medium in the memory is used to store at least one instruction.

[0209] Furthermore, the computer device may be a terminal or a server.

[0210] Taking a computer device as a server as an example, the server includes a processor and a memory. In some embodiments, the server may also optionally include: an input interface and an output interface. The processor, the memory, the input interface, and the output interface can be connected through a bus or a signal line. Each peripheral device can be connected to the input interface and the output interface through a bus, a signal line, or a circuit board. The input interface and the output interface can be used to connect at least one peripheral device related to input / output (I / O) to the processor and the memory. In some embodiments, the processor, the memory, the input interface, and the output interface are integrated on the same chip or circuit board; in some other embodiments, any one or two of the processor, the memory, the input interface, and the output interface can be implemented on a separate chip or circuit board, and the embodiments of the present application do not limit this.

[0211] Taking a computer device as a terminal as an example, the terminal includes a processor and a memory. In some embodiments, the terminal may also optionally include: a peripheral device interface and at least one peripheral device. The processor, the memory, and the peripheral device interface can be connected through a bus or a signal line. Each peripheral device can be connected to the peripheral device interface through a bus, a signal line, or a circuit board. Specifically, the peripheral device includes at least one of: a radio frequency circuit, a touch display screen, a camera assembly, an audio circuit, and a power supply.

[0212] Those skilled in the art can understand that the structures shown above do not constitute a limitation on the computer device, and it may include more or fewer components than those shown in the figure, or combine certain components, or adopt different component arrangements.

[0213] Those of ordinary skill in the art can understand that all or part of the steps for implementing the above embodiments can be completed by hardware, or can be completed by a program instructing related hardware. The program can be stored in a computer-readable storage medium, and the storage medium mentioned above can be a read-only memory, a disk, or an optical disc, etc.

[0214] Those skilled in the art should be able to realize that in one or more of the above examples, the functions described in the embodiments of the present application can be implemented by hardware, software, firmware, or any combination thereof. When implemented using software, these functions can be stored in a computer-readable medium or transmitted as one or more instructions or codes on a computer-readable medium. The computer-readable medium includes a computer storage medium and a communication medium, where the communication medium includes any medium that facilitates the transmission of a computer program from one place to another. The storage medium can be any available medium that can be accessed by a general-purpose or special-purpose computer.

[0215] The above are only alternative embodiments of the present application and are not intended to limit the present application. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present application shall be included within the protection scope of the present application.

Claims

1. A chip, characterized in that, The chip includes: a reservation station table, a selection unit, a masking unit, a first comparison unit, a first pipeline, and a second pipeline; the reservation station table, the selection unit, and the masking unit are pairwise connected, the selection unit is connected to the first pipeline, the masking unit is connected to the first comparison unit, and the first comparison unit is connected to the second pipeline; The selection unit is configured to determine a first load instruction from the reservation station table, the reservation station table is used to store at least two candidate load instructions to be executed, and the candidate load instructions are used to access data in a data cache; The masking unit is configured to determine a mask vector according to the first load instruction and other load instructions stored in the reservation station table, the mask vector is used to indicate whether a first storage area of the first load instruction in the data cache is the same as a target storage area of the other load instructions in the data cache, and the other load instructions are instructions in the reservation station table other than the first load instruction; The first comparison unit is configured to determine a second load instruction in the reservation station table according to the mask vector, and the first storage area corresponding to the first load instruction is different from the second storage area corresponding to the second load instruction; The first pipeline is configured to access data in the data cache according to the first load instruction; The second pipeline is configured to access data in the data cache according to the second load instruction, and the first pipeline and the second pipeline access data in parallel.

2. The chip according to claim 1, characterized in that, The masking unit includes an acquisition subunit and a processing subunit; The acquisition subunit is configured to acquire a storage area corresponding to each candidate load instruction stored in the reservation station table, and the storage area includes a first storage area of the first load instruction in the data cache and a target storage area of the other load instructions in the data cache; The processing subunit is configured to, when a first storage area corresponding to the i-th other load instruction is the same as the first storage area, determine the i-th element of the mask vector as a first value; and / or, when a first storage area corresponding to the j-th other load instruction is different from the first storage area, determine the j-th element of the mask vector as a second value, where both i and j are positive integers and i is different from j.

3. The chip according to claim 2, wherein the acquisition subunit is further configured to acquire first description information stored in the reservation station table, and the first description information is used to indicate whether the other load instructions stored in the reservation station table are valid; the processing subunit is further configured to, when a first storage area corresponding to the i-th other load instruction is the same as the first storage area, correct the i-th element of the first description information to a first value to obtain the mask vector.

4. The chip according to claim 2, wherein the acquisition subunit is further configured to acquire address information of each candidate load instruction stored in the reservation station table; The processing sub-unit is further configured to determine a storage area corresponding to each candidate load instruction according to the binary information recorded in the offset field in the address information.

5. The chip according to any one of claims 1 to 4, characterized in that The chip further includes: a masking unit, a second comparison unit, a discrimination unit, and a multiplexer; the reservation station table is connected to the masking unit, the masking unit is connected to the second comparison unit, the multiplexer is deployed between the first comparison unit and the second pipeline, a data output terminal of the multiplexer is connected to the second pipeline, a first data input terminal of the multiplexer is connected to the first comparison unit, a second data input terminal of the multiplexer is connected to the second comparison unit, an address code port of the multiplexer is connected to the discrimination unit, and the discrimination unit is connected to the mask unit; The masking unit is configured to determine a masking vector according to the at least two candidate load instructions stored in the reservation station table, and the masking vector is used to distinguish the first load instruction from the other load instructions in the reservation station table; The second comparison unit is configured to determine a third load instruction in the reservation station table according to the masking vector, and the first load instruction is different from the third load instruction; The discrimination unit is configured to determine an address code according to the mask vector, and the address code is used to indicate whether the target storage areas corresponding to the other load instructions are all the same as the first storage area corresponding to the first load instruction; The multiplexer is configured to determine the second load instruction as the output load instruction when the address code indicates that the target storage areas are not all the same as the first storage area; The multiplexer is further configured to determine the third load instruction as the output load instruction when the address code indicates that the target storage areas are all the same as the first storage area; The second pipeline is configured to access data in the data cache according to the output load instruction provided by the multiplexer.

6. The chip according to claim 5, wherein The masking unit is further configured to obtain second description information stored in the reservation station table, and the second description information is used to indicate whether the at least two candidate load instructions in the reservation station table are valid; The masking unit is further configured to modify the k-th element of the second description information to a third value to obtain the masking vector; Wherein, the k-th candidate load instruction corresponding to the k-th element is the first load instruction.

7. The chip according to claim 6, wherein The masking unit is further configured to obtain first attribute information corresponding to at least two candidate load instructions in the reservation station table, and the first attribute information carries at least one of the following: the storage time of the candidate load instruction in the reservation station table, the type information of the candidate load instruction, the application program to which the candidate load instruction belongs; The masking unit is further configured to perform at least one of the following: In the case where the difference between the storage time of the x-th candidate load instruction and the storage time of the first load instruction is greater than a preset time difference, correct the x-th element of the second description information to the third value; In the case where the type of the y-th candidate load instruction is the same as the type of the first load instruction, correct the y-th element of the second description information to the third value; In the case where the application program to which the z-th candidate load instruction belongs is the same as the application program to which the first load instruction belongs, correct the z-th element of the second description information to the third value; Where x, y, and z are all positive integers.

8. The chip according to any one of claims 1 to 4, characterized in that, The selection unit is further configured to: Based on the storage times of the at least two candidate load instructions, determine a first load instruction from the reservation station table, where the storage time is used to indicate the time when the reservation station table stores the corresponding candidate load instruction, and the storage time of the first load instruction is earlier than the storage times of the other load instructions.

9. The chip according to claim 8, characterized in that, The selection unit is further configured to: Obtain the second attribute information corresponding to at least two candidate load instructions in the reservation station table, where the second attribute information carries the storage time of the corresponding candidate load instruction in the reservation station table.

10. A computer device, characterized in that, The computer device includes a chip as described in any one of claims 1 to 9.

11. A data processing method, characterized in that, The method is applied to a chip, and the chip includes: a reservation station table, a selection unit, a mask unit, a first comparison unit, a first pipeline, and a second pipeline; the reservation station table, the selection unit, and the mask unit are connected to each other in pairs, the selection unit is connected to the first pipeline, the mask unit is connected to the first comparison unit, and the first comparison unit is connected to the second pipeline; the method includes: The selection unit determines a first load instruction from the reservation station table, where the reservation station table is used to store at least two candidate load instructions to be executed, and the candidate load instructions are used to access data in the data cache; The mask unit determines a mask vector according to the first load instruction and other load instructions stored in the reservation station table, where the mask vector is used to indicate whether the first storage area of the first load instruction in the data cache is the same as the target storage area of the other load instructions in the data cache, and the other load instructions are the instructions in the reservation station table except the first load instruction; The first comparison unit determines a second load instruction in the reservation station table according to the mask vector, where the first storage area corresponding to the first load instruction is different from the second storage area corresponding to the second load instruction; The first pipeline accesses data in the data cache according to the first load instruction; The second pipeline accesses data in the data cache according to the second load instruction, and the first pipeline and the second pipeline access data in parallel.

12. The method according to claim 11, wherein The mask unit in the chip includes an acquisition subunit and a processing subunit; The mask unit determines a mask vector according to the first load instruction and other load instructions stored in the reservation station table, including: The obtaining subunit obtains a storage area corresponding to each candidate load instruction stored in the reservation station table, where the storage area includes a first storage area of the first load instruction in the data cache and target storage areas of other load instructions in the data cache; When the i-th storage area corresponding to the i-th other load instruction is the same as the first storage area, the processing subunit determines the i-th element of the mask vector as a first value; and / or when the j-th storage area corresponding to the j-th other load instruction is different from the first storage area, the processing subunit determines the j-th element of the mask vector as a second value, where both i and j are positive integers and i is different from j.

13. The method according to claim 12, wherein The method further includes: The obtaining subunit obtains first description information stored in the reservation station table, where the first description information is used to indicate whether other load instructions stored in the reservation station table are valid; When the i-th storage area corresponding to the i-th other load instruction is the same as the first storage area, the processing subunit determines the i-th element of the mask vector as a first value, including: When the i-th storage area corresponding to the i-th other load instruction is the same as the first storage area, the processing subunit corrects the i-th element of the first description information to the first value to obtain the mask vector.

14. The method according to claim 12, wherein The obtaining subunit obtains a storage area corresponding to each candidate load instruction stored in the reservation station table, including: The obtaining subunit obtains address information of each candidate load instruction stored in the reservation station table; The processing subunit determines a storage area corresponding to each candidate load instruction according to binary information recorded in an offset field in the address information.

15. The method according to any one of claims 11 to 14, characterized in that, The chip further includes: a shielding unit, a second comparison unit, a discrimination unit, and a multiplexer; the reservation station table is connected to the shielding unit, the shielding unit is connected to the second comparison unit, the multiplexer is deployed between the first comparison unit and the second pipeline, a data output end of the multiplexer is connected to the second pipeline, a first data input end of the multiplexer is connected to the first comparison unit, a second data input end of the multiplexer is connected to the second comparison unit, an address code port of the multiplexer is connected to the discrimination unit, and the discrimination unit is connected to the mask unit; The method further includes: The shielding unit determines a shielding vector according to at least two candidate load instructions stored in the reservation station table, where the shielding vector is used to distinguish the first load instruction from the other load instructions in the reservation station table; The second comparison unit determines a third load instruction in the reservation station table according to the shielding vector, where the first load instruction is different from the third load instruction; The discrimination unit determines an address code according to the mask vector, where the address code is used to indicate whether target storage areas corresponding to the other load instructions are all the same as the first storage area corresponding to the first load instruction; When the multiplexer determines that the target storage area indicated by the address code is not the same as the first storage area, the multiplexer determines the second load instruction as the output load instruction; When the multiplexer determines that the target storage area indicated by the address code is the same as the first storage area, the multiplexer determines the third load instruction as the output load instruction; The second pipeline accesses data in the data cache according to the second load instruction, including: The second pipeline accesses data in the data cache according to the output load instruction provided by the multiplexer.

16. The method according to claim 15, wherein The masking unit determines a masking vector according to the at least two candidate load instructions stored in the reservation station table, including: The masking unit obtains second description information stored in the reservation station table, where the second description information is used to indicate whether the at least two candidate load instructions in the reservation station table are valid; The masking unit corrects the k-th element of the second description information to a third value to obtain the masking vector; Wherein, the k-th candidate load instruction corresponding to the k-th element is the first load instruction.

17. The method according to claim 16, characterized in that, The method further includes: The masking unit obtains first attribute information corresponding to at least two candidate load instructions in the reservation station table, where the first attribute information carries at least one of the following: the storage time of the candidate load instruction in the reservation station table, the type information of the candidate load instruction, and the application program to which the candidate load instruction belongs; When the difference between the storage time of the x-th candidate load instruction and the storage time of the first load instruction is greater than a preset time difference, the masking unit corrects the x-th element of the second description information to the third value; And / or, when the type of the y-th candidate load instruction is the same as the type of the first load instruction, the masking unit corrects the y-th element of the second description information to the third value; And / or, when the application program to which the z-th candidate load instruction belongs is the same as the application program to which the first load instruction belongs, the masking unit corrects the z-th element of the second description information to the third value; Wherein, x, y, and z are all positive integers.

18. The method according to any one of claims 11 to 14, characterized in that The selection unit determines the first load instruction from the reservation station table, including: The selection unit determines the first load instruction from the reservation station table based on the storage times of the at least two candidate load instructions, where the storage time is used to indicate the time when the reservation station table stores the corresponding candidate load instruction, and the storage time of the first load instruction is earlier than the storage times of the other load instructions.

19. The method according to claim 18, wherein The method further includes: The selection unit obtains second attribute information corresponding to at least two candidate load instructions in the reservation station table, where the second attribute information carries the storage time of the corresponding candidate load instruction in the reservation station table.

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