Performance test method and device for extended memory, electronic equipment and storage medium

Abstract

The invention discloses a performance test method and device for an extended memory, electronic equipment and a storage medium, and relates to the technical field of memory extension, which comprises the following steps: providing a configuration mode of adding a heterogeneous single-channel local memory and a variable-capacity and flat dual-channel local memory in an interactive interface to form a comprehensive test system, covering more application scenes, and improving the performance of the extended memory. And the extended memory performance can be accurately measured. By determining the target node corresponding to the target configuration mode, the test object is accurately positioned, and the test accuracy and pertinence are improved. And carrying out bandwidth testing on the target node to obtain quantitative performance data, setting exclusive performance evaluation indexes for different configuration modes, and establishing a reliable evaluation standard. According to the method, a comprehensive configuration mode is provided, test nodes are defined, objective data are obtained, and evaluation standards are established, so that the problem that the industry lacks comprehensive and reliable extended memory performance test methods and evaluation standards is effectively solved.

Description

Technical Field

[0001] This application relates to the technical field of memory expansion, and particularly to a performance testing method, device, electronic device, and storage medium for expanding memory. Background Art

[0002] With the explosive growth of data volume and the continuous climbing of high-performance computing requirements in large computer systems and data centers, the importance of memory expansion technology has become increasingly prominent. Compute Express Link (CXL) memory, as an open-standard-based memory expansion technology, provides a large memory pool for multiple processors in large computer systems and data centers through a cache coherence protocol, becoming a key way to improve computing performance.

[0003] Due to the complexity of CXL memory usage, it is extremely difficult to perform performance testing and evaluation on it. Currently, CXL memory includes three configuration modes: Heterogeneous mode (Heter), Single-channel local memory plus variable capacity mode (1LM+Vol), and Flat dual-channel local memory mode (Flat2LM), and the performance characteristics under different modes vary significantly. However, there is currently a lack of a comprehensive and reliable CXL memory performance testing method and evaluation standard in the industry. This makes it impossible to accurately and objectively measure the performance of CXL memory under different configuration modes, difficult to effectively guide the optimization design of CXL memory and its reasonable configuration in practical applications, hinders the CXL memory technology from further exerting its advantages, and limits the performance improvement of related computer systems and data centers. Summary of the Invention

[0004] This application provides a performance testing method, device, electronic device, and storage medium for expanding memory, so as to at least solve the problem of the lack of a comprehensive and reliable CXL memory performance testing method and evaluation standard in the related art.

[0005] This application provides a performance testing method for expanding memory, including: in response to an input for setting an extended memory configuration mode in the basic input / output system interface, determining a target configuration mode of the extended memory, where the target configuration mode is any one of a heterogeneous mode, a single-channel local memory plus variable capacity mode, and a flat dual-channel local memory mode; determining a target node corresponding to the target configuration mode, where the target node is the node where the extended memory is distributed; performing a bandwidth test on the target node to obtain a bandwidth test result; and evaluating the bandwidth test result according to a performance evaluation index corresponding to the target configuration mode.

[0006] This application also provides a performance testing device for expanding memory, including:

[0007] An interaction module, configured to determine a target configuration mode of the extended memory in response to an input for setting the extended memory configuration mode by a user in the basic input / output system interface, where the target configuration mode is any one of a heterogeneous mode, a single-channel local memory plus variable-capacity mode, and a flat dual-channel local memory mode;

[0008] A target node determination module, configured to determine a target node corresponding to the target configuration mode, where the target node is a node where the extended memory is distributed;

[0009] A bandwidth test module, configured to perform a bandwidth test on the target node to obtain a bandwidth test result;

[0010] An evaluation module, configured to evaluate the bandwidth test result according to a performance evaluation index corresponding to the target configuration mode.

[0011] This application further provides an electronic device, including: a memory, configured to store a computer program; a processor, configured to implement the steps of any one of the above-mentioned extended memory performance test methods when executing the computer program.

[0012] This application further provides a computer-readable storage medium, where a computer program is stored in the computer-readable storage medium, and where the computer program implements the steps of any one of the above-mentioned extended memory performance test methods when executed by a processor.

[0013] This application further provides a computer program product, including a computer program, where the computer program implements the steps of any one of the above-mentioned extended memory performance test methods when executed by a processor.

[0014] Through this application, a user can set an extended memory configuration mode in an interaction interface. The heterogeneous mode, the single-channel local memory plus variable-capacity mode, and the flat dual-channel local memory mode cover different possible configuration modes of CXL memory, forming a comprehensive test system. Compared with the previous situation lacking a comprehensive test method, it can enable the test to cover more scenarios, thereby more accurately and objectively measuring the performance of CXL memory under different configuration modes. By determining the target node corresponding to the target configuration mode, the specific memory node to be subjected to the performance test can be accurately located, making the test more targeted and accurate, and avoiding errors caused by blind testing. By performing a bandwidth test on the target node under different configuration modes, quantitative data on the performance of CXL memory can be obtained, and performance evaluation indexes are set for different configuration modes to establish a reliable evaluation standard, which can more reasonably evaluate the performance of CXL memory. In this way, by providing comprehensive configuration modes, clarifying the test object, obtaining objective test data, and establishing an evaluation standard, the problem that there is a lack of a comprehensive and reliable CXL memory performance test method and evaluation standard in the current industry is effectively solved. Description of the Drawings

[0015] To more clearly illustrate the embodiments of the present application, the following will briefly introduce the drawings required in the embodiments. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0016] Figure 1 It is a schematic flowchart of a method for testing the performance of extended memory provided by an embodiment of the present application;

[0017] Figure 2 It is a schematic diagram of the memory access mode provided by an embodiment of the present application;

[0018] Figure 3 It is a schematic structural diagram of a device for testing the performance of extended memory provided by an embodiment of the present application;

[0019] Figure 4 It is a schematic structural diagram of an electronic device provided by an embodiment of the present application. Detailed implementation manners

[0020] The following will clearly and completely describe the technical solutions in the embodiments of the present application in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only some embodiments of the present application, rather than all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the protection scope of the present application.

[0021] It should be noted that in the description of the present application, the terms "include", "comprise" or any other variant thereof are intended to cover a non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements but also includes other elements not explicitly listed, or further includes elements inherent to such process, method, article or device. The terms "first", "second", etc. in the present application are used to distinguish similar objects and not to describe a specific order or sequence.

[0022] To more clearly illustrate the embodiments of the present application, the following will briefly introduce the technical terms required in the embodiments:

[0023] Compute Express Link (CXL) is a high-speed interconnect protocol used to connect different computing components, such as Central Processing Unit (CPU), Graphics Processing Unit (GPU), Field Programmable Gate Array (FPGA), etc., to achieve efficient data transfer and sharing, and improve the overall performance and scalability of the system. CXL can also enable memory expansion and memory sharing.

[0024] CXL memory is an open-standard based memory expansion technology designed to make large memory pools available to multiple processors in large computer systems and data centers through a cache coherence protocol. The main goal of CXL memory is to help data center architects avoid over-provisioning each CPU in a multi-processor system or large data center servers with DRAM. With CXL, the CPU can communicate with peripheral devices and their attached memories in a load / store semantic manner, thus greatly expanding the amount of memory accessible by the CPU.

[0025] On the server platform, there are three configuration modes for CXL memory: Heterogeneous mode (Heter), Single-channel Local Memory plus Variable Capacity mode (1LM+Vol), and Flat Dual-channel Local Memory mode (Flat2LM).

[0026] In Heter mode, the CXL memory in the server platform coexists and works collaboratively with traditional memory (such as DDR memory) in a heterogeneous manner. CXL memory can be used for specific high-performance demand scenarios, such as accelerating specific workloads or providing dedicated memory resources for certain applications with high requirements for memory bandwidth and latency, while traditional memory is used for regular memory needs. Through this heterogeneous configuration, memory resources can be flexibly allocated according to the characteristics of different applications to achieve overall performance optimization.

[0027] In the 1LM+Vol mode, "1LM" means using single-channel local memory, that is, part of the memory channels in the server are configured as local memory for regular memory access. "Vol" represents variable-capacity CXL memory, and the capacity of this part of CXL memory can be dynamically adjusted according to the system's needs. For example, when the system needs to process large-scale data or run applications with high memory capacity requirements, the usage capacity of CXL memory can be increased; while when the load is low, the occupancy of CXL memory can be appropriately reduced to improve resource utilization. This mode combines the stability of local memory and the flexibility of CXL memory, and can better adapt to the dynamic memory requirements of different workloads.

[0028] In the Flat 2LM mode, the server platform emulates the CXL memory into an architecture similar to that of traditional dual-channel local memory, presenting a flat memory space to the system. That is, all memories (including CXL memory and a small amount of traditional memory that may exist) are logically regarded as a unified and continuous memory area, and the system can access it in the same way as accessing ordinary dual-channel local memory. The advantage of this mode is that it simplifies the memory management and access methods, enabling the operating system and application programs to handle memory in a unified way without special processing or optimization for CXL memory, improving the system's compatibility and usability. At the same time, through the dual-channel architecture design, the memory access bandwidth and performance can be improved to a certain extent to meet the memory performance requirements of the server platform.

[0029] The CPU is the core component of a computer system, responsible for executing instructions in computer programs, performing arithmetic and logical operations, and controlling the coordinated operation of various components of the computer. It is like the "brain" of the computer, playing a key control and coordination role in the operation of the entire system.

[0030] The GPU is a processor specifically designed for processing graphics data, capable of efficiently performing tasks such as graphics rendering, image processing, and parallel computing. It is commonly used in the graphics card of a computer, mainly responsible for converting the image data generated by the computer into a signal that can be displayed by the monitor, enabling users to see various graphics, images, and video content. In addition, in some fields that require a large amount of parallel computing, such as deep learning and scientific computing, the GPU is also widely used for accelerating calculations.

[0031] The FPGA is a reconfigurable integrated circuit chip that contains a large number of logic units and programmable interconnection resources. Users can configure it through programming to implement various different digital circuit functions, such as implementing specific algorithms, interface circuits, or customized logic controllers, etc. It has the advantages of high flexibility and short development cycle, and has a wide range of applications in multiple fields such as communication, industrial control, and aerospace.

[0032] Dynamic Random Access Memory (DRAM) is a common type of computer memory. It stores data through capacitors, but the charge in the capacitors will leak over time, so it needs to be refreshed regularly to maintain the correctness of the data. Its characteristics are low cost and large capacity, and it is commonly used in the main memory of a computer to temporarily store running programs and data.

[0033] Double Data Rate Synchronous Dynamic Random Access Memory (DDR) is a high-speed dynamic random access memory that transmits data on both the rising and falling edges of the clock signal, doubling the data transfer speed compared to traditional single data rate memory. DDR memory is widely used in computers and other electronic devices to increase system data transmission bandwidth and response speed to meet the rapid data access requirements of high-speed processors and other components. Common DDR memory generations include DDR3, DDR4, and DDR5, with each generation offering improvements and enhancements in performance and power consumption.

[0034] The Basic Input Output System (BIOS) is a type of firmware embedded in the computer's motherboard. Its primary function is to perform hardware initialization during the computer's power-on startup phase, such as checking whether the CPU, memory, hard drive, graphics card, and other hardware are functioning properly and initializing their settings. The BIOS is also responsible for loading the boot program from storage devices (such as hard drives, optical disks, etc.), which then loads the operating system. While the operating system is running, the BIOS also provides hardware abstraction for the operating system through the system management mode. For example, it provides the operating system with a hardware abstraction layer for the keyboard, display, and other I / O devices, allowing the operating system to easily interact with the hardware.

[0035] In order to enable those skilled in the art to better understand the present application, the present application is further described in detail below with reference to the accompanying drawings and specific implementation methods.

[0036] As mentioned above, in Hetero mode, DDR and CXL memory are interleaved, resulting in strict capacity and speed limitations. CXL memory has the same capacity and frequency as DDR, significantly limiting its performance. Flat2LM mode, while a layered mode, also has capacity limitations, requiring a 1:1 capacity ratio between DDR and CXL. This places stringent demands on memory configuration in practical applications. These complex configurations restrict CXL memory performance to multiple factors, severely impacting its adoption and adoption in diverse application scenarios. Currently, CXL memory performance testing requires separate testing for each configuration, and performance characteristics vary significantly across different modes. However, the industry lacks a comprehensive and reliable CXL memory performance testing methodology and evaluation standards. This makes it difficult to accurately and objectively measure CXL memory performance in different configurations, hindering effective guidance for optimized CXL memory design and proper deployment in practical applications. This hinders the further development of CXL memory technology and limits the performance improvements of related computer systems and data centers.

[0037] To solve some or all of the above technical problems, in combination with the specific application environment architecture or specific hardware architecture on which the execution of the performance testing method for extended memory depends, the specific application environment architecture or specific hardware architecture is described herein.

[0038] The hardware architecture includes a processor, a memory system, and a motherboard.

[0039] Among them, the processor needs to support the CXL protocol, be able to achieve high-speed interconnection with the CXL memory, and ensure the efficiency and stability of data transmission.

[0040] The memory system includes dual-channel local memory (DDR memory) and CXL memory. The DDR memory provides low-latency data access, while the CXL memory realizes large-capacity memory expansion. At the same time, parameters such as the number of memory channels and operating frequency need to meet the test requirements to ensure the full display of memory performance under different configuration modes.

[0041] The motherboard needs to have a CXL interface and corresponding circuit design, support the connection between the processor and the CXL memory and DDR memory, and be able to identify and manage different memory configuration modes. In addition, the motherboard also needs to provide necessary BIOS firmware support so that users can set the extended memory configuration mode in the BIOS interface.

[0042] The software architecture includes a BIOS system, an operating system, and test tools.

[0043] BIOS system: Provides a basic input / output system interface, supports users to set the extended memory configuration mode, completes the selection from options such as heterogeneous mode, single-channel local memory plus variable-capacity mode, and flat dual-channel local memory mode, and realizes the initialization and management of memory configuration.

[0044] Operating system: Needs to have the ability to identify and manage the CXL memory, be able to cooperate with the hardware to achieve unified memory addressing and access control, and at the same time support the operation of test tools such as MLC for memory bandwidth testing.

[0045] Test tools: Such as preset bandwidth test tools and performance evaluation tools, which can accurately perform bandwidth tests on target nodes under different configuration modes and analyze and evaluate the test results according to corresponding performance evaluation indicators.

[0046] The embodiments of the present application provide a performance testing method for extended memory. In combination with the execution process of the performance testing method for extended memory, the method is described in detail.

[0047] S101. In response to the input of the user setting the extended memory configuration mode in the basic input / output system interface, determine the target configuration mode of the extended memory.

[0048] Among them, the extended memory is CXL memory. The configuration mode of the extended memory can be any one of a heterogeneous mode (Heter), a single-channel local memory plus variable capacity mode (1LM+Vol), and a flat dual-channel local memory mode (Flat2LM).

[0049] Exemplarily, assuming that the user modifies the configuration mode of the extended memory (CXL memory) to the 1LM+Vol mode in the BIOS interface, it can be determined that the target configuration mode of the CXL memory is the 1LM+Vol mode.

[0050] The above steps support the user to modify the CXL memory configuration mode option in the BIOS interface to set the CXL memory configuration mode, and can flexibly adjust the allocation of memory resources according to business requirements to give full play to the advantages of the CXL memory. Integrating the setting of the CXL memory configuration mode into the BIOS interface allows the user to easily configure according to their own needs without using complex command-line tools or third-party software. This lowers the operation threshold for the user, enabling ordinary users to conveniently manage and optimize the CXL memory, improving the usability of the system. Setting the CXL memory configuration mode in the BIOS interface also helps to better achieve compatibility in systems with different architectures.

[0051] S102. Determine the target node corresponding to the target configuration mode.

[0052] Among them, the target node is the node where the extended memory is distributed. It can be the first node where the CXL memory is distributed alone, or the second node where the CXL memory and the dual-channel local (DDR) memory are distributed together. Different target configuration modes correspond to different target nodes.

[0053] In some embodiments, when the target configuration mode is the single-channel local memory plus variable capacity mode, determine the first node where the extended memory is distributed. The first node includes a local node and a remote node.

[0054] Exemplarily, in the 1LM+Vol mode, use the numactl–H command to access the node (node) where the CXL memory is distributed. It should be noted that in the numactl–H command, numactl is a command for controlling the non-uniform memory access (NUMA) technology mechanism of processes and shared storage, and –H (equivalent to --hardware) is an option of this command. Execute the numactl–H command to display the total physical memory owned by each node and the current remaining free memory.

[0055] Such as Figure 2As shown, the memory access methods include local access and remote access. Local access means that the CPU accesses the local node directly associated with it. For example, the access of CPU0 to node3 and CPU1 to node4 belongs to local access. Remote access means that the CPU can access the node associated with another CPU across nodes. For example, the access of CPU0 to node4 and CPU1 to node3 belongs to remote access. Figure 2 In Figure 2 , both CPU0 and CPU1 correspond to a node. CPU0 corresponds to node3 (labeled as the node mounted under CPU0), and CPU1 corresponds to node4 (labeled as the node mounted under CPU1).

[0056] In some embodiments, in the case where the target configuration mode is Hetero mode or Flat2LM mode, determine the second node corresponding to the extended memory and the dual-channel local memory.

[0057] Specifically, in Hetero mode or Flat2LM mode, use the numactl–H command to access the second node where the CXL memory and DDR memory are distributed as the target node.

[0058] Exemplarily, use the numactl–H command to determine the second node where the CXL memory and DDR memory are distributed together, such as node0 and node1.

[0059] The above steps view the corresponding node where the CXL memory is distributed in the target configuration mode, providing basic information for subsequent bandwidth testing. Using the numactl–H command to access the node where the CXL memory is distributed enables users to grasp the overall memory architecture of the system, intuitively understand the location relationship between the CXL memory and other conventional memories in the system, and how they are distributed on different nodes.

[0060] In some embodiments, in the case where the target configuration mode is Hetero mode or Flat2LM mode, after determining the second node corresponding to the extended memory and the dual-channel local memory, first set the memory parameters of the extended memory and the dual-channel local memory. The memory parameters include memory capacity, operating frequency, quantity / number of channels, etc. The setting of the memory parameters is related to the number of CPUs.

[0061] Exemplarily, as shown in Table 1, in Hetero mode, when the number of CPUs in the server platform is 1, set 4 CXL memories and 8-channel DDR; when the number of CPUs in the server platform is 2, set 8 CXL memories and 16-channel DDR. The server platform is, for example, the Birch stream platform.

[0062] Table 1

[0063] Server platform Memory configuration Single-CPU platform 8-channel DDR + 4 CXLs Dual-CPU platform 16-channel DDR + 8 CXLs

[0064] In the above Hetero mode, the memory capacities and frequencies of CXL memory and DDR are set to be the same, and the memory capacities of CXL memory and DDR are also set in a coordinated manner. This enables data to be evenly distributed and transferred between the two types of memory, avoiding data transfer bottlenecks caused by bandwidth differences. The coordinated setting of memory capacities allows data to be distributed across different memories according to access popularity, optimizing the bandwidth of the memory subsystem and enabling the system to handle multitasks and large-scale data processing more efficiently, thereby enhancing the overall system performance. By reasonably setting the memory capacities and their coordination methods, waste of memory resources can be avoided.

[0065] Exemplarily, in the Flat2LM mode, the total capacity of CXL memory is set to be the same as that of DDR. When the total capacities of CXL memory and DDR are the same, the hardware-assisted hierarchical management can function more effectively, thus achieving reasonable allocation and efficient utilization of memory resources, reducing the burden on the operating system's memory management, and improving the efficiency and accuracy of memory management. The same total capacity setting avoids performance bottlenecks caused by either type of memory having an overly large or small capacity, thereby enhancing the overall system performance and response speed.

[0066] S103. Perform a bandwidth test on the target node to obtain the bandwidth test result.

[0067] In some embodiments, in the 1LM+Vol mode, the bandwidth between the CPU and the first node is tested, including: testing the bandwidth between the CPU and the local node; testing the bandwidth between the CPU and the remote node.

[0068] The bandwidth test results include: full read bandwidth, three reads and one write bandwidth (3R1W), two reads and one write bandwidth (2R1W), one read and one write bandwidth (1R1W), and full write bandwidth.

[0069] Among them, the full-read bandwidth refers to the maximum rate at which the CPU continuously reads data from the CXL memory within a unit of time, usually measured in GB / s (gigabytes per second). 3R1W represents the average data transfer rate when, in a specific test scenario, for every 4 memory access operations, there are 3 read operations and 1 write operation. 2R1W is the average data transfer rate when there are 2 read operations and 1 write operation in every 3 memory accesses. 1R1W refers to the data transfer rate when read and write operations alternate in each memory access operation. The full-write bandwidth is the maximum rate at which the CPU continuously writes data to the CXL memory within a unit of time.

[0070] The full-read bandwidth test can clarify the speed at which data is transferred from the CXL memory to the CPU when only read operations are performed; while tests in mixed read-write modes such as 3R1W, 2R1W, and 1R1W are closer to the complex read-write scenarios in actual applications and can accurately reflect the performance of the system under different read-write ratios; the full-write bandwidth test can measure the speed at which data is written from the CPU to the CXL memory. These test results provide detailed and accurate data support for evaluating the performance of the system under different workloads.

[0071] Exemplarily, a preset test tool is used to perform a bandwidth test on the first node. Test the full-read, 3R1W, 2R1W, and 1R1W bandwidths of CPU0 and the local (connected under CPU0) CXL memory; test the full-read, 3R1W, 2R1W, and 1R1W bandwidths of CPU0 and the remote (connected under CPU1) CXL memory; test the full-read, 3R1W, 2R1W, and 1R1W bandwidths of CPU1 and the local (connected under CPU1) CXL memory; test the full-read, 3R1W, 2R1W, and 1R1W bandwidths of CPU1 and the remote (connected under CPU0) CXL memory; test the full-write bandwidth of CPU0 and the local CXL memory; test the full-write bandwidth of CPU0 and the remote CXL memory; test the full-write bandwidth of CPU1 and the local CXL memory; test the full-write bandwidth of CPU1 and the remote CXL memory.

[0072] The preset test tool can be a Multi-Layer Control (MLC) tool. The MLC tool is a software or hardware device used for network bandwidth testing and management. By performing multi-layer control and analysis on network traffic, it can accurately measure the bandwidth performance of the network, including key indicators such as upload speed, download speed, latency, and packet loss rate. The MLC tool can simulate different network environments and application scenarios to comprehensively evaluate the bandwidth performance of the network under various conditions, helping network administrators and engineers optimize network configurations and improve the reliability and performance of the network.

[0073] The pseudocode is as follows:

[0074]

[0075] In the above 1LM+Vol mode, a preset test tool is used to test the full read, 3R1W, 2R1W, 1R1W, and full write bandwidths of the CPU with local CXL memory or remote CXL memory, so as to accurately understand the data transfer ability between the CPU and the CXL memory.

[0076] In the case where the target configuration mode is the Hetero mode or the Flat2LM mode, a preset test tool is used for testing to obtain the bandwidth test results.

[0077] Exemplarily, in the Hetero or Flat2LM mode, the pseudo code for bandwidth testing of the second node using the MLC tool is as follows:

[0078]

[0079] In the above Hetero mode or Flat2LM mode, the MLC tool is used to test the bandwidths of the CXL memory and the DDR memory, and the bandwidths of the CXL memory and the DDR memory under different operations can be accurately measured.

[0080] The above steps perform different bandwidth tests under different configuration modes. Through targeted bandwidth tests, the bandwidth test results of the memory system in each mode can be accurately obtained, and these quantified metrics provide an accurate basis for evaluating the performance of the system under different workloads.

[0081] S104. Evaluate the bandwidth test results according to the performance evaluation metrics corresponding to the target configuration mode.

[0082] Different target configuration modes correspond to different performance evaluation metrics. The 1LM+Vol mode corresponds to the first evaluation metric, the Hetero mode corresponds to the second evaluation metric, and the Flat2LM mode corresponds to the third evaluation metric.

[0083] In some embodiments, before performing step S104, a calculation process of the performance evaluation metrics is further included. First, determine the operating frequency and the number of channels of the target memory corresponding to the target node, then calculate the theoretical bandwidth value of the target memory according to the operating frequency and the number of channels of the target memory, and further calculate the performance evaluation metrics corresponding to the target configuration mode according to the theoretical bandwidth value.

[0084] In the 1LM+Vol mode, first determine the operating frequency and the number of channels of the CXL memory corresponding to the first node. Then calculate the theoretical bandwidth value of the CXL memory according to the following formula: Theoretical bandwidth value of CXL memory = operating frequency * number of channels * 64bit / 8. Further calculate the performance evaluation metrics of the 1LM+Vol mode according to the theoretical bandwidth value of the CXL memory.

[0085] Optionally, when the target configuration mode is the 1LM+Vol mode, calculate the performance evaluation index corresponding to the target configuration mode according to the theoretical bandwidth value and the amount of extended memory. Specifically, calculate the first evaluation index of the 1LM+Vol mode according to the theoretical bandwidth value of the CXL memory and the number of CXL memories, including the full read evaluation index and the full write evaluation index. As shown in Table 2, where A = the theoretical bandwidth value of the CXL memory * the third preset coefficient, and the third preset coefficient can be 60%, and the present application does not specifically limit this.

[0086] Table 2

[0087]

[0088] In the above 1LM+Vol mode, first calculate the theoretical bandwidth value of the CXL memory according to the operating frequency and the number of channels of the CXL memory, and then determine the performance evaluation index corresponding to the 1LM+Vol mode in combination with the number of CXL memories, providing an accurate theoretical reference standard for the memory performance in the 1LM+Vol mode. This makes the evaluation process no longer a vague subjective judgment, but an analysis based on specific numerical values. Different system configurations may have different numbers of CXL memories. By combining the memory quantity with the theoretical bandwidth value, a unified scale is provided for the performance evaluation of the entire system in the 1LM+Vol mode. In this way, whether it is for the performance optimization of a single system or for the performance comparison between multiple systems with different configurations, it can be carried out under the same standard, making the evaluation results more comparable and persuasive.

[0089] In the Hetero mode, first determine the operating frequency and the number of channels of the CXL memory corresponding to the second node, and the operating frequency and the number of channels of the DDR memory. Then calculate the theoretical bandwidth value according to the following formula: theoretical bandwidth value = operating frequency * (the sum of the number of CXL and DDR channels) * 64bit / 8. Further calculate the performance evaluation index of the 1LM+Vol mode according to the theoretical bandwidth value of the CXL memory.

[0090] Optionally, when the target configuration mode is the Hetero mode, calculate the performance evaluation index corresponding to the target configuration mode according to the theoretical bandwidth value and the first preset coefficient. Specifically, calculate the second evaluation index of the Hetero mode according to the theoretical bandwidth value and the first preset coefficient N1.

[0091] In the Hetero mode described above, first calculate the theoretical bandwidth value based on the sum of the operating frequencies and the sum of the channel numbers of the CXL memory and the DDR memory, and then calculate the performance evaluation index corresponding to the Hetero mode in combination with the first preset coefficient, providing an accurate theoretical reference standard for the memory performance in the Hetero mode. It comprehensively considers the characteristics of the two different types of memory in the Hetero mode, incorporates the sum of the operating frequencies and the sum of the channel numbers of the CXL memory and the DDR memory into the calculation of the theoretical bandwidth value, and the introduction of the first preset coefficient further quantifies the memory performance.

[0092] In the Flat2LM mode, first determine the operating frequency and the number of channels of the CXL memory corresponding to the second node, and the operating frequency and the number of channels of the DDR memory. Then calculate the theoretical bandwidth value according to the following formula: Theoretical bandwidth value = operating frequency * sum of the number of CXL and DDR channels * 64bit / 8. Further calculate the performance evaluation index of the 1LM+Vol mode based on the theoretical bandwidth value of the CXL memory.

[0093] Optionally, when the target configuration mode is the Flat2LM mode, calculate the performance evaluation index corresponding to the target configuration mode according to the theoretical bandwidth value and the first preset coefficient. Specifically, calculate the third evaluation index of the Flat2LM mode according to the theoretical bandwidth value and the second preset coefficient N2.

[0094] In the Flat2LM mode described above, first calculate the theoretical bandwidth value based on the sum of the operating frequencies and the sum of the channel numbers of the CXL memory and the DDR memory, and then calculate the performance evaluation index corresponding to the Flat2LM mode in combination with the second preset coefficient, providing an accurate theoretical reference standard for the memory performance in the Flat2LM mode. It comprehensively considers the characteristics of the two different types of memory in the Flat2LM mode, incorporates the sum of the operating frequencies and the sum of the channel numbers of the CXL memory and the DDR memory into the calculation of the theoretical bandwidth value, and the introduction of the second preset coefficient further quantifies the memory performance.

[0095] Step S104 and its embodiments quantify the memory performance, establish a unified and practical evaluation scale for different modes, transform the performance evaluation from subjective judgment to objective analysis based on specific values, and enhance the comparability and persuasiveness of the evaluation results. By comparing the bandwidth test results with the calculated evaluation index, the gap between the actual memory performance and the theoretical value can be clearly found, and the performance bottleneck can be quickly located.

[0096] In summary, the embodiments of the present application provide a method for testing the performance of extended memory. The beneficial effects of this method compared with the related technologies are as follows:

[0097] (1) The user can set the extended memory configuration mode in the basic input / output system interface and select the target configuration mode from the heterogeneous mode, single-channel local memory plus variable capacity mode, and flat dual-channel local memory mode. This covers a variety of possible CXL memory configuration scenarios, comprehensively considering the usage patterns of CXL memory in different application scenarios, and avoiding the limitations of only testing a single mode.

[0098] (2) Determine the target node corresponding to the target configuration mode, that is, the node where the extended memory is distributed. This step clarifies the specific object of the test, enabling the test to accurately target the node where the CXL memory is located, avoiding testing of irrelevant nodes, and improving the accuracy and pertinence of the test.

[0099] (3) Conduct a bandwidth test on the target node to obtain the bandwidth test result. Bandwidth is an important indicator to measure memory performance. By conducting a bandwidth test on the target node, the data transfer ability of the CXL memory in a specific configuration mode can be directly obtained, providing key quantitative data for evaluating the performance of the CXL memory.

[0100] (4) Evaluate the bandwidth test result according to the performance evaluation index corresponding to the target configuration mode. Different configuration modes have their unique performance evaluation indexes, which are formulated by comprehensively considering various characteristics of the CXL memory and application requirements in that mode. By comparing the bandwidth test result with the corresponding performance evaluation index, it can be accurately determined whether the performance of the CXL memory in this configuration mode meets the requirements, thus providing a reliable evaluation standard for the performance of the CXL memory.

[0101] Through the description of the above embodiments, those skilled in the art can clearly understand that the method according to the above embodiments can be implemented by means of software plus a necessary general hardware platform. Of course, it can also be implemented by hardware, but in many cases, the former is a better implementation method.

[0102] The embodiments of the present application also provide a performance test device for extended memory, as Figure 3 shown. The device includes:

[0103] An interaction module 301, configured to determine the target configuration mode of the extended memory in response to an input for setting the extended memory configuration mode by the user in the basic input / output system interface. The target configuration mode is any one of the heterogeneous mode, single-channel local memory plus variable capacity mode, and flat dual-channel local memory mode;

[0104] A target node determination module 302, configured to determine the target node corresponding to the target configuration mode. The target node is the node where the extended memory is distributed;

[0105] The bandwidth test module 303 is used to perform a bandwidth test on the target node to obtain a bandwidth test result;

[0106] The evaluation module 304 is used to evaluate the bandwidth test result according to the performance evaluation index corresponding to the target configuration mode.

[0107] As an optional implementation manner provided by the embodiment of the present application, the target node determination module 302 is specifically used for:

[0108] In the case where the target configuration mode is the single-channel local memory plus variable capacity mode, determine the first node of the distributed extended memory, and the first node includes a local node and a remote node.

[0109] As an optional implementation manner provided by the embodiment of the present application, the bandwidth test module 303 is specifically used for:

[0110] Perform a bandwidth test on the local node and the remote node through a preset test tool to obtain a bandwidth test result, and the bandwidth test result includes: full read bandwidth, three reads and one write bandwidth, two reads and one write bandwidth, one read and one write bandwidth, and full write bandwidth.

[0111] As an optional implementation manner provided by the embodiment of the present application, the target node determination module 302 is specifically used for: in the case where the target configuration mode is a heterogeneous mode or a flat dual-channel local memory mode, determine the second node corresponding to the extended memory and the dual-channel local memory.

[0112] As an optional implementation manner provided by the embodiment of the present application, the device further includes a memory setting module, which is used to set the memory parameters of the extended memory and the dual-channel local memory in the case where the target configuration mode is a heterogeneous mode or a flat dual-channel local memory mode.

[0113] As an optional implementation manner provided by the embodiment of the present application, the device further includes a performance evaluation index calculation module, which is used for:

[0114] Determine the operating frequency and the number of channels of the target memory corresponding to the target node;

[0115] Calculate the theoretical bandwidth value of the target memory according to the operating frequency and the number of channels of the target memory;

[0116] Calculate the performance evaluation index corresponding to the target configuration mode according to the theoretical bandwidth value.

[0117] As an optional implementation manner provided by the embodiment of the present application, the performance evaluation index calculation module is specifically used for: in the case where the target configuration mode is the single-channel local memory plus variable capacity mode, calculate the performance evaluation index corresponding to the target configuration mode according to the theoretical bandwidth value and the number of extended memories;

[0118] When the target configuration mode is the heterogeneous mode, calculate the performance evaluation index corresponding to the target configuration mode according to the theoretical bandwidth value and the first preset coefficient;

[0119] When the target configuration mode is the flat dual-channel local memory mode, calculate the performance evaluation index corresponding to the target configuration mode according to the theoretical bandwidth value and the second preset coefficient.

[0120] For the description of the features in the embodiments corresponding to the performance test device of the extended memory, reference can be made to the relevant descriptions in the embodiments corresponding to the performance test method of the extended memory, which will not be elaborated here one by one.

[0121] An embodiment of the present application further provides an electronic device, including a memory 401 and a processor 402. A computer program is stored in the memory 401, and the processor 402 is configured to run the computer program to execute the steps in any one of the embodiments of the above-mentioned performance test method for the extended memory.

[0122] An embodiment of the present application further provides a computer-readable storage medium, in which a computer program is stored. The computer program is configured to execute the steps in any one of the embodiments of the above-mentioned performance test method for the extended memory when running.

[0123] In an exemplary embodiment, the above-mentioned computer-readable storage medium may include, but is not limited to: USB flash drive, read-only memory (abbreviated as ROM), random access memory (abbreviated as RAM), mobile hard disk, magnetic disk or optical disc and other various media that can store computer programs.

[0124] An embodiment of the present application further provides a computer program product. The above-mentioned computer program product includes a computer program, and when the computer program is executed by a processor, the steps in any one of the embodiments of the above-mentioned performance test method for the extended memory are implemented.

[0125] An embodiment of the present application further provides another computer program product, including a non-volatile computer-readable storage medium. The non-volatile computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps in any one of the embodiments of the above-mentioned performance test method for the extended memory are implemented.

[0126] Those skilled in the art may further realize that the units and algorithm steps of each example described in combination with the embodiments disclosed herein can be implemented by electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described according to functions in the above description. Whether these functions are executed in a hardware or software manner depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods for each specific application to implement the described functions, but such implementation should not be considered to exceed the scope of this application.

[0127] The above has introduced in detail a method, apparatus, electronic device, and storage medium for performance testing of extended memory provided by this application. Specific examples are used herein to elaborate on the principle and implementation manner of this application. The description of the above embodiments is only used to help understand the method and its core idea of this application. It should be noted that for those of ordinary skill in the art in this technical field, without departing from the principle of this application, several improvements and modifications can be made to this application, and these improvements and modifications also fall within the protection scope of the claims of this application.

Claims

1. A performance testing method for extended memory, characterized in that, including: In response to an input for setting an extended memory configuration mode in the basic input / output system interface, determining a target configuration mode of the extended memory, where the target configuration mode is any one of a heterogeneous mode, a single-channel local memory plus variable-capacity mode, and a flat dual-channel local memory mode; determining a target node corresponding to the target configuration mode, where the target node is a node where the extended memory is distributed; performing a bandwidth test on the target node to obtain a bandwidth test result; evaluating the bandwidth test result according to a performance evaluation index corresponding to the target configuration mode.

2. The method according to claim 1, characterized in that, The determining the target node corresponding to the target configuration mode includes: in a case where the target configuration mode is the single-channel local memory plus variable-capacity mode, determining a first node where the extended memory is distributed, where the first node includes a local node and a remote node.

3. The method according to claim 2, wherein The performing a bandwidth test on the target node to obtain a bandwidth test result includes: performing a bandwidth test on the local node and the remote node through a preset test tool to obtain a bandwidth test result, where the bandwidth test result includes: full read bandwidth, three-read one-write bandwidth, two-read one-write bandwidth, one-read one-write bandwidth, and full write bandwidth.

4. The method according to claim 1, characterized in that The determining the target node corresponding to the target configuration mode includes: in a case where the target configuration mode is the heterogeneous mode or the flat dual-channel local memory mode, determining a second node corresponding to the extended memory and the dual-channel local memory.

5. The method according to claim 1, wherein After the determining the target configuration mode of the extended memory in response to an input for setting an extended memory configuration mode in the interaction interface and before the determining the target node corresponding to the target configuration mode, the method further includes: in a case where the target configuration mode is the heterogeneous mode or the flat dual-channel local memory mode, setting memory parameters of the extended memory and the dual-channel local memory.

6. The method according to claim 1, characterized in that, Before the evaluating the bandwidth test result according to a performance evaluation index corresponding to the target configuration mode, the method further includes: determining an operating frequency and a number of channels of a target memory corresponding to the target node; calculating a theoretical bandwidth value of the target memory according to the operating frequency and the number of channels of the target memory; calculating a performance evaluation index corresponding to the target configuration mode according to the theoretical bandwidth value.

7. The method according to claim 6, wherein The calculating a performance evaluation index corresponding to the target configuration mode according to the theoretical bandwidth value includes: in a case where the target configuration mode is the single-channel local memory plus variable-capacity mode, calculating a performance evaluation index corresponding to the target configuration mode according to the theoretical bandwidth value and the quantity of the extended memory; in a case where the target configuration mode is the heterogeneous mode, calculating a performance evaluation index corresponding to the target configuration mode according to the theoretical bandwidth value and a first preset coefficient; in a case where the target configuration mode is the flat dual-channel local memory mode, calculating a performance evaluation index corresponding to the target configuration mode according to the theoretical bandwidth value and a second preset coefficient.

8. A performance testing device for expanding memory, characterized in that, including: An interaction module, configured to determine a target configuration mode of the extended memory in response to an input for setting an extended memory configuration mode by a user in a basic input / output system interface, where the target configuration mode is any one of a heterogeneous mode, a single-channel local memory plus variable capacity mode, and a flat dual-channel local memory mode; A target node determination module, configured to determine a target node corresponding to the target configuration mode, where the target node is a node where the extended memory is distributed; A bandwidth test module, configured to perform a bandwidth test on the target node to obtain a bandwidth test result; An evaluation module, configured to evaluate the bandwidth test result according to a performance evaluation index corresponding to the target configuration mode.

9. An electronic device, characterized in that, Comprising: A memory, configured to store a computer program; A processor, configured to implement the steps of the performance test method for the extended memory according to any one of claims 1 to 7 when executing the computer program.

10. A computer-readable storage medium, characterized in that, A computer program is stored in the computer-readable storage medium, where the computer program implements the steps of the performance test method for the extended memory according to any one of claims 1 to 7 when executed by a processor.

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