Memory system and operating method thereof

Abstract

A method for operating a storage system including a storage device includes calculating an average length of extensions allocated to a logical address region corresponding to a particular node of an address mapping tree associated with the storage device, and a mapping information format of the particular node is a first format, and based on the average length, assigning a mapping information format of the particular node to a logical address region corresponding to the particular node. And converting the mapping information format of the specific node from the first format to the second format.

Description

[0001] Cross - reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10 - 2024 - 0013202, filed on January 29, 2024, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Systems, methods, and computer - readable storage media consistent with the present disclosure relate to a storage system and an operation method thereof, and more particularly, to a storage system and an operation method thereof that adaptively convert a format of address mapping information according to characteristics of a workload injected into a storage device. Background Art

[0004] An extent - based address mapping scheme is a scheme for managing mapping information between logical addresses and physical addresses on an extent basis. Here, an extent refers to a set or collection of pages composed of consecutive pages on a logical address space.

[0005] It is known that the extent - based address mapping scheme is more efficient than the page - based mapping scheme in terms of memory cost. This increased efficiency is because, although the size of an extent entry (i.e., a unit of mapping information) is larger than that of a page entry (e.g., an extent entry also includes fields such as a logical page number of a starting page and an extent length), the total number of entries in the extent - based address mapping is generally smaller than that in the page - based mapping scheme.

[0006] However, in some cases, the memory cost required by the extent - based address mapping scheme may exceed the memory cost of the page - based address mapping scheme. Summary of the Invention

[0007] One aspect is to provide a storage system that can effectively manage mapping information between logical addresses and physical addresses, and a method for operating the storage system.

[0008] Another aspect is to provide a method that can reduce the cost of format conversion of address mapping information.

[0009] Yet another aspect is to provide a method that can accurately determine a threshold for format conversion of address mapping information.

[0010] Another aspect is to provide a method for processing requests (e.g., write and read requests) of a storage client.

[0011] Yet another aspect is to provide a processing method according to operations (e.g., insert, delete, node split, etc.) of an address mapping tree.

[0012] According to one aspect of one or more embodiments, a storage system is provided, including: one or more processors; and a storage device implemented as a non-volatile memory and storing one or more computer programs. At least one of the one or more processors accesses the storage device and executes the one or more computer programs to cause at least one of the one or more processors to perform an average length calculation of an average length of an extension allocated to a logical address region corresponding to a specific node of an address mapping tree associated with the storage device, and a mapping information format of the specific node is a first format. At least one of the one or more processors accesses the storage device and executes the one or more computer programs to cause at least one of the one or more processors to perform a format conversion based on the average length, and the format conversion converts the mapping information format of the specific node from the first format to a second format.

[0013] According to another aspect of one or more embodiments, a method for operating a storage system including a storage device is provided, the method including calculating an average length of an extension allocated to a logical address region corresponding to a specific node of an address mapping tree associated with the storage device, and a mapping information format of the specific node is a first format, and based on the average length, converting the mapping information format of the specific node from the first format to a second format.

[0014] According to still another aspect of one or more embodiments, a non-transitory computer-readable storage medium is provided, configured to store instructions that, when executed by one or more processors, cause the one or more processors to at least calculate an average length of an extension allocated to a logical address region corresponding to a specific node of an address mapping tree associated with a storage device that cooperates with the one or more processors, and a mapping information format of the specific node is a first format, and based on the average length, convert the mapping information format of the specific node from the first format to a second format. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The above and other aspects will become more apparent by referring to the example embodiments described in detail with reference to the accompanying drawings, in which:

[0016] Figure 1 is an example configuration diagram showing a storage system according to some embodiments;

[0017] Figure 2 shows an example of an address mapping tree;

[0018] Figure 3 and 4 is an example diagram for explaining a mapping information format of a node;

[0019] Figure 5 is an example flowchart showing a method for operating a storage system according to some embodiments;

[0020] Figure 6 and Figure 7 is for explaining according to some embodiments Figure 5 an example diagram of an operation for calculating an average length of a computational expansion shown in the method of;

[0021] Figure 8 is for explaining according to some embodiments the operation of converting into a page-based format shown in the method of Figure 5 an example diagram of;

[0022] Figure 9 is an example diagram showing a method for operating a storage system associated with merging nodes of an address mapping tree according to some embodiments;

[0023] Figure 10 and Figure 11 is an example diagram for explaining a method for operating a storage system when memory capacity is insufficient according to some embodiments;

[0024] Figure 12 is an example diagram for explaining a method for operating a storage system associated with a storage device that does not support in-place updates according to some embodiments;

[0025] Figure 13 is an example diagram for explaining a method for operating a storage system associated with write request processing according to some embodiments; and

[0026] Figure 14 is an example diagram for explaining a method for operating a storage system associated with read request processing according to some embodiments. DETAILED DESCRIPTION

[0027] As described above, in some cases, the memory cost based on an extended address mapping scheme may exceed the memory cost based on a page-based address mapping scheme. For example, depending on the characteristics of the workload injected into the storage device, the memory cost based on the extended address mapping scheme may exceed the memory cost based on the page-based address mapping scheme. For example, in a workload environment where random writes occur frequently, due to storage area or due to the segmentation phenomenon of the storage area, the memory cost based on the extended address mapping scheme may exceed the memory cost based on the page-based address mapping scheme.

[0028] In the following, exemplary embodiments will be described with reference to the accompanying drawings. By referring to the following detailed description of various exemplary embodiments and the drawings, the advantages and features of the present disclosure and the method of implementing the present disclosure can be more easily understood. However, the technology can be embodied in many different forms and should not be construed as limited to the various embodiments set forth herein. On the contrary, the various embodiments are provided so that the present disclosure will be thorough and complete, and will fully convey the concept of the technology to those skilled in the art, and the present disclosure will be defined only by the scope of the appended claims.

[0029] When adding reference numerals to the components of each drawing, it should be noted that, even if the components are shown in different drawings, the same reference numerals are assigned to the same components as much as possible. In addition, when describing the present disclosure, when it is determined that a detailed description of a related well-known configuration or function may obscure the gist of the present disclosure, its detailed description may be omitted for the sake of brevity.

[0030] Unless otherwise defined, all terms (including technical and scientific terms) used in this specification may be used in the sense commonly understood by those skilled in the art. In addition, terms defined in a commonly used dictionary are not ideally or overly interpreted unless they are specifically defined clearly. The terms used herein are for the purpose of describing particular embodiments only and are not intended to limit the present disclosure. In this specification, the singular also includes the plural unless otherwise clearly stated in the phrase.

[0031] In addition, when describing the components of the present disclosure, terms such as "first", "second", "A, B, (a), (b)" may be used. These terms are only used to distinguish a component from other components, and the nature or order of the components is not limited by the terms. In other words, the "first" component may be referred to as the "second" component, and vice versa. If a component is described as "connected", "coupled" or "contacted" to another component, the component may be directly connected to or in contact with the other component, but it should be understood that other components may also be "connected", "coupled" or "contacted" between each component.

[0032] Components described with reference to terms such as components, units, modules, blocks, and / or others used in the following embodiments and functional blocks shown in the drawings may be implemented in the form of software, hardware, or a combination thereof. The software may be, for example, machine code, firmware, embedded code, and / or application software. In addition, the hardware may include processing circuits, such as circuits, electronic circuits, processors, computers, integrated circuits, integrated circuit cores, passive components, or a combination thereof.

[0033] In the following, various embodiments will be described in detail with reference to the accompanying drawings.

[0034] Figure 1FIG. 0 schematically shows an example configuration diagram of a storage system 10 according to some embodiments. In some cases, the storage system 10 may be named a "storage device" or a "computing device / system".

[0035] As Figure 1 shown, the storage system 10 may be configured to include one or more processors 11, a bus 13, a communication interface 14, a memory 12 into which one or more computer programs 16 are loaded for execution by the one or more processors 11, and a storage device 15 that stores the one or more computer programs 16. In the following description, for convenience, the one or more processors 11 will be described with reference to "processor 11", and "processor 11" is intended to refer to within its scope to include one processor 11 or more than one processor 11. Note that Figure 1 only the components associated with the various embodiments are shown. Thus, those skilled in the art to which the present disclosure pertains will understand that other components (e.g., input / output devices, display devices, and / or cache modules ( Figure 10 of 101)) may further be included in the storage system 10. That is, in some embodiments, the storage system 10 may further include various components in addition to Figure 1 the components shown. Further, in some cases, the storage system 10 may be configured to omit some of the Figure 1 components shown. That is, in some embodiments, some of the Figure 1 components shown may be omitted. Each component of the storage system 10 shown in Figure 1 will be described below.

[0036] The processor 11 may control the overall operation of each component of the storage system 10. The processor 11 may be configured to include at least one of a CPU (Central Processing Unit), an MPU (Microprocessor Unit), an MCU (Microcontroller Unit), a GPU (Graphics Processing Unit), or any form of processor (or controller) known in the technical field of the present disclosure. As described above, the storage system 10 may include one or more processors.

[0037] The processor 11 may collectively refer to any software / hardware module equipped with processing / computing functions. For example, a module that performs a cache function between the memory 12 and the storage device 15 (e.g., Figure 10 of 101) may also be included in the category of the processor 11. In some embodiments, a module that converts the mapping information format of the translation address mapping tree 17, a module that performs address translation by referring to the address mapping tree 17, etc. may also be included in the category of the processor 11.

[0038] Processor 11 may perform steps / operations / methods according to various embodiments by executing one or more computer programs 16 loaded into memory 12. That is, one or more computer programs 16 stored in storage device 15 may be loaded into memory 12, and processor 11 may access memory 12 to execute one or more computer programs 16, enabling processor 11 to implement various steps / operations / methods. For example, processor 11 may execute Figure 5 the steps / operations shown (e.g., format conversion of address mapping information, etc.). Thus, the mapping information format of address mapping tree 17 may be adaptively converted depending on the workload characteristics of the storage client (e.g., application, tenant, etc.), and the memory cost for managing address mapping tree 17 may be reduced. This configuration and operation will be explained in detail with reference to the accompanying drawings Figure 5 later.

[0039] Memory 12 stores various data, instructions, and / or information. As described above, memory 12 may load one or more computer programs 16 from storage device 15 such that when one or more computer programs 16 are executed by processor 11, processor 11 performs steps / operations / methods according to various embodiments. In an embodiment, memory 12 may be implemented as a volatile memory such as RAM.

[0040] Bus 13 provides a communication function between the components of storage system 10. Bus 13 may be implemented by various types of buses, such as an address bus, a data bus, and / or a control bus.

[0041] Communication interface 14 supports wired and wireless Internet communication for storage system 10. Communication interface 14 may also support various communication schemes other than Internet communication. Communication interface 14 may be configured to include various communication modules used in storage system technology.

[0042] Storage device 15 non - temporarily stores various data, instructions, and / or information. For example, storage device 15 may store one or more computer programs 16, address mapping tree 17, etc. Address mapping tree 17 represents address mapping information in a tree structure for address conversion associated with storage device 15 (i.e., converting a logical address to a physical address), and the configuration and operation will be described below. In some cases, address mapping tree 17 may be named "address translation tree", etc.

[0043] The storage device 15 can be implemented as a non-volatile memory, such as a ROM (Read Only Memory), EPROM (Erasable Programmable ROM), EEPROM (Electrically Erasable Programmable ROM), flash memory, a hard disk, and / or a removable disk. In some embodiments, the storage device 15 can be configured to include any form of non-transitory computer-readable storage medium used in storage system technologies.

[0044] One or more computer programs 16 can include instructions that, when loaded into the memory 12, cause the processor 11 to execute steps / operations / methods according to various embodiments. That is, the processor 11 can execute steps / operations / methods according to various embodiments by executing the instructions loaded into the memory 12.

[0045] For example, one or more computer programs 16 can include instructions that cause the processor 11 (e.g., at least one of one or more processors) to perform the following operations: calculate an average length of an extension of a logical address region assigned to a specific node of the address mapping tree 17, and one or more computer programs 16 can include instructions that cause the processor 11 (e.g., at least one of one or more processors) to perform the following operations: convert a mapping information format of the specific node based on the calculated average length. Here, an extension represents a set or collection of pages continuously assigned to a logical address region (i.e., a logical storage region) and / or a physical address region (i.e., a physical storage region).

[0046] As another example, one or more computer programs 16 can include instructions that cause the processor 11 to perform at least some of the steps / operations / methods described with reference to Figures 1 to 14 According to an embodiment, at least one of one or more processors performs one of the steps / operations / methods. According to an embodiment, at least one of one or more processors can perform multiple of the steps / operations / methods. That is, the present disclosure contemplates that a processor performs steps / operations / methods on a one-to-one basis or on a one-to-many basis.

[0047] In some embodiments, a storage system can refer to a system (e.g., a cloud storage system) that includes multiple storage devices (e.g., 10). For example, a storage system can be a system that provides cloud storage services to multiple tenants by using multiple storage devices (e.g., 15). In this case, the storage system can adaptively convert the mapping information format of the address mapping tree 17 according to the workload characteristics of a tenant (i.e., the cloud service client of the tenant).

[0048] It has been referred to above with reference to Figure 1The schematic configuration of a storage system 10 according to some embodiments is described. Hereinafter, before describing the method for operating the storage system 10, for ease of understanding, the address mapping tree 17 and the mapping information format that may be mentioned in various embodiments of the present disclosure will be explained first.

[0049] Figure 2 An example of the address mapping tree 17 is shown. Figure 2 The case where the address mapping tree 17 is implemented as a "B+ tree" is shown. However, the extension of the present invention is not limited thereto, and the address mapping tree 17 may be implemented as other forms of trees.

[0050] As Figure 2 shown, the address mapping tree 17 consists of non-leaf nodes and leaf nodes. It should be understood that the address mapping tree 17 is a sorted tree based on logical address information (e.g., logical page number (LPN)). Those skilled in the art will be aware of the structure of the B+ tree, and thus, for the sake of brevity, the explanations of the constraints (e.g., the conditions to be observed to maintain the structure of the B+ tree) and operations (e.g., insertion, deletion, etc.) are omitted.

[0051] The non-leaf nodes include one or more entries, and the maximum number of entries can be determined based on the degree of the address mapping tree 17. Figure 2 The case where the address mapping tree 17 is implemented as a B+ tree with a degree of "3" is shown. The entries of the non-leaf nodes include a key field, and for example, the logical address information of a page (e.g., logical page number) can be stored in the key field. In some embodiments, the non-leaf nodes may also store pointer information indicating the child nodes.

[0052] The leaf nodes (e.g., 21) also include one or more entries, and the maximum number of entries can be determined based on the degree of the address mapping tree 17. The leaf node entries can store the extent-based or page-based address mapping information (hereinafter sometimes abbreviated as "mapping information"), and the format of the information can vary depending on whether the information is in an extent-based format (or page-based format).

[0053] If the mapping information format of the leaf node is in an extent-based format, the entry can include a key field and a record field. The key field can store, for example, the logical address information of the start page of the extent (i.e., the first logical page), and the record field can store the physical address information of the start page of the extent and the length of the extent (i.e., the number of consecutive pages). This configuration and operation will be explained later with reference to Figure 3 and Figure 4 The case where the mapping information format of the leaf nodes (e.g., 21, 25) is "extent-based" is shown. Figure 2

[0054] ​Hereinafter, for the sake of explanation, the extended mapping information format will be abbreviated as "extended format", and the page-based mapping information format will be abbreviated as "page format". In Figure 2 and the subsequent drawings, the name of the mapping format is represented by the abbreviation.

[0055] As Figure 2 shown, the size of the storage area (e.g., 23, 27) (or logical address area) corresponding to the leaf nodes (e.g., 21, 25) can be determined dynamically (i.e., variably). For example, the size of the storage area 23 (or logical address area) corresponding to the leaf node 21 can be determined to be different from the size of the storage area 27 (or logical address area) corresponding to the other leaf node 25. This difference in size can be understood to be due to the fact that extensions (e.g., 24-1) are dynamically allocated and / or released according to the storage client requests. That is, the size of the storage area (e.g., 23) (or logical address area) covered by a specific leaf node (e.g., 21) can be dynamically determined by the allocation process of the extensions (e.g., 24-1, 24-2). Figure 2 shows a case where the address mapping information of the extensions 24-1 and 24-2 allocated to the specific area 23 of the storage device 15 is stored in the entries 22-1 and 22-2 of the leaf node 21, and the address mapping information of the extensions 28-1 and 28-2 allocated to the other area 27 of the storage device 15 is stored in the entries 26-1 and 26-2 of the other leaf node 25.

[0056] The following will refer to Figure 3 and Figure 4 to describe the extended format and the page format that can be referred to in various embodiments of the present disclosure.

[0057] Figure 3 shows an example of the extended format 31 according to some embodiments. Figure 3 and Figure 4 show the mapping information format of one leaf node.

[0058] As Figure 3 shown, the extended format 31 can be configured to include fields such as a header, a keyword, and / or a record. In some embodiments, the extended format 31 can be configured to further include pointer-related fields indicating sibling nodes (see "NEXT_NODE", "PREVIOUS_NODE"). Here, it can be understood that one keyword field and one record field constitute one entry. In some cases, the entry of the extended format 31 can be named "extended entry".

[0059] The header may include a flag field (e.g., a flag bit) indicating whether format conversion is performed. In some embodiments, the header may further include fields / information such as the number of pre-allocated extensions and the size of the logical address region (or storage region).

[0060] As described above, the keyword field may store the logical address information (e.g., logical page number) of the starting (first) page of the extension.

[0061] The record field may store the physical address information (e.g., physical page number (PPN)) of the starting page of the extension and the length of the extension (i.e., the number of consecutive pages).

[0062] Figure 4 An example of page format 41 according to some embodiments is shown.

[0063] As Figure 4 shown, the page format 41 may be configured to include fields such as a header, records, and / or a bitmap. In some embodiments, the page format 41 may be further configured to include pointer-related fields indicating sibling nodes (see "NEXT_NODE" and "PREVIOUS_NODE"). Here, it can be understood that one record field constitutes one entry. In some embodiments, the entries of the page format 41 may be named "page entries".

[0064] The header may include a flag field (e.g., a flag bit) indicating whether format conversion is performed. In some embodiments, the header may further include fields / information such as the logical address information (e.g., logical page number) of the first page of the logical address region and the size of the logical address region (or storage region).

[0065] The record field may store the physical address information (e.g., physical page number) of the page. For example, the physical address information on each page of the logical address region covered by a specific leaf node may be stored in each record field. Multiple record fields (or entries) can be understood as being implemented as a data structure (e.g., a table / array) that supports direct / random access (e.g., the processor 11 can access the record field using the logical page number as an index to obtain the physical page number of the page).

[0066] The bitmap is a data structure and metadata for managing page validity information. For example, the bitmap can be understood as a collection of bits indicating the validity of each page of the logical address region covered by a specific leaf node.

[0067] The processor 11 of the storage system 10 may execute Figure 3 the extended format 31 shown and Figure 4Format conversion between the page formats 41 shown. For example, the processor 11 may convert the format of the address mapping information to the page format 41 within the storage space (e.g., current storage space, maximum storage space, etc.) occupied by the address mapping information of the extended format 31. If the size of the storage space occupied by the address mapping information of the page format 41 exceeds the size of the address mapping information of the extended format 31, the processor 110 may defer the format conversion until a later specific time point. The method by which the processor 11 performs the format conversion will be described in detail below with reference to Figure 5 and the subsequent drawings.

[0068] It has been described above with reference to Figures 2 to 4 the address mapping tree 17 and the mapping information format. Hereinafter, various methods for operating the storage system 10 will be explained with reference to Figure 5 and the subsequent drawings.

[0069] Hereinafter, for ease of understanding, an explanation will be given based on the assumption that the address mapping tree 17 is implemented as a "B+ tree" as shown in Figure 2 and the processor 11 of the storage system 10 performs the methods to be described below. Therefore, if the subject of a specific step / operation is omitted, it can be understood that it is performed by the processor 11. However, in some cases, some steps / operations of the methods to be described below may be performed by other modules.

[0070] Figure 5 is an example flowchart showing a method for operating the storage system 10 according to some embodiments. However, this flowchart is only an example embodiment, and in some embodiments, some operations may be added or deleted. Figure 5 shows a method for operating the storage system 10 associated with the conversion of the mapping information format according to some embodiments.

[0071] As Figure 5 shown, the operation method may start with an operation S51 of detecting an update to a specific node (e.g., a leaf node) of the address mapping tree 17. For example, the processor 11 may determine that the address mapping information stored in a specific leaf node of the address mapping tree 17 has been updated. The update of the address mapping information may occur during the process of processing a request from a storage client (e.g., write, read, delete requests, etc.). For example, when a new extent is allocated by a sequential write request from a storage client, an entry including the address mapping information of the new extent may be inserted into a specific leaf node.

[0072] The storage client is a module that uses the storage device 15 and may be, for example, an application installed on the storage system 10, a module that uses the storage device 15 outside the storage system 10 (e.g., a tenant's cloud service client), etc. However, the embodiments are not limited thereto.

[0073] In some embodiments, an update to a particular node may include a case where new extended entries are inserted into the particular node when the particular node is in a full state. Here, the case where the particular node is in a full state means the case where the number of entries in the particular node is the maximum number (e.g., the degree of the B+ tree - 1). The maximum number may be preset. In this case, the processor 11 may postpone the splitting (or partitioning) of the particular node and convert the mapping information format of the particular node from an extended format to a page format (if the conditions of operation S53 are met). Thus, the processing costs of node splitting (or partitioning) and format conversion can be reduced. Otherwise, the processing cost of node splitting (or partitioning) can be reduced by postponing the node splitting (or partitioning) until a later specific time point. By performing format conversion only on full - state nodes, the frequency of format conversion and the processing cost caused by format conversion can be reduced.

[0074] In operation S52, the average length of the extensions allocated to the logical address area (or storage area) corresponding to a particular node is calculated. Here, the reason for calculating the average length of the extensions can be understood from the fact that the average extension length is a measure that accurately indicates the degree of segmentation of the corresponding logical address area (or storage area). The processor 11 may calculate the average extension length based on the size of the logical address area corresponding to the particular node and the number of extensions allocated to the logical address area. However, the specific method for calculating the size of the logical address area and / or the number of extensions may vary according to embodiments.

[0075] In some embodiments, the processor 11 may calculate the size of the logical address area based on the difference between the logical address information of the first entry of a particular node and the logical address information of the first entry of a sibling node (here, the particular node is a node in extended format). For example, as Figure 6 shown, the processor 11 may calculate the size of the logical address area (SIZE_A) based on the difference between the logical page number (LPN_A, i.e., the logical page number of the start page of the first extension) stored in the first entry 63 of the particular node 61 and the logical page number (LPN_B) stored in the first entry 64 of the sibling node 62. As a reference, the upper column of the rectangle representing the extended - format entry (e.g., 63) in the present and subsequent figures represents the keyword field (i.e., the logical address field), and the lower two columns represent the record fields (i.e., the physical address and length fields). Figure 6

[0076] ​In some embodiments, the processor 11 may calculate the size of the logical address region based on the logical address information of the first entry and the logical address information and the extended length information of the last entry of a specific node (here, the specific node is a node in an extended format). For example, the processor 11 may derive the logical page number of the last page of the last extension by adding the extended length to the logical page number of the last entry of the specific node (i.e., the logical page number of the starting page of the last extension). Then, the processor 11 may calculate the size of the logical address region based on the difference between the derived logical page number and the logical page number of the first entry (i.e., the logical page number of the starting page of the first extension).

[0077] In some embodiments, the processor 11 may calculate the number of extensions of the logical address region allocated to a specific node based on the number of entries (or the number of keys) included in the specific node (here, the specific node is a node in a page format).

[0078] In some embodiments, the processor 11 may determine the number of extensions by counting the number of sets of pages with consecutive valid pages by using the bitmap information of a specific node (here, the specific node is a node in a page format). For example, as Figure 7 shown, the processor 11 may determine and count the sets of pages 73 to 76 composed of consecutive valid pages by using the bitmap 72 of the specific node 71. In some embodiments, the processor 11 may determine the sets of pages composed of consecutive valid pages in the physical address space by further using the physical address information of the pages stored in the entries of the specific node. Then, the processor 11 may count the number of the determined sets of pages to determine the number of extensions.

[0079] In some embodiments, the size and number of extensions of the logical address region may be calculated based on various combinations of the above embodiments.

[0080] Returning to Figure 5 , in operation S53, it is determined whether the average length of the extensions is equal to or greater than a threshold. When the average length is equal to or greater than the threshold (i.e., operation S53, yes), operation S54 is executed, and when the average length is less than the threshold (i.e., operation S53, no), operation S56 is executed.

[0081] The threshold value can be a reference value used to determine which of the extended format and the page format is more efficient. In some embodiments, the threshold value can be a preset fixed value. In some embodiments, the threshold value can be a value that fluctuates according to circumstances. For example, the threshold value can be a fixed value predetermined based on the entry size of the extended format (e.g., the size of the address mapping information of a single extended) and / or the entry size of the page format (e.g., the size of the address mapping information of a single page). In this case, a reference value for determining which of the two formats is more efficient can be accurately derived. As another example, the threshold value can be adjusted (e.g., pre-adjusted, dynamically adjusted, etc.) based on the request processing speed associated with the storage client. For example, when the storage client uses a high request processing speed, the threshold value can be adjusted to be higher than the original threshold value to increase the page format retention time of the node (because the page format that supports direct access can provide a faster address conversion speed than the address conversion speed of the extended format). When the storage client uses a low request processing speed, the threshold value can be adjusted to be lower than the original threshold value.

[0082] In operation S54, it is determined whether the current format of a specific node is a page-based format. When the current format of the specific node is a page-based format (operation S54, yes), in operation S55, based on determining that the current format of the specific node is the page format, the mapping information format of the specific node is converted (switched) to the extended format. Wherein the case where the average length of the extension assigned to the logical address area (or storage area) corresponding to the specific node is equal to or greater than the threshold value indicates that the degree of segmentation of this area is not high. Therefore, the processor 11 can reduce the memory cost by converting the mapping information format of the specific node to the extended format. For example, the processor 11 can identify the extensions of the logical address area assigned to the specific node (e.g., a set of consecutive valid pages), generate an entry corresponding to each of the identified extensions, and convert the mapping information format of the specific node to the extended format. When the current format of the specific node is not a page-based format (operation S54, no), the conversion can be postponed to a later specific time point, and the method can end.

[0083] In some embodiments, the processor 11 can set a value (information) indicating the format conversion to be used for the header (see Figure 4 ) of the specific node based on determining that the current format of the specific node is the page format. In addition, the processor 11 can perform the format conversion according to the (information) set in the header at an appropriate time. For example, the processor 11 can perform the format conversion during the time when the storage device 15 processes input / output requests (see Figure 11 ), during idle time, and / or during the time when various conditions are met. Various conditions can be predetermined. Therefore, the format conversion can be performed more efficiently.

[0084] In operation S56, it can be determined whether the current format of a specific node is an extended-based format. And when the current format is an extended-based format (operation S56, yes), in operation S57, based on determining that the current format of the specific node is an extended format, the mapping information format of the specific node is converted (switched) to a page-based format. The case where the average length of the extension assigned to the logical address area (or storage area) corresponding to the specific node is less than a threshold means a high degree of segmentation of that area. Therefore, the processor 11 can reduce the memory cost by converting the mapping information format of the specific node to a page format. When the current format of the specific node is not an extended-based format (operation S56, no), the conversion can be postponed to a later specific time point, and the method can end.

[0085] For example, assume that a specific node includes entries 82 to 85 for four extensions, as Figure 8 shown. For ease of understanding, Figure 8 assume a case where the storage area 81 (i.e., the physical address area) has the same configuration as the logical address area. In this case, the processor 11 can generate an entry 87 for a page belonging to the logical address area (e.g., 81) corresponding to the specific node, and a bitmap 86 indicating the validity of the page. Thus, the format of the specific node can be accurately converted to a page format.

[0086] For reference, the entry 87 shown in tabular form in Figure 8 and subsequent figures represents an entry for a page format that supports direct access based on a logical page number.

[0087] In some embodiments, the processor 11 can set a value (information) indicating the format conversion that will be used for the header of the specific node (see Figure 3 ) based on determining that the current format of the specific node is an extended format. Then, the processor 11 can perform the format conversion according to the value (information) set in the header at an appropriate time. For example, the processor 11 can perform the format conversion during the time when the storage device 15 processes an input / output request (see Figure 11 ), during idle time, and / or during the time when various conditions are met. The various conditions can be determined in advance. Thus, the format conversion can be performed more efficiently.

[0088] Although Figure 5 only the format conversion of one node of the address mapping tree 17 is processed, those skilled in the art will understand that the format conversion can be performed on each node forming the address mapping tree 17. For example, the processor 11 can perform the format conversion on a first node covering a first logical address area (or a first storage area), and can perform the format conversion on a second node covering a second logical address area (or a second storage area), and so on.

[0089] Figure 5 Suppose the update of a specific node is set as a trigger condition for format conversion of the specific node. However, in some embodiments, the processor 11 may periodically or aperiodically calculate the average extended length of a specific node, and may determine whether to convert the format of the address mapping information based on the calculation result. In some embodiments, the processor 11 may calculate the average extended length of a specific node based on other trigger conditions.

[0090] Figure 5 The illustrated embodiments can be easily applied to an environment where there are multiple mapping information formats or an environment where there are other mapping information formats in addition to the extended format and the page format. For example, in an embodiment, the processor 11 may perform format conversion between a first format, a second format, and a third format based on a value of a metric that determines the memory efficiency among the first format, the second format, and the third format (e.g., the average length of the extension, etc.).

[0091] It has been referred to above Figures 5 to 8 A method for operating the storage system 10 according to some embodiments has been described. As described above, based on the average length of the extension of the logical address region (or storage region) assigned to a specific node (e.g., a leaf node) of the address mapping tree 17, the mapping information format of the specific node can be adaptively converted. For example, if the average length of the extension is equal to or greater than a threshold, the mapping information format of the specific node can be converted to the extended format, and if the average length of the extension is less than the threshold, the mapping information format can be converted to the page format. In this case, depending on the characteristics of the workload injected into the logical address region (or storage region), the mapping information format of the node covering the region can be converted to an appropriate format (i.e., a format with less memory cost), and thus, the total memory cost for managing the address mapping information can be significantly reduced.

[0092] It will be referred to below Figures 9 to 14 Various embodiments related to the method for operating the storage system 10 will be described.

[0093] First, a method for operating the storage system 10 associated with the constraints on the address mapping tree 17 will be described with reference to Figure 9 FIG. 266 is an example diagram for explaining a method for operating the storage system 10 in combination with node merging of the address mapping tree 17 according to some embodiments.

[0094] Figure 9 FIG. 266

[0095] As Figure 9As shown, there may be a situation where it is advantageous to perform a merge between a first node 91 and a second node 92 having different mapping information formats due to constraints associated with the structure maintenance of the address mapping tree 17. Here, the second node 92 represents a sibling node of the first node 91, and Figure 9 FIG. shows a case where the mapping information formats of the first node 91 and the second node 92 are an "extended format" and a "page format", respectively. The cases where it is advantageous to perform node merging are referred to the description of "B+ tree".

[0096] In this case, the processor 11 may generate a virtual merge node 93 for the first node 91 and the second node 92, and may derive an extended average length of the logical address area assigned to the virtual merge node 93. When the derived average length is less than the threshold, the processor 11 may postpone the merge of the first node 91 and the second node 92. If the derived average length is equal to or greater than the threshold, the processor 11 may merge the first node 91 and the second node 92 to generate an actual merge node in the extended format. By doing so, the frequency of format conversion can be reduced, and the memory cost can be reduced because the merged nodes start in the extended format.

[0097] There may be a situation where it is advantageous to perform an entry move (or borrowing) from the second node 92 to the first node 91 due to the constraints of the address mapping tree 17. For this case, reference will be made to the description of "B+ tree" associated with the borrowing of node elements.

[0098] In this case, the processor 11 may determine the extension of the second node 92 at the boundary between the first node 91 and the second node 92, generate an entry for the extension, and insert the generated entry into the first node 91.

[0099] More specifically, the processor 11 may determine the extension of the second node 92 (e.g., determine consecutive valid pages) that is located closest to the extension managed by the first node 91 (i.e., located closest to the boundary between the two nodes 91 and 92) based on the mapping information (e.g., information such as page entries, bitmaps, etc.). Next, the processor 11 may generate an entry including the address mapping information of the determined extension and insert the generated entry into the first node 91.

[0100] The operations of the storage system 10 associated with the constraints of the address mapping tree 17 have been described above with reference to Figure 9 Next, methods for operating the storage system 10 associated with a situation where the capacity of the memory 12 is insufficient will be described with reference to Figure 10 and Figure 11 Hereinafter, methods for operating the storage system 10 associated with a situation where the capacity of the memory 12 is insufficient will be described.

[0101] As Figure 10As shown, if the capacity of the memory 12 is insufficient to load the entire address mapping tree 17, the processor 11 may load at least some of the non-leaf nodes of the address mapping tree 17 into the memory 12 (since the non-leaf nodes have a smaller data size and are accessed more frequently). In some embodiments, the processor 11 may load at least some of the leaf nodes into the memory 12. In some embodiments, the mapping information of the leaf nodes may be loaded into the memory 12 or evicted to the storage device 15 through the cache module 101. Here, the cache module 101 refers to a module that operates based on a cache replacement algorithm (e.g., the LRU algorithm, etc.).

[0102] In this case, when a specific leaf node is being loaded or evicted through the cache module 101, the processor 11 may perform format conversion on the specific leaf node. This configuration and operation enable the following effect to be achieved: hiding the processing time of format conversion in the input / output processing time of the storage device 15. Specifically, the processor 11 may perform format conversion on a specific leaf node when the mapping information of the specific leaf node is being loaded from the storage device 15 into the memory 12 and / or when the mapping information of the specific leaf node is being evicted from the memory 12 to the storage device 15.

[0103] The above has been referenced Figure 10 and Figure 11 the method for operating the storage system 10 associated with the case where the capacity of the memory 12 is insufficient. Hereinafter, the method for operating the storage system 10 associated with the storage device 15 that does not support in-place update will be described with reference to Figure 12 the method for operating the storage system 10 associated with the storage device 15 that does not support in-place update will be described with reference to

[0104] Assume that the storage device 15 included in the storage system 10 is implemented as a non-volatile memory (or medium) that does not support in-place update (e.g., rewrite). Examples of such a memory may include flash memory, but the embodiments are not limited thereto.

[0105] In this case, whenever an update occurs in a specific node, the processor 11 may update all the ancestor nodes of the specific node together.

[0106] Specifically, as Figure 12As shown, when an update occurs in the mapping information of a specific leaf node 121 (e.g., entry addition, entry correction, and / or entry deletion, etc.), the processor 11 can generate a new leaf node 124 that includes the updated mapping information (since it is impossible to correct the information of leaf node 121). Next, the processor 11 can generate new ancestor nodes 125 and 126 for each of all the ancestor nodes 122 and 123 corresponding to the specific leaf node 121 (since it is also impossible to modify the information of the ancestor nodes (e.g., 122)). Then, the processor 11 can store the new nodes 124 to 126 in the storage device 15. By doing so, the address mapping tree 17 can be updated accurately and easily.

[0107] For reference, the data of the existing nodes 121 to 123 (e.g., the physical pages in which data is stored) is processed as invalid and can be collected through garbage collection techniques.

[0108] The method for operating the storage system 10 associated with the storage device 15 that does not support in-place update has been described above. The following will refer to Figure 13 and Figure 14 describe the method for operating the storage system 10 associated with the request processing of the storage client.

[0109] Figure 13 is an example diagram for explaining the method for operating the storage system 10 associated with the write request processing according to some embodiments.

[0110] As Figure 13 shown, it is assumed that a write request is received from the storage client, and the logical address area of the write request is associated with two sibling nodes 131 and 132 (i.e., leaf nodes). In addition, it is assumed that the mapping information formats of the first node 131 and the second node 132 are "extended format" and "page format", respectively. Hereinafter, for the sake of clear illustration, the logical address area of the write request associated with the first node 131 (e.g., see "[START_LBA:K1)") will be denoted as "the first area", and the logical address area of the write request associated with the second node 132 (e.g., see "[K1:START_LBA+LEN)") will be denoted as "the second area".

[0111] In this case, the processor 11 may remove the entry 133 with one or more extensions 136 having an area overlapping with the first area from the entries included in the first node 131, and may insert a new entry 134 including the address mapping information of the first area (i.e., the new extension 137) into the first node 131. In some embodiments, the processor 11 may update the information of the existing entry 133 by using the address mapping information of the new extension 137 (e.g., if the number of entries to be removed is equal to the number of entries to be inserted, the entry information may also be updated). This configuration and operation enable the write requests of the storage client to be accurately processed.

[0112] Next, the processor 11 may determine the entry 138 of the page associated with the second area in the entry 138 included in the second node 132, and may process the write request for the second area by referring to the entry 138. In some embodiments, the processor 11 may update the address mapping information or the bitmap, etc. of the entry 138 (e.g., perform the update when the physical address changes, and update the valid value of the bitmap).

[0113] Figure 14 is an example diagram for explaining a method for operating a storage system 10 associated with read request processing according to some embodiments.

[0114] As Figure 14 shown, it is assumed that a read request is received from a storage client, and the logical address area of the read request is associated with two sibling nodes 141 and 142 (i.e., leaf nodes). Further, it is assumed that the mapping information formats of the first node 141 and the second node 142 are the "extension format" and the "page format", respectively. Hereinafter, for the sake of clear explanation, the logical address area of the read request associated with the first node 141 (e.g., see "[START_LBA:K1)") will be denoted as the "first area", and the logical address area of the read request associated with the second node 142 (e.g., see "[K1:START_LBA+LEN)") will be denoted as the "second area".

[0115] In this case, the processor 11 may search for the entry of the first node 141 through a binary search scheme (e.g., multiple extension entries arranged by logical address information) to perform address translation of the first area. The processor 11 may access the page entry of the second node 142 associated with the second area through a direct access scheme (e.g., access using the logical page number as an index) to perform address translation on the second area. In other words, the processor 11 may access the page entry associated with the second area in the page entry of the second node 142 through a direct access scheme to perform address translation on the second area. This configuration and operation enable the read requests of the storage client to be accurately processed.

[0116] The above has been referred to Figure 13 and Figure 14 described the operation of the storage system 10 associated with the processing of storage client requests. According to the above, even if the requests of the storage client are associated with multiple nodes having different formats, the requests can be accurately processed.

[0117] The above has been referred to Figures 1 to 14 described various embodiments and the effects of various embodiments.

[0118] According to some embodiments, the mapping information format of a specific node can be adaptively converted based on the average length of the expansion of the logical address area (or storage area) assigned to a specific node (e.g., a leaf node) corresponding to the address mapping tree. For example, when the average length of the expansion is equal to or greater than a threshold, the mapping information format of the specific node can be converted to an expansion-based format (hereinafter referred to as the "expansion format"), and when the average length of the expansion is less than the threshold, the mapping information format of the specific node can be converted to a page-based format (hereinafter abbreviated as the "page format"). In this case, depending on the workload characteristics injected into the logical address area (or storage area), the mapping information format of the nodes covering the area can be converted to an appropriate format (i.e., a format with less memory cost), and thus, the total memory cost for managing the address mapping information can be significantly reduced. In addition, even when multiple tenants use different storage areas, the address mapping information of the storage can be effectively managed according to the workload characteristics of the tenants.

[0119] If a specific node is in a full state and an expansion entry is inserted into the specific node, the node split (or division) is postponed until a later specific time point, and the format conversion can be performed on the address mapping information of the specific node. In this case, the processing cost of the node split (or division) and format conversion can be reduced.

[0120] By comprehensively considering the size of the expansion entry and the size of the page entry, the threshold used as the format conversion standard can be accurately determined.

[0121] While the address mapping information of a specific node is loaded into the memory or evicted to the storage device, the format conversion can be performed on the address mapping information of the specific node. In this case, the effect of hiding the processing time of the format conversion in the input / output processing time of the memory can be achieved.

[0122] By performing node merging when the average expansion length of the virtual merge node is equal to or greater than a threshold, the frequency of format conversion can be reduced (i.e., the total processing cost caused by format conversion can be reduced). Since the merged nodes start in an expanded format, the total memory cost for managing address mapping information can be further reduced.

[0123] When an update occurs in a specific node of the address mapping tree, a new node can be generated for the specific node, and new ancestor nodes corresponding to the ancestor nodes can also be generated. Then the generated new nodes can be stored in the storage device. In this case, even if the storage device is implemented as a non-volatile memory that does not support in-place updates, the update of the address mapping tree can be accurately performed.

[0124] By applying a binary search scheme to the nodes in the expanded format and applying a direct access scheme to the nodes in the page format, the read requests of the storage client can be accurately and easily processed.

[0125] By removing the existing expanded entries having regions overlapping with the logical address region of the write request, and by inserting new expanded entries into a specific node, the write requests of the storage client can be accurately and easily processed.

[0126] The advantages of the technical concept according to the present disclosure are not limited to the above advantages, and those skilled in the art will clearly understand other advantages not mentioned from the following description.

[0127] The above technology can be embodied as computer-readable code on a computer-readable medium. The computer-readable medium can be, for example, a removable recording medium (CD, DVD, Blu-ray disc, USB storage device, removable hard disk) or a fixed recording medium (ROM, RAM, hard disk equipped with a computer). The computer program recorded on the computer-readable medium can be transmitted to other computing devices via a network such as the Internet and installed in other computing devices, so as to be used in other computing devices.

[0128] Although the operations are shown in a specific order in the drawings, it should not be understood that the desired results can be obtained only when the operations are performed in a specific order or in a successive order or when all the operations are performed. In some embodiments, multitasking and parallel processing can be advantageous and can be employed. According to the above embodiments, it should be understood that the described program components and systems can generally be integrated into a single software product or encapsulated into multiple software products together.

[0129] Those skilled in the art will understand that many variations and modifications can be made to the exemplary embodiments without substantially departing from the principles of the present disclosure. Therefore, the described exemplary embodiments are used only in a general and descriptive sense, and not for the purpose of limitation. The scope of the embodiments is defined by the appended claims.

Claims

1. A storage system, comprising: One or more processors; And A storage device, which is implemented as a non-volatile memory and stores one or more computer programs, Wherein, at least one of the one or more processors accesses the storage device and executes the one or more computer programs, so that at least one of the one or more processors performs an average length calculation of an extended average length, the extension being assigned to a logical address area corresponding to a specific node of an address mapping tree, the address mapping tree being associated with the storage device, and the mapping information format of the specific node being a first format; And At least one of the one or more processors accesses the storage device and executes the one or more computer programs, so that at least one of the one or more processors performs a format conversion based on the average length, the format conversion converting the mapping information format of the specific node from the first format to a second format.

2. The storage system according to claim 1, Among them, The address mapping tree is a B+ tree, and The specific node is a leaf node of the address mapping tree.

3. The storage system according to claim 1, Among them, The size of the logical address area is dynamically determined by the allocation process of the extension.

4. The storage system according to claim 1, Among them, The average length calculation includes: Calculating the average length of the extension based on the size of the logical address area and the number of extensions assigned to the logical address area.

5. The storage system according to claim 4, Among them, The address mapping tree is a sorting tree based on logical address information, and The size of the logical address area is calculated based on the difference between the first logical address information of the first entry of the specific node and the second logical address information of the first entry of the sibling node of the specific node.

6. The storage system according to claim 4, Among them, The first format is an extension-based format, in the extension-based format, each entry of a node corresponds to a separate extension, and The number of the extensions is determined by the number of entries included in the specific node.

7. The storage system according to claim 4, Among them, The first format is a page-based format, the page-based format includes a bitmap for managing the validity information of pages, and The average length calculation includes: Determining the number of the extensions by: counting the number of page sets composed of consecutive valid pages by using the bitmap.

8. The storage system according to claim 1, Among them, The first format is an extension-based format, The second format is a page-based format, and The format conversion is performed in response to the average length being less than a threshold.

9. The storage system according to claim 8, Among them, In response to the number of entries of the specific node being the maximum number and a new extension entry being inserted into the specific node, postpone the splitting of the specific node and perform the format conversion.

10. The storage system according to claim 8, Among them, Entries in the first format include separate and extended address mapping information, Entries in the second format include address mapping information for individual pages, and The threshold is based on the size of entries in the first format and the size of entries in the second format.

11. The storage system according to claim 8, Among them, The threshold is based on the request processing speed associated with the storage client.

12. The storage system according to claim 1, Among them, The first format is a page-based mapping format, The second format is an extended mapping format, and The format conversion is performed in response to the average length being equal to or greater than the threshold.

13. The storage system according to claim 1, further comprising a volatile memory, Among them, The format conversion is performed when the mapping information of the specific node is being loaded from the storage device into the volatile memory, or when the mapping information of the specific node is being evicted from the volatile memory to the storage device.

14. The storage system according to claim 1, Among them, The address mapping tree includes a first node in an extended-based format, and a second node that is a sibling node of the first node, and At least one of the one or more processors is configured to access the storage device and execute the one or more computer programs to cause the at least one of the one or more processors to: When a merge between the first node and the second node is to be performed due to constraints of the address mapping tree: Generate a virtual merge node of the first node and the second node, where the mapping information format of the second node is different from the mapping information format of the first node; Determine the average length of the extension allocated to the logical address area corresponding to the virtual merge node; Postpone the merge in response to the determined average length being less than the threshold; And In response to the determined average length being equal to or greater than the threshold, merge the first node and the second node to generate a merged node in the extended-based format.

15. The storage system according to claim 1, Among them, The address mapping tree includes a first node and a second node, where the second node is a sibling node of the first node, The mapping information format of the first node and the mapping information format of the second node are a page-based format and an extended-based format respectively, and At least one of the one or more processors is configured to access the storage device and execute the one or more computer programs to cause the at least one of the one or more processors to: When an entry movement from the first node to the second node is to be performed due to constraints of the address mapping tree: Determine the extension of the first node based on the mapping information of the first node, where the extension of the first node is located closest to the extension managed by the second node; And Generate an entry including the address mapping information of the determined extension and insert the generated entry into the second node.

16. The storage system according to claim 1, Among them, The address mapping tree includes a first node in an extended-based format, and At least one of the one or more processors is configured to access the storage device and execute the one or more computer programs to cause the at least one of the one or more processors to: Receive a write request from a storage client, the logical address region of the write request including a first region associated with the first node; Remove an entry having an extent that overlaps with the first region from the entries included in the first node; and Insert a new entry including address mapping information for the first region into the first node.

17. The storage system according to claim 1, Among them, The address mapping tree includes a first node and a second node, the second node being a sibling node of the first node, The mapping information of the first node includes a plurality of sorted extents, The mapping information of the second node includes a plurality of page entries that support direct access, and Wherein at least one of the one or more processors is configured to access the storage device and execute the one or more computer programs to cause the at least one of the one or more processors to: Receive a read request from a storage client, the logical address region of the read request including a first region associated with the first node and a second region associated with the second node; Search the plurality of sorted extents of the first node in a binary search scheme to perform address translation on the first region; and Access a page entry associated with the second region among the plurality of page entries in a direct access scheme to perform address translation on the second region.

18. The storage system according to claim 1, Among them, The non-volatile memory does not support in-place updates, and At least one of the one or more processors is configured to access the storage device and execute the one or more computer programs to cause the at least one of the one or more processors to: When the mapping information of a first node included in the address mapping tree is updated: Generate a second node including the updated mapping information; Generate an ancestor node of the second node corresponding to an ancestor node of the first node; and And Store the mapping information of the second node and the mapping information of the ancestor node of the second node in the storage device.

19. A method for operating a storage system including a storage device, the method comprising: Calculating an average length of an extent allocated to a logical address region corresponding to a specific node of an address mapping tree associated with the storage device, and the mapping information format of the specific node being a first format; And Based on the average length, converting the mapping information format of the specific node from the first format to a second format.

20. A non-transitory computer-readable storage medium configured to store instructions that, when executed by one or more processors, cause the one or more processors to at least: Calculate an average length of an extension of a logical address region assigned to a particular node of an address mapping tree associated with a storage device cooperating with the one or more processors, and a mapping information format of the particular node is a first format; and Based on the average length, convert the mapping information format of the particular node from the first format to a second format.

Images