Multi-core processor system and cache line locking control method

Abstract

The embodiment of the invention provides a multi-core processor system and a cache line locking control method, and the multi-core processor system comprises a plurality of cores and a cache line locking control unit, each core comprises at least one level of cache; each level of cache is used for identifying a cache access request in the received monitoring information; when it is identified that the cache access request is a request for accessing the cache line locked by the cache at the same level and the locked cache behavior core has the cache line under the use condition, a delay signal is sent out, and processing of the monitoring information is paused; when the execution signal is obtained, processing of the monitoring information is recovered, and the locked cache line is released; the cache line locking control unit is used for receiving the delay signal and sending out an execution signal at a preset delay moment; the locked cache line is realized on the basis of a lock obtained by a core execution lock grabbing mechanism. According to the technical scheme provided by the embodiment of the invention, the efficiency of executing a lock grabbing mechanism can be improved, and the overall performance of a multi-core processor system is improved.

Description

Technical Field

[0001] Embodiments of the present application relate to the field of computer technology, and more particularly to a multi-core processor system and a method for controlling cache line locking. Background Art

[0002] In a multi-core processor system, each core has its own private cache, thus there is a cache coherence problem. Cache line locking and cache coherence are to solve the data consistency problem in a multi-core processor system, ensuring data consistency and system stability when multiple cores access the same cache line. Among them, cache line locking is a fine-grained locking mechanism that maintains the consistency between the local core cache and other non-local core caches through a cache coherence protocol.

[0003] The execution efficiency of the cache line locking mechanism affects the performance of the multi-core processor system. Therefore, how to provide a technical solution to improve the execution efficiency of the cache line locking mechanism has become a technical problem that those skilled in the art urgently need to solve. Summary of the Invention

[0004] In view of this, embodiments of the present invention provide a multi-core processor system and a method for controlling cache line locking to improve the execution efficiency of the cache line locking mechanism.

[0005] To achieve the above object, embodiments of the present invention provide the following technical solutions.

[0006] In a first aspect, embodiments of the present invention provide a multi-core processor system, including: a plurality of cores and a cache line locking control unit; each core includes at least one level of cache;

[0007] Each level of cache is configured to identify a cache access request in the received snooping information; and when it is identified that the cache access request is a request to access a cache line locked at this level of cache and it is determined that the locked cache line is a cache line in use by the core, issue a delay signal to pause processing the snooping information; when an execution signal returned based on the delay signal is obtained, resume processing the snooping information and release the locked cache line;

[0008] The cache line locking control unit is configured to receive the delay signal issued by each level of cache and issue an execution signal at a preset delay moment indicated by the delay signal;

[0009] Wherein, the locked cache line is implemented based on a lock obtained by the core executing a lock stealing mechanism.

[0010] In a second aspect, embodiments of the present invention provide a method for controlling cache line locking, applied to the multi-core processor system as described in the first aspect, the method includes:

[0011] Receive monitoring information and identify the cache access requests in the monitoring information;

[0012] When it is identified that the cache access request is a request to access a locked cache line and it is determined that the locked cache line is a cache line with usage by the core, send a delay signal to pause processing the monitoring information;

[0013] When an execution signal returned based on the delay signal is obtained, resume processing the monitoring information and release the locked cache line;

[0014] Among them, the locked cache line is implemented based on the lock obtained by the core executing the lock grabbing mechanism.

[0015] A multi-core processor system provided by an embodiment of the present invention includes: a plurality of cores and a cache line locking control unit; each core includes at least one level of cache; each level of cache is configured to identify the cache access requests in the received monitoring information; and when it is identified that the cache access request is a request to access a cache line locked by the current level of cache and it is determined that the locked cache line is a cache line with usage by the core, send a delay signal to pause processing the monitoring information; when an execution signal returned based on the delay signal is obtained, resume processing the monitoring information and release the locked cache line; the cache line locking control unit is configured to receive the delay signals sent by each level of cache and send an execution signal at a preset delay moment indicated by the delay signal; among them, the locked cache line is implemented based on the lock obtained by the core executing the lock grabbing mechanism.

[0016] It can be seen that in the technical solution provided by the embodiment of the present invention, by adding a cache line locking control unit in the multi-core processor system, the cache line locking control unit can cooperate with each level of cache in each core. In the multi-core processor system, in order to maintain data consistency and improve the performance of the multi-core processor system, a cache coherence protocol is applied in the multi-core processor system to maintain data consistency; based on this, each level of cache in each core of the multi-core processor system has the function of maintaining cache coherence. With the help of the cache coherence maintenance function of the cache, after receiving the snooping information and before processing the snooping information, the present invention embodiment uses each level of cache to pre-identify the cache access request in the snooping information; and when it is identified that the cache line requested to be accessed by the cache access request is a locked cache line and the locked cache line is a cache line with a usage situation in the core, a delay signal is issued to cause the cache to delay the execution of the snooping information and delay the release of the locked cache line. Since the locked cache line is implemented based on the lock obtained by the core executing the lock stealing mechanism, the residence time of the lock in the locked cache line (the residence time in the cache) can be extended. Thus, the core can maintain the lock on the cache line within the preset delay time indicated by the delay signal, so as to avoid frequent operations of locking the cache line by each level of cache in the core when the core needs to use the locked cache line, and thus avoid the core from repeatedly executing the lock stealing mechanism to steal the lock for locking and unlocking the cache line. Since each level of cache frequently executes the lock stealing mechanism, the lock is frequently switched between cores, which will increase the additional performance overhead and communication overhead of the system. Therefore, in the technical solution provided by the embodiment of the present invention, when it is determined that the cache line accessed by the cache access request is a locked cache line and is a cache line with a usage situation in the core, the release of the cache line is delayed, the residence time of the lock in the locked cache line is extended, and the cache does not need to frequently execute the lock stealing mechanism to switch the lock within the preset delay time, thereby improving the execution efficiency of the cache line locking mechanism and further improving the overall performance of the multi-core processor system. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the drawings in the following description are only the embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained according to the provided drawings without creative efforts.

[0018] Figure 1 is a schematic structural diagram of a multi-core processor system;

[0019] Figure 2 is a schematic structural diagram of the multi-core processor system provided by the embodiment of the present invention;

[0020] Figure 3 is Figure 1 A schematic diagram showing the implementation process of mapping to hardware cache coherence when the multi-core processor system performs a lock stealing mechanism;

[0021] Figure 4 is Figure 2 A schematic diagram showing the implementation process of mapping to hardware cache coherence when the multi-core processor system performs a lock stealing mechanism;

[0022] Figure 5 A schematic flowchart of a control method for cache line locking provided by an embodiment of the present invention;

[0023] Figure 6 Another schematic flowchart of a control method for cache line locking provided by an embodiment of the present invention. Detailed implementation manners

[0024] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without making creative efforts shall fall within the protection scope of the present invention.

[0025] As the main frequency of the CPU (Central Processing Unit) approaches the physical limit, multi-core processors have become the main way to improve computing power. A multi-core processor system improves the computing power of the processor system by integrating multiple cores. Each core can execute tasks independently, thereby improving the overall processing speed and throughput of the processor system. Each core usually has its own L1 and L2 caches, and higher-level caches (such as L3 caches) may be shared by multiple cores. Please refer to Figure 1 , Figure 1 which is a schematic structural diagram of a multi-core processor system.

[0026] Referring to Figure 1 , a multi-core processor system may include a processor 1, Figure 1 Taking the example that processor 1 includes 2 cores, each core includes an L1 cache and an L2 cache. Further, the multi-core processor system may also include a shared cache (such as an L3 cache), a main memory (Memory) 4, and an on-chip network 5. Among them, the on-chip network 5 is responsible for implementing data interaction between the cores, the shared cache (such as an L3 cache), and the main memory.

[0027] In a multi-core processor system, each core has its own cache. When multiple cores need to access the same data, cache coherence problems may occur. The cache coherence protocol (Modify Exclusive Shared Invalid, MESI) is designed to ensure the coherence of data in the caches of all cores, that is, when a core modifies the data in its own cache, the corresponding data in the caches of other cores must also be updated or marked as invalid.

[0028] In a multi-core processor system, each core executes a lock-stealing mechanism to synchronize the access of each core to shared resources (shared data or shared cache lines) at the software level. The cache coherence protocol at the hardware level ensures the coherence of data in a multi-core environment. The two work together to ensure the safe and efficient access to shared resources in a multi-core processor system.

[0029] In programming and operating systems, the lock-stealing mechanism involves using synchronization primitives (such as mutexes, semaphores, etc.) to control the access of each core to shared resources, ensuring that only one thread or core can execute a specific code segment (i.e., the critical section) at any given time.

[0030] For example, when multiple cores need to access the same shared resource, the lock-stealing mechanism is used to ensure that only one core can modify the shared resource to prevent data races and inconsistencies. That is, at any time, only one core can hold the lock obtained by the lock-stealing mechanism (at the software level) to access and modify the shared resource corresponding to the lock (which is manifested as the cache line locked at each level of the cache at the hardware level), and other cores must wait until the lock is released.

[0031] It can be seen that both the cache coherence protocol and the lock-stealing mechanism are aimed at maintaining the coherence of data in a multi-core processor system. The execution of the lock-stealing mechanism at the software level triggers the implementation of cache coherence at the hardware level.

[0032] However, since each core executes the lock-stealing mechanism multiple times in a loop, each execution of the lock-stealing mechanism involves a lock switch, which causes the lock to switch frequently between different cores, thereby increasing the overhead of context switching, lock contention waiting, etc., and affecting the overall performance of the multi-core processor system.

[0033] To solve the above problems, the embodiments of the present invention provide a multi-core processor system, which improves the efficiency of the core executing the lock-stealing mechanism by making improvements at the hardware level to improve the overall performance of the multi-core processor system.

[0034] Please refer to Figure 2 , Figure 2 which is a schematic structural diagram of the multi-core processor system provided by the embodiments of the present invention.

[0035] AsFigure 2 As shown, the multi-core processor system includes: multiple cores within processor 1, and a cache line locking control unit 2; each core includes at least one level of cache, such as L1 / L2 cache;

[0036] Each level of cache is used to identify cache access requests in the received snooping information; and when it is identified that the cache access request is a request to access a cache line locked by this level of cache, and it is determined that the locked cache line is a cache line with usage by the core, a delay signal is issued to pause processing the snooping information; when an execution signal returned based on the delay signal is obtained, resume processing the snooping information and release the locked cache line;

[0037] The cache line locking control unit 2 is used to receive the delay signals issued by each level of cache and issue an execution signal at a preset delay moment indicated by the delay signal;

[0038] Among them, the locked cache line is implemented based on a lock obtained by the core executing a lock stealing mechanism.

[0039] The cache line locked by cache locking can be a cache line locked in the cache based on the cache coherence protocol after the core obtains the lock. The lock stealing mechanism can be executed by the cache controller inside the core.

[0040] In the cache coherence protocol, each cache line not only knows its own read and write operations, but also snoops on the read and write operations of other cache lines. The state of the cache line will migrate among the four states defined by the MESI protocol according to the read and write operations of this core and other cores: Modified (M) state, Exclusive (E) state, Shared (S) state, and Invalid (I) state.

[0041] When the cache line is in the M or E state, the cache where the cache line is located will constantly snoop on the read operations of other cores on the main memory address corresponding to this cache line. Once snooped, write the cache line of this core back to the main memory and mark it as the S state. When the cache line is in the S state, it will snoop on the write operations of other cores on this cache line. Once snooped, mark the cache line of this core as the I state.

[0042] In the case of cache locking a cache line, the processor does not declare a LOCK lock signal on the bus, but uses the cache coherence protocol to ensure the atomicity of the operation. Therefore, each level of cache can use the snooping mechanism of the MESI protocol to identify cache access requests in the snooping information, determine whether the cache access request is a request to access its locked cache line, and maintain cache coherence according to the snooping information.

[0043] When it is recognized that the cache access request is a request to access a cache line locked by the cache, it is further determined whether the locked cache line is a cache line in use by this core (i.e., the core where the cache is located). If so, a delay signal is issued to delay the processing of the snooping information, that is, to extend the time for the cache to release the locked cache line. Since the locked cache line is locked based on the lock obtained by the core executing the lock stealing mechanism, the residence time of the obtained lock in the cache can be delayed.

[0044] When it is determined that the locked cache line is a cache line in use by the core, if the snooping information is directly processed and the locked cache line is released, the cache of this core needs to execute the lock stealing mechanism again to re-obtain the lock, and then trigger the locking of the cache line based on cache coherence. Frequent acquisition and release of locks (frequent execution of the lock stealing mechanism) will cause the core to frequently switch from the running state to the waiting state and then back to the running state, and this kind of switching will bring certain performance overhead; at the same time, it will increase the communication times between cores.

[0045] Therefore, in the embodiment of the present invention, when it is determined that the locked cache line is a cache line in use by this core, the cache pauses processing the snooping information and issues a delay signal, and when the cache obtains the execution signal returned based on the delay signal, it resumes processing the snooping information. Since the execution signal is issued by the cache line locking control unit 2 at the preset delay moment indicated by the delay signal, the locking state of the locked cache line by the cache can be increased, so as to achieve the purpose of extending the residence time of the lock in the cache, enabling the core to directly use the lock in the cache within the preset delay moment, without the need to frequently acquire and release the lock, reducing the overhead of context switching, reducing the processing overhead of the cache coherence protocol, and improving the overall performance of the processor system.

[0046] During the process of waiting to receive the execution signal, the core can use the lock, and then modify the data in the locked cache line. Optionally, within the preset delay moment, the core is further configured to, when each level of cache issues the delay signal, within the preset delay moment indicated by the delay signal, perform data processing using the locked data in the locked cache line.

[0047] Performing data processing using the locked data means that within the preset delay moment, the core can use the obtained lock to execute the operations of locking and unlocking the cache line multiple times in a loop, so as to avoid frequent lock switching; at the same time, since the lock is located in the cache within the core, it is convenient for the core to quickly acquire and use the lock, and improve the efficiency of the core executing the lock stealing mechanism.

[0048] To facilitate understanding of the implementation steps of cache coherence at the hardware level when the core in the multi-core processor system executes the lock stealing mechanism, please refer to Figure 3 and Figure 4 ,Figure 3 Yes Figure 1 It is a schematic diagram of the implementation process of mapping the lock grabbing mechanism of the multi-core processor system shown in Figure 3 to the hardware cache coherence. Figure 4 Yes Figure 2 It is a schematic diagram of the implementation process of mapping the lock grabbing mechanism of the multi-core processor system shown in Figure 4 to the hardware cache coherence.

[0049] As Figure 3 shown, this process includes the following four steps: Step 1, Step 2, Step 3, and Step 4.

[0050] Step 1 includes the following processes:

[0051] Core0 and Core1 initiate ReadE requests;

[0052] The ReadE (Read for Ownership) request indicates that the core wants to obtain exclusive access to a certain cache line. If both Core0 and Core1 initiate ReadE lock grabbing operations, it means that both Core0 and Core1 want to obtain exclusive access to the same cache line;

[0053] Furthermore, after Core0 initiates a ReadE request, if Core0 first obtains the E-state data (i.e., DataE) returned for the ReadE request in the shared cache (L3 cache), then Core0 successfully grabs the lock, performs a locking operation, locks the cache line (the cache line caching DataE), and changes the state of the cache line to the M state;

[0054] For example, after Core0 obtains the lock, it can modify the data in the locked cache line, changing the E-state data to M-state data; at the hardware level, the cache changes the state of the cache line to the M state based on the cache coherence protocol;

[0055] Furthermore, after Core1 initiates a ReadE request, the shared cache sends a snooping message (snooping message of other cores accessing the cache line locked by Core0), such as a SnptoI (Snapshot to Invalidate, the cache line state is changed to invalid) message, to Core0 based on Core1's ReadE request. This snooping message will inform Core0 that Core1 also wants to obtain exclusive access to the cache line corresponding to the E-state data;

[0056] After Core0 receives the SnptoI information, in response to the snooping information, it changes the state of the cache line (in M state) to the invalid state (I state); then it returns a snooping response to the shared cache and writes the modified latest data back to the shared cache. For example, the SnpRspIWb (Snapshot Response Invalidate Writeback) information indicates that Core0 has relinquished the exclusive right to the cache line and written the modified data back to the shared cache;

[0057] Core0 has written the modified data back to the shared cache. The shared cache now has the latest data copy and provides this data to Core1 in the form of E state, that is, it returns E state data to Core1.

[0058] It can be seen that during the process of Step1, when Core1 attempts to obtain exclusive access to the cache line, since Core0 has successfully acquired the lock and changed the cache line state to M state, after Core1 initiates a ReadE request, in order to satisfy Core1's request, the shared cache must ensure that no other core has the modified cache line, thus requiring Core0 to relinquish the exclusive right. This process actually means that when Core1 attempts to obtain exclusive access, Core0 already has the exclusive right, so Core1's ReadE request is delayed until Core0 releases the exclusive right and writes the data back to the shared cache. During this process, Core1 does not obtain exclusive access to the cache line, so the lock acquisition fails.

[0059] In Step2, Core0 initiates a ReadE request again; Core0 obtains the E state data returned by the shared cache and changes the E state data to M state data. At this time, the data in this cache line is M state data, and the locked cache line is released.

[0060] In Step3, Core1 initiates a ReadS request; Core1 reads the S state data and determines whether the lock on the cache line corresponding to the S state data has been released, that is, whether the state of this cache line is the shared state. At this time, based on the ReadS request initiated by Core1, the shared cache sends snooping information, such as SnptoS information, to Core0 to inform Core0 that the cache line corresponding to the S state data that Core1 wants to access is the cache line locked by Core0; thus, Core0 processes the snooping information and returns a snooping response, such as SnpRspIWb information, indicating that the cache line has been released and is in the shared state. The shared cache returns the S state data to Core1.

[0061] In Step 4, Core 1 initiates a ReadE request. Since Core 0 released the cache line when Core 1 initiated a ReadS request in Step 3, Core 1 can now determine that the lock has been released and the cache line is in a shared state. Therefore, it can initiate a ReadE operation to grab the lock. After grabbing the lock, Core 1 succeeds.

[0062] Core0 and Core1 repeat the process from Step 1 to Step 4.

[0063] exist Figure 3 In the process shown, since Core0 and Core1 both execute the lock-grabbing mechanism in a loop (for example, execute the lock-grabbing mechanism in a loop 100,000,000 times), that is, Core0 and Core1 both execute the locking and unlocking operations in a loop, if the Core that grabs the lock in the lock-grabbing mechanism can increase the time that the lock resides in L1 / L2, it can execute multiple cache line locking and unlocking operations (changing the state of the cache line) as quickly as possible at the hardware level without having to frequently switch locks.

[0064] For example, after Core 0 acquires a lock, the lock resides in Core 0's L1 cache for a sufficient period of time. During this time, Core 0 can execute the lock-grabbing mechanism multiple times. This process influences Core 0's L1 cache coherence at the hardware level, enabling it to lock (set the cache line to exclusive or modified) and unlock (set the cache line to shared) the corresponding cache line. During this time, Core 0 can lock and unlock the cache line 100 times. Then, when the lock is acquired by Core 1 and resides in Core 1's L1, Core 1 executes the lock-grabbing mechanism 100 times in a loop. This approach reduces the frequency of lock switching between cores, allowing each core that acquires the lock to quickly and easily use the lock in its internal cache to lock and unlock the cache line multiple times. This results in better overall performance for a multi-core processor system than if each core only executes the lock-grabbing mechanism a small number of times (e.g., 10 times) before being seized by another core.

[0065] In order to increase the residence time of a lock in a core's cache, the embodiment of the present invention makes improvements at the hardware level. Figure 2 refer to Figure 4 .

[0066] like Figure 4 As shown, the improved implementation process includes the following Step 1, Step 2, Step 3, Step 4 and Step 5.

[0067] The Step1 stage includes the following processes:

[0068] Both Core0 and Core1 initiate a ReadE request.

[0069] Core0 first obtains the data in the shared cache (such as the L3 cache), that is, the E-state data. Then Core0 successfully grabs the lock and can lock the cache line of the E-state data in the cache within Core0. After Core1 reads the E-state data and determines that the cache line corresponding to the E-state data has been locked, Core1 fails to grab the lock.

[0070] In the Step2 stage:

[0071] Core0 initiates a ReadE request again.

[0072] Core0 obtains the E-state data and unlocks the locked cache line. At this time, although the locked cache line is unlocked, it only allows other cores to access the cache line, but does not allow other cores to modify the cache line. That is, Core0 still has exclusive rights to the cache line.

[0073] In the Step3 stage:

[0074] Core1 initiates a ReadS request.

[0075] Core1 requests to obtain the S-state data and determines whether the cache line corresponding to the S-state data has been released.

[0076] In the Step4 stage:

[0077] Within a preset delay time, the lock acquisition and unlocking operations are performed multiple times in a loop.

[0078] The L1 / L2 cache of Core0 receives the snooping information sent by the shared cache, such as the SnptoS information, and identifies the cache access requests in the snooping information. When it is identified that the cache line to be accessed is the locked cache line in Core0 and the locked cache line is a cache line in use in Core0, a delay signal is issued to pause the processing of the SnptoS information. At this time, within the preset delay time indicated by the delay signal, Core0 can use the lock already grabbed in the locked cache line to perform multiple lock acquisition and unlocking operations, that is, the lock grabbing mechanism can be executed multiple times in a loop.

[0079] As an example, in the embodiment of the present invention, when the delay signal is issued, the snooping information targeted is the SnptoS information, and the identified cache access request is a ReadS request.

[0080] When identifying whether a locked cache line is a cache line in use by Core0, it is possible to determine by judging the data status in the locked cache line. For example, it is judged whether the locked cache line includes locked data in the modified state, and the locked data is the data included in the locked cache line; alternatively, it can be judged whether there are frequent locking and unlocking situations for the locked cache line; if the judgment result is yes, it indicates that the locked cache line is a cache line in use by Core0.

[0081] In the Step5 stage:

[0082] Based on the received execution signal, resume the processing of the monitoring information, return the monitoring response, and the cache line has been released.

[0083] After the preset delay time indicated by the delay signal arrives, based on the execution signal returned by the cache line locking control unit, the cache of Core0 resumes the processing of the SnptoS information. At this time, based on the normal processing of the monitoring information, a monitoring response can be returned, such as the SnpRspIWb information, and the locked cache line is released.

[0084] Releasing the locked cache line means: based on the monitoring information, return the corresponding monitoring response, such as the SnpRspIWb information, write the data in the final modified state corresponding to the preset delay time back to the shared cache, and at the same time notify other cores that the cache line has been in the shared state and has the latest data updated, so that other cores can use this data.

[0085] In some embodiments, when each level of cache determines that the locked cache line includes locked data in the modified state, it determines that the locked cache line is a cache line in use by the core, or when it determines that the cache line replacement policy indicates that the locked cache line is frequently replaced, it determines that the locked cache line is a cache line in use by the core.

[0086] If the locked cache line includes locked data in the modified state (M state), it means that the data in the locked cache line has been modified, and this modification is exclusive to this core. This means that the core has performed a write operation on this cache line, and the data in this cache line is inconsistent with the data in the main memory. At this time, this cache line only exists in the current cache, indicating that the core is using this locked cache line.

[0087] The usage frequency of the cache line is also related to its replacement policy in the cache. If a cache line is rarely replaced, it may be because it is frequently accessed, so it stays in the cache for a long time. Therefore, it is possible to determine whether it is a cache line in use by the core through the cache line replacement policy of the locked cache line.

[0088] When determining whether a locked cache line is a cache line in use by a core, it can be obtained by comprehensively judging the locked cache line. The above examples are only some implementation methods for determining that a locked cache line is a cache line in use by a core. In other embodiments, other implementation means may also be included.

[0089] Exemplarily, when determining that a locked cache line is a cache line in use by a core, it can also be implemented by the following means:

[0090] Use the cache coherence protocol to judge: In the MESI protocol, a cache line in the M state indicates that the data in this cache line is the latest, and the corresponding cache line in the caches of other cores should be invalid (I state). Frequent changes in the state of such cache lines may indicate that the core has performed multiple read and write operations on this data, thus implying that the locked cache line is a cache line in use by the core.

[0091] Judge the number of lockings of the locked cache line: When a core locks a cache line and modifies the data, it will set the state of the cache line to the M state. If such locking and modification operations occur frequently, it can be considered that the locked cache line is a cache line in use by the core.

[0092] Judge by the performance overhead of the locked cache line: Frequent locking and unlocking operations will increase additional performance overhead. Especially in a high-concurrency environment, frequent synchronization operations will reduce system performance. Therefore, if a cache line is frequently locked and unlocked, it can indicate that it is hot data frequently accessed by the core.

[0093] Judge by the shareability of the cache line: If a cache line is frequently accessed by multiple cores, it may often be in the S (Shared) state. But when a certain core obtains exclusive access and changes the state to the M state, this indicates that the core is frequently modifying the data, thus indicating that the locked cache line is a cache line in use by the core.

[0094] In summary, the embodiments of the present application can use multiple methods to determine whether a locked cache line is a cache line in use by a core.

[0095] The cache line locking control unit 2 can cooperate with each level of cache. When each level of cache identifies that the cache line requested by a cache access request is a locked cache line and the locked cache line is a cache line with usage in the core, it receives a delay signal sent by each level of cache and issues an execution signal at a preset delay moment indicated by the delay signal, so that each level of cache can resume processing the monitoring information based on the execution signal. At the same time, the core can directly use the lock in the locked cache line within the preset delay moment without frequently switching the lock, realizing the locking and unlocking operations of the cache line and improving the execution efficiency of the lock grabbing mechanism.

[0096] In one implementation, the cache line locking control unit 2 can be a timer; when the timer receives a delay signal sent by the cache, it starts timing, and when the timing value reaches the preset delay moment indicated by the delay signal, it sends an execution signal to the cache.

[0097] The counter can start timing from an initial value (such as 0) after receiving the delay signal until the timing value reaches the value of the preset delay moment and then issue an execution signal. It can also set a corresponding timing value according to the preset delay moment inside the counter and then start counting down when receiving the delay signal until the timing value counts down to 0 and then issue an execution signal.

[0098] In other implementations, the cache line locking control unit 2 can also be a hardware structure such as an interrupt controller or an event register. The embodiments of the present application can control the cache to pause executing the monitoring information within the preset delay moment and execute the monitoring information at the preset delay moment.

[0099] It can be seen that the technical solution provided by the embodiment of the present invention, by adding a cache line lock control unit in the multi-core processor system, enables the cache line lock control unit to cooperate with each level of cache in each core. In order to maintain data consistency and improve the performance of the multi-core processor system in the multi-core processor system, a cache consistency protocol is applied in the multi-core processor system to maintain data consistency; based on this, each level of cache in each core in the multi-core processor system has the function of cache consistency maintenance. The embodiment of the present invention uses the cache consistency maintenance function of the cache to pre-identify the cache access request in the monitoring information after receiving the monitoring information and before processing the monitoring information; and when it is identified that the cache line locked by the cache behavior requested by the cache access request is a cache line, and the locked cache line is in use by the core, a delay signal is sent to delay the execution of the monitoring information by the cache, and delay the release of the locked cache line. Since the locked cache line is based on the lock obtained by the core execution lock grabbing mechanism, the residence time of the lock in the locked cache line can be extended (the residence time in the cache can be extended). Thus, the core can maintain the lock on the cache line within the preset delay time indicated by the delay signal, so that when the core needs to use the locked cache line, each level of cache in the core can be prevented from frequently executing the operation of locking the cache line, thereby preventing the core from repeatedly executing the lock-grabbing mechanism to lock and unlock the cache line. Since each level of cache frequently executes the lock-grabbing mechanism, the lock is frequently switched between the cores, which will increase the system's additional performance overhead and the communication overhead between the cores. Therefore, the technical solution provided by the embodiment of the present invention, when it is determined that the cache line accessed by the cache access request is a locked cache line and is a cache line that is in use by the core, delays the release of the cache line, prolongs the retention time of the lock in the locked cache line, and within the preset delay time, the cache can no longer frequently execute the lock-grabbing mechanism to switch the lock, thereby improving the execution efficiency of the cache line locking mechanism, and further improving the overall performance of the multi-core processor system.

[0100] To ensure cache consistency maintenance of a multi-core processor system, in one embodiment, the core is used to initiate a cache access request; the multi-core processor system further includes:

[0101] The shared cache 3 is configured to return a corresponding response signal based on the type of cache access request initiated by the core.

[0102] Wherein, when the core successfully executes the locking operation, the returned response signal includes monitoring information.

[0103] Cores with different cache coherence and memory access behaviors initiate different types of cache access requests. Cores initiate cache access requests of the appropriate type based on the type of data being accessed and the access mode (whether data modification is required). These requests are handled by the hardware-level cache coherence protocol, ensuring that all cores in a multi-core environment have synchronized and consistent access to shared data.

[0104] Therefore, the shared cache 3 can return response signals in a targeted manner according to different types of cache access requests to maintain cache consistency.

[0105] In one embodiment, the type of the cache access request includes a first-type cache access request requesting access to exclusive state data; when the cache access request initiated by the core is the first-type cache access request, the response signal returned by the shared cache 3 based on the first-type cache access request is: a signal formed by the exclusive state data;

[0106] Among them, when it is determined that the cache behavior corresponding to the exclusive state data is not locked, the core is also used to perform a locking operation to lock the cache line of the exclusive state data; when it is determined that the cache behavior corresponding to the exclusive state data is locked, the core is also used to cancel the locking operation.

[0107] The first type of cache access request for accessing exclusive state data (E state data) is the ReadE request described in the above embodiment. At this time, the shared cache 3 can return a response signal formed by the E state data based on the first type of cache access request.

[0108] After receiving the E-state data returned by shared cache 3, the core considers that the lock is successfully grabbed only when it determines that the cache line corresponding to the E-state data is not locked. It can then perform a locking operation on the cache line to lock the cache line that stores the E-state data.

[0109] When it is determined that the cache line corresponding to the E-state data has been locked by other cores, the core fails to lock, and modification of the locked cache line is not allowed. The locking operation is canceled, and the lock grabbing mechanism is executed after the locked cache line is released to lock the cache line.

[0110] For the core that successfully grabs the lock, after it locks the cache line of cache E-state data, that is, after the core performs a locking operation and changes the state of the cache line to M state, the core is also used to initiate the first type of cache access request again and unlock the locked cache line.

[0111] In a multi-core processor system, when a core has successfully acquired a lock, it can initiate a ReadE request again to ensure cache coherence, update the cache line state, maintain the effectiveness of the locking mechanism, handle cache line invalidation, perform synchronization operations, comply with hardware and software design requirements, and optimize performance. This ensures secure and consistent access to shared resources in a multi-core environment.

[0112] In some other embodiments, the type of the cache access request further includes a second type of cache access request for requesting access to shared status data; when the shared cache 3 receives the second type of cache access request, the shared cache 3 is further configured to determine the execution status of the locking operation of the core, and for different determination results, return a response signal corresponding to the second type of cache access request to the core;

[0113] Among them, when the determination result is that the core executes the locking operation, the response signal returned corresponding to the second type of cache access request is a signal formed by the snooping information;

[0114] When the determination result is to cancel the execution of the locking operation, and when the shared cache 3 determines that the locked cache line has been released according to the received snooping response, the response signal returned corresponding to the second type of cache access request is a signal formed by the shared status data.

[0115] The second type of cache access request for requesting access to shared status data is a ReadS request. At this time, the ReadS request is usually initiated by a core that fails to acquire the lock (cancels the execution of the locking operation). And the core that has successfully acquired the lock (executes the locking operation) will snoop on the access of other cores to the cache line it has locked in real time. Therefore, based on cores with different locking operation execution statuses, the shared cache 3 specifically feeds back response signals to meet the needs of different cores.

[0116] The shared cache 3 returns the snooping information: SnptoS to the core that executes the locking operation, informing the core that has successfully acquired the lock that there is another core accessing the cache line it has locked. At the same time, the shared cache 3 returns the shared status data: DataS to the core that cancels the execution of the locking operation. Of course, the shared cache 3 returns the shared status data when the core that cancels the execution of the locking operation determines that the cache line corresponding to the shared status data has been released by the core that has successfully acquired the lock.

[0117] The embodiment of the present invention further provides a control method for cache line locking, which is implemented on the multi-core processor system provided in the foregoing embodiment to improve the execution efficiency of the lock acquisition mechanism and improve the overall performance of the multi-core processor system.

[0118] Please refer to Figure 5 , Figure 5It is a flowchart diagram of a cache line locking control method provided by an embodiment of the present invention.

[0119] As Figure 5 shown, the method includes the following steps:

[0120] Step S101, receive the monitoring information and identify the cache access request in the monitoring information.

[0121] The monitoring information is the information sent by the shared cache to each core based on cache coherence. It includes cache access requests initiated by each core: ReadS requests.

[0122] The monitoring information described in this article mainly refers to the monitoring information sent by the shared cache based on ReadS requests.

[0123] After receiving the monitoring information, the core can identify and process the cache access requests for accessing the local private cache therein.

[0124] Step S102, when it is identified that the cache access request is a request to access a locked cache line and it is determined that the locked cache line is a cache line in use by the core, send a delay signal to pause processing the monitoring information.

[0125] To extend the residence time of the lock in the private cache of the core (extend the time to release the locked cache line) and avoid frequent switching and acquisition of the lock, in an embodiment of the present invention, when it is identified that another core accesses the locked cache line and the locked cache line is in use by the core, a delay signal can be sent to pause processing the monitoring information. Therefore, the locking of the cache line can be maintained, that is, the residence time of the lock in the cache line can be extended.

[0126] Step S103, when an execution signal returned based on the delay signal is obtained, resume processing the monitoring information and release the locked cache line.

[0127] Among them, the locked cache line is implemented based on the lock obtained by the core executing the lock grabbing mechanism.

[0128] After obtaining the execution signal, the processing of the monitoring information can be resumed. At this time, the locked cache line can be released to facilitate access by other cores.

[0129] It can be seen that the technical solution provided by the embodiment of the present invention, due to the addition of a cache line lock control unit in the multi-core processor system, enables the cache line lock control unit to cooperate with each level of cache in each core, delay the cache processing access to the locked cache line, and the monitoring information of the cache line that is in use for the core, and delay the residence time of the lock in the cache. In order to maintain data consistency and improve the performance of the multi-core processor system, the multi-core processor system applies a cache consistency protocol to maintain data consistency; based on this, each level of cache of each core in the multi-core processor system has the function of cache consistency maintenance. The embodiment of the present invention, with the help of the cache consistency maintenance function of the cache, uses each level of cache to pre-identify the cache access request in the monitoring information after receiving the monitoring information and before processing the monitoring information; and when it is identified that the cache line requested by the cache access request is a cache line locked by the cache line, and the locked cache line is a cache line in use by the core, a delay signal is issued to cause the cache to delay the execution of the monitoring information and delay the release of the locked cache line. Thus, the core can maintain the lock on the cache line within the preset delay time indicated by the delay signal, so that when the core needs to use the locked cache line, each level of cache in the core can be prevented from frequently executing the operation of locking the cache line, thereby preventing the core from repeatedly executing the lock-grabbing mechanism to lock and unlock the cache line. Since each level of cache frequently executes the lock-grabbing mechanism, the lock is frequently switched between the cores, which will increase the system's additional performance overhead and the communication overhead between the cores. Therefore, the technical solution provided by the embodiment of the present invention, when it is determined that the cache line accessed by the cache access request is a locked cache line and is a cache line that is in use by the core, delays the release of the cache line, prolongs the retention time of the lock in the locked cache line, and within the preset delay time, the cache can no longer frequently execute the lock-grabbing mechanism to switch the lock, thereby improving the execution efficiency of the cache line locking mechanism, and further improving the overall performance of the multi-core processor system.

[0130] In one embodiment, step S102 may include:

[0131] When it is identified that the cache access request is a request for accessing a locked cache line and it is determined that the locked cache line includes locked data in a modified state, a delay signal is issued,

[0132] Alternatively, when it is identified that the cache access request is a request for accessing a locked cache line and it is determined that the cache line replacement policy indicates that data in the locked cache line is frequently replaced, a delay signal is issued.

[0133] The identification of the locked cache line can be achieved by identifying whether the cache line contains the lock obtained through the lock grabbing mechanism; whether the locked cache line is a cache line in use by the core can be determined by the status of the locked cache line. For example, it can be determined whether the modified status data is included in the locked cache line, or whether multiple lock acquisitions and releases occur for the locked cache line, etc., so as to promptly pause the core from processing the monitoring information and delay the release of the locked cache line, thereby reducing the number of lock switches and improving the execution efficiency of the lock grabbing mechanism.

[0134] In one implementation, step S103 may include:

[0135] When obtaining the execution signal returned based on the delay signal, generating a monitoring response based on the monitoring information, where the monitoring response indicates that the locked cache line has been released; and writing the data processing result at the preset delay moment back to the shared cache.

[0136] The monitoring response: SnpRspIWb, can notify the shared cache and other cores that the core that has successfully grabbed the lock has released its locked cache line, and the data in this cache line in the shared cache is the latest data (the data processing result at the preset delay moment): the data corresponding to the preset delay moment, so that other cores can obtain the latest data and ensure cache consistency.

[0137] Please continue to refer to Figure 5 , before step S101, the method further includes:

[0138] Step S110, initiate a cache access request.

[0139] The cache access request is initiated by the core.

[0140] Step S111, based on the type of the cache access request, receive the corresponding response signal; when the core in the multi-core processor system performs a lock acquisition operation to lock the cache line, the received response signal contains monitoring information.

[0141] The types of cache access requests are different, and the received response signals are also different to conform to different cache access scenarios.

[0142] Based on different cache access scenarios, the core initiates different types of cache access requests. Taking the first type of cache access request where the core first initiates a request to access exclusive state data as an example for illustration. Please refer to Figure 6 , Figure 6 is another flow diagram of the cache line locking control method provided by the embodiments of the present invention.

[0143] As Figure 6 shown, the method includes the following steps:

[0144] Step S200, initiate a first - type cache access request.

[0145] The first - type cache access request is a ReadE request.

[0146] Step S201, based on the first - type cache access request, receive a response signal formed by exclusive - state data.

[0147] The response signal corresponding to the ReadE request is formed by DataE.

[0148] Step S202, determine whether the cache line corresponding to the exclusive - state data is locked. If not, execute step S203; if so, execute step S204.

[0149] Determining whether the cache line corresponding to the exclusive - state data is locked can determine whether the core can successfully acquire the lock, so as to execute the lock - acquisition operation and lock the cache line of the exclusive - state data, making the cache line only available for the core itself.

[0150] Step S203, perform a locking operation to lock the cache line storing the exclusive - state data.

[0151] If it is determined that the cache line corresponding to the exclusive - state data is not locked, that is, the state of the cache line is not the modified state or the exclusive state, the core can perform a locking operation to lock the cache line.

[0152] Step S204, cancel the execution of the locking operation.

[0153] If it is determined that the cache line corresponding to the exclusive - state data is locked, that is, the state of the cache line is the modified state or the exclusive state, the core cancels the execution of the locking operation, and the core fails to acquire the lock.

[0154] After performing the locking operation to lock the cache line in step S203, it further includes:

[0155] Step S205, in response to the first - type cache access request sent by the core that cancels the locking operation, change the cache line in the modified state to the invalid state, initiate the first - type cache access request again, obtain the response signal formed by the exclusive - state data, and perform an unlocking operation.

[0156] Initiate the first - type cache access request again to unlock the locked cache line. After the core successfully acquires the lock, based on the first - type cache access request sent by other cores, the core that has successfully acquired the lock changes the modified state of the locked cache line to the invalid state at this time, and initiates the first - type cache access request again to unlock the locked cache line, notifying other cores that they can access this cache line.

[0157] Note that the unlocked cache line is still exclusive to this core at this time. Other cores can only access this cache line, and modifying the cache line is prohibited. Only when the cache line is released by the core will its state change to the shared state, and other cores can modify this cache line.

[0158] In some other embodiments, the type of the cache access request further includes a second type of cache access request for requesting access to shared state data; the method further includes:

[0159] Initiating the second type of cache access request; and receiving a response signal corresponding to the second type of cache access request.

[0160] After the shared cache receives the second type of cache access request, it will return a corresponding response signal regardless of whether the core successfully grabs the lock. Therefore, in order to facilitate the core to receive an accurate response signal for the second type of cache access request, the shared cache can also judge the execution situation of the core's lock-grabbing operation.

[0161] Exemplarily, the receiving the response signal corresponding to the second type of cache access request includes:

[0162] Judging the execution situation of the core's locking operation, and receiving the response signal corresponding to the second type of cache access request for different judgment results.

[0163] For the second type of cache access request (ReadS request), the shared cache will return different response signals to the core based on different execution situations of the core's locking operation. Therefore, the response signal received by the core is related to the current execution situation of its locking operation, so as to receive an accurate response signal.

[0164] The execution situation of the locking operation is related to the judgment result after the core obtains the exclusive state data. Therefore, based on the operations under different judgment results, the response signal returned for the second type of cache access request can be received.

[0165] Please continue to refer to Figure 6 as Figure 6 shown. When the execution situation of the core's locking operation is to execute the locking operation, the method further includes:

[0166] Step S206, receiving a response signal including monitoring information.

[0167] The core's execution of the locking operation indicates that the core has successfully grabbed the lock. At this time, the core will monitor the access situation of other cores to its local cache in real time. Therefore, the received response signal is a signal formed by the monitoring information, which is convenient for identifying the cache access request in the monitoring information. At this time, the cache access request in the monitoring information is a ReadS request.

[0168] Step S207, identify the second - type cache access requests in the monitored information.

[0169] Step S208, when it is identified that the second - type cache access request is a request to access a locked cache line and the locked cache line is a cache line with usage in the core, send a delay signal.

[0170] The cache line requested to be accessed by the second - type cache access request is the locked cache line in the internal cache of the core that has successfully grabbed the lock, and the locked cache line is a cache line with usage in the core that has successfully grabbed the lock. At this time, in order to prevent the core that has successfully grabbed the lock from executing the monitored information and then executing the lock - grabbing mechanism again, resulting in frequent lock switching, the processing of the monitored information is paused based on the delay signal, so that the core can continue to perform lock - locking and unlocking operations on the locked cache line based on the lock that has been successfully grabbed.

[0171] Step S209, perform data processing using the locked data in the locked cache line within a preset delay time.

[0172] Step S210, when an execution signal returned based on the delay signal is obtained, resume the processing of the monitored information and release the locked cache line.

[0173] Within the preset delay time, since the processing of the monitored information is paused, the lock that the core has successfully grabbed is still stored in the internal cache. Therefore, the core can quickly perform multiple lock - locking and unlocking operations using the grabbed lock, avoiding frequent lock switching and acquisition, and improving the execution efficiency of the lock - grabbing mechanism.

[0174] When it is determined that the execution situation of the core's lock - locking operation is: cancel the execution of the lock - locking operation, receive the response signal formed by the shared status data; the response signal formed by the shared status data is returned when the shared cache determines that the locked cache line has been released based on the received monitoring response.

[0175] Canceling the execution of the lock - locking operation indicates that the core fails to grab the lock. At this time, the response signal obtained by the core is the signal formed by the shared status data requested to be accessed by the second - type cache access request. Then, the shared status data can be obtained according to the shared status of the cache line corresponding to the shared status data.

[0176] Please continue to refer to Figure 6 , when the execution situation of the core's lock - locking operation is to cancel the execution of the lock - locking operation, the method further includes:

[0177] Step S211, initiate a second - type cache access request.

[0178] Step S212, when it is determined that the cache line accessed by the second type of cache access request has been released, receive a response signal formed by shared state data.

[0179] If the cache line corresponding to the shared state data has been released by the core that has successfully grabbed the lock, other cores are allowed to access the cache line to obtain the shared state data.

[0180] After obtaining the shared state data, the core can cache it in the local cache and modify the local cache state from the I state to the S state. Furthermore, the core can initiate a ReadE request to request exclusive access to the cache line.

[0181] The above describes multiple embodiment solutions provided by the embodiments of the present invention. The optional methods described in each embodiment solution can be combined and cross-referenced with each other without conflict, thereby extending a variety of possible embodiment solutions, all of which can be considered as the embodiment solutions disclosed and made public by the embodiments of the present invention.

[0182] Although the embodiments of the present invention are disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be subject to the scope defined by the claims.

Claims

1. A multi-core processor system, characterized in that, Comprising: Multiple cores and cache line locking control units; each core includes at least one level of cache; Each level of cache is used to identify cache access requests in the received snooping information; And when it is identified that the cache access request is a request to access a cache line locked at this level of cache, and it is determined that the locked cache line is a cache line with usage by the core, a delay signal is issued to pause processing the snooping information; when an execution signal returned based on the delay signal is obtained, resume processing the snooping information and release the locked cache line; The cache line locking control unit is used to receive the delay signals issued by each level of cache and issue an execution signal at a preset delay moment indicated by the delay signal; Wherein, the locked cache line is implemented based on a lock obtained by the core executing a lock stealing mechanism.

2. The multi-core processor system according to claim 1, characterized in that, The core is used to initiate cache access requests; The multi-core processor system further includes: A shared cache, which is used to return a corresponding response signal based on the type of the cache access request initiated by the core.

3. The multi-core processor system according to claim 2, wherein The types of the cache access requests include a first type of cache access request for requesting access to exclusive state data; when the cache access request initiated by the core is the first type of cache access request, the response signal returned by the shared cache based on the first type of cache access request is: a signal formed by the exclusive state data; Wherein, when it is determined that the cache line corresponding to the exclusive state data is not locked, the core is further used to perform a locking operation to lock the cache line of the exclusive state data; when it is determined that the cache line corresponding to the exclusive state data is locked, the core is further used to cancel the execution of the locking operation.

4. The multi-core processor system according to claim 3, characterized in that, After the core performs the locking operation, the core is further used to initiate the first type of cache access request again and unlock the locked cache line.

5. The multi-core processor system according to claim 3, wherein The types of the cache access requests further include a second type of cache access request for requesting access to shared state data; when the shared cache receives the second type of cache access request, the shared cache is further used to judge the execution situation of the core's locking operation, and for different judgment results, return a response signal corresponding to the second type of cache access request to the core; Wherein, when the judgment result is that the core executes the locking operation, the response signal returned corresponding to the second type of cache access request is a signal formed by snooping information; When the judgment result is to cancel the execution of the locking operation, and the shared cache determines that the locked cache line has been released according to the received snooping response, the response signal returned corresponding to the second type of cache access request is a signal formed by the shared state data.

6. The multi-core processor system according to any one of claims 1-5, characterized in that The core is further used to, when each level of cache issues the delay signal, within the preset delay moment indicated by the delay signal, perform data processing using the locked data in the locked cache line.

7. The multi-core processor system according to any one of claims 1-5, characterized in that, The cache line locking control unit is a timer; when the timer receives the delay signal issued by the cache, it starts timing, and when the timing value reaches the preset delay moment indicated by the delay signal, it issues an execution signal to the cache.

8. The multi-core processor system according to any one of claims 1-5, characterized in that, When each level of cache determines that the locked cache line includes locked data with a modified state, it determines that the locked cache line is a cache line with usage by the core, or, when it determines that the cache line replacement policy indicates that the locked cache line is frequently replaced, it determines that the locked cache line is a cache line with usage by the core.

9. A control method for cache line locking, characterized in that, Applied to the multi-core processor system as described in any one of claims 1-8, the method includes: Receiving snoop information and identifying the cache access requests in the snoop information; When it is identified that the cache access request is a request to access a locked cache line and it is determined that the locked cache line is a cache line with usage by the core, sending a delay signal to pause processing the snoop information; When an execution signal returned based on the delay signal is obtained, resume processing the snoop information and release the locked cache line; Wherein, the locked cache line is implemented based on the lock obtained by the core executing a lock stealing mechanism.

10. The control method for cache line locking according to claim 9, wherein Before the step of receiving snoop information, it further includes: Initiating a cache access request; Receiving a corresponding response signal based on the type of the cache access request; Wherein, when the core in the multi-core processor system performs a locking operation to lock a cache line, the received response signal contains snoop information.

11. The control method for cache line locking according to claim 10, characterized in that, The type of the cache access request includes a first type of cache access request for requesting access to exclusive state data; the receiving a corresponding response signal based on the type of the cache access request includes: Based on the first type of cache access request, receiving a response signal formed by exclusive state data; The method further includes: Based on the response signal formed by exclusive state data, determining whether the cache line corresponding to the exclusive state data has been locked; If not, performing a locking operation to lock the cache line of the exclusive state data; If so, canceling the execution of the locking operation.

12. The control method for cache line locking according to claim 11, characterized in that, After the step of performing the locking operation, it further includes: In response to a first type of cache access request sent by the core that cancels the locking operation, changing the cache line with a modified state to an invalid state; And, resending the first type of cache access request, obtaining a response signal formed by exclusive state data, and performing an unlocking operation to unlock the locked cache line.

13. The control method for cache line locking according to claim 12, wherein, The type of the cache access request further includes a second type of cache access request for requesting access to shared state data; after the step of canceling the execution of the locking operation, the method further includes: Initiating the second type of cache access request; And, receiving a response signal corresponding to the second type of cache access request.

14. The control method for cache line locking according to claim 13, wherein The receiving a response signal corresponding to the second type of cache access request includes: Judging the execution situation of the core's locking operation, and for different judgment results, receiving a response signal corresponding to the second type of cache access request.

15. The control method for cache line locking according to claim 14, characterized in that, The judging the execution situation of the core's locking operation, and for different judgment results, receiving a response signal corresponding to the second type of cache access request includes: When the judgment result is that the core performs a locking operation, receiving the response signal corresponding to the second type of cache access request as a signal formed by snoop information; When the judgment result is that the core cancels the lock operation, receive the response signal corresponding to the second type of cache access request as the response signal formed by the shared state data; Among them, the response signal is returned by the shared cache when the shared cache determines that the locked cache line has been released according to the received snoop response.

16. The control method for cache line locking according to claim 15, characterized in that, When the response signal corresponding to the second type of cache access request is the signal formed by the snoop information, the step of issuing a delay signal when it is recognized that the cache access request is a request to access a locked cache line and it is determined that the locked cache line is a cache line with a usage situation by the core includes: When it is recognized that the second type of cache access request is a request to access a locked cache line and the locked cache line includes locked data in a modified state, determine that the locked cache line is a cache line with a usage situation by the core and issue a delay signal.

17. The control method for cache line locking according to claim 16, wherein After the step of issuing the delay signal, it further includes: Within the preset delay time indicated by the delay signal, perform data processing using the locked data in the locked cache line.

18. The control method for cache line locking according to any one of claims 9-17, characterized in that, The step of issuing a delay signal when it is recognized that the cache access request is a request to access a locked cache line and it is determined that the locked cache line is a cache line with a usage situation by the core includes: When it is recognized that the cache access request is a request to access a locked cache line and it is determined that the locked cache line includes locked data in a modified state, issue a delay signal, Or, when it is recognized that the cache access request is a request to access a locked cache line and it is determined that the cache line replacement policy indicates that the data in the locked cache line is frequently replaced, issue a delay signal.

19. The control method for cache line locking according to any one of claims 9-17, characterized in that, The step of resuming the processing of the snoop information and releasing the locked cache line when the execution signal returned based on the delay signal is obtained includes: When the execution signal returned based on the delay signal is obtained, generate a snoop response based on the snoop information, and the snoop response indicates that the locked cache line has been released; And write the data processing result at the preset delay time back to the shared cache.

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