Storage device repair method and repair system

Abstract

The present application discloses a repair method and repair system for a storage device, relating to the field of storage technology. The repair method includes: determining a first number of failed storage cells corresponding to a target signal line among a plurality of first signal lines of a storage array and each first signal line group of the storage array; marking the target signal line as a first-class signal line in response to the first number of failed storage cells corresponding to the first signal line group being greater than the second number of first redundant signal lines corresponding to the second signal line group of the first signal line group; and replacing the first-class signal line with the second redundant signal line of the redundant storage array to achieve repair. The first-class signal line is obtained with high accuracy and speed, thereby improving the repair rate and efficiency of the failed storage cells.

Description

Technical Field

[0001] Embodiments of the present application relate to the field of storage technology, and in particular, to a method for repairing a storage device and a system for repairing a storage device. Background Art

[0002] Dynamic Random Access Memory (DRAM) chips, as storage devices, are now widely used in mobile phones, computers, servers, and other devices due to their simple structure, high integration, and low power consumption, playing a vital role in the consumer electronics sector. During the DRAM chip manufacturing process, failed memory cells may appear in the DRAM chip's memory array. To address this, a portion of the redundant memory array is reserved during DRAM chip design. The redundant memory cells in the redundant memory array are used to replace failed memory cells in the memory array, ensuring the normal operation of the DRAM chip.

[0003] Typically, in the process of repairing failed memory cells using redundant memory cells, redundant word lines or redundant bit lines of a redundant memory array are used to replace the word lines or bit lines of the memory array having failed memory cells, thereby enabling the redundant memory cells to repair the failed memory cells of the memory array. By improving the accuracy of determining the word lines that need to be replaced by redundant word lines, the repair rate and efficiency of the failed memory cells can be improved. Summary of the Invention

[0004] Embodiments of the present application provide a method for repairing a storage device and a system for repairing a storage device, which can optimize the determination of a first signal line that needs to be replaced with a second redundant signal line, improve the accuracy of determining the first signal line that needs to be replaced with the second redundant signal line, and increase the repair rate of a failed storage unit.

[0005] A method for repairing a storage device, wherein the storage device includes a storage array and a redundant storage array; the method comprising:

[0006] Determining a first number of failed memory cells corresponding to a target signal line among a plurality of first signal lines of the memory array and each first signal line group of the memory array; the first signal line extends along a first direction, the plurality of first signal lines are arranged at intervals along a second direction, and the second direction intersects the first direction; the plurality of first signal line groups are respectively arranged corresponding to the plurality of second signal line groups of the redundant memory array; the plurality of second signal lines of the first signal line group are arranged at intervals along the first direction and extend along the second direction; the plurality of first redundant signal lines of the second signal line group are parallel to the second signal lines;

[0007] In response to the first number of failed memory cells corresponding to the first signal line group existing on the target signal line being greater than the second number of first redundant signal lines corresponding to the second signal line group of the first signal line group, marking the target signal line as a first-category signal line;

[0008] The first type of signal line is replaced by the second redundant signal line of the redundant memory array to achieve repair.

[0009] In one embodiment, determining a first number of failed memory cells corresponding to a target signal line among a plurality of first signal lines of the memory array and each first signal line group of the memory array includes:

[0010] determining a third number of the failed storage cells on each of the first signal lines;

[0011] In response to a third number of failed memory cells on the first signal line being less than or equal to a fourth number of the first redundant signal lines of the redundant memory array, using the first signal line as the target signal line;

[0012] A first number of the failed memory cells on the target signal line corresponding to each of the first signal line groups is determined.

[0013] In one embodiment, in response to the third number of failed memory cells on the first signal line being less than or equal to the fourth number of the first redundant signal lines of the redundant memory array, using the first signal line as the target signal line includes:

[0014] In response to the third number of failed memory cells on the first signal line being less than or equal to the fourth number of the first redundant signal lines of the redundant memory array, using the first signal line as a first intermediate target signal line;

[0015] In response to the third number of failed memory cells on the first intermediate target signal line being greater than the second number of the first redundant signal lines of each of the second signal line groups, the first intermediate target signal line is used as the target signal line.

[0016] In one embodiment, in response to the third number of failed memory cells on the first signal line being less than the fourth number of the first redundant signal lines of the redundant memory array, using the first signal line as the target signal line includes:

[0017] In response to the third number of failed memory cells on the first signal line being greater than the second number of the first redundant signal lines of each of the second signal line groups, using the first signal line as a second intermediate target signal line;

[0018] In response to the third number of failed memory cells on the second intermediate target signal line being less than or equal to the fourth number of the first redundant signal lines of the redundant memory array, the second intermediate target signal line is used as the target signal line.

[0019] In one embodiment, determining a first number of failed memory cells corresponding to a target signal line among a plurality of first signal lines of the memory array and each first signal line group of the memory array includes:

[0020] determining a third number of the failed storage cells on each of the first signal lines;

[0021] selecting the first signal lines as the target signal lines in descending order of the third number of failed storage cells on the first signal lines;

[0022] The first number of the failed memory cells on the target signal line corresponding to each of the first signal line groups is determined.

[0023] In one embodiment, the method for repairing a storage device further includes:

[0024] determining a third number of the failed storage cells on each of the first signal lines;

[0025] In response to the third number of failed memory cells on the first signal line being greater than the fourth number of the first redundant signal lines of the redundant memory array, the first signal line is directly marked as the first-type signal line.

[0026] In one embodiment, in response to the first number of failed memory cells corresponding to the first signal line group existing on the target signal line being greater than the second number of first redundant signal lines corresponding to the second signal line group of the first signal line group, marking the target signal line as a first-category signal line includes:

[0027] sequentially acquiring the first number of failed memory cells corresponding to the target signal line and each of the first signal line groups;

[0028] In response to the first number of failed storage cells corresponding to any one of the first signal line groups being greater than the second number corresponding to the first signal line group, a flag bit of the signal line address corresponding to the target signal line in the failure repair array is set to mark the first type of signal line.

[0029] In one embodiment, the first signal line is a word line, the second signal line is a bit line, the first redundant signal line is a redundant bit line, and the second redundant signal line is a redundant word line.

[0030] A repair system for a storage device, wherein the storage device includes a storage array and a redundant storage array, and the repair system includes:

[0031] An acquisition module is configured to determine a first number of failed memory cells corresponding to a target signal line among a plurality of first signal lines of the memory array and each first signal line group of the memory array; the first signal lines extend along a first direction, the plurality of first signal lines are spaced apart along a second direction, and the second direction intersects the first direction; the plurality of first signal line groups are respectively arranged corresponding to the plurality of second signal line groups of the redundant memory array; the plurality of second signal lines of the first signal line group are spaced apart along the first direction and extend along the second direction; and the plurality of first redundant signal lines of the second signal line group are parallel to the second signal lines;

[0032] a computing module connected to the acquiring module and configured to mark the target signal line as a first-category signal line in response to the first number of failed storage cells corresponding to the first signal line group existing on the target signal line being greater than the second number of first redundant signal lines corresponding to the second signal line group of the first signal line group;

[0033] A repair module is connected to the operation module and is used to replace the first type of signal line with the second redundant signal line of the redundant storage array to achieve repair; the second redundant signal line is parallel to the first signal line.

[0034] A storage device repair system, comprising:

[0035] Main control device;

[0036] A storage device connected to the main control device, the storage device comprising:

[0037] A memory die, comprising at least one memory module, wherein the memory module comprises a memory array and a redundant memory array;

[0038] The main control device is connected to the storage chip and is used to obtain the failed storage information of the failed storage unit of the storage array, and execute the above-mentioned repair method of the storage device according to the failed storage information to generate repair information, wherein the repair information includes corresponding information of the second redundant signal line and the first type signal line of the redundant storage array.

[0039] In one embodiment, the storage device further includes:

[0040] a control chip, connected to the main control device and the storage chip respectively, and used to generate a repair signal according to the repair information;

[0041] The memory chip is used for replacing the first type of signal line with the second redundant signal line of the redundant memory array according to the repair signal to implement repair.

[0042] In one embodiment, the memory chip includes a plurality of memory groups, each memory group includes a plurality of memory modules, and the control chip includes a redundant loading device and a plurality of control devices, wherein the redundant loading device is respectively connected to the main control device and the plurality of control devices, and the plurality of control devices are respectively connected to the plurality of memory groups.

[0043] The redundant loading device is used to generate a plurality of repair control signals according to the repair information; the plurality of repair control signals respectively correspond to the plurality of control devices;

[0044] The control device is configured to output corresponding repair signals to the connected plurality of storage modules according to the repair control signal output by the connected redundant loading device.

[0045] In the above-mentioned repair method for the storage device, when the first number of failed storage units corresponding to the target signal line and each first signal line group is greater than the second number of the first redundant signal lines of the second signal line group corresponding to the first signal line group, the target signal line is determined to be a first-type signal line that needs to be replaced with the second redundant signal line, so that the first-type signal line is obtained with high accuracy and high speed, thereby improving the repair rate and efficiency of the failed storage unit.

[0046] In the repair system of the above-mentioned storage device, when the first number of failed storage units corresponding to the target signal line and each first signal line group is greater than the second number of the first redundant signal lines of the second signal line group corresponding to the first signal line group, the computing module determines that the target signal line is a first-type signal line that needs to be replaced with the second redundant signal line. The first-type signal line is obtained with high accuracy and speed, thereby improving the rate and efficiency of the repair module in repairing the failed storage unit.

[0047] In the repair system of the above-mentioned storage device, during the process of generating repair information, the main control device determines that the target signal line is a first-type signal line that needs to be replaced with a second redundant signal line when the first number of failed storage units corresponding to the target signal line and each first signal line group is greater than the second number of first redundant signal lines of the second signal line group corresponding to the first signal line group. The first-type signal line is obtained with high accuracy and high speed, thereby improving the repair rate and efficiency of the failed storage unit. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] In order to more clearly illustrate the technical solutions in the embodiments of the present application or related technologies, the following briefly introduces the drawings required for use in the embodiments or related technical descriptions. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0049] Figure 1 This is one of the structural diagrams of the storage device in the embodiment of the present application;

[0050] Figure 2 This is one of the flowcharts of the method for repairing a storage device according to an embodiment of the present application;

[0051] Figure 3 This is one of the corresponding schematic diagrams of the first signal line group and the second signal line group of the storage device in an embodiment of the present disclosure;

[0052] Figure 4 This is one of the structural diagrams of the repair system for a storage device according to an embodiment of the present disclosure;

[0053] Figure 5 This is a second structural diagram of a repair system for a storage device according to an embodiment of the present disclosure;

[0054] Figure 6 This is the third structural diagram of the repair system for a storage device according to an embodiment of the present disclosure;

[0055] Figure 7 This is a fourth structural diagram of a repair system for a storage device according to an embodiment of the present disclosure;

[0056] Figure 8 This is a fifth structural diagram of a repair system for a storage device according to an embodiment of the present disclosure;

[0057] Figure 9 This is the sixth structural diagram of the repair system for a storage device in an embodiment of the present disclosure.

[0058] Description of reference numerals:

[0059] First signal line group 10; second signal line group 20; acquisition module 102; computing module 104; repair module 106; main control device 202; storage device 204; storage die 302; control die 304; storage group 400; storage module 402; redundant loading device 404; control device 406. DETAILED DESCRIPTION

[0060] To facilitate understanding of the embodiments of the present application, a more comprehensive description of the embodiments of the present application will be provided below with reference to the accompanying drawings. The accompanying drawings provide preferred embodiments of the embodiments of the present application. However, the embodiments of the present application can be implemented in many different forms and are not limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and comprehensive disclosure of the embodiments of the present application.

[0061] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art to which the embodiments of the present application pertain. The terms used herein in the description of the embodiments of the present application are intended only to describe specific embodiments and are not intended to limit the embodiments of the present application. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0062] In the description of the embodiments of the present application, it should be understood that the terms "upper", "lower", "vertical", "horizontal", "inside", "outside", etc., indicating orientations or positional relationships, are based on the methods or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the embodiments of the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the embodiments of the present application.

[0063] It should be understood that the terms "first," "second," and the like used herein may be used to describe various elements herein, but these elements are not limited by these terms. These terms are used solely to distinguish a first element from another element. For example, a first signal line may be referred to as a second signal line, and similarly, a second signal line may be referred to as a first signal line, without departing from the scope of this application. The first signal line and the second signal line are both signal lines, but they are not the same signal line.

[0064] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include at least one of the features. In the description of this application, the meaning of "plurality" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined. In the description of this application, the meaning of "several" is at least one, such as one, two, etc., unless otherwise clearly and specifically defined.

[0065] Figure 1 This is one of the structural diagrams of the storage device in the embodiment of the present application, see Figure 1The memory device includes a memory array and a redundant memory array; wherein the memory array includes word lines (WL) and bit lines (BL), one of the word lines and the bit lines extends along a first direction X, and the other extends along a second direction Y intersecting the first direction X, and the memory cell is located at the intersection of the word line and the bit line on the plane (for ease of explanation, Figure 1 Indicated by a black dot in the figure, the intersection position is a virtual position). " shows a failed memory cell in a memory array; the redundant memory array includes redundant word lines (YWL) and redundant bit lines (YBL), the redundant word lines and word lines extend in the same direction, and the redundant bit lines and bit lines extend in the same direction. Figure 1 The redundant memory cells in the system are located at the intersection of the redundant word lines and the bit lines on the plane, and the intersection of the redundant bit lines and the word lines on the plane ( Figure 1 (shown as a black dot in the figure, the intersection position is a virtual position), the redundant storage cells in the redundant storage array are used to repair the failed storage cells in the storage array. As an example, Figure 1 In the embodiment, the word line extends along the first direction X, and a plurality of word lines are arranged at intervals along the second direction Y. The bit line extends along the second direction Y, and a plurality of bit lines are arranged at intervals along the first direction X. Furthermore, the first direction X is perpendicular to the second direction Y. As an example, Figure 1 For example, a memory array includes eight word lines WL0 ˜ WL7 and eight bit lines BL0 ˜ BL7 , and a redundant memory array includes three redundant word lines YWL0 ˜ YWL2 and four redundant bit lines YBL0 ˜ YBL3 .

[0066] It can be understood that when the redundant memory cells in the redundant memory array repair the failed memory cells in the memory array, the signal line addresses of the word lines and / or bit lines are mapped to the redundant word lines and / or the redundant signal line addresses of the redundant word lines, so that the redundant memory cells in the redundant memory array repair the failed memory cells in the memory array.

[0067] In the process of repairing failed memory cells using redundant memory cells, it was discovered that even when the number of failed memory cells on a word line WLx of a memory array is less than the number of redundant bit lines in the redundant memory array, it is still impossible to use the redundant bit lines in the redundant array to replace the bit lines corresponding to the failed memory cells on the word line WLx to repair the failed memory cells on the word line WLx. Therefore, how to accurately determine which word line needs to be replaced by the redundant word lines in the redundant array has become an urgent problem to be solved.

[0068] Figure 2 This is one of the flow charts of the method for repairing a storage device in an embodiment of the present application, see Figure 2In order to solve the above problem, in this embodiment, a method for repairing a storage device is provided. The storage device includes a storage array and a redundant storage array. The repair method includes:

[0069] S102 , determining a first number of failed memory cells corresponding to a target signal line among a plurality of first signal lines of a memory array and each first signal line group of the memory array.

[0070] The memory array includes a plurality of first signal lines and a plurality of first signal line groups, each of which includes a plurality of second signal lines; the redundant memory array includes a plurality of second signal line groups and a plurality of second redundant signal lines, each of which includes a plurality of first redundant signal lines, the plurality of first signal line groups are respectively arranged corresponding to the plurality of second signal line groups, the first signal lines extend along a first direction, the plurality of first signal lines are arranged at intervals along a second direction, the second signal lines extend along the second direction, the plurality of second signal lines are arranged at intervals along the first direction, the first redundant signal lines are parallel to the second signal lines, and the second redundant signal lines are parallel to the first signal lines; wherein the second direction intersects with the first direction.

[0071] It is understood that the number of second signal lines in the first signal line group is greater than the number of first redundant signal lines in the second signal line group. As an example, the number of second signal lines in each first signal line group is the same, and the number of first redundant signal lines in each second signal line group is the same.

[0072] Multiple first signal line groups are respectively configured to correspond to multiple second signal line groups. It can be understood that the addresses of the multiple first redundant signal lines of the second signal line group correspond to the addresses of the multiple second signal line of the first signal line group, where the first redundant signal line address is the address of the first redundant signal line, and the second signal line address is the address of the second signal line. The first redundant signal line of the second signal line group is used to replace any second signal line of the first signal line group that has a failed memory cell, thereby repairing the failed memory cell on the second signal line.

[0073] In the process of replacing the second signal line corresponding to the first signal line group with a failed storage unit by the first redundant signal line, the second signal lines with the failed storage unit can be replaced in sequence according to the arrangement direction of the second signal line addresses of the second signal lines of the first signal line group, or the second signal lines with the failed storage unit can be replaced in sequence according to the order from largest to smallest in the number of failed storage units on the second signal line of the first signal line group.

[0074] It can be understood that one of the first signal line and the second signal line is a word line, and the other is a bit line. The redundant signal line corresponding to the word line is a redundant word line, and the redundant signal line corresponding to the bit line is a redundant bit line.

[0075] The following describes the repair method of the storage device of the present application by taking the first signal line as a word line WL, the second signal line as a bit line BL, the first redundant signal line as a redundant bit line YBL, and the second redundant signal line as a redundant word line YWL as an example.

[0076] See also Figure 1 The memory array schematically includes two first signal line groups 10, each of which includes a plurality of second signal lines. Figure 1 Each first signal line group 10 schematically includes four second signal lines. For ease of description, the two first signal line groups 10 are group A1 and group A2. Group A1 includes second signal lines BL0 to BL3, and group A2 includes second signal lines BL4 to BL7. The redundant memory array schematically includes two second signal line groups 20. Each second signal line group 20 includes multiple first redundant signal lines. Figure 1 Each second signal line group 20 schematically includes two first redundant signal lines. For the convenience of description, the two second signal line groups 20 are respectively group B1 and group B2. Group B1 includes first redundant signal lines YBL0 to YBL1, and group B2 includes first redundant signal lines YBL2 to YBL3. The two first signal line groups 10 are respectively arranged corresponding to the two second signal line groups 20, that is, one of group A1 and group A2 is arranged corresponding to group B1, and the other is arranged corresponding to group B2.

[0077] Figure 3 This is one of the corresponding schematic diagrams of the first signal line group and the second signal line group of the storage device in the embodiment of the present disclosure, see Figure 3 , Figure 3The corresponding memory array includes n first signal lines WL0 to WLn-1 and 16 first signal line groups 10, each of which includes 64 second signal lines. For ease of description, the 16 first signal line groups 10 are group A0, group A2, ..., group A15, group A0 includes second signal lines BL0 to second signal lines BL63, group A1 includes second signal lines BL64 to second signal lines BL127, ..., group A15 includes second signal lines BL960 to second signal lines BL1023, and the redundant memory array includes m second redundant signal lines YWL0 to YWLm-1 and 16 second signal line groups 20, each of which includes 64 second signal lines. The signal line group 20 includes three first redundant signal lines. For ease of description, the 16 second signal line groups 20 are respectively group B0, group B1, ..., group B15, group B0 includes first redundant signal lines YBL0 to first redundant signal lines YBL2, group B1 includes first redundant signal lines YBL3 to first redundant signal lines YBL5, ..., group B15 includes first redundant signal lines YBL45 to first redundant signal lines YBL47; the 16 first signal line groups 10 and the 16 second signal line groups 20 are respectively arranged in correspondence; as an example, group A0 and group B0 are arranged in correspondence, group A1 and group B1 are arranged in correspondence, ..., group A15 and group B15 are arranged in correspondence, Figure 3 According to the corresponding relationship between the first signal line group 10 and the second signal line group 20, the multiple second signal lines of the first signal line group 10 and the multiple first redundant signal lines corresponding to the second signal line group 20 are arranged adjacent to each other, but it can be understood that in the physical structure of the storage device, the second signal line of the A0 group and the second signal line of the A1 group are adjacent to each other.

[0078] A storage array includes storage cells. Data is written to and read from each storage cell in the storage array. If the read data matches the written data, the storage cell is considered normal. If the read data matches the written data, the storage cell is considered faulty. A faulty storage cell is an abnormal storage cell that needs to be repaired.

[0079] A target signal line is selected from a plurality of first signal lines WL0 to WLn-1 of the memory array, and a first number ebit_cnt of failed memory cells corresponding to the target signal line and each first signal line group (group A0 to group A15) is determined. The plurality of first numbers (ebit_cnt0 to ebit_cnt15) correspond one-to-one to the plurality of first signal line groups (group A0 to group A15). The first number ebit_cnt of failed memory cells corresponding to the first signal line group (one of the groups A0 to group A15) can be understood as the number of failed memory cells simultaneously connected to the target signal line and the second signal line of the first signal line group (one of the groups A0 to group A15).

[0080] After writing data to the memory cells on the target signal line, data is read from the memory cells on the target signal line that are connected to multiple second signal lines of any first signal line group (one of groups A0 to A15). The number of memory cells for which the read data is inconsistent with the written data is counted. The resulting number is the first number, ebit_cnt, of failed memory cells corresponding to the target signal line and the first signal line group (one of groups A0 to A15). The first number, ebit_cnt, of failed memory cells corresponding to the target signal line and each first signal line group is determined using the above method.

[0081] See also Figure 3 A target signal line (e.g., word line WL3) is selected from the n word lines WL0 to WLn-1 of the memory array. A first number ebit_cnt of failed memory cells corresponding to word line WL3 and each first signal line group (groups A0 to A15) is determined. The 16 first numbers ebit_cnt correspond one-to-one to the 16 first signal line groups, i.e., the first number ebit_cnt0 corresponds to group A0, the first number ebit_cnt1 corresponds to group A1, ..., and the first number ebit_cnt15 corresponds to group A15. The first number ebit_cnt0 corresponding to group A0 is the number of failed memory cells on word line WL3 connected to bit lines BL0 to BL63 of group A0.

[0082] As an example, data of 64 memory cells corresponding to word line WL3 and A0 group are read in sequence, and memory cells whose read data are inconsistent with written data are counted. The value obtained by counting is the first number ebit_cnt0 of failed memory cells corresponding to A0 group on word line WL3, and the first number ebit_cnt1 to the first number ebit_cnt15 of failed memory cells corresponding to word line WL3 and A1 group to A15 group are determined in sequence.

[0083] S104 , in response to a first number of failed memory cells corresponding to the first signal line group on the target signal line being greater than a second number of first redundant signal lines corresponding to the second signal line group of the first signal line group, marking the target signal line as a first type signal line.

[0084] Compare the target signal line with the multiple first numbers ebit_cnt corresponding to the multiple first signal line groups, and the second number of the first redundant signal lines of the second signal line group corresponding to each first signal line group. If there is a first number ebit_cnt corresponding to the first signal line group that is greater than the second number of the first redundant signal lines of the second signal line group corresponding to the first signal line group, it is determined that the first redundant signal line cannot be used to replace the second signal line to repair all failed storage cells on the target signal line, and the target signal line is marked as a first-category signal line; wherein the second number is the number of the first redundant signal lines of the second signal line group. Figure 3 For example, the second number of the first redundant signal lines of groups B0 to B15 is 3, and the word line WL3 is used as the target signal line. When the first number ebit_cnt0 of the failed storage cells corresponding to group A0 on the target signal line (word line WL3) is 4 and the first number ebit_cnt1 of the failed storage cells corresponding to group A1 on the target signal line (word line WL3) is 1, the first number ebit_cnt0 (4) of the failed storage cells corresponding to group A0 and the second number (3) of the first redundant signal line of group B0 corresponding to group A0 are compared. When the first number ebit_cnt0 (4) is greater than the second number ebit_cnt1 (3), the first number ebit_cnt0 (4) of the failed storage cells corresponding to group A0 is greater than the second number ebit_cnt1 (3). When the number (3) is equal to or greater than the first number of failed storage cells corresponding to the first signal line group on the target signal line (word line WL3), it is determined that the first number of failed storage cells corresponding to the first signal line group on the target signal line (word line WL3) is greater than the second number of the second redundant signal lines of the second signal line group corresponding to the first signal line group, that is, the first number ebit_cnt0(4) of failed storage cells corresponding to the A0 group on the target signal line (word line WL3) is greater than the second number (3) of the first redundant signal lines of the B0 group corresponding to the A0 group, and the target signal line (word line WL3) is marked as a first-category signal line. The first-category signal line is a first signal line that needs to be replaced with a second redundant signal line to repair the failed storage cell located thereon.

[0085] It can be understood that if the first number ebit_cnt0 of failed memory cells corresponding to group A0 is less than or equal to the second number of first redundant signal lines of group B0, the first number ebit_cnt of failed memory cells corresponding to the remaining first signal line groups will continue to be compared with the second number of first redundant signal lines of the second signal line groups corresponding to each first signal line group until the first number ebit_cntx of failed memory cells corresponding to group Ax is greater than the second number of first redundant signal lines of group Bx corresponding to group Ax, or until the first number ebit_cnt15 of failed memory cells corresponding to group A15 is compared with the second number of first redundant signal lines of group B15 corresponding to group A15, and then the judgment of the target signal line (word line WL3) is terminated.

[0086] For example, the above flags can be recorded in a fail repair array (ebit_cnt_main_row). Table 1 shows the flag WL_Flag corresponding to the signal line address of each first signal line in the fail repair array (ebit_cnt_main_row). For example, the storage array includes: Figure 3 As shown, n first signal lines WL0 to WLn-1 are represented in the failure repair array as WL0 to WLn-1, and the failure repair array (ebit_cnt_main_row) has n flag bits of n flags WL_Flag corresponding to the signal line addresses of the first signal lines WL0 to the first signal line WLn-1. When the first number ebit_cnt0 (4) of failed storage cells corresponding to the first signal line group (e.g., group A0) on the target signal line (word line WL3) is greater than the second number (3) of first redundant signal lines included in group B0 corresponding to group A0, the flag bit of the flag WL_Flag of the signal line address WL3 corresponding to the target signal line (word line WL3) is set (e.g., changed from 0 to 1) to mark the target signal line (word line WL3) as a first-class signal line.

[0087] Table 1

[0088]

[0089] S106: Use the second redundant signal line of the redundant memory array to replace the first type of signal line to achieve repair.

[0090] Any second redundant signal line of the redundant memory array is used to replace the first type of signal line, so as to repair the failed memory cell on the first type of signal line.

[0091] by Figure 3 For example, one of the second redundant signal lines YWL0 to YWLm-1 is used to replace the word line (e.g., word line WL3) marked as the first type of signal line in step S104 to repair the failed memory cell on word line WL3.

[0092] It can be understood that after the first type of signal line is replaced with the second redundant signal line of the redundant memory array, the number of failed memory cells on the first type of signal line is cleared, that is, the third number ebit_cnt_row3 of failed memory cells of the first type of signal line (for example, word line WL3) is cleared. The third number ebit_cnt_row can be understood as the total number of failed memory cells on one first signal line, that is, the sum of the first numbers (ebit_cnt0 to ebit_cnt15) of failed memory cells corresponding to the first signal line (for example, word line WL3) and each first signal line group (A0 group to A15 group) of the memory array.

[0093] by Figure 3 For example, after the word line (eg, WL3 ) marked as the first type signal line in step S104 is replaced by the second redundant signal line (eg, YWL0 ), the third number ebit_cnt_row3 of failed memory cells on the word line WL3 is cleared.

[0094] It can be understood that the second number of the first redundant signal lines of the second signal line group 20 is the number of the first redundant signal lines in the second signal line group 20 that have not been used to replace the second signal lines, for example, Figure 3 If a failed memory cell corresponding to the first signal line WL0 and the first signal line WL1 exists on the second signal line BL1 in the A0 group, the first redundant signal line YBL0 of the B0 group corresponding to the A0 group is used to replace the second signal line BL1. After that, the third numbers ebit_cnt_row0 and ebit_cnt_row1 of failed memory cells corresponding to the first signal line WL0 and the first signal line WL1 are both reduced by 1, and the second number of the first redundant signal line of the B0 group corresponding to the A0 group is also reduced by 1. In the above-mentioned memory device repair method, if, among the first numbers (ebit_cnt0 to ebit_cnt15) of failed memory cells corresponding to each of the first signal line groups (groups A0 to A15) on the target signal line, the first number of at least one of the first signal line groups is greater than the second number of the first redundant signal line of the corresponding second signal line group, the target signal line is determined to be a first-category signal line that needs to be replaced with the second redundant signal line. This provides high accuracy and speed in obtaining the first-category signal line, thereby improving the repair rate and efficiency of the failed memory cells.

[0095] In some embodiments, the aforementioned step S102 of "determining a first number of failed memory cells corresponding to a target signal line among a plurality of first signal lines of the memory array and each first signal line group of the memory array" further includes: S1021: determining a third number of failed memory cells on each first signal line; S1022: in response to the third number of failed memory cells on the first signal line being less than or equal to a fourth number of first redundant signal lines of the redundant memory array, using the first signal line as a target signal line; S1024: determining the first number of failed memory cells corresponding to each first signal line group on the target signal line.

[0096] S1021: Data is written to and read from each storage cell on the first signal line, and the number of storage cells on the first signal line whose read data is inconsistent with the written data is counted, which is the third number ebit_cnt_row of failed storage cells on the first signal line; the above steps are repeated to obtain the third number (ebit_cnt_row0 to ebit_cnt_rown-1) of failed storage cells on each first signal line (WL0 to WLn-1) in sequence.

[0097] S1022: Obtain the total number of first redundant signal lines of the redundant memory array, that is, the fourth number of first redundant signal lines of the redundant memory array. It can be understood that the fourth number is the sum of the second numbers of first redundant signal lines of each second signal line group; compare the third number ebit_cnt_row and the fourth number of failed memory cells on the first signal line. If the third number ebit_cnt_row is less than or equal to the fourth number, use the first signal line as the target signal line.

[0098] S1024: Determine the first number of failed memory cells on the target signal line corresponding to each first signal line group. For specific steps, refer to the method of determining the first number of failed memory cells on the target signal line corresponding to each first signal line group in S102 above, which will not be repeated here.

[0099] by Figure 3 For example, data is written and read for 1024 memory cells on word line WL0, and the number of memory cells whose read data is different from the written data is counted, which is the third number ebit_cnt_row0 of failed memory cells on word line WL0. That is, the third number ebit_cnt_row0 is the total number of failed memory cells on word line WL0. The third numbers ebit_cnt_row1 to ebit_cnt_rown-1 of failed memory cells on word lines WL1 to WLn-1 are determined in sequence. If the third number ebit_cnt_rowx of failed memory cells on word line WLx is less than or equal to the fourth number, word line WLx is determined as the target signal line (it needs to be further confirmed whether it is a first-type signal line). The fourth number is the total number of first redundant signal lines in the redundant memory array, that is, the fourth number is the sum of the second numbers of first redundant signal lines of each second signal line group. Figure 3 The fourth number of first redundant signal lines in the redundant memory array is, for example, 48. When the third number ebit_cnt_rowx of failed memory cells on word line WLx is less than or equal to the fourth number (e.g., 48), word line WLx is used as the target signal line, that is, the target signal line is selected from the first signal lines where the number of failed memory cells ebit_cnt_rowx is ≤ 48.

[0100] Determine a first number ebit_cnt0 of failed memory cells on the target signal line (word line WLx) connected to multiple second signal lines (bit line BL0 to bit line BL63) of the A0 group; determine a first number ebit_cnt1 of failed memory cells connected to the target signal line (word line WLx) and multiple second signal lines (bit line BL64 to bit line BL127) of the A1 group, ..., determine a first number ebit_cnt15 of failed memory cells simultaneously connected to the target signal line (word line WLx) and multiple second signal lines (bit line BL960 to bit line BL1023) of the A15 group, that is, determine a first number ebit_cnt (first number ebit_cnt0 to first number ebit_cnt15) of failed memory cells corresponding to the target signal line (word line WLx) and each first signal line group.

[0101] By comparing the third number of failed memory cells on the first signal line and the fourth number of the first redundant signal lines of the redundant memory array, the first signal lines whose third number is less than or equal to the fourth number are used as target signal lines, and the first signal lines that can be directly determined as first-category signal lines are removed from the first signal lines, that is, the first signal lines that do not need to be used as target signal lines are removed, and the first signal lines that need to be further determined whether they need to be used as first-category signal lines are obtained. The number of first signal lines used as target signal lines is reduced, the determination rate of first-category signal lines is increased, and the repair rate and repair efficiency of failed memory cells are improved.

[0102] In some embodiments, S1022: in response to the third number of failed memory cells on the first signal line being less than or equal to the fourth number of the first redundant signal lines of the redundant memory array, the first signal line is used as the target signal line, further comprising: in response to the third number of failed memory cells on the first signal line being less than or equal to the fourth number of the first redundant signal lines of the redundant memory array, the first signal line is used as the first intermediate target signal line (S10221); in response to the third number of failed memory cells on the first intermediate target signal line being greater than the second number of the first redundant signal lines of each second signal line group, the first intermediate target signal line is used as the target signal line (S10222).

[0103] S10221: Compare a third number ebit_cnt_row of failed memory cells on the first signal line with a fourth number of first redundant signal lines of the redundant memory array; if the third number ebit_cnt_row is less than or equal to the fourth number, use the first signal line as a first intermediate signal line.

[0104] By comparing the third number ebit_cnt_row of failed memory cells on the first signal line with the fourth number of the first redundant signal lines of the redundant memory array, first signal lines that can be directly determined as first-category signal lines are removed from the first signal lines, and first signal lines that require further determination as first-category signal lines are obtained. These first signal lines are used as first intermediate signal lines, thereby preliminarily reducing the number of first signal lines that serve as target signal lines.

[0105] S10222: Compare the third number ebit_cnt_row of failed storage cells on the first intermediate signal line with the second number of the first redundant signal lines of each second signal line group. When the third number ebit_cnt_row of failed storage cells on the first intermediate signal line is greater than the second number of the first redundant signal lines of each second signal line group (for example, each second number is equal to 3, or the minimum value of the second numbers), use the first intermediate target signal line as the target signal line.

[0106] By comparing the third number ebit_cnt_row of failed storage cells on the first intermediate target signal line and the second number of the first redundant signal lines of each second signal line group, the first signal lines that can be replaced by the first redundant signal lines to repair the failed storage cells in the first intermediate target signal lines are removed, thereby further reducing the number of first signal lines serving as target signal lines and improving the determination rate of the first type of signal lines.

[0107] by Figure 3 For example, the third number ebit_cnt_rowx and the fourth number (48) of failed memory cells on the word line WLx are compared. If the third number ebit_cnt_rowx is less than or equal to the fourth number (48), the word line WLx is used as the first intermediate target signal line, that is, the first signal line with the number of failed memory cells less than or equal to the fourth number (48) is selected as the first intermediate target signal line. If the third number ebit_cnt_rowx of failed memory cells on the word line WLx as the first intermediate target signal line is less than or equal to the second number (3) of the first redundant signal lines of each second signal line group, it is determined that the first redundant signal line can be used to replace the second signal line to repair the failed memory cell on the word line WLx (the first intermediate target signal line), and the word line WLx does not need to be used as the target signal line to determine whether it is a first-class signal line. When the third number ebit_cnt_rowx of failed storage cells on the word line WLx (the first intermediate target signal line) is greater than the second number (3) of the first redundant signal lines of each second signal line group, it is determined that further judgment needs to be made on the word line WLx (the first intermediate target signal line) and it is used as the target signal line.

[0108] In some embodiments, S1022: in response to the third number of failed memory cells on the first signal line being less than the fourth number of the first redundant signal lines of the redundant memory array, the first signal line is used as the target signal line, further comprising: in response to the third number of failed memory cells on the first signal line being greater than the second number of the first redundant signal lines of each second signal line group, the first signal line is used as the second intermediate target signal line (S10223); in response to the third number of failed memory cells on the second intermediate target signal line being less than or equal to the fourth number of the first redundant signal lines of the redundant memory array, the second intermediate target signal line is used as the target signal line (S10224).

[0109] S10223: Compare the third number ebit_cnt_row of failed storage cells on the first signal line with the second number of first redundant signal lines of each second signal line group. When the third number ebit_cnt_row of failed storage cells on the first signal line is greater than the second number of first redundant signal lines of each second signal line group (for example, each second number is equal to 3, or the minimum value of the second numbers), use the first signal line as the second intermediate target signal line.

[0110] By comparing the third number ebit_cnt_row of failed storage cells on the first signal line and the second number of the first redundant signal lines of each second signal line group, first signal lines that can be replaced by the first redundant signal lines to repair failed storage cells are removed from the first signal lines, and first signal lines that need to be further determined whether they need to be first-category signal lines are obtained. These first signal lines are used as second intermediate signal lines, thereby preliminarily reducing the number of first signal lines that serve as target signal lines.

[0111] S10224: Compare the third number ebit_cnt_row of failed memory cells on the second intermediate target signal line and the fourth number of the first redundant signal line of the redundant memory array; if the third number is less than or equal to the fourth number, use the second intermediate target signal line as the target signal line.

[0112] By comparing the third number ebit_cnt_row of failed storage cells on the second intermediate target signal line and the fourth number of the first redundant signal lines of the redundant memory array, the first signal lines that must be replaced by the second redundant signal lines to repair failed storage cells in the second intermediate target signal lines are removed, thereby further reducing the number of first signal lines that serve as target signal lines and improving the determination rate of the first type of signal lines.

[0113] by Figure 3For example, when the third number ebit_cnt_rowx of failed storage cells on word line WLx is greater than the second number (3) of the first redundant signal lines of each second signal line group, it is determined that further judgment needs to be made on word line WLx and it is used as the second intermediate target signal line, that is, the first signal line with the number of failed storage cells greater than the second number (3) is selected as the second intermediate target signal line. When the third number ebit_cnt_rowx of failed storage cells on word line WLx as the second intermediate signal line is greater than the fourth number (48) of the first redundant signal lines of the redundant memory array, it is determined that the second redundant signal line must be used to replace the second intermediate target signal line to repair the failed storage cells on the second intermediate target signal line (word line WLx), and word line WLx does not need to be used as a target signal line to determine whether it is a first-class signal line. When the third number ebit_cnt_rowx of failed storage cells on word line WLx as the second intermediate signal line is less than or equal to the fourth number (48), it is determined that further judgment needs to be made on the second intermediate target signal line (word line WLx) and it is used as the target signal line.

[0114] In some embodiments, step S102 of "determining the first number of failed memory cells corresponding to a target signal line among a plurality of first signal lines of a memory array and each first signal line group of the memory array" includes: determining a third number of failed memory cells on each first signal line; selecting first signal lines as target signal lines in descending order of the third number of failed memory cells on each first signal line; and determining the first number of failed memory cells corresponding to the target signal line and each first signal line group of the memory array. This configuration can improve the determination rate of the first type of signal lines and thus the repair rate of failed memory cells.

[0115] For the specific steps of determining the third number of failed storage units on each first signal line, refer to the above description of determining the third number of failed storage units on the first signal line, which will not be repeated here.

[0116] Compare the third numbers of failed memory cells on each first signal line, select the first signal lines as target signal lines in descending order of the third numbers, and determine the first number of failed memory cells corresponding to the target signal lines and each first signal line group of the memory array; wherein, the specific steps of determining the first number of failed memory cells corresponding to the target signal lines and each first signal line group of the memory array refer to the above description of determining the first number of failed memory cells corresponding to the target signal lines and each first signal line group of the memory array, which will not be repeated here.

[0117] This method first selects the first signal line with the most failed memory cells as the target signal line, and then selects the first signal line with the fewest failed memory cells as the target signal line. This can improve the speed of identifying first-category signal lines. Furthermore, if the first signal line to be targeted is not a first-category signal line, the selection of the target signal line can be stopped, thus reducing the time required to identify first-category signal lines and improving the efficiency of first-category signal line identification.

[0118] by Figure 3 For example, determine the third number ebit_cnt_row0 of failed memory cells on word line WL0, determine the third number ebit_cnt_row1 of failed memory cells on word line WL1, the third number ebit_cnt_row2 of failed memory cells on word line WL2, ..., the third number ebit_cnt_rown-1 of failed memory cells on word line WLn-1, and select the word lines corresponding to the third number ebit_cnt_row as target signal lines in descending order of the third number ebit_cnt_row0, the third number ebit_cnt_row1, ebit_cnt_row2, ..., the third number ebit_cnt_rown-1.

[0119] In some embodiments, the repair method of the storage device further includes: S1021: determining a third number of failed storage cells on each first signal line; S1023: in response to the third number of failed storage cells on the first signal line being greater than the fourth number of first redundant signal lines of the redundant storage array, directly marking the first signal line as a first-category signal line.

[0120] S1021 (same as S1021 described above): Obtain a third number ebit_cnt_row of failed memory cells on each first signal line. S1023 (performed before or after S1022 described above, or alternatively with S1022 described above): Obtain a fourth number of first redundant signal lines of the redundant memory array. Compare the third number ebit_cnt_row of failed memory cells on the first signal line with the fourth number of first redundant signal lines of the redundant memory array. If the third number ebit_cnt_row is greater than the fourth number, directly mark the first signal line as a first-category signal line. This setting can determine all first-category signal lines present in the first signal lines, thereby improving the repair rate of failed memory cells.

[0121] by Figure 3For example, the third number ebit_cnt_row of failed storage cells on each first signal line WL0 to WLn-1 is obtained; the fourth number (48) of the first redundant signal lines of the redundant memory array is obtained; the third number ebit_cnt_rowx of failed storage cells on the word line WLx is compared with the fourth number (48), and when the third number ebit_cnt_rowx is greater than the fourth number (48), the word line WLx is determined to be the first signal line that must be replaced by the second redundant signal line, and the word line WLx is directly marked as a first-class signal line.

[0122] In some embodiments, the aforementioned step S104 of "marking the target signal line as a first-category signal line in response to a first number of failed memory cells corresponding to the first signal line group on the target signal line being greater than a second number of first redundant signal lines corresponding to the second signal line group of the first signal line group" further includes: S1041: sequentially obtaining a first number of failed memory cells corresponding to each of the first signal line groups on the target signal line; and S1042: in response to the first number of failed memory cells corresponding to any of the first signal line groups being greater than the second number corresponding to the first signal line group, setting a flag bit of the signal line address corresponding to the target signal line in the failure repair array (ebit_cnt_main_row) to mark the first-category signal line. This setting enables marking of the first-category signal line, facilitating subsequent replacement of the first-category signal line with the second redundant signal line.

[0123] According to the order of the first signal line groups, data is written and read for the storage cells that are simultaneously located on the target signal line and multiple second signal lines of the first first signal line group, and the number of storage cells whose read data is inconsistent with the written data is counted, and the number is taken as the first number ebit_cnt0 corresponding to the first first signal group; and so on, the first number ebit_cnt1 to ebit_cnt15 of failed storage cells on the target signal line corresponding to each first signal line group is obtained; the first number ebit_cnt corresponding to the target signal line and each first signal line group is compared with the second number of the second signal line group corresponding to the first signal line group. When the first number ebit_cnt of failed storage cells corresponding to any one of the first signal line groups is greater than the second number corresponding to the first signal line group, the flag bit of the signal line address corresponding to the target signal line in the failure repair array ebit_cnt_main_row is set to mark it as a first-category signal line.

[0124] by Figure 3For example, taking word line WL3 as a target signal line, a first number ebit_cnt0 of failed memory cells on word line WL3 corresponding to group A0, a first number ebit_cnt1 of failed memory cells on word line WL3 corresponding to group A1, ..., a first number ebit_cnt15 of failed memory cells on word line WL3 corresponding to group A15 are sequentially obtained. Among the first numbers ebit_cnt0, the first number ebit_cnt2, ..., the first number ebit_cnt15, any first number ebit_cntx is greater than the second number of first redundant signal lines of group Bx, wherein the first number ebit_cntx is the first number corresponding to group Ax, and groups Ax and Bx are correspondingly set. The flag bit of flag WL_Flag corresponding to the signal line address corresponding to word line WL3 (target signal line) in Table 1 is set to mark word line WL3 as a first-category signal line.

[0125] It should be understood that although Figure 2 The steps in the flowchart are shown in sequence as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order restriction for the execution of these steps, and these steps can be executed in other orders. In addition, Figure 2 At least part of the steps may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily executed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be executed in turn or alternately with other steps or at least part of the sub-steps or stages of other steps.

[0126] Based on the same inventive concept, the present application also provides a storage device repair system, and the parts that are the same as or corresponding to the embodiments of the above-mentioned storage device repair method will not be described in detail below. Figure 3 This is one of the structural diagrams of the repair system of the storage device in the embodiment of the present disclosure, see Figure 3 In this embodiment, a repair system for a storage device is provided. The storage device includes a storage array and a redundant storage array. The repair system includes: an acquisition module 102 , a calculation module 104 , and a repair module 106 .

[0127] The acquisition module 102 is used to determine a first number of failed storage cells corresponding to a target signal line among a plurality of first signal lines of a storage array and each first signal line group of the storage array; the first signal line extends along a first direction, and the plurality of first signal lines are arranged at intervals along a second direction, and the second direction intersects the first direction; the plurality of first signal line groups are respectively arranged corresponding to the plurality of second signal line groups of the redundant storage array; the plurality of second signal lines of the first signal line group are arranged at intervals along the first direction and extend along the second direction; and the plurality of first redundant signal lines of the second signal line group are parallel to the second signal lines.

[0128] The computing module 104 is connected to the acquisition module 102 and is configured to mark the target signal line as a first-category signal line in response to a first number of failed memory cells corresponding to the first signal line group being greater than a second number of first redundant signal lines corresponding to the second signal line group in the first signal line group. As an example, the computing module 104 includes a comparator.

[0129] The repair module 106 is connected to the operation module 104 and is used to replace the first type of signal line with the second redundant signal line of the redundant memory array to implement repair; the second redundant signal line is parallel to the first signal line.

[0130] In the repair system of the above-mentioned storage device, when the first number of failed storage cells corresponding to the target signal line and each first signal line group is greater than the second number of the first redundant signal lines of the second signal line group corresponding to the first signal line group, the computing module 104 determines that the target signal line is a first-category signal line that needs to be replaced with the second redundant signal line. The first-category signal line is obtained with high accuracy and speed, thereby improving the rate and efficiency of the repair module 106 in repairing the failed storage cells.

[0131] Based on the same inventive concept, the present application also provides a storage device repair system. Parts identical or corresponding to the above-mentioned storage device repair method embodiments will not be described in detail below. Figure 4 This is the second structural diagram of the repair system of the storage device in the embodiment of the present disclosure, see Figure 4 In this embodiment, a storage device repair system is provided, including: a main control device 202 and a storage device 204.

[0132] The storage device 204 is connected to the main control device 202 . The storage device 204 includes a storage die 302 . The storage die 302 includes at least one storage module 402 . The storage module 402 includes a storage array and a redundant storage array.

[0133] The master control device 202 is connected to the storage die 302 and is configured to obtain failure storage information of a failed storage cell in the storage array and execute the aforementioned storage device repair method based on the failure storage information to generate repair information. The failure storage information represents the location of the failed storage cell in the storage array; the repair information includes corresponding information between the second redundant signal lines and the first type signal lines of the redundant storage array. For example, the master control device 202 can be a host computer in a test machine, or it can be packaged together with the storage device 204 to form a memory, with the master control device 202 serving as the master chip in the memory.

[0134] In the repair system of the above-mentioned storage device, during the process of generating repair information, the main control device 202 determines that the target signal line is a first-type signal line that needs to be replaced with a second redundant signal line when the first number of failed storage units corresponding to the target signal line and each first signal line group is greater than the second number of the first redundant signal lines of the second signal line group corresponding to the first signal line group. The first-type signal line is obtained with high accuracy and high speed, thereby improving the repair rate and efficiency of the failed storage unit.

[0135] Figure 5 This is the third structural diagram of the repair system of the storage device in the embodiment of the present disclosure, see Figure 5 In some embodiments, the storage device 204 further includes a control die 304. The control die 304 is connected to the main control device 202 and the storage die 302, respectively, and is configured to generate a repair signal based on the repair information. The storage die 302 is configured to replace the first-type signal line with the second redundant signal line of the redundant storage array in response to the repair signal to implement the repair. It is understood that the storage die 302 maps the signal line address of the first-type signal line to the redundant signal line address corresponding to the second redundant signal line in response to the repair signal.

[0136] Figure 6 This is a fourth structural diagram of the repair system for the storage device according to the embodiment of the present disclosure, see Figure 6 In some embodiments, the control die 304 includes a redundancy loader 404 and a control device (RTL IP) 406. The redundancy loader 404 is connected to the main control device 202 and the control device 406, respectively, and the control device 406 is connected to the storage module 402. The redundancy loader 404 is used to generate a repair control signal based on the repair information, and the control device 406 is used to output a corresponding repair signal to the connected storage module 402 based on the repair control signal output by the connected redundancy loader 404.

[0137] Figure 7 This is the fifth structural diagram of the repair system of the storage device in the embodiment of the present disclosure, see Figure 7In some embodiments, the storage die 302 includes a storage group 400, and the storage group 400 includes multiple storage modules 402; the control die 304 includes: a redundant loading device 404 and a control device 406; the redundant loading device 404 is connected to the main control device 202 and the control device 406 respectively, and the control device 406 is correspondingly connected to the storage group 400; the redundant loading device 404 is used to generate a repair control signal according to the repair information, and the control device 406 is used to output a corresponding repair signal to the multiple storage modules 402 of the connected storage group 400 according to the repair control signal output by the connected redundant loading device 404.

[0138] Figure 8 This is the sixth structural diagram of the repair system of the storage device in the embodiment of the present disclosure, see Figure 8 In some embodiments, the memory die 302 includes a plurality of memory groups 400 , each memory group 400 includes a plurality of memory modules 402 ; the control die 304 includes a redundant loading device 404 and a plurality of control devices 406 .

[0139] The redundant loading device 404 is connected to the main control device 202 and multiple control devices 406 respectively, and the multiple control devices 406 are respectively connected to the multiple storage groups 400; the redundant loading device 404 is used to generate multiple repair control signals according to the repair information; the multiple repair control signals correspond to the multiple control devices 406 respectively; the control device 406 is used to output corresponding repair signals to the multiple storage modules 402 of the connected storage group 400 according to the repair control signals output by the connected redundant loading device 404.

[0140] The redundant loading device 404 generates a plurality of repair control signals according to the repair information output by the main control device 202, and transmits the plurality of repair control signals to the redundant latch (RDN LATCH) of the corresponding control device (RTL IP) 406 according to the first control information; wherein the first control information includes the first address information RTL_IP_ID representing the address of the control device 406, the first switch information RDN_LDEN for controlling the opening and closing of the redundant loading device 404, and the second switch information for controlling the storage and stopping of the repair control signal; the redundant loading device 404 is used to transmit the repair control signal to the control device 406 corresponding to the first address information RTL_IP_ID according to the first address information RTL_IP_ID when the first switch information RDN_LDEN and the second switch information are simultaneously valid; illustratively, the first switch information is valid when the first switch information is a high level 1, and the second switch information is valid when the second switch information is a high level 1.

[0141] As an example, the second switch information includes row switch information RDN_ROWEN and column switch information RDN_COLEN; the redundant loading device 404 is used to store the row repair information in the redundant latch (RDN LATCH) of the control device (RTL IP) 406 corresponding to the first address information RTL_IP_ID when the first switch information RDN_LDEN and the row switch information RDN_ROWEN are both valid; the redundant loading device 404 is also used to store the column repair information in the redundant latch (RDN LATCH) of the control device (RTL IP) 406 corresponding to the first address information RTL_IP_ID when the first switch information RDN_LDEN and the column switch information RDN_COLEN are both valid. LATCH); wherein the repair information includes row repair information and column repair information, the row repair information includes a mapping relationship between a redundant word line address corresponding to a redundant memory cell for repairing a failed memory cell in the redundant memory array and a word line address corresponding to the failed memory cell on each first signal line of the failed group, the redundant word line address is an address of a redundant word line corresponding to the redundant memory cell, and the word line address is an address of a word line corresponding to the failed memory cell; the column repair information includes a mapping relationship between a redundant bit line address corresponding to a redundant memory cell for repairing a failed memory cell in the redundant memory array and a bit line address corresponding to the failed memory cell on each first signal line of the failed group, the redundant bit line address is an address of a redundant bit line corresponding to the redundant memory cell, and the bit line address is an address of a bit line corresponding to the failed memory cell.

[0142] The control device (RTL IP) 406 outputs a repair signal based on a control instruction and a repair control signal; wherein the control instruction includes at least one of a read instruction, a write instruction, and a refresh instruction; the control device 406 outputs a repair signal based on the control instruction and the repair control signal when the bit line address and / or word line address of the storage unit corresponding to the control instruction matches (is the same as) the bit line address and / or word line address of the failed storage unit.

[0143] Illustratively, the multiple memory groups 400 in the memory die 302 are located on the same wafer. Furthermore, the multiple memory modules 402 of the memory group 400 in the memory die 302 are located on multiple wafers that are stacked.

[0144] In some embodiments, the control chip 304 also includes: a test module; the test module is connected to the main control device 202 and the storage chip 302 respectively, and the test module is used to receive the test information output by the main control device 202; the main control device 202 is used to receive the failure storage information generated by the storage module 402 in the storage chip 302 based on the test information.

[0145] Furthermore, the test module has a BIST circuit, and the test module and the control device are packaged together to form a buffer die in the control die 304 .

[0146] Those skilled in the art will appreciate that all or part of the processes in the above-described method embodiments can be implemented by instructing the relevant hardware through a computer program. The computer program can be stored in a non-volatile computer-readable storage medium. When executed, the computer program can include the processes of the above-described method embodiments. Any reference to memory, storage, database, or other media used in the embodiments provided herein may include at least one of non-volatile and volatile memory. Non-volatile memory may include read-only memory (ROM), magnetic tape, floppy disk, flash memory, or optical storage. Volatile memory may include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM).

[0147] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features in the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0148] The above-described embodiments merely represent several implementation methods of the embodiments of the present application. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention. It should be noted that a person skilled in the art may make various modifications and improvements without departing from the concept of the embodiments of the present application, and these modifications and improvements fall within the scope of protection of the embodiments of the present application.

Claims

1. A method for repairing a storage device, characterized in that: The storage device includes a storage array and a redundant storage array; The repair method includes: Determining a first number of failed memory cells corresponding to target signal lines among a plurality of first signal lines of the memory array and respective first signal line groups of the memory array; the first signal lines extend along a first direction, the plurality of first signal lines are spaced apart along a second direction, and the second direction intersects the first direction; the plurality of first signal line groups are respectively arranged corresponding to the plurality of second signal line groups of the redundant memory array; the plurality of second signal lines of the first signal line group are spaced apart along the first direction and extend along the second direction; the plurality of first redundant signal lines of the second signal line group are parallel to the second signal lines; the first redundant signal line is used to replace any second signal line corresponding to the first signal line group having a failed memory cell, so as to repair the failed memory cell on the second signal line; In response to the first number of failed memory cells corresponding to the first signal line group existing on the target signal line being greater than the second number of first redundant signal lines corresponding to the second signal line group of the first signal line group, marking the target signal line as a first-category signal line; The first type of signal line is replaced by a second redundant signal line of the redundant memory array to achieve repair; the second redundant signal line is parallel to the first signal line.

2. The repair method according to claim 1, characterized in that: The determining a first number of failed memory cells corresponding to a target signal line among a plurality of first signal lines of the memory array and each first signal line group of the memory array includes: determining a third number of the failed storage cells on each of the first signal lines; In response to the third number of failed memory cells on the first signal line being less than or equal to the fourth number of the first redundant signal lines of the redundant memory array, using the first signal line as the target signal line; The first number of the failed memory cells on the target signal line corresponding to each of the first signal line groups is determined.

3. The repair method according to claim 2, characterized in that: In response to the third number of failed memory cells on the first signal line being less than or equal to the fourth number of the first redundant signal lines of the redundant memory array, using the first signal line as the target signal line comprises: In response to the third number of failed memory cells on the first signal line being less than or equal to the fourth number of the first redundant signal lines of the redundant memory array, using the first signal line as a first intermediate target signal line; In response to the third number of failed memory cells on the first intermediate target signal line being greater than the second number of the first redundant signal lines of each of the second signal line groups, the first intermediate target signal line is used as the target signal line.

4. The repair method according to claim 2, characterized in that: In response to the third number of failed memory cells on the first signal line being less than a fourth number of the first redundant signal lines of the redundant memory array, using the first signal line as the target signal line comprises: In response to the third number of failed memory cells on the first signal line being greater than the second number of the first redundant signal lines of each of the second signal line groups, using the first signal line as a second intermediate target signal line; In response to the third number of failed memory cells on the second intermediate target signal line being less than or equal to the fourth number of the first redundant signal lines of the redundant memory array, the second intermediate target signal line is used as the target signal line.

5. The repair method according to claim 1, characterized in that: Determining a first number of failed memory cells corresponding to a target signal line among a plurality of first signal lines of the memory array and each first signal line group of the memory array includes: determining a third number of the failed storage cells on each of the first signal lines; selecting the first signal lines as the target signal lines in descending order of the third number of failed storage cells on the first signal lines; The first number of the failed memory cells on the target signal line corresponding to each of the first signal line groups is determined.

6. The repair method according to claim 1, characterized in that: Also includes: determining a third number of the failed storage cells on each of the first signal lines; In response to the third number of failed memory cells on the first signal line being greater than the fourth number of the first redundant signal lines of the redundant memory array, the first signal line is directly marked as the first-type signal line.

7. The repair method according to claim 1, characterized in that: In response to the first number of failed memory cells corresponding to the first signal line group existing on the target signal line being greater than the second number of first redundant signal lines corresponding to the second signal line group of the first signal line group, marking the target signal line as a first-category signal line comprises: sequentially acquiring the first number of failed memory cells on the target signal line corresponding to each of the first signal line groups; In response to the first number of failed storage cells corresponding to any one of the first signal line groups being greater than the second number corresponding to the first signal line group, a flag bit of the signal line address corresponding to the target signal line in the failure repair array is set to mark the first type of signal line.

8. The repair method according to claim 1, characterized in that: The first signal line is a word line, the second signal line is a bit line, the first redundant signal line is a redundant bit line, and the second redundant signal line is a redundant word line.

9. A storage device repair system, characterized in that: The storage device includes a storage array and a redundant storage array, and the repair system includes: An acquisition module is configured to determine a first number of failed storage cells corresponding to a target signal line among a plurality of first signal lines of the storage array and each first signal line group of the storage array; the first signal line extends along a first direction, the plurality of first signal lines are spaced apart along a second direction, and the second direction intersects the first direction; the plurality of first signal line groups are respectively arranged corresponding to the plurality of second signal line groups of the redundant storage array; the plurality of second signal lines of the first signal line group are spaced apart along the first direction and extend along the second direction; the plurality of first redundant signal lines of the second signal line group are parallel to the second signal lines; the first redundant signal line is used to replace a second signal line corresponding to any one of the first signal line groups having a failed storage cell, so as to repair the failed storage cell on the second signal line; a computing module connected to the acquiring module, configured to mark the target signal line as a first-category signal line in response to the first number of failed storage cells corresponding to the first signal line group existing on the target signal line being greater than the second number of first redundant signal lines corresponding to the second signal line group of the first signal line group; A repair module is connected to the operation module and is used to replace the first type of signal line with the second redundant signal line of the redundant storage array to achieve repair; the second redundant signal line is parallel to the first signal line.

10. A storage device repair system, characterized in that: include: Main control device; A storage device connected to the main control device, the storage device comprising: A memory die, comprising at least one memory module, wherein the memory module comprises a memory array and a redundant memory array; The main control device is connected to the storage chip and is used to obtain failure storage information of the failed storage unit of the storage array, and execute the repair method of the storage device according to any one of claims 1 to 7 according to the failure storage information to generate repair information, wherein the repair information includes corresponding information of the second redundant signal line and the first type signal line of the redundant storage array.

11. The repair system according to claim 10, characterized in that: The storage device further includes: a control chip, connected to the main control device and the storage chip respectively, and used to generate a repair signal according to the repair information; The memory chip is used for replacing the first type of signal line with the second redundant signal line of the redundant memory array according to the repair signal to implement repair.

12. The repair system according to claim 11, characterized in that The storage die includes a plurality of storage groups, each of which includes a plurality of storage modules. The control die includes a redundant loading device and a plurality of control devices. The redundant loading devices are respectively connected to the main control device and the plurality of control devices. The plurality of control devices are respectively connected to the plurality of storage groups. The redundant loading device is used to generate a plurality of repair control signals according to the repair information; the plurality of repair control signals respectively correspond to the plurality of control devices; The control device is configured to output corresponding repair signals to the connected plurality of storage modules according to the repair control signal output by the connected redundant loading device.

Images