A method of packaging a gallium nitride half-bridge module

Abstract

The application provides a gallium nitride half-bridge module packaging method and belongs to the technical field of semiconductor production. The application comprises the following steps: designing a current loop in a planar packaging structure, constructing a gradient current path electrode layout on an insulating substrate, preparing a heterogeneous structure heat dissipation substrate containing a micro-channel heat dissipation layer and a thermal resistance suppression layer, fixing a chip and constructing a gate drive path by using a direct bonding technology, connecting a device by using a non-inductive lead process and setting a current resonance suppression structure, constructing an electromagnetic shielding cavity by using a three-dimensional packaging technology, optimizing a parasitic inductance compensation network by using a pre-trained parasitic parameter optimization network model, enhancing the interfacial bonding force through surface microstructure processing, and finally performing terminal packaging test and verifying dynamic response characteristics, so that the technical problem of voltage peak control and thermal management balance under high-frequency switching conditions is solved.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of semiconductor production, and particularly relates to a gallium nitride half-bridge module packaging method. BACKGROUND

[0002] Gallium nitride power devices have become key components of high-frequency and high-efficiency power conversion systems due to their wide bandgap characteristics, high electron mobility, and low on-resistance. Traditional gallium nitride half-bridge module packaging methods mainly use planar packaging or heat sink stacking structures to suppress voltage spikes during switching by optimizing electrode layout and adding buffer circuits. However, these methods mainly focus on a single aspect of electrical performance or thermal management, lacking a systematic level of collaborative design.

[0003] As the switching frequency of gallium nitride devices continues to increase (exceeding 1 MHz), traditional packaging methods face serious challenges: on the one hand, voltage spikes generated by high-frequency switching can cause device breakdown; on the other hand, the hotspot effect caused by concentrated switching losses accelerates device aging. Existing technologies usually suppress voltage spikes by increasing gate resistance or adding buffer circuits, but this increases switching losses and exacerbates thermal management difficulties; while strengthening the heat dissipation design often increases the current loop area, leading to increased parasitic inductance and voltage spikes.

[0004] Currently, there is a lack of effective methods to simultaneously solve the voltage spike control and thermal management problems of gallium nitride half-bridge modules during high-frequency switching. The coupling effect of electromagnetic fields and temperature fields makes them form a mutually restraining relationship, making it difficult to balance voltage spikes and thermal distribution while increasing switching frequency. SUMMARY

[0005] Therefore, the application provides a gallium nitride half-bridge module packaging method, which can solve the technical problem of simultaneous optimization of voltage spikes and thermal management of gallium nitride half-bridge modules under high-frequency switching conditions in the prior art.

[0006] The application is implemented as follows: The application provides a gallium nitride half-bridge module packaging method, which includes: designing a half-bridge module current loop and determining the maximum allowed loop area; constructing an electrode layout on an insulating substrate; preparing a heterogeneous layer structure heat dissipation substrate; fixing a gallium nitride chip on the heat dissipation substrate; connecting upper and lower bridge arm devices and setting a current resonance suppression structure; packaging the half-bridge module and constructing an electromagnetic shielding cavity; using a parasitic parameter optimization network model to optimize the parameters of the parasitic inductance compensation network, outputting an optimal inductance compensation parameter vector for guiding the design of the parasitic inductance compensation network; wherein the parasitic parameter optimization network model maps the geometric topology structure and physical characteristics of the half-bridge module to the optimal parasitic parameter space, realizing the collaborative optimization of electromagnetic fields and temperature fields.

[0007] The step of designing the current loop of the half-bridge module comprises: using a planar packaging structure to design the current loop of the half-bridge module, determining a maximum allowed loop area according to a voltage spike threshold, and adopting current density distribution simulation to verify the rationality of the loop design.

[0008] The step of constructing the electrode layout comprises: adopting a gradient current path design on the insulating substrate to make the high-frequency current distribution uniform and reduce electromagnetic interference spectrum diffusion.

[0009] The step of preparing the heterogeneous layer structure heat dissipation substrate comprises: preparing the heterogeneous layer structure heat dissipation substrate comprising a micro-channel heat dissipation layer and a thermal resistance suppression layer, ensuring that the thermal gradient balance is maintained in a high-frequency working state, and applying a heat diffusion equation to calculate the thermal resistance.

[0010] The step of fixing the gallium nitride chip comprises: fixing the gallium nitride chip on the heat dissipation substrate by direct bonding technology, forming a low thermal resistance interface, and constructing a gate drive path.

[0011] The step of connecting the upper and lower bridge arm devices comprises: connecting the upper and lower bridge arm devices by using a non-inductive lead process, forming an optimized current path, and setting a current resonance suppression structure to reduce switching overshoot.

[0012] The step of packaging the half-bridge module comprises: using a three-dimensional packaging technology to package the half-bridge module, constructing an electromagnetic shielding cavity, and filling a heat dissipation composite material.

[0013] The parasitic inductance compensation parameter vector refers to a set of key parameters required for optimizing the parasitic inductance compensation network, including compensation inductance value, compensation capacitance value, layout position coordinates and connection topology structure parameters; the parasitic inductance compensation network is a circuit structure composed of inductance and capacitance elements, which offsets the influence of the original parasitic inductance through the reverse inductance effect, and reduces the voltage overshoot amplitude.

[0014] The specific structure of the parasitic parameter optimization network model is a hybrid architecture combining a multi-layer graph convolution network and a parameter generation network, which includes a topology feature extraction module, a physical property coding module, a parameter regression module and a constraint optimization module.

[0015] It also includes: applying surface microstructure processing technology to enhance the interfacial bonding force, improve the packaging thermal cycle resistance, and prolong the service life of the module; verifying the dynamic response characteristics of the half-bridge module through terminal packaging test, including switching speed, on-state loss and switching loss measurement, and confirming the effectiveness of the current path design.

[0016] The application realizes the collaborative optimization of current density distribution and thermal gradient by combining the gradient current path design with the heterogeneous layer structure heat dissipation substrate. The method first determines a reasonable loop design by using current density distribution simulation, then compensates for the parasitic inductance through a parasitic parameter optimization network model, and finally constructs a three-dimensional packaging structure to form an electromagnetic shielding cavity.

[0017] The half-bridge module designed by the method effectively balances the thermal gradient distribution while maintaining a small loop area through the synergistic effect of the micro-channel heat dissipation layer and the thermal resistance suppression layer. In particular, the application of the parasitic parameter optimization network model converts the electromagnetic field and temperature field coupling problem into a parameter optimization problem, and generates optimal parasitic inductance compensation parameters by learning from historical design experience to guide the actual design process.

[0018] The application solves the problem of collaborative optimization of voltage spike control and thermal management in gallium nitride half-bridge module high-frequency switching, enabling the module to operate safely and stably at a higher frequency (> 2MHz), effectively suppressing the voltage spike amplitude while maintaining uniform temperature distribution, prolonging the service life of the device and improving the power density. BRIEF DESCRIPTION OF DRAWINGS

[0019] Figure 1 is a flowchart of the method of the application.

[0020] Figure 2 is a schematic diagram of the gallium nitride half-bridge module of Example 2.

[0021] Figure 3 is a schematic diagram of the heterogeneous layer structure heat dissipation substrate structure of Example 2.

[0022] Figure 4 is a schematic diagram of the inductance-free lead and current resonance suppression structure of Example 2. DETAILED DESCRIPTION

[0023] To make the purpose, technical scheme and advantages of the embodiments of the application clearer, the technical scheme in the embodiments of the application will be described clearly and completely below with reference to the drawings in the embodiments of the application.

[0024] As Figure 1 shown, is a flowchart of a gallium nitride half-bridge module packaging method provided by the application, the method comprising the following steps:

[0025] S01, design a half-bridge module current loop using a planar packaging structure, determine the maximum allowed loop area according to the voltage spike threshold, and verify the rationality of the loop design using current density distribution simulation;

[0026] S02, build electrode layout on insulating substrate, adopt gradient current path design to make high-frequency current distribution uniform and reduce electromagnetic interference spectrum diffusion;

[0027] S03, prepare heterogeneous layer structure heat dissipation substrate, containing micro-channel heat dissipation layer and thermal resistance suppression layer, to ensure maintaining thermal gradient balance in high-frequency working state, and use heat diffusion equation to calculate thermal resistance;

[0028] S04, fix gallium nitride chip on heat dissipation substrate by direct bonding technology, form low thermal resistance interface, and build gate drive path;

[0029] S05, connect upper and lower bridge arm devices using non-inductive lead process to form optimized current path, and set current resonance suppression structure to reduce switching overshoot;

[0030] S06, use three-dimensional packaging technology to package half-bridge module, build electromagnetic shielding cavity, and fill heat dissipation composite material;

[0031] S07, use pre-trained parasitic parameter optimization network model to optimize parasitic inductance compensation network parameters, input loop area, current density distribution, switching frequency and thermal gradient balance data, and output optimal inductance compensation parameter vector to guide parasitic inductance compensation network design;

[0032] S08, optionally, further includes applying surface microstructure processing technology to enhance interface bonding force, improve packaging thermal cycle resistance, and prolong module service life;

[0033] S09, optionally, further includes verifying dynamic response characteristics of half-bridge module through terminal packaging test, including switching speed, on-state loss and switching loss measurement, and confirming effectiveness of current path design.

[0034] Wherein, the voltage spike matrix refers to the voltage overshoot distribution map caused by parasitic inductance and capacitance resonance during high-frequency switching of gallium nitride device, which is the two-dimensional distribution of voltage overshoot amplitude and duration under different switching states.

[0035] Wherein, the high-frequency electromagnetic interference spectrum refers to the distribution of electromagnetic radiation energy in frequency domain generated by gallium nitride device during high-frequency switching, mainly concentrated in switching frequency and harmonic frequency, and the distribution range expands with the increase of switching speed.

[0036] Wherein, the thermal gradient balance refers to the stable temperature distribution state formed during the process of heat transfer from high temperature area to low temperature area in the package, which can effectively prevent local hot spot formation and reduce thermal stress.

[0037] The loop area refers to the geometric area of the closed path through which the current flows in the half-bridge module, directly affecting the size of the parasitic inductance. The smaller the loop area, the lower the parasitic inductance, and the smaller the voltage spike.

[0038] The current density distribution refers to the spatial distribution of the current in the conductor material of the half-bridge module, obtained by the current density distribution simulation in step S01, and used to analyze the current concentration area and the location of the hot spot.

[0039] The current path refers to the physical channel through which the current flows inside the half-bridge module. Optimized design can reduce the current loop area, reduce the parasitic inductance, make the current density distribution more uniform, and reduce local hot spots.

[0040] The current resonance suppression structure refers to a special damping circuit design used to suppress the high-frequency oscillation phenomenon of the current at the switching moment, reduce electromagnetic interference, and reduce switching loss.

[0041] The parasitic inductance compensation network is a circuit structure composed of a certain arrangement of inductance and capacitance elements, which counteracts the influence of the original parasitic inductance through the reverse inductance effect, and reduces the voltage overshoot amplitude.

[0042] The parasitic inductance compensation parameter vector refers to the key parameter set required for optimizing the parasitic inductance compensation network, including compensation inductance value, compensation capacitance value, layout position coordinates, and connection topology structure parameters.

[0043] The surface microstructure treatment technology is to form a micron or nanometer special morphology on the surface of the interface material, increase the contact area and form a mechanical interlocking structure, and improve the interface bonding strength and thermal conductivity efficiency.

[0044] The heat diffusion equation is used to calculate the heat conduction and distribution inside the half-bridge module, analyze the heat gradient formation mechanism, and input includes material thermal conductivity, power density distribution, substrate thickness, micro-channel structure parameters, and environmental temperature. The output is a three-dimensional temperature field distribution and a heat flux vector field, which is used for heat resistance calculation and heat gradient balance evaluation in step S03.

[0045] The specific structure of the parasitic parameter optimization network model is a hybrid architecture combining multi-layer graph convolution network and parameter generation network, including topology feature extraction module, physical property coding module, parameter regression module and constraint optimization module. It can map the geometric topology structure and physical properties of the half-bridge module to the optimal parasitic parameter space and generate the parasitic inductance compensation parameter vector. The number of graph convolution layers in the model is determined based on the complexity of the current loop topology, the dimension of the current density distribution, and the dimension of the heat gradient balance distribution. The adaptive connection algorithm is used to establish the coupling relationship between different physical fields, and the physical consistency of the compensation parameters is improved.

[0046] The step of establishing a training data set in the parasitic parameter optimization network model training process specifically includes: first, performing large-scale electromagnetic-thermal coupling simulation on the half-bridge module under different structural parameters and working conditions through a multi-physics field simulation software to obtain electromagnetic field distribution and temperature field distribution data; then constructing a topology structure diagram based on the simulation results, mapping the physical structure of the half-bridge module to a graph structure, with nodes representing key components and edges representing the interaction between components; then labeling each topology structure with an optimal parasitic inductance compensation parameter vector, determining the compensation parameter combination that minimizes the voltage spike through parameter scanning and optimization algorithms; subsequently performing data enhancement and normalization processing to expand the training samples and unify the data scale; and finally dividing the training set and the validation set according to the structural complexity and working conditions.

[0047] The step of training the parasitic parameter optimization network model specifically includes: first, training different modules of the network in stages, training the topology feature extraction module to identify key structural features in the first stage, training the physical property encoding module to encode electromagnetic-thermal coupling effects in the second stage, training the parameter regression module to generate compensation parameters in the third stage, and training the constraint optimization module to ensure that the parameters meet the physical constraints in the fourth stage; then adopting an end-to-end fine-tuning strategy to optimize the overall network performance; introducing a physical consistency loss function during the training process to ensure that the generated parameters comply with electromagnetic theory; simultaneously adopting a hybrid optimization algorithm to combine the advantages of gradient descent and evolutionary algorithms to avoid being trapped in local optima; and finally evaluating the model performance through cross-validation to ensure the generalization ability for different types of half-bridge module structures. The trained model can generate an optimal parasitic inductance compensation parameter vector based on the results of steps S01 to S06, which is used to guide the parasitic inductance compensation network design in step S07, thereby effectively suppressing the formation of voltage spike matrix.

[0048] The specific implementation of the above steps will be described in detail below.

[0049] The specific implementation of step S01 is to use a three-dimensional electromagnetic field solver to design a planar packaging structure. First, a three-dimensional geometric model of the half-bridge module is established, including the upper bridge arm device, the lower bridge arm device, the electrode layout, and the connection lines. Then, material parameters are defined, including the electrical conductivity of the aluminum substrate being 3.8×10 7 Siemens / meter, the electrical conductivity of the copper electrode being 5.8×10 7 Siemens / meter, the electrical conductivity of the gallium nitride chip being 5.5×10 3 Siemens / meter, and the thermal conductivity of the heat dissipation substrate being 180 watts / meter·kelvin. According to the breakdown voltage limit of the gallium nitride power device, the maximum allowable voltage spike is determined to be 650 volts. The maximum allowable loop area is calculated using a planar current loop construction algorithm, which is based on the Maxwell equations to solve the dynamic electromagnetic field distribution. The calculation result shows that the maximum allowable loop area is 107 mm 2Subsequently, the current density distribution simulation is performed using the finite element analysis to calculate the current density distribution when the current flows through each part of the conductor in the power cycle, and the convergent solution is obtained through the iterative solution method based on the Poisson equation and the Ampere law to complete the loop design rationality verification. This step aims to determine the current loop design in the half-bridge module, reduce the parasitic inductance by controlling the loop area, thereby reducing the voltage spike, and ensure the rationality of the current path design through the current density distribution simulation to avoid the local hotspot problem caused by current concentration.

[0050] The specific implementation of step S02 is to construct the electrode layout on the alumina insulating substrate. First, a gradient current path is designed, with the thickness of the conductive layer gradually changing from the center to the edge. The copper layer thickness is 105 microns in the center area and 70 microns in the edge area, forming a continuous gradient distribution. The curvature optimization algorithm is used to design the electrode corner, with the inner radius of the corner not less than 0.8 mm to ensure smooth transition of the current streamline. For the skin effect under high-frequency state, surface treatment technology is adopted to form a micro-rough structure on the surface of the conductor, increasing the effective channel of high-frequency current, with the roughness controlled within the range of 1.2 microns to 1.8 microns. The Laplace equation and the Helmholtz equation are combined to calculate the high-frequency current distribution, and the electrode structure is optimized through iteration to make the current distribution uniformity index reach above 0.92 within the range of 100 kHz to 1 MHz. This step aims to optimize the electrode layout, make the high-frequency current distribution uniform through gradient design, reduce the concentrated hot spots, and reduce the electromagnetic interference spectrum diffusion through electrode shape optimization to improve the electromagnetic compatibility of the module under high-frequency working state.

[0051] The specific implementation of step S03 is to prepare the heterogeneous layer structure heat dissipation substrate. First, the plasma-enhanced chemical vapor deposition technology is used to deposit a silicon carbide micro-channel heat dissipation layer on the copper substrate, with a thickness of 28 microns to 32 microns, a channel width of 50 microns, a depth of 35 microns, and a spacing of 100 microns. Then, the electrochemical deposition method is used to prepare a thermal resistance suppression layer composed of copper-silver alloy, with a thickness of 15 microns to 18 microns and a silver content of 12% to 15%. The finite difference time domain method is used to solve the heat diffusion equation, with input parameters including material thermal conductivity (copper: 398 W / m·K, silicon carbide: 350 W / m·K), power density distribution data (peak power density: 280 W / cm 2 ), silicon carbide layer thickness (30 microns), micro-channel structure parameters (width 50 microns, depth 35 microns, spacing 100 microns), and environmental temperature (25 degrees Celsius). The three-dimensional temperature field distribution and heat flux density vector field are calculated, and the thermal resistance is calculated based on the calculation results to ensure that the overall thermal resistance is less than 0.35 °C / W. This step aims to establish an efficient heat dissipation structure, increase the heat dissipation area through the micro-channel structure, and reduce the interface thermal resistance through the thermal resistance suppression layer to ensure the thermal gradient balance under high-frequency working state, avoid the formation of local hot spots, and improve the module reliability.

[0052] The specific implementation of step S04 is to fix the gallium nitride chip on the heat dissipation substrate by using direct bonding technology. First, the back surface of the gallium nitride chip and the surface of the heat dissipation substrate are subjected to plasma activation treatment, the power is controlled at 90-110 watts, and the time is 60-90 seconds to form an active surface. Then, under the conditions of low oxygen environment (oxygen content less than 5 picograms) and high temperature (temperature 300-320 degrees Celsius), compression is carried out, the pressure is 0.8-1.2 megapascals, and the holding time is 180-240 seconds to form a low thermal resistance interface, and the interface thermal resistance is controlled at 0.06 ℃ / W·cm 2 Then, the gate drive path is constructed, the shielded winding structure is used to reduce the interference of the drive signal, the impedance matching design is used to make the reflection coefficient of the drive signal less than 0.05, and the integrity of the drive signal is ensured. Finally, a temperature sensor array is arranged near the interface between the chip and the substrate, and 8-point distributed monitoring is adopted to realize real-time monitoring of the temperature field. This step aims to realize high-quality combination of the gallium nitride chip and the heat dissipation substrate, form a low thermal resistance interface through direct bonding technology, improve the heat dissipation efficiency, construct a high-quality gate drive path, and ensure the integrity of the drive signal, laying a foundation for efficient work of the half-bridge module.

[0053] The specific implementation of step S05 is to connect the upper and lower bridge arm devices by using the inductance-free lead process. First, the parallel plate current path design is used to create mutual inductance effect by reversing the current flow of the upper and lower metal layers to offset the self-inductance effect, the lead width is 1.2 mm, the spacing is 0.15 mm, and the length is not more than 5 mm. Then, the multi-point bonding technology is used to establish metal interconnection, 8 gold wires with a diameter of 50 microns are connected in parallel at each power connection point, the spacing is 200 microns, and a low-impedance current channel is formed. A current resonance suppression structure is arranged at the connection between the device source and the drain, which includes a damping resistance network and a resonance absorption capacitor, the damping resistance value is 4.7-5.3 ohms, and the absorption capacitance value is 1.0-1.2 nanofarads. The damping network absorbs the switching transient resonance energy to reduce the oscillation amplitude. Finally, the optimized current path design is adopted to make the current path present an S-shaped distribution, reduce the path loop area, and verify by finite element simulation that the loop area is reduced by more than 40%, and the switching overshoot is reduced by more than 35%. This step aims to optimize the internal connection of the half-bridge module, reduce the parasitic inductance by using the inductance-free lead design, reduce the switching overshoot by using the current resonance suppression structure, and improve the switching performance and reliability of the module.

[0054] The specific implementation of step S06 is to package the half-bridge module using a three-dimensional packaging technology. First, an electromagnetic shielding cavity is constructed, which adopts a composite structure of an aluminum alloy base and a copper-zinc alloy inner wall, with a wall thickness of 1.5 to 2.0 millimeters and a silver-plated surface thickness of 10 to 15 micrometers, forming a Faraday cage structure with a shielding effectiveness of not less than 85 decibels in the frequency band of 20 to 100 megahertz and not less than 70 decibels in the frequency band of 100 to 500 megahertz. Then, aluminum nitride powder reinforced epoxy composite material is filled, with a powder content of 65 to 70%, a particle size distribution of 1 to 10 micrometers, a thermal conductivity of 3.2 watts per meter per kelvin or higher, and a breakdown strength of more than 25 kilovolts per millimeter. Vacuum injection molding process is adopted for filling, with a vacuum degree controlled at 50 to 100 pascals and a temperature controlled at 60 to 70 degrees Celsius, and an injection rate of 0.5 to 0.8 milliliters per minute to ensure no air bubbles are formed. Finally, heat curing treatment is performed, with a temperature gradient rising from 80 degrees Celsius to 150 degrees Celsius at a rate of 2 degrees Celsius per minute and maintaining for 120 to 150 minutes. This step aims to provide good mechanical protection and electromagnetic shielding, reduce electromagnetic interference through the shielding cavity structure, and improve heat conduction efficiency through the heat dissipation composite material filling to ensure the reliability of the module in high-frequency working state.

[0055] The specific implementation of step S07 is to optimize the parasitic inductance compensation network using a pre-trained parasitic parameter optimization network model. First, the loop area, current density distribution, switching frequency, and thermal gradient balance data are input into the network model, including a loop area of 94 mm 2 , current density distribution data with a dimension of 128 x 128 x 3, switching frequency of 500 kilohertz, and thermal gradient balance data as a 64 x 64 x 3 matrix. Then, the topological structure features are extracted through a graph convolution network with a convolution kernel size of 3 x 3 and 12 layers, and the activation function adopts the Leaky ReLU function. Then, the electromagnetic field distribution and temperature field distribution are mapped to the feature space through a physical property encoding module with an encoding dimension of 256 and a self-attention mechanism to establish the field distribution correlation. Next, the initial values of the compensation inductance and capacitance are generated through a parameter regression module, which adopts a multi-layer perceptron structure with a hidden layer size of [512, 256, 128]. Finally, the parameters are adjusted through a constraint optimization module to ensure physical consistency, and the parasitic inductance compensation parameter vector is output, including a compensation inductance value of 3.2 nanohenry, a compensation capacitance value of 0.47 nanofarad, a layout position coordinate of (12.5 mm, 8.7 mm, -1.2 mm), and a star-shaped connection topology. This step aims to optimize the parasitic inductance compensation network design using artificial intelligence technology, quickly generate the optimal compensation parameters through the pre-trained model, and improve the electrical performance and reliability of the half-bridge module.

[0056] Step S08 is an optional step, and its specific implementation is to enhance the interfacial bonding force by applying surface microstructure processing technology. First, laser micro-texture processing technology is used to form micro-groove structures on the surface of the substrate. The groove depth is 10-15 microns, the width is 20-30 microns, the pitch is 50-70 microns, and the grooves are arranged in a honeycomb distribution. Then, plasma surface activation is performed using oxygen-argon mixed gas (oxygen: argon = 1:4), with a power of 150-180 watts and a processing time of 90-120 seconds to form a high-activity surface. In metal interface processing, an electrochemical deposition method is used to form a silver-tin alloy layer on the surface of the copper electrode, with a thickness of 3-5 microns and a silver-tin ratio of 96:4 to improve wettability and bonding force. Finally, hot pressing treatment is performed at a temperature of 250-270 degrees Celsius, a pressure of 2.0-2.5 megapascals, and a holding time of 300-360 seconds to form a high-strength interfacial bond with a bonding strength of more than 18 megapascals. This step aims to improve the interfacial bonding force inside the package, increase the effective contact area through surface microstructure design, and improve the interfacial affinity of the materials through surface activation and metal processing to achieve high-strength bonding and improve the thermal cycle resistance and service life of the module.

[0057] Step S09 is an optional step, and its specific implementation is to verify the dynamic response characteristics of the half-bridge module through terminal package testing. First, a double-pulse test method is used to measure the switching speed, with a DC voltage of 200-600 volts, a current range of 5-30 amperes, and an ambient temperature of 25 degrees Celsius. The turn-on delay time is less than 12 nanoseconds, the turn-off delay time is less than 25 nanoseconds, the voltage rise time is less than 10 nanoseconds, and the voltage fall time is less than 8 nanoseconds. Then, a method combining thermocouple arrays and infrared thermal imaging is used to measure the temperature distribution. The thermocouple is arranged in 16 points, the sampling frequency is 10 hertz, the infrared thermal imager has a resolution of 320x240 pixels and an accuracy of ±0.5 degrees Celsius, and the deviation between the hot spot position and the simulation prediction is less than 10%. The on-state loss and switching loss are measured. At an ambient temperature of 25 degrees Celsius, a current of 20 amperes, and a voltage of 400 volts, the on-state resistance is 25 milliohms, the on-state loss is 10 watts, and the switching loss is 2.5 watts, with a deviation of less than 8% from the theoretical calculation value. Finally, electromagnetic interference testing is performed, with a frequency range of 150 kilohertz to 30 megahertz and a distance of 3 meters. The electromagnetic radiation intensity meets the international electromagnetic compatibility standards, with a radiation emission level that is 10 decibels lower than the standard limit. This step aims to comprehensively verify the electrical and thermal performance of the half-bridge module, confirm the effectiveness of the current path design through various testing methods, and provide performance guarantees for the actual application of the module.

[0058] The mathematical models or calculation processes involved in the present application are described in detail below.

[0059] The maximum allowed loop area calculation in step S01 uses Maxwell's equations to solve the dynamic electromagnetic field distribution, which is specifically expressed as follows:

[0060]

[0061] In the formula, L p is the parasitic inductance, with the unit of henry; μ0 is the vacuum permeability, with the value of 4π×10 -7 henry / meter; A is the loop area, with the unit of square meter; l is the loop perimeter, with the unit of meter; V peak is the voltage peak value, with the unit of volt; dI / dt is the current change rate, with the unit of ampere / second; V peak，th is the voltage peak threshold, with the value of 650 volts; A max is the maximum allowed loop area, with the unit of square meter.

[0062] Among them, the parameter acquisition method is: the loop perimeter l is obtained by measuring the three-dimensional geometric model of the half-bridge module, and the typical value is 0.036 meters; the current change rate is calculated by the formula , wherein I max is the maximum working current, and the typical value is 30 amperes, t rise is the current rise time, and the typical value is 10 nanoseconds, and the calculation result is ampere / second.

[0063] This equation is based on Faraday's law of electromagnetic induction and the principle of energy conservation, and reflects the linear relationship between the loop area and the parasitic inductance, as well as the causal relationship between the parasitic inductance and the voltage peak. By controlling the loop area, the parasitic inductance can be effectively reduced, thereby suppressing the voltage peak and improving the module reliability. Considering the transient characteristics of the electromagnetic field in the fast switching process, the voltage peak in the limit case is more accurately predicted compared with the traditional method.

[0064] The heat diffusion equation in step S03 is used to calculate the heat conduction and distribution inside the half-bridge module, which is specifically expressed as follows:

[0065]

[0066] In the formula, ρ is the material density, with the unit of kilogram / cubic meter; c p is the specific heat capacity, with the unit of joule / kilogram·kelvin; T is the temperature field, with the unit of kelvin; t is the time, with the unit of second; k is the thermal conductivity, with the unit of watt / meter·kelvin; Q is the internal heat source term, with the unit of watt / cubic meter; α is the thermal diffusion coefficient, with the unit of square meter / second; R th is the thermal resistance, with the unit of kelvin / watt; T max is the maximum temperature, with the unit of kelvin; Tamb The ambient temperature is expressed in Kelvin; P total Total power loss, in watts.

[0067] The parameters were obtained as follows: material density ρ was obtained from the material data sheet, with copper at 8960 kg / m³ and silicon carbide at 3210 kg / m³; specific heat capacity c... p The thermal conductivity (k) was obtained from the material data sheets: 385 joules / kg·Kelvin for copper and 670 joules / kg·Kelvin for silicon carbide; the thermal conductivity (k) was obtained from the material data sheets: 398 watts / m·Kelvin for copper and 350 watts / m·Kelvin for silicon carbide; the internal heat source term (Q) was obtained through power loss distribution calculations. Where P loss This refers to the chip's power loss, typically 20 watts, V. chip This refers to the chip size, typically 4 × 10⁻⁶. -8 cubic meters, calculated as Q = 5 × 10 8 Watts per cubic meter.

[0068] This equation, based on the first law of thermodynamics and Fourier's law of thermal conduction, describes the heat conduction process in solid materials. Solving this equation yields the three-dimensional temperature field distribution within the module, providing a foundation for thermal resistance calculations and thermal gradient balance assessments. Considering transient thermal conduction characteristics and internal heat source distribution, it more accurately reflects the heat distribution characteristics under high-frequency operating conditions compared to traditional one-dimensional thermal resistance models.

[0069] The parasitic inductance compensation parameter vector optimization process in step S07 involves multiple mathematical models and algorithms, among which the core optimization objective function is specifically expressed as follows:

[0070] min θ J(θ) = α1·J voltage (θ)+ɑ2·J loss (θ)+ɑ3·J thermal (θ)+α4·J constraint (θ);

[0071]

[0072] θ=[L comp C comp x pos y pos , z pos top type ];

[0073] In the formula, J(θ) is the overall objective function; θ is the parasitic inductance compensation parameter vector; α1, α2, α3, and α4 are weighting coefficients, with typical values ​​of 0.5, 0.2, 0.2, and 0.1, respectively; J voltageis the voltage spike error term; J loss is the loss error term; J thermal is the thermal balance error term; J constraint is the constraint error term; V peak，i is the voltage spike value of the i-th operating point, in volts; V target，i is the target voltage value of the i-th operating point, in volts; N is the number of evaluation operating points, typically 20; P sw is the switching loss, in watts; P comp is the compensation network loss, in watts; P base is the reference power loss, in watts; T j is the junction temperature of the j-th monitoring point, in kelvin; T avg is the average junction temperature, in kelvin; T max is the maximum allowed junction temperature, in kelvin; T amb is the ambient temperature, in kelvin; M is the number of temperature monitoring points, typically 16; λ k is the Lagrange multiplier of the k-th constraint; g k is the k-th constraint function; K is the number of constraints, typically 8; L comp is the compensation inductance value, in henry; C comp is the compensation capacitance value, in farad; x pos , y pos , z pos is the layout position coordinate, in meters; top type is the connection topology parameter, taking an integer value from 0 to 3, representing star, mesh, tree, and hybrid topologies, respectively.

[0074] wherein the parameter acquisition method is: the weight coefficients α1, α2, α3, α4 are determined by grid search algorithm optimization, and are arranged and combined in steps of 0.1 within the range of [0.1, 0.9], and the combination with the best performance on the validation set is selected; the target voltage value V target，i is determined according to the device voltage rating, and is typically 70% of the rated voltage, typically 450 volts; the reference power loss P base is obtained by measuring the system loss under the condition of no compensation network, and is typically 25 watts; the maximum allowed junction temperature T max is determined according to the device specifications, and is typically 175 degrees Celsius; the ambient temperature T amb is set to the standard test temperature, typically 25 degrees Celsius; the constraint function g k includes size constraints, electrical parameter range constraints, and physical implementation feasibility constraints, such as g1(θ) = L comp -L max , g2(θ) = C min -Ccomp etc.

[0075] This optimization objective function comprehensively considers the voltage spike suppression effect, system loss, thermal balance and physical constraint conditions, and finds the optimal parameter combination through multi-objective weighted optimization method. The quadratic error form is used to enhance the punishment of large deviation, and the normalization processing is used to make the error terms of different dimensions comparable. Compared with the traditional single objective optimization, this method not only ensures the voltage spike suppression effect, but also takes into account the system efficiency and thermal performance.

[0076] In the double pulse test of step S09, the switch loss calculation equation is specifically expressed as follows:

[0077]

[0078] P sw =(E on +E off )·f sw ;

[0079]

[0080] P total =P sw +P cond ;

[0081] In the formula, E on is the turn-on energy, unit: joule; E off is the turn-off energy, unit: joule; v ds (t) is the drain-source voltage time function, unit: volt; i d (t) is the drain current time function, unit: ampere; t1, t2 are the start and end times of the turn-on process, unit: second; t3, t4 are the start and end times of the turn-off process, unit: second; P sw is the switch loss, unit: watt; f sw is the switch frequency, unit: hertz; P cond is the conduction loss, unit: watt; R ds(on) is the on-resistance, unit: ohm; I rms is the current effective value, unit: ampere; P total is the total loss, unit: watt.

[0082] Among them, the parameter acquisition method is: the drain-source voltage v ds (t) and the drain current i d(t) measured by high bandwidth oscilloscope (bandwidth no less than 1 gigahertz) and high precision voltage and current probes (voltage probe bandwidth no less than 500 megahertz, current probe bandwidth no less than 100 megahertz), sampling rate set to at least 10 gigasamples per second; turn-on process start and end times t1, t2 defined as the time when the drain current rises to 10% of the final value and the time 2 microseconds after the drain-source voltage drops to 10% of the final value; turn-off process start and end times t3, t4 defined as the time when the drain-source voltage rises to 10% of the final value and the time 2 microseconds after the drain current drops to 10% of the final value; switching frequency f sw determined by application requirements, typical value 500 kilohertz; on-state resistance R ds(on) measured by IV curve measurement instrument under specified gate-source voltage (typical value 6 volts) and junction temperature (typical value 25 degrees Celsius); current effective value I rms calculated by actual working waveform, where T is the switching period, in seconds.

[0083] This loss calculation equation is based on the energy conservation principle in power electronics, and the energy loss is calculated by time integration of voltage and current product. The non-linear characteristics and actual waveform in the switching process are considered, which is more accurate than the traditional simplified model to reflect the loss characteristics of gallium nitride devices. Turn-on loss and turn-off loss are calculated and summed up, which comprehensively evaluates the loss under different working conditions, and provides a basis for thermal design and efficiency optimization of half-bridge module.

[0084] Optionally, the equation for calculating the high-frequency current distribution uniformity in step S02 is specifically represented as follows:

[0085]

[0086] In the formula, J h is a complex representation of high-frequency current density, in amperes per square meter; k is the wave number, in 1 / m; j is the imaginary unit; ω is the angular frequency, ω = 2πf, in rad / s; σ is the electrical conductivity of the conductor, in siemens / m; μ is the magnetic permeability of the material, in henry / m; E0 is the applied electric field strength, in volts / m; δ is the skin depth, in meters; J s (x) is a function of surface current density with depth x; J0 is the surface current density, in amperes per square meter; UI is the current distribution uniformity index; N is the number of sampling points, typically 100; J max is the maximum current density, in amperes per square meter; J i is the current density of the i-th sampling point, in amperes per square meter; J avg is the average current density, in amperes per square meter.

[0087] Wherein, the parameter acquisition method is: the angular frequency ω is calculated from the working frequency f, and multiple frequency points are taken in the range of 100 kilohertz to 1 megahertz; the conductor conductivity σ takes the conductivity of the copper electrode, and the value is 5.8*10 7 Siemens; the material permeability μ is usually taken as the approximate value μ0=4π*10 -7 Henry / meter; the applied electric field intensity E0 is obtained by setting the boundary conditions through finite element simulation, and the typical value is 100 volts / meter; the sampling points are uniformly arranged on the electrode surface, and the point spacing is not greater than 0.5 millimeters.

[0088] This group of equations is based on Maxwell's equations and Helmholtz's equation, which describes the distribution of high-frequency current in the conductor, especially the skin effect phenomenon. The current distribution uniformity index reflects the uniformity of the current distribution, and the value closer to 1 indicates that the distribution is more uniform. Through the gradient current path design and optimization of the electrode structure, the current distribution uniformity can be improved, the local hot spots can be reduced, and the module reliability can be improved.

[0089] Specifically, the principle of the present application is: the core technical principle of the present application is to establish the mapping relationship between the electromagnetic field and the temperature field through the collaborative design method guided by the physical field coupling theory, and to realize the optimization balance of the electromagnetic performance and the thermal performance. First, from the circuit topology level, the present application is based on the parasitic parameter theory, and the relationship between the loop area and the parasitic inductance is clear. The electrode layout is determined through current density distribution simulation, and the current loop is constructed as small as possible to reduce the parasitic inductance from the source; secondly, from the material level, the heterogeneous layer structure heat dissipation substrate is adopted, the micro-channel heat dissipation layer and the thermal resistance suppression layer are designed according to the power density distribution, the heat dissipation capacity of the hot spot area is enhanced, and a stable thermal gradient is formed; thirdly, from the interface level, the direct bonding technology and the surface microstructure treatment are applied, the thermal interface resistance is reduced, the bonding strength is enhanced, and the thermal cycle resistance is improved.

[0090] The technical innovation point of the present application is to introduce a parasitic parameter optimization network model, which maps the geometric topology structure and physical characteristics of the half-bridge module to the parasitic parameter space. The model is trained through multi-physical field simulation data, and a complex correlation between electromagnetic field distribution and temperature field distribution is established. According to the input loop area, current density distribution and other parameters, the optimal parasitic inductance compensation parameter vector can be output. The model adopts a multi-layer graph convolution network structure, which represents the physical structure of the half-bridge module as a graph structure, the nodes represent key components, and the edges represent the interaction between components, which can accurately capture the coupling relationship between different physical quantities.

[0091] In addition, the application also constructs an electromagnetic shielding cavity through a three-dimensional packaging technology, and applies a current resonance suppression structure to reduce switching overshoot, and multi-angle collaborative optimization of electromagnetic performance and thermal performance. This collaborative design method based on the physical field coupling theory theoretically breaks through the problem that electromagnetic optimization and thermal optimization are restricted by each other in traditional design, and provides a systematic solution for high-frequency application of the gallium nitride half-bridge module.

[0092] A specific embodiment 1 of the application is provided below, and the specific implementation of each step in the embodiment 1 is described in detail as follows.

[0093] The specific implementation of step S01 is to use a three-dimensional electromagnetic field solver to design a planar packaging structure. First, a three-dimensional geometric model of the half-bridge module is established, including upper bridge arm devices, lower bridge arm devices, electrode layout and connection lines. Then, material parameters are defined, including an aluminum substrate conductivity of 3.8×10 7 Siemens / meter, a copper electrode conductivity of 5.8×10 7 Siemens / meter, and a gallium nitride chip conductivity of 5.5×10 3 Siemens / meter, and a heat dissipation substrate thermal conductivity of 180 watts / meter·kelvin. According to the breakdown voltage limit of the gallium nitride power device, the maximum allowable voltage spike is 650 volts. A planar current loop construction algorithm is used to calculate the maximum allowable loop area. The algorithm is based on the Maxwell equation set to solve the dynamic electromagnetic field distribution, and the calculation formula is as follows:

[0094]

[0095] In the formula, L p is the parasitic inductance, the unit is henry; μ0 is the vacuum permeability, the value is 4π×10 -7 henry / meter; A is the loop area, the unit is square meter; l is the loop length, the unit is meter; V peak is the voltage spike value, the unit is volt; is the current change rate, the unit is ampere / second; V peak，th is the voltage spike threshold value, the value is 650 volts; A max is the maximum allowable loop area, the unit is square meter. The calculation shows that the maximum allowable loop area is 107 mm 2 . Then, finite element analysis is used to simulate the current density distribution, the current density distribution of the current flowing through each part of the conductor in the power cycle is calculated, a convergent solution is obtained through an iterative solution method based on the Poisson equation and the Ampere law, and the loop design rationality verification is completed. This step aims to determine the current loop design in the half-bridge module, reduce the parasitic inductance by controlling the loop area, thereby reducing the voltage spike, and ensure that the current path design is reasonable through the current density distribution simulation, so as to avoid the local hot spot problem caused by current concentration.

[0096] The specific implementation of step S02 is to construct an electrode layout on an alumina insulating substrate. First, a gradient current path is designed, and the thickness of the conductive layer is gradually changed from the center to the edge. The thickness of the copper layer in the center area is 105 microns, and the thickness of the copper layer in the edge area is 70 microns, forming a continuous gradient distribution. The curvature optimization algorithm is used to design the electrode corner, and the inside radius of the corner is not less than 0.8 mm, which ensures the smooth transition of the current streamline. In view of the skin effect under high frequency, surface treatment technology is applied to form a micro rough structure on the surface of the conductor, increase the effective channel of high frequency current, and control the roughness in the range of 1.2 microns to 1.8 microns. The high frequency current distribution is calculated by combining Laplace equation and Helmholtz equation, and the calculation formula is as follows:

[0097]

[0098] In the formula, J h is the complex representation of high frequency current density, with the unit of ampere per square meter; k is the wave number, with the unit of 1 / m; j is the imaginary unit; ω is the angular frequency, ω = 2πf, with the unit of radian per second; σ is the conductivity of the conductor, with the unit of siemens per meter; μ is the magnetic permeability of the material, with the unit of henry per meter; E0 is the applied electric field strength, with the unit of volt per meter; δ is the skin depth, with the unit of meter; J s (x) is the function of surface current density with depth x; J0 is the surface current density, with the unit of ampere per square meter; UI is the current distribution uniformity index; N is the number of sampling points, and the typical value is 100; J max is the maximum current density, with the unit of ampere per square meter; J i is the current density of the i-th sampling point, with the unit of ampere per square meter; J avg is the average current density, with the unit of ampere per square meter. The electrode structure is optimized by iteration to make the current distribution uniformity index reach above 0.92 in the range of 100 kHz to 1 MHz. The purpose of this step is to optimize the electrode layout, make the high frequency current distribution uniform through gradient design, reduce the concentrated hot spots, and at the same time reduce the electromagnetic interference spectrum diffusion through electrode shape optimization, improve the electromagnetic compatibility of the module under high frequency working state.

[0099] The specific implementation of step S03 is to prepare a heterogeneous layer structure heat dissipation substrate. First, a silicon carbide micro-channel heat dissipation layer is deposited on the copper substrate by plasma enhanced chemical vapor deposition technology, with a thickness of 28 microns to 32 microns, a channel width of 50 microns, a depth of 35 microns, and a spacing of 100 microns. Then, a thermal resistance suppression layer is prepared by electrochemical deposition, which is composed of copper-silver alloy, with a thickness of 15 microns to 18 microns and a silver content of 12% to 15%. The heat diffusion equation is solved by finite difference time domain method, and the calculation formula is as follows:

[0100]

[0101] In the formula, ρ is the material density, with units of kilograms per cubic meter; c p Specific heat capacity, in joules per kilogram of Kelvin; T, temperature field, in Kelvin; t, time, in seconds; k, thermal conductivity, in watts per meter of Kelvin; Q, internal heat source term, in watts per cubic meter; α, thermal diffusivity. The unit is square meters per second; R th Thermal resistance, measured in Kelvin per watt; T max The highest temperature, measured in Kelvin; T amb The ambient temperature is expressed in Kelvin; P total Total power loss, in watts. Input parameters include material thermal conductivity (copper: 398 W / m·Kelvin, silicon carbide: 350 W / m·Kelvin) and power density distribution data (peak power density: 280 W / cm²). 2 The silicon carbide layer thickness (30 μm), microchannel structure parameters (50 μm width, 35 μm depth, 100 μm spacing), and ambient temperature (25°C) were used to calculate the three-dimensional temperature field distribution and heat flux density vector field. Based on the calculation results, thermal resistance was calculated to ensure that the overall thermal resistance is less than 0.35°C / W. This step aims to establish an efficient heat dissipation structure by increasing the heat dissipation area through the microchannel structure and reducing the interface thermal resistance through the thermal resistance suppression layer. This ensures that the thermal gradient balance is maintained under high-frequency operating conditions, avoids the formation of local hot spots, and improves the reliability of the module.

[0102] The specific implementation of step S04 involves using direct bonding technology to fix the gallium nitride chip onto a heat sink substrate. First, plasma activation treatment is performed on the back side of the gallium nitride chip and the surface of the heat sink substrate, with a power controlled at 90 to 110 watts for 60 to 90 seconds, forming an active surface. Subsequently, pressing is performed under low-oxygen conditions (oxygen content below 5 picograms) and high-temperature conditions (300 to 320 degrees Celsius), with a pressure of 0.8 to 1.2 MPa and a holding time of 180 to 240 seconds, forming a low thermal resistance interface. The interface thermal resistance is controlled at 0.06 °C / W·cm. 2 The following steps are followed: First, a gate drive path is constructed, employing a shielded winding structure to reduce drive signal interference. Impedance matching design ensures the drive signal reflection coefficient is less than 0.05, guaranteeing drive signal integrity. Finally, a temperature sensor array is arranged near the chip-substrate interface, using 8-point distributed monitoring to achieve real-time temperature field monitoring. This step aims to achieve a high-quality bond between the gallium nitride chip and the heat dissipation substrate, forming a low thermal resistance interface through direct bonding technology to improve heat dissipation efficiency. Simultaneously, a high-quality gate drive path is constructed to ensure drive signal integrity, laying the foundation for the efficient operation of the half-bridge module.

[0103] The specific implementation of step S05 is to connect the upper and lower bridge arm devices using a non-inductive lead process. First, a parallel plate current path design is used to create a mutual inductance effect by reversing the current flow through the upper and lower metal layers, which offsets the self-inductance effect. The lead width is 1.2 mm, the spacing is 0.15 mm, and the length is not more than 5 mm. Then, a multi-point bonding technology is used to establish metal interconnection. Each power connection point uses 8 gold wires with a diameter of 50 microns connected in parallel, with a spacing of 200 microns, forming a low-impedance current channel. A current resonance suppression structure is provided at the device source and drain connection, including a damping resistance network and a resonance absorption capacitor, with a damping resistance value of 4.7 ohms to 5.3 ohms and an absorption capacitance value of 1.0 nanofarad to 1.2 nanofarad. The damping network absorbs switch transient resonance energy, reducing the oscillation amplitude. Finally, an optimized current path design is used to make the current path S-shaped distribution, reducing the path loop area. Finite element simulation verifies that the loop area is reduced by more than 40%, and the switch overshoot is reduced by more than 35%. This step aims to optimize the internal connection of the half-bridge module, reduce parasitic inductance through non-inductive lead design, and reduce switch overshoot through current resonance suppression structure, improving module switching performance and reliability.

[0104] The specific implementation of step S06 is to use three-dimensional packaging technology to package the half-bridge module. First, an electromagnetic shielding cavity is constructed using an aluminum alloy base and a copper-zinc alloy inner wall composite structure with a wall thickness of 1.5 mm to 2.0 mm and a silver plating thickness of 10 microns to 15 microns, forming a Faraday cage structure with a shielding effectiveness of not less than 85 decibels in the 20 MHz to 100 MHz frequency band and not less than 70 decibels in the 100 MHz to 500 MHz frequency band. Then, an aluminum nitride powder reinforced epoxy composite material is filled, with a powder content of 65% to 70% and a particle size distribution of 1 micron to 10 microns, a thermal conductivity of 3.2 W / m·K or higher, and a breakdown strength of more than 25 kV / mm. A vacuum injection process is used for filling, with a vacuum degree of 50 Pa to 100 Pa, a temperature control of 60°C to 70°C, and an injection rate of 0.5 ml / min to 0.8 ml / min to ensure no air bubbles are formed. Finally, a heat curing process is performed with a temperature gradient, starting from 80°C, increasing to 150°C at a rate of 2°C / min, and maintaining for 120 min to 150 min. This step aims to provide good mechanical protection and electromagnetic shielding, reducing electromagnetic interference through the shielding cavity structure and improving heat conduction efficiency through the heat dissipation composite material filling, ensuring the reliability of the module in high-frequency working state.

[0105] The specific implementation of step S07 is to use a pre-trained parasitic parameter optimization network model to optimize the parameters of the parasitic inductance compensation network. First, the loop area, current density distribution, switch frequency, and thermal gradient balance data are input into the network model, including a loop area of 94 mm 2, the current density distribution data dimension is 128*128*3, the switching frequency is 500 kHz, and the thermal gradient balance data is a 64*64*3 matrix. Then, the optimal parameter combination is found through a multi-objective weighted optimization method, and the optimization objective function calculation formula is as follows:

[0106] min θ J(θ)=α1·J voltage (θ)+α2·J loss (θ)+α3·J thermal (θ)+α4·J constraint (θ);

[0107]

[0108] θ=[L comp ,C comp ,x pos ,y pos ,z pos ,top type ];

[0109] In the formula, J(θ) is the total objective function; θ is the parasitic inductance compensation parameter vector; α1, α2, α3 and α4 are weight coefficients, and typical values are 0.5, 0.2, 0.2 and 0.1 respectively; J voltage is the voltage peak error term; J loss is the loss error term; J thermal is the thermal balance error term; J constraint is the constraint condition error term; V peak，i is the voltage peak value of the i-th working point, in volts; V target，i is the target voltage value of the i-th working point, in volts; N is the number of evaluation working points, and a typical value is 20; P sw is the switching loss, in watts; P comp is the compensation network loss, in watts; P base is the reference power loss, in watts; T j is the junction temperature of the j-th monitoring point, in Kelvin; T avg is the average junction temperature, in Kelvin; T max is the maximum allowable junction temperature, in Kelvin; T amb is the environmental temperature, in Kelvin; M is the number of temperature monitoring points, and a typical value is 16; λ k is the Lagrange multiplier of the k-th constraint condition; g k is the k-th constraint condition function; K is the number of constraint conditions, and a typical value is 8; L comp is the compensation inductance value, in henry; C comp is the compensation capacitance value, in farad; x pos , ypos , z pos is the layout position coordinate in meters; top type is the connection topology parameter, taking an integer value of 0 to 3, representing star, mesh, tree, and hybrid topologies, respectively. The topology feature is extracted by a graph convolution network, with a convolution kernel size of 3x3, 12 layers, and a Leaky ReLU activation function. Then, the electromagnetic field distribution and temperature field distribution are mapped to the feature space by a physical property encoding module, with an encoding dimension of 256, and a self-attention mechanism is used to establish the correlation between the field distributions. Next, the initial values of the compensation inductance and capacitance are generated by a parameter regression module, using a multi-layer perceptron structure with hidden layer sizes of [512, 256, 128]. Finally, the parameters are adjusted by a constraint optimization module to ensure physical consistency, and the parasitic inductance compensation parameter vector is output, including a compensation inductance value of 3.2 nanohenry, a compensation capacitance value of 0.47 nanofarad, and a layout position coordinate of (12.5mm, 8.7mm, -1.2mm) with a star-shaped connection topology. This step aims to optimize the parasitic inductance compensation network design using artificial intelligence technology, quickly generating optimal compensation parameters through a pre-trained model, and improving the electrical performance and reliability of the half-bridge module.

[0110] The specific implementation of step S08 is to enhance the interfacial bonding force by applying surface microstructure processing technology. First, laser micro-texture processing technology is used to form micro-groove structures on the surface of the substrate, with a groove depth of 10-15 microns, a width of 20-30 microns, and a pitch of 50-70 microns, with the grooves arranged in a honeycomb pattern. Then, plasma surface activation is performed using oxygen-argon mixed gas (oxygen: argon = 1:4) at a power of 150-180 watts for 90-120 seconds to form a high-activity surface. For metal interface treatment, an electrochemical deposition method is used to form a silver-tin alloy layer on the surface of the copper electrode with a thickness of 3-5 microns and a silver-tin ratio of 96:4 to improve wettability and bonding force. Finally, hot pressing is performed at a temperature of 250-270 degrees Celsius, a pressure of 2.0-2.5 megapascals, and a holding time of 300-360 seconds to form a high-strength interfacial bond with a bonding strength of more than 18 megapascals. This step aims to improve the interfacial bonding force within the package, increase the effective contact area through surface microstructure design, and improve the material interfacial affinity through surface activation and metal treatment to achieve high-strength bonding, thereby improving the thermal cycle resistance and service life of the module.

[0111] The specific implementation of step S09 is to verify the dynamic response characteristics of the half-bridge module through terminal package test. First, the switching speed is measured by using double pulse test method, applying 200 volts to 600 volts DC voltage, current range of 5 amperes to 30 amperes, environmental temperature of 25 degrees Celsius, measuring turn-on delay time less than 12 nanoseconds, turn-off delay time less than 25 nanoseconds, voltage rise time less than 10 nanoseconds, and voltage fall time less than 8 nanoseconds. Then, the temperature distribution is measured by using the method of combining thermocouple array with infrared thermal imaging, the thermocouple is arranged in 16 points, the sampling frequency is 10 hertz, the infrared thermal imager has a resolution of 320*240 pixels, and the accuracy is ± 0.5 degrees Celsius, and the deviation between the hot spot position and the simulation prediction is less than 10%. The turn-on loss and the switching loss are measured, and the calculation formula is as follows:

[0112]

[0113] P sw =(E on +E off )·f sw ;

[0114]

[0115] P total =P sw +P cond ;

[0116] In the formula, E on is the turn-on energy, unit: joule; E off is the turn-off energy, unit: joule; v ds (t) is the drain-source voltage time function, unit: volt; i d (t) is the drain current time function, unit: ampere; t1, t2 are the start and end times of the turn-on process, unit: second; t3, t4 are the start and end times of the turn-off process, unit: second; P sw is the switching loss, unit: watt; f sw is the switching frequency, unit: hertz; P cond is the turn-on loss, unit: watt; R ds(on) is the turn-on resistance, unit: ohm; I rms is the current effective value, unit: ampere; P totalThe total loss is in watts. Under the condition of an ambient temperature of 25 degrees Celsius, a current of 20 amperes, and a voltage of 400 volts, the on-resistance is 25 milliohms, the conduction loss is 10 watts, and the switching loss is 2.5 watts, with a deviation of less than 8% from the theoretical calculation value. Finally, electromagnetic interference testing is performed, with a measurement frequency range of 150 kilohertz to 30 megahertz, a distance of 3 meters, and a test electromagnetic radiation intensity that meets international electromagnetic compatibility standards, with a radiation emission level that is more than 10 decibels lower than the standard limit. This step aims to comprehensively verify the electrical and thermal performance of the half-bridge module and confirm the effectiveness of the current path design through various testing methods, providing performance assurance for the actual application of the module.

[0117] To better understand and implement the present application, the following provides an embodiment 2 of a specific application scenario of the present application: researchers developed a new gallium nitride half-bridge module packaging method to meet the demand for power semiconductor devices in high-frequency high-power electric vehicle drive systems. In this embodiment, for the inverter design requiring a switching frequency of 500 kHz in an 800V electric vehicle drive system, the gallium nitride half-bridge module packaging method of the present application is used for design and implementation. As shown in Figure 2 , the main components of the gallium nitride half-bridge module are displayed. These include an electromagnetic shielding cavity (step S06), an insulating substrate (step S02), a micro-channel heat dissipation system (step S03), upper and lower bridge arm devices (step S04), and an optimized current path (step S05), among other key structures.

[0118] First, researchers use the three-dimensional electromagnetic field solver ANSYS Q3D to design a planar packaging structure in step S01, establishing a geometric model of the half-bridge module. According to the 900V breakdown voltage limit of the gallium nitride HEMT device, the maximum allowed voltage spike is determined to be 650V. The maximum allowed loop area is calculated to be 92.5mm 2 using the planar current loop construction algorithm. The loop circumference is 0.035m, the current change rate is 3.5x10 9 A / s, and the formula: is used to calculate it. Researchers verify the rationality of this design through current density distribution simulation, with the maximum current density to average current density ratio of each connection area being less than 1.28.

[0119] In step S02, researchers construct a gradient-type current path design electrode layout on an alumina insulating substrate with a thickness of 0.38mm. The electrode layout parameters are shown in Table 1:

[0120] Table 1 Gradient-type electrode layout parameter table

[0121] Parameter name Parameter value Center region copper layer thickness 105 μm Edge region copper layer thickness 70 μm Electrode corner inside radius 0.85 mm Surface roughness 1.5 μm Current distribution uniformity index 0.93

[0122] The researchers calculated the high-frequency current distribution by the Helmholtz equation. At a working frequency of 500 kHz, the calculated value of the skin depth is The surface current density is about 22% higher than the interior, which is consistent with the expected results of the current skin effect.

[0123] In step S03, the researchers prepared a heterogeneous layer structure heat dissipation substrate. A 30 μm thick silicon carbide micro-channel heat dissipation layer was deposited on a copper substrate by plasma-enhanced chemical vapor deposition technology, with a channel width of 50 μm, a depth of 35 μm, and a pitch of 100 μm. Subsequently, a 16 μm thick copper-silver alloy thermal resistance suppression layer was prepared by electrochemical deposition, with a silver content of 13.5%. The thermal characteristic parameters calculated by solving the heat diffusion equation using the finite difference time domain method are shown in Table 2:

[0124] Table 2 Thermal characteristic parameters of heat dissipation substrate

[0125]

[0126]

[0127] As shown in Figure 3 , the structure of the copper substrate, the silicon carbide micro-channel heat dissipation layer, and the copper-silver alloy thermal resistance suppression layer is shown in detail.

[0128] In step S04, the researchers used direct bonding technology to fix the gallium nitride chip on the heat dissipation substrate. The back surface of the gallium nitride chip and the surface of the heat dissipation substrate were subjected to plasma activation treatment, with a power of 105 W and a treatment time of 75 seconds. In an environment with an oxygen content of 3 ppm, the temperature was 310°C, the pressure was 1.0 MPa, and the holding time was 210 seconds, and the interface thermal resistance test value was 0.054°C / W·cm 2 .

[0129] In step S05, the upper and lower bridge arm devices were connected using the non-inductive lead process, as shown in Figure 4 The parallel plate current path design has a lead width of 1.2 mm, a pitch of 0.15 mm, and a length of 4.8 mm. Each power connection point is connected in parallel using 8 gold wires with a diameter of 50 μm and a pitch of 200 μm. The current resonance suppression structure parameters are shown in Table 3:

[0130] Table 3 Current resonance suppression structure parameters

[0131] Parameter name Parameter value Damping resistance value 5.0 Ω Resonance absorption capacitance value 1.1 nF Oscillation amplitude before switching 85V Oscillation amplitude after suppression 32V Oscillation frequency 115 MHz Decay time constant 22 ns

[0132] The optimized current path is S-shaped, with a loop area reduction of 47% and a switch overshoot reduction of 42%, effectively improving system reliability.

[0133] In step S06, the researchers use three-dimensional packaging technology for module packaging. The aluminum alloy base and copper-zinc alloy inner wall composite structure wall thickness is 1.8 mm, and the surface silver plating thickness is 12 μm. The filled aluminum nitride powder reinforced epoxy composite material has a powder content of 68%, a particle size distribution of 1-10 μm, a measured thermal conductivity of 3.5 W / m·K, and a breakdown strength of 27 kV / mm. The vacuum injection process has a vacuum degree of 75 Pa, a temperature of 65 °C, and an injection rate of 0.65 mL / min. The thermal curing treatment starts at 80 °C and rises to 150 °C at a rate of 2 °C / min, and maintains for 130 minutes. The shielding effectiveness test results reach 89 dB at 60 MHz frequency band.

[0134] In step S07, the researchers use a pre-trained parasitic parameter optimization network model to optimize the parameters of the parasitic inductance compensation network. The input loop area is 88.3 mm 2 , the current density distribution data dimension is 128×128×3, the switching frequency is 500 kHz, and the thermal gradient balance data is a 64×64×3 matrix. The objective function J(θ) is calculated as J voltage (θ) + α2·J loss (θ) + α3·J thermal (θ) + α4·J constraint (θ), where the weight coefficients are α1=0.5, α2=0.2, α3=0.2, and α4=0.1. The final output parasitic inductance compensation parameter vector includes a compensation inductance value of 3.2 nH, a compensation capacitance value of 0.47 nF, a layout position coordinate of (12.5 mm, 8.7 mm, -1.2 mm), and a star-shaped connection topology.

[0135] In step S08, the researchers use surface microstructure treatment technology to enhance the interface bonding force. Laser micro-texture processing forms micro-grooves with a depth of 12 μm, a width of 25 μm, and a pitch of 60 μm, distributed in a honeycomb pattern. Plasma surface activation uses oxygen-argon mixed gas (oxygen: argon = 1:4) with a power of 165 W and a processing time of 105 seconds. The electrochemically deposited silver-tin alloy layer has a thickness of 4 μm and a silver-tin ratio of 96:4. The hot pressing treatment temperature is 260 °C, the pressure is 2.2 MPa, and the holding time is 330 seconds, with a measured bonding strength of 21 MPa.

[0136] In step S09, researchers verified the dynamic response characteristics of the half-bridge module through terminal packaging testing. In a dual-pulse test, using a 500V DC voltage, a 25A current, and an ambient temperature of 25℃, the measured turn-on delay time was 9.5ns, the turn-off delay time was 21ns, the voltage rise time was 8.2ns, and the voltage fall time was 7.1ns. Temperature distribution was measured using a combination of thermocouple arrays and infrared thermal imaging, confirming that the hotspot location deviated from the simulation prediction by 7.8%. This was confirmed by formula P. total =P sw +P cond The total losses were calculated. Under ambient temperature of 25℃, current of 20A, and voltage of 400V, the measured on-resistance was 23mΩ, the on-loss was 9.2W, and the switching loss was 2.3W, which deviated from the theoretical calculation by 6.5%. Electromagnetic interference test results showed that the radiated emission level was more than 12dB lower than the standard limit.

[0137] Traditional power module packaging technologies primarily employ planar structures and use aluminum wire bonding to connect chips, resulting in significant parasitic inductance (typically 15-20 nH). This leads to excessive voltage spikes at high frequencies, limiting the improvement of switching frequency and system efficiency. Thermal management relies mainly on single-material heat conduction and lacks microchannel design, resulting in thermal resistance typically exceeding 0.5 °C / W, which is insufficient for high-frequency, high-power applications. In contrast, the gallium nitride half-bridge module packaging method employed in this invention utilizes innovative technologies such as gradient current path design, heterogeneous layer heat dissipation substrate, inductive lead technology, and AI-optimized parasitic inductance compensation network to reduce parasitic inductance to below 3.5 nH and thermal resistance to 0.31 °C / W, achieving a high-frequency switching capability of 500 kHz.

[0138] It should be noted that the variables involved in this invention are explained in detail in Tables 4 and 5 below.

[0139] Table 4. Variable Explanation Table (Part 1)

[0140]

[0141] Table 5. Variable Explanation Table (Part Two)

[0142]

[0143] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in the present invention should be included within the scope of protection of the present invention.

Claims

1. A method of packaging a gallium nitride half-bridge module, comprising: The application relates to a gallium nitride (GaN) semiconductor half-bridge module, and relates to a design method of the module. The application comprises the following steps: A half-bridge module current loop is designed, and a maximum allowable loop area is determined; An electrode layout is constructed on an insulating substrate; A heterogeneous layer structure heat dissipation substrate is prepared; A gallium nitride chip is fixed on the heat dissipation substrate; Upper and lower bridge arm devices are connected, and a current resonance suppression structure is arranged; 2. The gallium nitride half-bridge module packaging method of claim 1, wherein, The half-bridge module is packaged, and an electromagnetic shielding cavity is constructed; a parasitic parameter optimization network model is used to optimize parameters of a parasitic inductance compensation network, and an optimal inductance compensation parameter vector is output, which is used to guide the design of the parasitic inductance compensation network; wherein the parasitic parameter optimization network model maps the geometric topology structure and physical characteristics of the half-bridge module to an optimal parasitic parameter space, and realizes the collaborative optimization of electromagnetic fields and temperature fields.

3. The gallium nitride half-bridge module packaging method of claim 2, wherein, The steps of designing the half-bridge module current loop comprise the following steps: a planar packaging structure is used to design the half-bridge module current loop, the maximum allowable loop area is determined according to a voltage peak threshold, and the rationality of the loop design is verified by using current density distribution simulation.

4. The gallium nitride half-bridge module packaging method of claim 3, wherein, The steps of constructing the electrode layout comprise the following steps: a gradient type current path is used on the insulating substrate to make the high-frequency current distribution uniform and reduce electromagnetic interference spectrum diffusion.

5. The gallium nitride half-bridge module packaging method of claim 4, wherein, The steps of preparing the heterogeneous layer structure heat dissipation substrate comprise the following steps: a heterogeneous layer structure heat dissipation substrate containing a micro-channel heat dissipation layer and a thermal resistance suppression layer is prepared, so that the thermal gradient balance can be maintained under a high-frequency working state, and a thermal resistance calculation is performed by using a heat diffusion equation.

6. The gallium nitride half-bridge module packaging method of claim 5, wherein, The steps of fixing the gallium nitride chip comprise the following steps: the gallium nitride chip is fixed on the heat dissipation substrate by using a direct bonding technology, a low thermal resistance interface is formed, and a gate drive path is constructed.

7. The gallium nitride half-bridge module packaging method of claim 6, wherein, The steps of connecting the upper and lower bridge arm devices comprise the following steps: the upper and lower bridge arm devices are connected by using a non-inductive lead process, an optimal current path is formed, and a current resonance suppression structure is arranged to reduce switch overshoot.

8. The gallium nitride half-bridge module packaging method of claim 7, wherein, The steps of packaging the half-bridge module comprise the following steps: the half-bridge module is packaged by using a three-dimensional packaging technology, an electromagnetic shielding cavity is constructed, and a heat dissipation composite material is filled.

9. The gallium nitride half-bridge module packaging method of claim 8, wherein, The parasitic inductance compensation parameter vector refers to a key parameter set required for optimizing the parasitic inductance compensation network, and comprises compensation inductance values, compensation capacitance values, layout position coordinates and connection topology structure parameters; the parasitic inductance compensation network is a circuit structure composed of inductance and capacitance elements, which offsets the influence of original parasitic inductance through a reverse inductance effect, and reduces a voltage overshoot amplitude.

10. The method of claim 9, wherein, The specific structure of the parasitic parameter optimization network model is a hybrid architecture combining a multi-layer graph convolution network and a parameter generation network, and comprises a topology feature extraction module, a physical characteristic coding module, a parameter regression module and a constraint optimization module. The application further comprises the following steps: A surface microstructure treatment technology is applied to enhance interface bonding force, improve packaging thermal cycle resistance, and prolong module service life. Terminal packaging test is used to verify dynamic response characteristics of the half-bridge module, including switch speed, conduction loss and switch loss measurement, and the effectiveness of the current path design is confirmed.

Images