Chip module

Abstract

The invention relates to the technical field of semiconductor packaging, and discloses a chip module, the chip module comprises a plurality of packaging substrates and a plurality of dielectric layers, and the packaging substrates and the dielectric layers are alternately stacked; at least one groove is formed in the surface of at least part of the packaging substrate, and a chip is arranged in the groove; the packaging substrate is provided with a plurality of dielectric layers, the dielectric layers are provided with metal wires, the metal wires are used for connecting the chips, and the metal wires in different dielectric layers are connected through conductive through holes in the packaging substrate. The chip module has the advantages that the technical problem that the packaging size is limited in multi-chip packaging in the prior art is solved, the packaging size of the chip module is effectively reduced, the integration degree of multiple chips in the chip module is remarkably improved, integration of the multiple chips and multiple layers of wires is achieved, and the chip module is convenient to use. Therefore, the requirements of lightening, thinning and miniaturization of the chip module can be met.

Description

Technical Field

[0001] This application relates to the field of semiconductor packaging technology, and particularly to a chip module. Background Art

[0002] With the development of technology, people's requirements for the performance and size of electronic devices are constantly increasing, which promotes the development of electronic devices towards thinness, lightness, and miniaturization while ensuring high computing performance. There is a chip module in the electronic device, and its size is restricted by the chip packaging technology. In the case of packaging multiple chips, traditional packaging technology usually lays the chips flat on the surface of the substrate or simply stacks the chips three-dimensionally. For an electronic device containing multiple chips, traditional packaging technology will result in an overly large size of the packaging module, unable to effectively meet the requirement of reducing the volume of the electronic device, thereby restricting the process of thinness and miniaturization of the chip module. Therefore, there is an urgent need to propose a chip module that can be applied to multi-chip packaging and provide support for the miniaturization of electronic devices. Summary of the Invention

[0003] This application provides a chip module, which solves the technical problem that the packaging size is restricted in multi-chip packaging in related technologies, effectively reduces the packaging size of the chip module, significantly improves the integration degree of multiple chips in the chip module, and realizes the integration of multiple chips and multi-layer wiring, so as to be able to meet the requirements of thinness and miniaturization of the chip module.

[0004] To achieve the above object, the main technical solutions adopted in this application include:

[0005] An embodiment of this application provides a chip module, which includes a plurality of packaging substrates and a plurality of dielectric layers, and the packaging substrates and the dielectric layers are stacked alternately;

[0006] At least one groove is provided on the surface of at least part of the packaging substrates, and a chip is provided in the groove;

[0007] The dielectric layers have metal traces, the metal traces are used to connect the chips, and the metal traces in different dielectric layers are connected through conductive vias in the packaging substrates.

[0008] The chip module proposed in the embodiments of the present application solves the problem of increased module size caused by laying chips flat by setting grooves on the surface of the packaging substrate and arranging chips in the grooves, improves the space utilization rate of the chip module, and effectively reduces the size of the packaging module. At the same time, the present application also designs and forms complex metal traces in multiple dielectric layers to form effective connections between chips, further improving the space utilization rate of the module and realizing the integration of multiple chips and multi-layer traces. Compared with the related technologies, under the strict requirements for both the packaging size and the module thickness, the present application can not only significantly reduce the size of the chip module to meet the miniaturization requirements of electronic devices, but also improve the integration degree of chips, providing strong support for the thinning and miniaturization of high-performance chip modules.

[0009] Optionally, the depth of the groove is less than the thickness of the packaging substrate where it is located, the height of the chip matches the depth of the groove, the pins of the chip face the dielectric layer and are connected to the metal traces.

[0010] According to the above structure, the chip can be placed completely and stably in the packaging substrate, avoiding the chip from shaking or contacting the metal traces in other dielectric layers, and reducing the influence of the chip thickness on the size of the chip module.

[0011] Optionally, the chip module is provided with pin pads, and the first substrate among the multiple packaging substrates that is farthest from the pin pads is the packaging cover plate of the chip module.

[0012] The first substrate provides packaging protection for the chip module, thus eliminating the molding packaging step in the chip packaging process, simplifying the packaging process, and reducing the packaging cost.

[0013] Optionally, the pins of the chip in the first substrate face the pin pads.

[0014] Optionally, the chip module is provided with pin pads, and the pin pads are arranged on the second substrate among the multiple packaging substrates that is closest to the pin pads;

[0015] The conductive vias in the second substrate are connected to the pin pads.

[0016] The conductive vias in the second substrate are connected to the solder balls in the pin pads for connecting the chip to electronic devices outside the chip module.

[0017] Optionally, the pins of the chip in the second substrate face away from the side of the pin pads.

[0018] Optionally, the material of the packaging substrate uses any one of glass, quartz or ceramic.

[0019] Materials such as glass, quartz, or ceramics have significant advantages in thermal conductivity. When applied to chips with high heat generation, such as processor chips, power chips, and RF chips, they can quickly dissipate heat and reduce the impact of heat accumulation on the chips.

[0020] Optionally, the chip module is provided with pin pads.

[0021] The multiple packaging substrates include a first substrate that is the farthest from the pin pads, a second substrate that is the closest to the pin pads, and at least one third substrate located between the first substrate and the second substrate.

[0022] The surfaces of the third substrates are all adjacent to the dielectric layer. Grooves can be provided on any surface of the third substrates according to actual needs for placing chips.

[0023] Optionally, the pins of the chips in the third substrates face the pin pads; and / or

[0024] The pins of the chips in the third substrates face away from the pin pads.

[0025] Optionally, the chip module is provided with pin pads. The pin pads are provided with a plurality of soldering windows, and a solder mask layer is coated on the pin pads at locations other than the soldering windows.

[0026] Solder balls are provided in the soldering windows for connecting the chip module to electronic devices. A solder resist material is coated at locations other than the soldering windows to form a solder mask layer for protecting the pin pads and improving the soldering quality. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] In order to more clearly illustrate the specific embodiments of the present application or the technical solutions in the prior art, the following will briefly introduce the drawings required for use in the description of the specific embodiments or the prior art. Obviously, the drawings in the following description are some embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0028] Figure 1a It is the first schematic diagram of the traditional packaging technology in the embodiment of the present application;

[0029] Figure 1b It is the second schematic diagram of the traditional packaging technology in the embodiment of the present application;

[0030] Figure 2 It is the structural schematic diagram of the chip module provided by the embodiment of the present application;

[0031] Figure 3 It is the process step diagram of the preparation method of the chip module in the embodiment of the present application;

[0032] Figure 4 It is a schematic structural diagram of the first substrate in the embodiment of the present application;

[0033] Figure 5 It is a schematic structural diagram of the second substrate in the embodiment of the present application;

[0034] Figure 6 It is a schematic diagram of a chip module including a third substrate in the embodiment of the present application.

[0035] Among them, the reference numerals of the accompanying drawings in the specification are as follows: 110. Package substrate, 111. First substrate, 112. Second substrate, 113. Third substrate, 120. Dielectric layer, 130. Groove, 140. Chip, 150. Metal trace, 160. Conductive via, 170. Pin pad. Detailed implementation manners

[0036] To facilitate the understanding of the present application, the present application will be described more comprehensively below with reference to the relevant accompanying drawings. Embodiments of the present application are shown in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, these embodiments are provided so that the disclosure of the present application is more thorough and comprehensive.

[0037] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the technical field to which the present application belongs. The terms used in the specification of the present application herein are only for the purpose of describing specific embodiments and are not intended to limit the present application.

[0038] It should be understood that when an element or layer is referred to as "on", "adjacent to", "connected to", or "coupled to" another element or layer, it can be directly on, adjacent to, connected or coupled to the other element or layer, or there may be intervening elements or layers. In contrast, when an element is referred to as "directly on", "directly adjacent to", "directly connected to", or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types, and / or portions, these elements, components, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type, or portion from another element, component, region, layer, doping type, or portion. Thus, without departing from the teachings of the present invention, the first element, component, region, layer, doping type, or portion discussed below may be referred to as the second element, component, region, layer, or portion; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.

[0039] Spatial relationship terms such as "under", "below", "lower", "beneath", "above", "upper", etc. may be used herein to describe the relationship of one element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientation shown in the figures, spatial relationship terms also include different orientations of the device in use and operation. For example, if the device in the figures is flipped, an element or feature described as "under" or "beneath" or "below" other elements or features will be oriented "on" the other elements or features. Thus, the exemplary terms "under" and "below" can include both an upper and a lower orientation. In addition, the device may also include additional orientations (such as, rotated 90 degrees or other orientations), and the spatial descriptors used herein are to be interpreted accordingly.

[0040] As used herein, the singular forms "a", "an", and "the" may also include the plural forms unless the context clearly dictates otherwise. It should also be understood that the terms "comprises / include" or "has" etc. specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. At the same time, in this specification, the term "and / or" includes any and all combinations of the related listed items.

[0041] With the development of technology, people's requirements for the performance and size of electronic devices are constantly increasing, which promotes the development of electronic devices towards thinner, lighter and smaller while ensuring high computing performance. There is a chip module in the electronic device, and its size is restricted by the chip packaging technology.

[0042] In the case of packaging multiple chips, traditional packaging technologies usually lay the chips flat on the surface of the substrate or simply stack the chips three-dimensionally. However, the above-mentioned packaging solutions will result in an oversized packaging module, which cannot effectively meet the requirement of reducing the volume of the electronic device, thereby restricting the process of making the chip module thinner and smaller. Refer to Figures 1a to 1b , where Figure 1a shows the solution of laying multiple chips flat on the surface of the substrate in traditional packaging technology, and this solution will greatly increase the area occupied by the chips on the surface of the substrate, restricting the size of the chip module and unable to meet the miniaturization requirements. Figure 1b shows the solution of simply stacking the chips three-dimensionally using a Through Silicon Via (TSV) transfer board in traditional packaging technology. This solution makes the chip module restricted by the thickness of the chips in the vertical direction, resulting in an increase in the thickness of the chip module. At the same time, it also increases the packaging complexity and cost.

[0043] Based on the above problems, the present application provides a chip module, which includes a plurality of packaging substrates and a plurality of dielectric layers, and the packaging substrates and the dielectric layers are stacked alternately; at least one groove is provided on the surface of at least part of the packaging substrates, and a chip is provided in the groove; there are metal traces in the dielectric layers, and the metal traces are used to connect the chips, and the metal traces in different dielectric layers are connected through conductive vias in the packaging substrates.

[0044] The chip module provided by the present application solves the problem of the increase in the size of the module caused by laying the chips flat by setting grooves on the surface of the packaging substrates and arranging the chips in the grooves, improves the space utilization rate of the chip module, and effectively reduces the size of the packaging module. At the same time, the present application also designs and forms complex metal traces in a plurality of dielectric layers to form effective connections between the chips, further improving the space utilization rate of the module and realizing the integration of multiple chips and multi-layer traces.

[0045] Compared with the related technologies, in the case of strict requirements for both the packaging size and the module thickness, the present application can not only significantly reduce the size of the chip module to meet the miniaturization requirements of electronic devices, but also improve the integration degree of the chips, providing strong support for the thinning and miniaturization of high-performance chip modules.

[0046] The chip module provided in this specification can be applied to electronic devices with miniaturization requirements, including but not limited to notebooks, desktop computers, smartphones, smart wearable devices (such as virtual reality glasses, smart watches, etc.), and tablet computers. It can be understood that after adaptive modification, this application can also be used in fields that require high space utilization of the chip module, such as data center servers and edge computing devices.

[0047] Embodiments of the invention are described herein with reference to cross-sectional views that are schematic illustrations of ideal embodiments (and intermediate structures) of the invention. It is to be expected that variations in the shapes as shown will result, for example, from manufacturing techniques and / or tolerances. Accordingly, embodiments of the invention should not be limited to the particular shapes of regions shown herein, but include shape deviations resulting, for example, from manufacturing techniques. For example, an implanted region shown as rectangular will typically have rounded or curved features at its edges and / or an implanted concentration gradient, rather than a binary change from the implanted region to the non-implanted region. Similarly, a buried region formed by implantation can result in some implantation in the region between the buried region and the surface through which the implantation takes place. Thus, the regions shown in the figures are substantially schematic, and their shapes do not represent the actual shapes of regions of the device and do not limit the scope of the invention.

[0048] In this embodiment, a chip module is provided, which can be used in the above-mentioned electronic devices. Referring to Figure 2 as shown, the chip module includes a plurality of packaging substrates and a plurality of dielectric layers, and the packaging substrates and the dielectric layers are stacked alternately;

[0049] At least one groove is provided on the surface of at least part of the packaging substrate, and a chip is provided in the groove;

[0050] Metal traces are provided in the dielectric layer, and the metal traces are used to connect the chips, and the metal traces in different dielectric layers are connected through conductive vias in the packaging substrate.

[0051] Specifically, the chip module includes a packaging substrate 110 and a dielectric layer 120. The packaging substrate 110 and the dielectric layer 120 are stacked alternately. The packaging substrate 110 is used to set the groove 130 and place the chip 140. The dielectric layer 120 can be an electrical isolation layer filled with an insulating medium, which is used to provide electrical isolation between adjacent packaging substrates 110 and ensure effective connection between the chips 140.

[0052] Furthermore, in the chip module, grooves 130 are provided on the surface of at least part of the encapsulation substrate 110 for placing chips 140. One or more chips 140 can be placed in each groove 130 according to actual requirements. The number of grooves 130 can be one or more, and the specific number is determined according to the number of chips 140. By placing the chips 140 in the grooves 130 of the encapsulation substrate 110, the influence of the thickness of the chips 140 during encapsulation on the size of the chip module is reduced, and the thickness of the chip module is effectively reduced. At the same time, setting the grooves 130 on the encapsulation substrate 110 also utilizes the space of the encapsulation substrate 110 in the horizontal direction, expands the range where the chips 140 can be set, significantly improves the space utilization rate of the chip module, and reduces the overall size of the chip module.

[0053] In some embodiments, the grooves 130 can be obtained by etching on the encapsulation substrate 110. The encapsulation substrate 110 in this embodiment can be an existing encapsulation substrate 110 without the need to design a special encapsulation substrate 110 for chip encapsulation. It can be understood that the use of the existing encapsulation substrate 110 reduces the encapsulation cost, and at the same time reduces the complexity and difficulty of encapsulation.

[0054] Furthermore, conductive vias 160 are also provided in at least part of the encapsulation substrate 110 in the chip module. The relative positions of the conductive vias 160 and the grooves 130 can be pre-designed to reduce the length of the metal traces 150 and lower the trace cost. Exemplarily, the conductive vias 160 can be obtained by Through Glass Via (TGV) technology, and conductive materials, including but not limited to metal materials such as copper or aluminum, are filled in the conductive vias 160 through techniques such as copper filling process.

[0055] Furthermore, metal traces 150 are provided in the dielectric layer 120. The metal traces 150 are used to connect different chips 140, as well as the chips 140 and the conductive vias 160 to achieve electrical connection between the chips 140 and form passive devices, including but not limited to inductors or capacitors, etc. The material of the metal traces 150 can be copper or aluminum, etc. Exemplarily, the metal traces 150 can be formed by the Redistribution Layer (RDL) process. Through this process, various functional traces can also be formed in the chip module to control and manage the chips 140.

[0056] In some embodiments, the number of substrates 110 can be at least two layers. A single-layer substrate 110 has a problem of fragility. By combining multiple layers of substrates 110, the reliability of the chip module can be effectively improved, and the probability of chip module damage can be reduced. Exemplarily, the substrates 110 can be connected by bonding. After connection, an insulating medium is filled between the substrates 110 to form a dielectric layer 120, and the substrates 110 are stacked and pressed through a multi-layer lamination process to form a chip module with a multi-layer substrate 110 structure.

[0057] Exemplarily illustrate the manufacturing method of the chip module, including:

[0058] S310. Form vias in the package substrate 110, and obtain conductive vias 160 with electrical connection functions through copper filling process.

[0059] S320. Form grooves 130 on the surface of the package substrate 110 by etching, and place chips 140 in the grooves 130.

[0060] S330. Form metal traces 150 on the surface of the package substrate 110, and connect the chips 140 and the conductive vias 160 to form a substrate to be laminated.

[0061] S340. Repeat the above steps to obtain at least two layers of substrates to be laminated.

[0062] S350. Coat an insulating medium on the surface of the substrate to be laminated, stack and press the multi-layer substrates to be laminated to obtain a chip module.

[0063] Among them, the metal traces 150 are formed on the package substrate through a redistribution layer process. Before stacking and pressing the multi-layer substrates to be laminated, adjacent substrates to be laminated are bonded, and an insulating medium is filled between the substrates to be laminated, and finally pressed to obtain a chip module.

[0064] The chip module provided in this embodiment solves the problem of increased module size caused by laying chips flat by setting grooves on the surface of the package substrate and placing chips in the grooves, improves the space utilization rate of the chip module, and effectively reduces the size of the package module. At the same time, the present application also designs and forms complex metal traces in multiple dielectric layers to form effective connections between chips, further improving the space utilization rate of the module and realizing the integration of multiple chips and multi-layer traces.

[0065] Compared with the related technology, in the case of strict requirements for both package size and module thickness, the present application can not only significantly reduce the size of the chip module to meet the miniaturization requirements of electronic devices, but also improve the integration of chips, providing strong support for the thinness and miniaturization of high-performance chip modules.

[0066] As an embodiment of the present application, the depth of the groove is less than the thickness of the encapsulation substrate where it is located, the height of the chip matches the depth of the groove, the pins of the chip face the dielectric layer, and are connected to the metal traces.

[0067] Specifically, the depth of the groove 130 is less than the thickness of the encapsulation substrate 110 where it is located, so that the chip 140 can be stably placed within the encapsulation substrate 110, preventing the chip 140 from shaking or contacting the metal traces 150 in other dielectric layers 120, which may cause connection failure.

[0068] Furthermore, the height of the chip 140 matches the depth of the groove 130, and the chip 140 can be completely placed within the groove 130, so that the thickness of the encapsulation substrate 110 remains unchanged after the chip 140 is placed, reducing the influence of the chip 140 thickness on the size of the chip module.

[0069] It can be understood that the groove 130 is on the surface of the encapsulation substrate 110, facing any dielectric layer 120 adjacent to the encapsulation substrate 110, and metal traces 150 are formed in this dielectric layer 120 to connect the chip 140 in the groove 130. Therefore, the pins of the chip 140 face the dielectric layer 120 to facilitate connection to the metal traces 150.

[0070] As an embodiment of the present application, the chip module is provided with pin pads, and the first substrate among multiple encapsulation substrates that is the farthest from the pin pads is the encapsulation cover of the chip module.

[0071] Specifically, the encapsulation substrate 110 includes a first substrate 111, and the first substrate 111 is the encapsulation substrate 110 that is the farthest from the pin pads 170. Exemplarily, when the chip module is connected to other electronic devices with the pin pads 170 facing down, at this time the first substrate 111 is the uppermost encapsulation substrate 110 in the chip module.

[0072] Refer to Figure 4 As shown, as the encapsulation cover of the chip module, the first substrate 111 does not have conductive vias 160, preventing the chips 140 and metal traces 150 in the first substrate 111 from making electrical connections outside the chip module, ensuring the effective connection of the chips 140.

[0073] As an embodiment of the present application, the pins of the chips in the first substrate face the pin pads.

[0074] Specifically, the first substrate 111 includes a first surface and a second surface, wherein the first surface of the first substrate 111 faces the pin pad 170, and the second surface of the first substrate 111 faces away from the pin pad 170. A plurality of grooves 130 can be provided on the first surface of the first substrate 111 according to actual needs for placing the chips 140. The second surface of the first substrate 111 is a complete surface, that is, no groove 130 is provided on the second surface of the first substrate 111. The second surface of the first substrate 111 provides encapsulation protection for the chip module, thus eliminating the molding encapsulation step in the chip encapsulation process, simplifying the encapsulation process, and reducing the encapsulation cost.

[0075] It can be understood that the first surface of the first substrate 111 is adjacent to the dielectric layer 120, and the groove 130 is provided only on the first surface of the first substrate 111. Therefore, in order to connect the chip 140 in the first substrate 111 to the metal traces 150 in the adjacent dielectric layer 120, the pin direction of the chip 140 faces the adjacent dielectric layer 120, that is, faces the pin pad 170, and is electrically connected to the metal traces 150 in the adjacent dielectric layer 120.

[0076] As an embodiment of the present application, the chip module is provided with pin pads, and the pin pads are arranged on the second substrate that is the closest to the pin pads among the plurality of packaging substrates. The conductive vias in the second substrate are connected to the pin pads.

[0077] Specifically, the packaging substrate 110 includes a second substrate 112, and the second substrate 112 is the packaging substrate 110 that is the closest to the pin pad 170. Exemplarily, when the chip module is connected to other electronic devices with the pin pad 170 facing downwards, at this time, the second substrate 112 is the lowermost packaging substrate 110 in the chip module.

[0078] Refer to Figure 5 As shown, at least one conductive via 160 can be provided in the second substrate 112 according to actual needs for connecting to the pin pad 170. It can be understood that the conductive via 160 in the second substrate 112 is connected to the solder balls in the pin pad 170 for connecting the chip 140 to electronic devices outside the chip module.

[0079] As an embodiment of the present application, the pins of the chips in the second substrate face away from the pin pads.

[0080] Specifically, the second substrate 112 includes a first surface and a second surface. The first surface of the second substrate 112 faces the pin pad 170, and the second surface of the second substrate 112 faces away from the pin pad 170. The first surface of the second substrate 112 is a complete surface, that is, no groove 130 is provided on the first surface of the second substrate 112, and the first surface of the second substrate 112 is directly connected to the pin pad 170. Multiple grooves 130 can be provided on the second surface of the second substrate 112 according to actual needs for placing the chips 140.

[0081] Similarly, the second surface of the second substrate 112 is adjacent to the dielectric layer 120, and grooves 130 are provided only on the second surface of the second substrate 112. Therefore, in order for the chips 140 in the second substrate 112 to be connected to the metal traces 150 in the adjacent dielectric layer 120, their pin directions face the adjacent dielectric layer 120, that is, face away from the pin pad 170, and are electrically connected to the metal traces 150 in the adjacent dielectric layer 120.

[0082] As an embodiment of the present application, the chip module is provided with pin pads. The multiple packaging substrates include a first substrate farthest from the pin pads, a second substrate closest to the pin pads, and at least one third substrate located between the first substrate and the second substrate.

[0083] Specifically, in addition to the first substrate 111 and the second substrate 112, the packaging substrate 110 may further include at least one third substrate 113, and the third substrate 113 is disposed between the first substrate 111 and the second substrate 112. At least one conductive via 160 can be provided in the third substrate 113 according to actual needs for connecting the metal traces 150 in different dielectric layers 120 and connecting the metal traces 150 to the pin pads 170.

[0084] As an embodiment of the present application, the pins of the chips in the third substrate face the pin pads; and / or the pins of the chips in the third substrate face away from the pin pads.

[0085] Specifically, the third substrate 113 includes a first surface and a second surface. The first surface of the third substrate 113 faces the pin pad 170, and the second surface of the third substrate 113 faces away from the pin pad 170. Both the first surface and the second surface of the third substrate 113 are adjacent to the dielectric layer 120, and grooves 130 can be provided on either surface of the third substrate 113 according to actual needs for placing the chips 140.

[0086] It can be understood that the grooves 130 on the first surface of the third substrate 113 face the pin pads 170. Therefore, for the chip 140 placed on the first surface of the third substrate 113, its pins face the pin pads 170 and are electrically connected to the metal traces 150 in the adjacent dielectric layer 120. Similarly, the grooves 130 on the second surface of the third substrate 113 face the side away from the pin pads 170. Therefore, for the chip 140 placed on the second surface of the third substrate 113, its pins face the side away from the pin pads 170 and are electrically connected to the metal traces 150 in the adjacent dielectric layer 120.

[0087] Referring Figure 6 as shown Figure 6 Taking one layer of the third substrate as an example. When the chip module includes the third substrate 113, the third substrate 113 is disposed between the first substrate 111 and the second substrate 112, and grooves 130 can be provided on both surfaces of the third substrate 113 for placing the chips 140. In addition, increasing the number of the third substrates 113 can also improve the structural strength of the chip module and enhance the reliability of the chip module.

[0088] It can be understood that increasing the third substrate 113 can increase the number of chips that can be encapsulated in the chip module. However, too many third substrates 113 will also cause an increase in the thickness of the chip module, resulting in failure to meet the miniaturization requirements, and too many third substrates 113 will also make the metal traces 150 in the dielectric layer 120 too complex. Therefore, in practical applications, the number of the third substrates 113 can be determined by design according to the number of chips and the size requirements of the chip module.

[0089] As an embodiment of the present application, the material of the packaging substrate is any one of glass, quartz or ceramic.

[0090] Specifically, in the related art, the chip 140 is usually placed on a resin substrate. However, the resin has a low thermal conductivity, and for high-power devices and radio frequency devices with large heat generation, there will be a problem of heat accumulation due to failure to dissipate heat in time, which will further affect the performance and reliability of the chip 140. Compared with resin, materials such as glass, quartz or ceramic have obvious advantages in thermal conductivity. When applied to chips with large heat generation such as processor chips, power chips and radio frequency chips, they can dissipate heat quickly and reduce the influence of heat accumulation on the chip 140.

[0091] As an embodiment of the present application, the chip module is provided with pin pads. The pin pads are provided with a plurality of soldering windows, and a solder mask layer is coated on the pin pads at places other than the soldering windows.

[0092] Specifically, the chip module is connected to the pin pad 170, and the welding window of the pin pad 170 is connected to the conductive through hole 160 in the second substrate 112. Solder balls are provided in the welding window for connecting the chip module to the electronic device.

[0093] Furthermore, the pin pad 170 is protected by using a Mask technology, that is, a solder resist material is coated on the areas outside the welding window to form a solder resist layer to protect the pin pad 170 and improve the welding quality.

[0094] Although the embodiments of the present application have been described in conjunction with the accompanying drawings, those skilled in the art can make various modifications and variations without departing from the spirit and scope of the present application, and such modifications and variations all fall within the scope defined by the appended claims.

[0095] It should also be noted that the term "comprising", "including" or any other variation thereof is intended to cover a non-exclusive inclusion, so that a process, method, commodity or device including a series of elements not only includes those elements but also includes other elements not expressly listed, or further includes elements inherent to such process, method, commodity or device. Without further limitation, an element defined by the statement "including a..." does not exclude the existence of additional identical elements in the process, method, commodity or device including the said element.

[0096] Each embodiment in this specification is described in a progressive manner. The same or similar parts among the embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the system embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the description of the method embodiment.

[0097] The above are only the embodiments of the present application and are not intended to limit the present application. For those skilled in the art, the present application can have various changes and modifications. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included within the scope of the claims of the present application.

[0098] Although the embodiments of the present application have been described in conjunction with the accompanying drawings, those skilled in the art can make various modifications and variations without departing from the spirit and scope of the present application, and such modifications and variations all fall within the scope defined by the appended claims.

Claims

1. A chip module, characterized in that, The chip module includes a plurality of packaging substrates and a plurality of dielectric layers, and the packaging substrates and the dielectric layers are stacked alternately; At least one groove is provided on the surface of at least part of the packaging substrates, and a chip is provided in the groove; Metal traces are provided in the dielectric layers, and the metal traces are used to connect the chips, and the metal traces in different dielectric layers are connected through conductive vias in the packaging substrates.

2. The chip module according to claim 1, wherein The depth of the groove is less than the thickness of the packaging substrate where it is located, the height of the chip matches the depth of the groove, the pins of the chip face the dielectric layer and are connected to the metal traces.

3. The chip module according to claim 1, characterized in that The chip module is provided with pin pads, and the first substrate that is the farthest from the pin pads among the plurality of packaging substrates is the packaging cover plate of the chip module.

4. The chip module according to claim 3, wherein The pins of the chip in the first substrate face the pin pads.

5. The chip module according to claim 1, characterized in that, The chip module is provided with pin pads, and the pin pads are arranged on the second substrate that is the closest to the pin pads among the plurality of packaging substrates; The conductive vias in the second substrate are connected to the pin pads.

6. The chip module according to claim 5, wherein, The pins of the chip in the second substrate face away from the pin pads.

7. The chip module according to claim 1, characterized in that The material of the packaging substrate uses any one of glass, quartz or ceramic.

8. The chip module according to claim 1, characterized in that, The chip module is provided with pin pads; The plurality of packaging substrates include a first substrate that is the farthest from the pin pads, a second substrate that is the closest to the pin pads, and at least one third substrate located between the first substrate and the second substrate.

9. The chip module according to claim 8, wherein, The pins of the chip in the third substrate face the pin pads; and / or The pins of the chip in the third substrate face away from the pin pads.

10. The chip module according to claim 1, wherein The chip module is provided with pin pads, the pin pads are provided with a plurality of soldering windows, and a solder mask layer is coated on the pin pads at places other than the soldering windows.

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