Chip packaging structure, manufacturing method thereof and electronic equipment

Abstract

The invention discloses a chip packaging structure and a manufacturing method thereof, and electronic equipment, the chip packaging structure comprises at least one first packaging body, at least one second bare chip and a second substrate, the first packaging body comprises a first bare chip, a first substrate and a first packaging layer, the first bare chip is welded on the first substrate, the first bare chip is electrically connected with the first substrate, and the first packaging layer is electrically connected with the second bare chip. The first packaging layer is located on the first substrate and wraps the side face of the first bare chip, the first packaging body and the second bare chip are both welded to the second substrate, the first substrate and the second bare chip are both electrically connected with the second substrate, the first substrate is at least used for achieving electrical connection between the first bare chip and the second substrate, and the second substrate is at least used for achieving electrical connection between the first bare chip and the second substrate. The second substrate is at least used for realizing interconnection between the first packaging body and the second bare chip and electric connection between the first packaging body and the second bare chip and other devices, so that the layer number, the area and the manufacturing cost of the packaging substrate, namely the second substrate, can be reduced, and the probability of welding risks such as short circuit between the first packaging body and the second substrate can be reduced.

Description

Technical Field

[0001] This application relates to the field of chip technology, and particularly to a chip packaging structure, a manufacturing method thereof, and an electronic device. Background Art

[0002] Current chip packaging structures all include a packaging substrate and a bare die (Die) soldered on the packaging substrate. Among them, the bare die can be electrically connected to other devices such as a printed circuit board through signal lines and pads on the packaging substrate. However, as the integration degree of chips gets higher and higher, the number of bare dies soldered on a single packaging substrate is increasing, resulting in an increasing number of layers, a larger area, and a higher cost of the packaging substrate. Summary of the Invention

[0003] This application discloses a chip packaging structure, a manufacturing method thereof, and an electronic device to solve the problems of an increasing number of stacked layers, a larger area, and a higher cost of the packaging substrate.

[0004] In a first aspect, this application discloses a chip packaging structure, including: at least one first package body, the first package body including a first bare die, a first substrate, and a first packaging layer; the first bare die is soldered on the first substrate, and the first bare die is electrically connected to the first substrate; the first packaging layer is located on the first substrate, and the first packaging layer wraps the side surface of the first bare die; at least one second bare die and a second substrate, the first package body and the second bare die are both soldered on the second substrate, and the first substrate and the second bare die are both electrically connected to the second substrate; the first substrate is at least used to realize the electrical connection between the first bare die and the second substrate; the second substrate is at least used to realize the interconnection between the first package body and the second bare die and the electrical connection between the first package body and the second bare die and other devices.

[0005] In this way, first, the first bare die is soldered on the first substrate and the first packaging layer that wraps the side surface of the first bare die is formed on the first substrate to form the first package body, and then the first package body and the second bare die are soldered on the second substrate, so that the pitch of the pads of the first bare die can be enlarged through the first substrate, and the interconnection between the first bare dies and the electrical connection between the first bare die and other devices such as a printed circuit board can be realized through the second substrate. Furthermore, not only can the line matching between the first bare die and other devices such as a printed circuit board be realized, the number of layers, the area, and the manufacturing cost of the packaging substrate, that is, the second substrate, be reduced, but also the probability of welding risks such as short circuits between the first package body and the second substrate can be reduced, and thus the probability of welding risks in the chip packaging structure can be reduced.

[0006] Moreover, even if there are soldering problems such as short circuits between a certain first package and the second substrate, it will not affect the soldering between other first packages or second dies and the second substrate, which can improve the yield and stability of the chip packaging structure.

[0007] Secondly, since the first package and the second die can be soldered to the second substrate, the difference in area between the first substrate and the first die is smaller than the difference in area between the second substrate and the first die. As a result, the warping of the first substrate after soldering the first die can be reduced, and further, the warping of the second substrate and the chip packaging structure can be reduced.

[0008] In some embodiments of the present application, the side of the first die facing the first substrate has a plurality of first pads; the side of the first substrate facing away from the first die has a plurality of second pads; the side of the second die facing the second substrate has a plurality of third pads; the pitch of the second pads is greater than the pitch of the first pads; and / or, the pitch of the third pads is greater than the pitch of the first pads.

[0009] In this way, not only can the number of layers, area, and manufacturing cost of the packaging substrate, i.e., the second substrate, be reduced by making the pitch of the second pads greater than the pitch of the first pads, and the probability of soldering risks such as short circuits between the first package and the second substrate be reduced, but also the probability of soldering risks such as short circuits between the second substrate and other devices such as printed circuit boards can be reduced by making the pitch of the third pads greater than the pitch of the second pads. Furthermore, the probability of soldering risks in the chip packaging structure can be reduced.

[0010] In some embodiments of the present application, the first package includes a first type of package and / or a second type of package; the first type of package includes one first die and one first substrate; the second type of package includes a plurality of first dies and one first substrate; the first substrate in the second type of package is also used to realize the interconnection between the first dies.

[0011] In this way, the integration degree of the chip packaging structure can be further improved.

[0012] In some embodiments of the present application, the first substrate includes a plurality of first signal lines; the plurality of first pads are electrically connected to the plurality of second pads respectively through the plurality of first signal lines; the second substrate includes a plurality of second signal lines; the plurality of second pads are electrically connected to the plurality of third pads respectively through the plurality of second signal lines; the width of the second signal lines is greater than the width of the first signal lines, and / or, the pitch of the second signal lines is greater than the pitch of the first signal lines.

[0013] In this way, the number of layers of the second substrate can be reduced, thereby reducing the manufacturing process requirements for the second substrate and further reducing the manufacturing cost of the second substrate.

[0014] In some embodiments of the present application, the chip packaging structure further includes a second packaging layer; the second packaging layer is located on the second substrate, and the second packaging layer wraps the sides of the first package and the second die.

[0015] In this way, a plurality of first packages and the second substrate can form a second package, which can improve the structural stability of the chip packaging structure.

[0016] In some embodiments of the present application, the materials of the first substrate and the second substrate both include organic materials.

[0017] In this way, the first substrate and the second substrate can have good mechanical properties and electrical properties, are easy to process and assemble, and have a low manufacturing cost.

[0018] In some embodiments of the present application, the chip packaging structure further includes a packaging cover; the packaging cover is fixed on the second substrate, and the packaging cover and the second substrate enclose a receiving space; the first package and the second die are located in the receiving space; at least one hollowed-out area is provided on the side of the packaging cover facing away from the second substrate; the at least one hollowed-out area exposes the top surface of the first die of the at least one first package respectively; the hollowed-out area is used for dissipating heat from the first die; and / or, the packaging cover includes a packaging cover plate and a packaging retaining wall; the packaging retaining wall is fixed on the second substrate, and the packaging retaining wall surrounds the first package and the second die; the packaging cover plate is integrally formed with the packaging retaining wall, or the packaging cover plate is fixedly connected to the side of the packaging retaining wall facing away from the second substrate.

[0019] In this way, not only can the side of the first die facing away from the first substrate be in contact with the radiator through the hollowed-out area, so that the first die can be directly cooled by the radiator, thereby improving the heat dissipation effect of the chip packaging structure, but also the packaging retaining wall can be used as a reinforcing rib to suppress the warping of the second substrate and further reduce the soldering risk of the chip packaging structure.

[0020] In some embodiments of the present application, the chip packaging structure further includes a reinforcing rib; the reinforcing rib is fixed on the second substrate, and the reinforcing rib is located between adjacent first packages, or the reinforcing rib is located between the first package and the second die, or the reinforcing rib is located between the second dies.

[0021] In this way, the warping of the second substrate and / or the first substrate can be further suppressed by the reinforcing ribs, and the soldering risk of the chip packaging structure can be further reduced.

[0022] In a second aspect, the present application discloses a method for manufacturing a chip packaging structure, including: soldering a first die on a first substrate to electrically connect the first die to the first substrate, and forming a first encapsulation layer on the first substrate to wrap the side surfaces of the first die to form a first encapsulation body; soldering both the first encapsulation body and a second die on a second substrate, and electrically connecting both the first substrate and the second die to the second substrate; wherein, the first substrate is at least used to realize the electrical connection between the first die and the second substrate; the second substrate is at least used to realize the interconnection between the first encapsulation body and the second die and the electrical connection between the first encapsulation body and the second die and other devices.

[0023] In this way, first, solder the first die on the first substrate and form a first encapsulation layer on the first substrate to wrap the side surfaces of the first die to form a first encapsulation body, and then solder the first encapsulation body and the second die on the second substrate. Thus, the pitch of the pads of the first die can be enlarged through the first substrate, and the interconnection between the first dies and the electrical connection between the first die and other devices such as a printed circuit board can be realized through the second substrate. Furthermore, not only can the line matching between the first die and other devices such as a printed circuit board be achieved, the number of layers, area, and manufacturing cost of the packaging substrate, i.e., the second substrate, be reduced, but also the probability of soldering risks such as short circuits occurring between the first encapsulation body and the second substrate can be reduced, and thus the probability of soldering risks occurring in the chip packaging structure can be reduced.

[0024] In a third aspect, the present application discloses an electronic device, including the chip packaging structure as described in any one of the above.

[0025] In this way, the cost of the electronic device can be reduced, the probability of soldering risks such as short circuits occurring in the electronic device can be reduced, and the yield and stability of the electronic device can be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the background art, the drawings required to be used in the embodiments of the present application or the background art will be described below.

[0027] Figure 1 It is a schematic cross-sectional structure diagram of a chip packaging structure disclosed in the present application.

[0028] Figure 2 It is a schematic top view structure diagram of a chip packaging structure disclosed in an embodiment of the present application.

[0029] Figure 3 For Figure 2Schematic cross-sectional structure diagram of the chip package structure shown along the cutting line AA.

[0030] Figure 4 Schematic cross-sectional structure diagram of another chip package structure disclosed in an embodiment of the present application.

[0031] Figure 5 Schematic top-view structure diagram of another chip package structure disclosed in an embodiment of the present application.

[0032] Figure 6 is Figure 5 Schematic cross-sectional structure diagram of the chip package structure shown along the cutting line AA.

[0033] Figure 7 Schematic top-view structure diagram of another chip package structure disclosed in an embodiment of the present application.

[0034] Figure 8 Schematic top-view structure diagram of another chip package structure disclosed in an embodiment of the present application.

[0035] Figure 9 Schematic cross-sectional structure diagram of another chip package structure disclosed in an embodiment of the present application.

[0036] Figure 10 Schematic cross-sectional structure diagram of another chip package structure disclosed in an embodiment of the present application.

[0037] Figure 11 Schematic top-view structure diagram of another chip package structure disclosed in an embodiment of the present application.

[0038] Figure 12 Schematic cross-sectional structure diagram of another chip package structure disclosed in an embodiment of the present application.

[0039] Figure 13 Schematic cross-sectional structure diagram of another chip package structure disclosed in an embodiment of the present application.

[0040] Figure 14 Flowchart of a method for manufacturing a chip package structure disclosed in an embodiment of the present application.

[0041] Figures 15 to 17 Schematic cross-sectional structure diagrams of each step in the method for manufacturing the chip package structure disclosed in an embodiment of the present application. Detailed implementation manners

[0042] Next, the technical solutions in the embodiments of the present application will be described in conjunction with the accompanying drawings in the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without making creative efforts shall fall within the scope of protection of the present application.

[0043] As Figure 1 shown Figure 1 in the figure, it is a schematic cross-sectional structure diagram of a chip packaging structure disclosed in the present application. The chip packaging structure includes a plurality of bare chips 10, a packaging substrate 11, and a packaging cover 12. The packaging cover 12 and the packaging substrate 11 enclose an accommodation space. A plurality of bare chips 10 are located in the accommodation space, and the plurality of bare chips 10 are electrically connected to the packaging substrate 11. Among them, the packaging substrate 11 is used to realize the electrical connection between the plurality of bare chips 10 and the electrical connection between the plurality of bare chips 10 and other devices such as a printed circuit board.

[0044] However, the applicant's research finds that as the integration degree of the chip is getting higher and higher, the number of bare chips 10 soldered on a single packaging substrate 11 is increasing, resulting in an increasing number of layers, a larger area, and a higher cost of the packaging substrate.

[0045] Based on this, the present application discloses a chip packaging structure. First, a first bare chip is soldered on a first substrate to form a first package body, and then the first package body and a second bare chip are soldered on a second substrate to reduce the number of layers, area, and cost of the second substrate, that is, the packaging substrate.

[0046] As an optional implementation of the disclosed content of the present application, an embodiment of the present application discloses a chip packaging structure, as Figure 2 and Figure 3 shown Figure 2 in the figure, it is a schematic top view structure diagram of a chip packaging structure disclosed in an embodiment of the present application. Figure 3 It is Figure 2 a schematic cross-sectional structure diagram of the chip packaging structure shown along the cutting line AA. The chip packaging structure includes at least one first package body 20, at least one second bare chip 21, and a second substrate 22.

[0047] Among them, the first package body 20 includes a first bare chip 200, a first substrate 201, and a first packaging layer 202. The first bare chip 200 is soldered on the first substrate 201, and the first bare chip 200 is electrically connected to the first substrate 201. The first packaging layer 202 is located on the first substrate 201, and the first packaging layer 202 wraps the side surface of the first bare chip 200.

[0048] At least one first package body 20 and at least one second bare chip 21 are soldered on the second substrate 22, and the first substrate 201 of at least one first package body 20 and at least one second bare chip 21 are electrically connected to the second substrate 22. The first substrate 201 is at least used to realize the electrical connection between the first bare chip 200 and the second substrate 22. The second substrate 22 is at least used to realize the interconnection between the first package body 20 and the second bare chip 21 and the electrical connection between the first package body 20 and the second bare chip 21 and other devices such as a printed circuit board.

[0049] In this way, first, the first die 200 is first soldered onto the first substrate 201, and a first encapsulation layer 202 that wraps the sides of the first die 200 is formed on the first substrate 201 to form the first encapsulation body 20. Then, the first encapsulation body 20 and the second die 21 are soldered onto the second substrate 22. Thus, the pitch of the pads of the first die 200 can be increased through the first substrate 201, the interconnection between the first dies 200 and the electrical connection between the first dies 200 and other devices such as a printed circuit board can be achieved through the second substrate 22. Furthermore, not only can the line matching between the first die 200 and other devices such as a printed circuit board be achieved, the number of layers, area, and manufacturing cost of the encapsulation substrate, i.e., the second substrate 22, be reduced, but also the probability of soldering risks such as short circuits occurring between the first encapsulation body 20 and the second substrate 22 can be decreased. Consequently, the probability of soldering risks occurring in the chip encapsulation structure can be reduced.

[0050] Moreover, even if a soldering problem such as a short circuit occurs between a certain first encapsulation body 20 and the second substrate 22, it will not affect the soldering between other first encapsulation bodies 20 or the second die 21 and the second substrate 22, and the yield and stability of the chip encapsulation structure can be improved.

[0051] Secondly, since the first encapsulation body 20 and the second die 21 can be soldered onto the second substrate 22, the difference in area between the first substrate 201 and the first die 200 is smaller compared to the difference in area between the second substrate 22 and the first die 200. As a result, the warping of the first substrate 201 after soldering the first die 200 can be reduced, and further, the warping of the second substrate 22 and the chip encapsulation structure can be reduced.

[0052] In some embodiments of the present application, as Figure 3 shown, the side of the first die 200 facing the first substrate 201 has a plurality of first pads 2001, the side of the first substrate 201 facing away from the first die 200 has a plurality of second pads 2010, the side of the second substrate 22 facing away from the first substrate 201 has a plurality of third pads 211, the pitch of the second pads 2010 is greater than the pitch of the first pads 2001, and / or the pitch of the third pads 211 is greater than the pitch of the second pads 2010.

[0053] In this way, not only can the number of layers, area, and manufacturing cost of the encapsulation substrate, i.e., the second substrate 22, be reduced and the probability of soldering risks such as short circuits occurring between the first encapsulation body 20 and the second substrate 22 be decreased by making the pitch of the second pads 2010 greater than the pitch of the first pads 2001, but also the probability of soldering risks such as short circuits occurring between the second substrate 22 and other devices such as a printed circuit board can be decreased by making the pitch of the third pads 211 greater than the pitch of the second pads 2010. Consequently, the probability of soldering risks occurring in the chip encapsulation structure can be reduced.

[0054] Of course, the present application is not limited to this. In some other embodiments, the pitch of the third pads 211 may also be equal to the pitch of the second pads 2010, which will not be elaborated herein.

[0055] In some embodiments of the present application, the first substrate 201 includes a plurality of first signal lines, the second substrate 22 includes a plurality of second signal lines, a plurality of first pads 2001 are electrically connected to a plurality of second pads 2010 through the plurality of first signal lines, and the plurality of second pads 2010 are electrically connected to a plurality of third pads 211 through the plurality of second signal lines. The width of the second signal lines is greater than the width of the first signal lines, and / or the pitch of the second signal lines is greater than the pitch of the first signal lines.

[0056] It can be understood that when the pitch of the second pads 2010 is greater than the pitch of the first pads 2001, the number of the second signal lines can be larger, and the line width and line pitch of the second signal lines can be larger, so that the number of layers of the second substrate 22 can be reduced, and thus the manufacturing process requirements for the second substrate 22 can be reduced, and further the manufacturing cost of the second substrate 22 can be reduced.

[0057] It should be noted that a traditional packaging substrate not only needs to realize the interconnection between the first dies 200 and the electrical connection between the first dies 200 and other devices such as a printed circuit board, but also needs to increase the pitch of the pads of the first dies 200 to match the lines of other devices such as a printed circuit board. In the embodiments of the present application, the pitch of the pads of the first dies 200 is increased through the first substrate 201, and the interconnection between the first dies 200 and the electrical connection between the first dies 200 and other devices such as a printed circuit board are realized through the second substrate 22. This can not only realize the matching of the lines between the first dies 200 and other devices such as a printed circuit board, but also reduce the number of signal lines and pads in the packaging substrate, i.e., the second substrate 22, and further reduce the area and manufacturing cost of the packaging substrate, i.e., the second substrate 22.

[0058] In some embodiments of the present application, as Figure 3 shown, the first pads 2001, the second pads 2010, and the third pads 211 all include solder balls. The pitch of the first pads 2001 refers to the distance L1 between the solder balls of adjacent first pads 2001, the pitch of the second pads 2010 refers to the distance L2 between the solder balls of adjacent second pads 2010, and the pitch of the third pads 211 refers to the distance L3 between the solder balls of adjacent third pads 211. Of course, the present application is not limited to this. In some other embodiments, the third pads 211 may not include solder balls, and the pitch of the third pads 211 refers to the distance between adjacent third pads.

[0059] It should be noted that if the third pad 211 includes solder balls, the second substrate 22 can be directly soldered to the printed circuit board through the solder balls of the third pad 211. However, if the third pad 211 does not include solder balls, the second substrate 22 needs to be electrically connected to the printed circuit board through a connector.

[0060] In some embodiments of the present application, such as Figure 4 shown, Figure 4 FIG. is a schematic cross-sectional structure diagram of another chip packaging structure disclosed in an embodiment of the present application. The chip packaging structure further includes a second encapsulation layer 220. The second encapsulation layer 220 is located on the second substrate 22, and the second encapsulation layer 220 wraps the sides of the first encapsulation body 20 and the second die 21. In this way, at least one first encapsulation body 20, at least one second die 21, and the second substrate 22 can form a second encapsulation body, which can improve the structural stability of the chip packaging structure. Of course, the present application is not limited thereto. In other embodiments, the chip packaging structure may not include the second encapsulation layer 220, which will not be elaborated here.

[0061] In some embodiments of the present application, the first encapsulation body 20 includes a first type of encapsulation body, such as Figure 3 or Figure 4 shown. The first type of encapsulation body includes a first die 200 and a first substrate 201. Of course, the present application is not limited thereto. In other embodiments, such as Figure 5 and Figure 6 shown, Figure 5 is a schematic top view structure diagram of another chip packaging structure disclosed in an embodiment of the present application. Figure 6 is Figure 5 shown in the schematic cross-sectional structure diagram of the chip packaging structure along the cutting line AA. The first encapsulation body 20 includes a second type of encapsulation body. The second type of encapsulation body includes a plurality of first dies 200 and a first substrate 201. The first substrate 201 is further used to realize the interconnection between the first dies 200. In this way, the integration degree of the chip packaging structure can be further improved.

[0062] It should be noted that the number of first dies 200 included in the first encapsulation body 20 can be set according to actual needs. However, in order to avoid excessive warping of the first substrate 201, the number of first dies 200 included in the first encapsulation body 20 should not be too large.

[0063] It should be noted that in the embodiments of the present application, the chip packaging structure may include one first encapsulation body 20 and one second die 21, or may include a plurality of first encapsulation bodies 20 and a plurality of second dies 21. When the chip packaging structure includes a plurality of first encapsulation bodies 20 and a plurality of second dies 21, the second substrate 22 is further used to realize the interconnection between the first encapsulation bodies 20 and the interconnection between the second dies 21.

[0064] In some embodiments of the present application, the first package 20 and the second die 21 may be arranged in an array on the second substrate 22 as shown. However, the present application is not limited thereto. In other embodiments, as shown in Figure 2 or Figure 7 or Figure 8 shown, Figure 7 is a top view structural schematic diagram of another chip packaging structure disclosed in the embodiments of the present application. Figure 8 is a top view structural schematic diagram of another chip packaging structure disclosed in the embodiments of the present application. The first package 20 and the second die 21 may also be arranged non-arrayedly.

[0065] It should also be noted that the sizes of the first dies 200 in each of the first packages 20 may be the same or different. The sizes of the first dies 200 and the second die 21 may be the same or different. In the embodiments of the present application, the arrangement form can be set according to the sizes of the first package 20 and the second die 21, which will not be elaborated herein.

[0066] In some embodiments of the present application, the materials of the first substrate 201 and the second substrate 22 both include organic materials. Among them, the second substrate 22 may be an ABF substrate or a PCB substrate, etc. In this way, the first substrate 201 and the second substrate 22 can have good mechanical properties and electrical properties, be easy to process and assemble, and the manufacturing cost is also relatively low. Of course, the present application is not limited thereto. In other embodiments, the material of the first substrate 201 may also be an inorganic material such as glass or silicon.

[0067] In some embodiments of the present application, as shown in Figure 9 shown, Figure 9 is a cross-sectional structural schematic diagram of another chip packaging structure disclosed in the embodiments of the present application. The chip packaging structure further includes a packaging cover 12, which is fixed on the second substrate 22, and the packaging cover 12 and the second substrate 22 enclose a receiving space, and at least one first package 20 and at least one second die 21 are located in the receiving space.

[0068] Among them, the packaging cover 12 includes a metal cover, and the packaging cover 12 is in contact with the side of the first die 200 facing away from the first substrate 201. For example, the side of the first die 200 facing away from the first substrate 201 is in contact with the packaging cover 12 through a heat-conducting material, so as to transfer the heat generated by the first die 200 to the packaging cover 12 through the heat-conducting material.

[0069] Of course, the present application is not limited thereto. In other embodiments, as shown in Figure 10 shown, Figure 10The figure is a schematic cross-sectional structure diagram of another chip packaging structure disclosed in an embodiment of the present application. On the side of the packaging cover 12 facing away from the second substrate 22, there is at least one hollowed-out area 120. At least one hollowed-out area 120 exposes the top surface of the first die 200 of at least one first package 20. This hollowed-out area 120 is used for dissipating heat from the first die 200.

[0070] In this way, the side of the first die 200 facing away from the first substrate 201 can be in contact with the heat sink through the hollowed-out area 120, so that the heat sink can directly dissipate heat from the first die 200, thereby improving the heat dissipation effect of the chip packaging structure.

[0071] In some embodiments of the present application, as Figure 9 and Figure 10 shown, the packaging cover 12 includes a packaging cover plate 121 and a packaging retaining wall 122. The packaging retaining wall 122 is fixed on the second substrate 22, and the packaging retaining wall 122 surrounds the first package 20 and the second die 21. The packaging cover plate 121 and the packaging retaining wall 122 are integrally formed. In this way, not only can the packaging retaining wall 122 be used as a reinforcing rib to suppress the warping of the second substrate 22 and further reduce the soldering risk of the chip packaging structure, but also the packaging cover plate 121 and the packaging retaining wall 122 can be integrally formed to simplify the manufacturing process.

[0072] Of course, the present application is not limited to this. In some other embodiments, the packaging cover plate 121 can also be fixedly connected to the side of the packaging retaining wall 122 facing away from the second substrate 22. That is to say, the packaging retaining wall 122 can be first fixed on the second substrate 22, and then the packaging cover plate 121 can be fixedly connected to the side of the packaging retaining wall 122 facing away from the second substrate 22. In this way, the warping of the second substrate 22 can also be further suppressed, and the soldering risk of the chip packaging structure can be further reduced.

[0073] Among them, the packaging retaining wall 122 can be fixed on the second substrate 22 by welding or bonding, etc., and the packaging cover plate 121 can also be fixedly connected to the side of the packaging retaining wall 122 facing away from the second substrate 22 by welding or bonding, etc.

[0074] In some embodiments of the present application, as Figure 11 and Figure 12 shown, Figure 11 The figure is a schematic top view structure diagram of another chip packaging structure disclosed in an embodiment of the present application. FigureThis is a schematic cross-sectional structure diagram of another chip packaging structure disclosed in an embodiment of the present application. The chip packaging structure also includes a reinforcing rib 23, which is fixed on the second substrate 22. The reinforcing rib 23 is located between adjacent first packaging bodies 20, or the reinforcing rib 23 is located between the first packaging body 20 and the second bare chip 21, or the reinforcing rib 23 is located between adjacent second bare chips 21.

[0075] The reinforcing ribs 23 are made of an inert metal material. They can be secured to the second substrate 22 by welding or bonding. Furthermore, the reinforcing ribs 23 can be positioned around the first package body 20, around the second die 21, or around both the first package body 20 and the second die 21, though further details are omitted here. In this manner, the reinforcing ribs 23 can further suppress warping of the second substrate 22 and / or the first substrate 201, further reducing soldering risks in the chip packaging structure.

[0076] In some embodiments of the present application, ​ As shown, ​ This is a schematic cross-sectional structure diagram of another chip packaging structure disclosed in an embodiment of the present application. The chip packaging structure also includes a first passive component 24 and / or a second passive component 25. The first passive component 24 is arranged on the first substrate 201, and the first passive component 24 is electrically connected to the first substrate 201. The second passive component 25 is arranged on the second substrate 22, and the second passive component 25 is electrically connected to the second substrate 22.

[0077] The first passive component 24 and the second passive component 25 include capacitors or resistors, etc. Moreover, the first passive component 24 can be located on the side of the first substrate 201 facing toward or away from the second substrate 22, and the second passive component 25 can also be located on the side of the second substrate 22 facing toward or away from the first substrate 201.

[0078] In this way, signal interference in the first substrate 201 and the second substrate 22 can be eliminated to the greatest extent, thereby improving the signal quality of the chip packaging structure.

[0079] As another optional implementation of the disclosure of this application, the embodiment of this application also discloses a method for manufacturing a chip packaging structure, such as ​ As shown, ​ This is a flow chart of a method for manufacturing a chip packaging structure disclosed in an embodiment of the present application. The manufacturing method includes:

[0080] S101: soldering a first bare die onto a first substrate to electrically connect the first bare die to the first substrate, and forming a first packaging layer on the first substrate to wrap around a side surface of the first bare die to form a first package body.

[0081] First, if​ As shown ​ This is a schematic cross-sectional structure diagram of another chip packaging structure disclosed in the embodiment of the present application. The first die 200 is soldered on the first substrate 201, and the first die 200 is electrically connected to the first substrate 201. Then, as ​ shown ​ This is a schematic cross-sectional structure diagram of another chip packaging structure disclosed in the embodiment of the present application. A first encapsulation layer 202 that wraps the side of the first die 200 is formed on the first substrate 201 to form a first package 20.

[0082] S102: Solder the first package and the second die on the second substrate, and electrically connect the first substrate of the first package and the second die to the second substrate.

[0083] As ​ shown ​ This is a schematic cross-sectional structure diagram of another chip packaging structure disclosed in the embodiment of the present application. At least one first package 20 and at least one second die 21 are soldered on the second substrate 22, and the first substrate 201 of each first package 20 and each second die 21 are electrically connected to the second substrate 22. Among them, the first substrate 201 is at least used to realize the electrical connection between the first die 200 and the second substrate 22; the second substrate 22 is at least used to realize the interconnection between the first package 20 and the second die 21 and the electrical connection between the first package 20 and the second die 21 and other devices such as a printed circuit board.

[0084] Of course, in some other embodiments, a second encapsulation layer 220 that wraps the sides of the first package 20 and the second die 21, a reinforcing rib 23 at least located between the first package 20 and the second die 21, a package cover 12 that surrounds the first package 20 and the second die 21, etc. can also be formed on the second substrate 22, which will not be elaborated here.

[0085] In this way, first, the first die 200 is soldered on the first substrate 201 and a first encapsulation layer 202 that wraps the side of the first die 200 is formed on the first substrate 201 to form a first package 20. Then, the first package 20 and the second die 21 are soldered on the second substrate 22. Thus, the pitch of the pads of the first die 200 can be enlarged through the first substrate 201, and the interconnection between the first die 200 and the electrical connection between the first die 200 and other devices such as a printed circuit board can be realized through the second substrate 22. Furthermore, not only can the line matching between the first die 200 and other devices such as a printed circuit board be realized, the number of layers, area, and manufacturing cost of the packaging substrate, i.e., the second substrate 22, be reduced, but also the probability of welding risks such as short circuits occurring between the first package 20 and the second substrate 22 can be reduced. Furthermore, the probability of welding risks occurring in the chip packaging structure can be reduced.

[0086] Moreover, even if there are soldering problems such as short circuits between a certain first package 20 and the second substrate 22, it will not affect the soldering between other first packages 20 or second dies 21 and the second substrate 22, which can improve the yield and stability of the chip packaging structure.

[0087] Secondly, since the first package 20 and the second die 21 can be soldered to the second substrate 22, the difference in area between the first substrate 201 and the first die 200 is smaller than the difference in area between the second substrate 22 and the first die 200. As a result, the warping of the first substrate 201 after soldering the first die 200 can be reduced, and further, the warping of the second substrate 22 and the chip packaging structure can be reduced.

[0088] As another optional implementation of the disclosure of this application, embodiments of this application also disclose an electronic device including the chip packaging structure disclosed in any of the above embodiments. In this way, the cost of the electronic device can be reduced, the probability of soldering risks such as short circuits in the electronic device can be reduced, and the yield and stability of the electronic device can be improved.

[0089] In some embodiments of this application, the electronic device further includes a printed circuit board or the like electrically connected to the chip packaging structure. The electronic device can be, for example, a computer server, a cloud server, a distributed server, or the like.

[0090] The technical features of the above embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope described in this specification.

[0091] The above embodiments only represent several implementation manners of this specification. The description is relatively specific and detailed, but it cannot be understood as a limitation to the scope of the patent application. It should be noted that for those of ordinary skill in the art, without departing from the concept of this specification, several modifications and improvements can still be made, and these all belong to the protection scope of this specification. Therefore, the protection scope of the patent of this specification should be subject to the appended claims.

Claims

1. A chip packaging structure, characterized in that, Comprising: At least one first package, the first package including a first die, a first substrate, and a first encapsulation layer; The first die is soldered on the first substrate, and the first die is electrically connected to the first substrate; the first encapsulation layer is located on the first substrate, and the first encapsulation layer wraps the side surface of the first die; At least one second die and a second substrate, the first package and the second die are both soldered on the second substrate, and the first substrate and the second die are both electrically connected to the second substrate; The first substrate is at least used to realize the electrical connection between the first die and the second substrate; The second substrate is at least used to realize the interconnection between the first package and the second die and the electrical connection between the first package, the second die and other devices.

2. The chip packaging structure according to claim 1, wherein One side of the first die facing the first substrate has a plurality of first pads; one side of the first substrate facing away from the first die has a plurality of second pads; one side of the second die facing the second substrate has a plurality of third pads; the pitch of the second pads is greater than the pitch of the first pads; and / or, the pitch of the third pads is greater than the pitch of the first pads.

3. The chip packaging structure according to claim 1, wherein The first package includes a first type of package and / or a second type of package; The first type of package includes one first die and one first substrate; The second type of package includes a plurality of first dies and one first substrate; the first substrate in the second type of package is also used to realize the interconnection between the first dies.

4. The chip packaging structure according to claim 1, wherein The first substrate includes a plurality of first signal lines; the plurality of first pads are respectively electrically connected to the plurality of second pads through the plurality of first signal lines; The second substrate includes a plurality of second signal lines; the plurality of second pads are respectively electrically connected to the plurality of third pads through the plurality of second signal lines; The width of the second signal lines is greater than the width of the first signal lines, and / or, the pitch of the second signal lines is greater than the pitch of the first signal lines.

5. The chip package structure according to claim 1, characterized in that, The chip package structure further includes a second encapsulation layer; the second encapsulation layer is located on the second substrate, and the second encapsulation layer wraps the side surfaces of the first package and the second die.

6. The chip packaging structure according to claim 1, wherein, The materials of the first substrate and the second substrate both include organic materials.

7. The chip packaging structure according to claim 1, wherein The chip package structure further includes a package cover; the package cover is fixed on the second substrate, and the package cover and the second substrate enclose a receiving space; The first package and the second die are located in the receiving space; One side of the package cover facing away from the second substrate has at least one hollowed-out area; The at least one hollowed-out area respectively exposes the top surface of the first die of the at least one first package; the hollowed-out area is used for dissipating heat from the first die; and / or, The packaging cover shell includes a packaging cover plate and a packaging retaining wall; the packaging retaining wall is fixed on the second substrate, and the packaging retaining wall is arranged around the first packaging body and the second bare chip; the packaging cover plate and the packaging retaining wall are integrally formed, or the packaging cover plate is fixedly connected to the side of the packaging retaining wall facing away from the second substrate.

8. The chip packaging structure according to claim 1, characterized in that The chip packaging structure further includes a reinforcing rib; the reinforcing rib is fixed on the second substrate, and the reinforcing rib is located between adjacent first packaging bodies, or the reinforcing rib is located between the first packaging body and the second bare chip, or the reinforcing rib is located between the second bare chips.

9. A method for manufacturing a chip packaging structure, characterized in that, include: Soldering a first bare die onto a first substrate to electrically connect the first bare die to the first substrate, and forming a first packaging layer on the first substrate to wrap around sides of the first bare die to form a first package body; Soldering the first package and the second bare chip onto a second substrate, and electrically connecting the first substrate and the second bare chip to the second substrate; Wherein, the first substrate is at least used to realize electrical connection between the first bare chip and the second substrate; The second substrate is at least used to realize the interconnection between the first package and the second die, and the electrical connection between the first package and the second die and other devices.

10. An electronic device, characterized in that, The chip packaging structure comprises the chip packaging structure according to any one of claims 1 to 8.

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