Chip packaging structure, manufacturing method thereof and electronic equipment

Abstract

The invention discloses a chip packaging structure and a manufacturing method thereof and electronic equipment, the chip packaging structure comprises a plurality of first packaging bodies and a second substrate, each first packaging body comprises a bare chip, a first substrate and a first packaging layer, the bare chips are welded on the first substrate and are electrically connected with the first substrate, the first packaging layer is located on the first substrate, and the second substrate is electrically connected with the first packaging layer. The first packaging layer wraps the side face of the bare chip, the multiple first packaging bodies are welded to the second substrate, the first substrate is electrically connected with the second substrate, the first substrate is at least used for achieving electric connection between the bare chip and the second substrate, and the second substrate is at least used for achieving interconnection between the first packaging bodies and electric connection between the first packaging bodies and other devices. Therefore, the probability of welding risk of the chip packaging structure can be reduced, and the yield and stability of the chip packaging structure can be improved.

Description

Technical Field

[0001] This application relates to the field of chip technology, and particularly to a chip packaging structure, a manufacturing method thereof, and an electronic device. Background Art

[0002] Current chip packaging structures all include a packaging substrate and a die (chip) soldered on the packaging substrate. Among them, the die can be electrically connected to other devices such as a printed circuit board through signal lines and pads on the packaging substrate. However, as the integration degree of chips is getting higher and higher, the number of dies soldered on a single packaging substrate is increasing, resulting in an increasing probability of welding risks such as short circuits in the dies. Summary of the Invention

[0003] This application discloses a chip packaging structure, a manufacturing method thereof, and an electronic device to solve the problem of the increasing welding risk of the chip packaging structure.

[0004] In a first aspect, this application discloses a chip packaging structure, including: a plurality of first packaging bodies; each first packaging body includes a die, a first substrate, and a first packaging layer; the die is soldered on the first substrate and is electrically connected to the first substrate; the first packaging layer is located on the first substrate and wraps the side surface of the die; a second substrate; the plurality of first packaging bodies are soldered on the second substrate, and the first substrate is electrically connected to the second substrate; the first substrate is at least used to realize the electrical connection between the die and the second substrate; the second substrate is at least used to realize the interconnection between the first packaging bodies and the electrical connection between the first packaging bodies and other devices.

[0005] In this way, first, because a plurality of first packaging bodies can be soldered on the second substrate, the difference in area between the first substrate and the die is smaller compared to the difference in area between the second substrate and the die. Thus, the warping of the first substrate after soldering the die can be made smaller, and further, the probability of welding problems such as short circuits between the first packaging body and the second substrate can be reduced, and further, the probability of welding risks in the chip packaging structure can be reduced.

[0006] Secondly, first solder the die on the first substrate and form a first packaging layer that wraps the side surface of the die on the first substrate to form a first packaging body, and then solder a plurality of first packaging bodies on the second substrate. By making the pitch of the pads on the first substrate larger than the pitch of the pads on the die, the probability of welding risks such as short circuits between the first packaging body and the second substrate can be reduced, and further, the probability of welding risks in the chip packaging structure can be further reduced.

[0007] Moreover, even if there are soldering problems such as short circuits between a certain first package and the second substrate, it will not affect the soldering between other first packages and the second substrate, which can improve the yield and stability of the chip packaging structure.

[0008] In some embodiments of the present application, the chip packaging structure further includes a second encapsulation layer; the second encapsulation layer is located on the second substrate, and the second encapsulation layer wraps the side surfaces of the first packages.

[0009] In this way, multiple first packages and the second substrate can form a second package, which can improve the structural stability of the chip packaging structure.

[0010] In some embodiments of the present application, one side of the die facing the first substrate has a plurality of first pads; the side of the first substrate facing away from the die has a plurality of second pads; the side of the second substrate facing away from the first substrate has a plurality of third pads; the pitch of the second pads is greater than the pitch of the first pads; and / or the pitch of the third pads is greater than the pitch of the second pads.

[0011] In this way, not only can the probability of soldering risks such as short circuits between the first package and the second substrate be reduced by making the pitch of the second pads greater than the pitch of the first pads, but also the probability of soldering risks such as short circuits between the second substrate and other devices such as a printed circuit board can be reduced by making the pitch of the third pads greater than the pitch of the second pads, and thus the probability of soldering risks in the chip packaging structure can be further reduced.

[0012] In some embodiments of the present application, the materials of the first substrate and the second substrate both include organic materials.

[0013] In this way, the first substrate and the second substrate can have good mechanical properties and electrical properties, be easy to process and assemble, and the manufacturing cost is also relatively low.

[0014] In some embodiments of the present application, the chip packaging structure further includes a packaging cover; the packaging cover is fixed on the second substrate, and the packaging cover and the second substrate enclose an accommodation space; the plurality of first packages are located in the accommodation space; the side of the packaging cover facing away from the second substrate has a plurality of hollowed-out areas; the plurality of hollowed-out areas respectively expose the top surfaces of the plurality of dies; the hollowed-out areas are used for dissipating heat from the dies.

[0015] In this way, one side of the die facing away from the first substrate can be in contact with a radiator through the hollowed-out areas, so that the radiator can directly dissipate heat from the die, and thus the heat dissipation effect of the chip packaging structure can be improved.

[0016] In some embodiments of the present application, the packaging cover shell includes a packaging cover plate and a packaging retaining wall; the packaging retaining wall is fixed on the second substrate, and the packaging retaining wall is arranged around the multiple first packaging bodies; the packaging cover plate and the packaging retaining wall are integrally formed, or the packaging cover plate is fixedly connected to the side of the packaging retaining wall facing away from the second substrate.

[0017] In this way, not only can the packaging retaining wall be used as a reinforcing rib to suppress the warping of the second substrate and further reduce the welding risk of the chip packaging structure, but the packaging cover plate and the packaging retaining wall can also be integrally formed to simplify the manufacturing process.

[0018] In some embodiments of the present application, the chip packaging structure further includes a reinforcing rib; the reinforcing rib is fixed on the second substrate, and the reinforcing rib is at least located between adjacent first packaging bodies.

[0019] In this way, the warping of the second substrate can be further suppressed by the reinforcing ribs, further reducing the welding risk of the chip packaging structure.

[0020] In some embodiments of the present application, the chip packaging structure also includes a first passive device and / or a second passive device; the first passive device is arranged on the first substrate, and the first passive device is electrically connected to the first substrate; the second passive device is arranged on the second substrate, and the second passive device is electrically connected to the second substrate.

[0021] In this way, signal interference in the first substrate and the second substrate can be eliminated to the greatest extent, and the signal quality of the chip packaging structure can be improved.

[0022] In the second aspect, the present application discloses a method for manufacturing a chip packaging structure, comprising: soldering a bare die on a first substrate, electrically connecting the bare die to the first substrate, and forming a first packaging layer on the first substrate to wrap the side of the bare die to form a first package body; soldering a plurality of the first package bodies on a second substrate, and electrically connecting the first substrate to the second substrate; wherein the first substrate is at least used to realize the electrical connection between the bare die and the second substrate; and the second substrate is at least used to realize the interconnection between the first package bodies and the electrical connection between the first package body and other devices.

[0023] In this way, first, the warpage of the first substrate after welding the die can be made smaller, thereby reducing the probability of welding problems such as short circuits between the first package and the second substrate, and further reducing the probability of welding risks in the chip packaging structure. Second, by first welding the die on the first substrate to form the first package and then welding multiple first packages on the second substrate, the probability of welding risks such as short circuits between the first package and the second substrate can be reduced by making the pitch of the pads on the first substrate larger than the pitch of the pads on the die, and further reducing the probability of welding risks in the chip packaging structure. Moreover, even if there is a welding problem such as a short circuit between a certain first package and the second substrate, it will not affect the welding between other first packages and the second substrate, which can improve the yield and stability of the chip packaging structure.

[0024] In a third aspect, the present application discloses an electronic device including the chip packaging structure disclosed in any one of the above.

[0025] In this way, the probability of welding risks such as short circuits in the electronic device can be reduced, and the yield and stability of the electronic device can be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the background art, the drawings required to be used in the embodiments of the present application or the background art will be described below.

[0027] Figure 1 It is a schematic cross-sectional structure diagram of a chip packaging structure disclosed in the present application.

[0028] Figure 2 It is a schematic top view structure diagram of a chip packaging structure disclosed in an embodiment of the present application.

[0029] Figure 3 For Figure 2 The schematic cross-sectional structure diagram of the chip packaging structure shown along the cutting line AA.

[0030] Figure 4 It is a schematic cross-sectional structure diagram of another chip packaging structure disclosed in an embodiment of the present application.

[0031] Figure 5 It is a schematic cross-sectional structure diagram of another chip packaging structure disclosed in an embodiment of the present application.

[0032] Figure 6 It is a schematic top view structure diagram of another chip packaging structure disclosed in an embodiment of the present application.

[0033] Figure 7 It is a schematic top view structure diagram of another chip packaging structure disclosed in an embodiment of the present application.

[0034] Figure 8 Schematic cross-sectional structure diagram of another chip packaging structure disclosed in an embodiment of the present application.

[0035] Figure 9 Schematic cross-sectional structure diagram of another chip packaging structure disclosed in an embodiment of the present application.

[0036] Figure 10 Schematic top view structure diagram of another chip packaging structure disclosed in an embodiment of the present application.

[0037] Figure 11 Schematic cross-sectional structure diagram of another chip packaging structure disclosed in an embodiment of the present application.

[0038] Figure 12 Schematic cross-sectional structure diagram of another chip packaging structure disclosed in an embodiment of the present application.

[0039] Figure 13 Flowchart of a method for manufacturing a chip packaging structure disclosed in an embodiment of the present application.

[0040] Figures 14 to 16 Schematic cross-sectional structure diagrams of each step in a method for manufacturing a chip packaging structure disclosed in an embodiment of the present application. Detailed implementation manners

[0041] Next, the technical solutions in the embodiments of the present application will be described in conjunction with the accompanying drawings in the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present application.

[0042] As Figure 1 shown, Figure 1 Schematic cross-sectional structure diagram of a chip packaging structure disclosed in the present application. The chip packaging structure includes a plurality of bare chips 10, a packaging substrate 11, and a packaging cover 12. The packaging cover 12 and the packaging substrate 11 enclose an accommodation space. A plurality of bare chips 10 are located in the accommodation space, and the plurality of bare chips 10 are electrically connected to the packaging substrate 11. Among them, the packaging substrate 11 is used to realize the electrical connection between the plurality of bare chips 10 and the electrical connection between the plurality of bare chips 10 and other devices such as a printed circuit board.

[0043] In the process of manufacturing the chip packaging structure, the solder balls 10a between the bare chips 10 and the packaging substrate 11 are melted by using a reflow soldering process to realize the electrical connection between the bare chips 10 and the packaging substrate 11. However, the applicant has found through research that as the integration degree of the chip becomes higher and higher, the number of bare chips 10 soldered on a single packaging substrate 11 is increasing, the number of solder balls 10a is increasing, and the pitch is decreasing, resulting in an increasing probability of welding risks such as short circuits in the chip packaging structure.

[0044] Based on this, the present application discloses a chip packaging structure. First, a die is soldered onto a first substrate to form a first package body, and then a plurality of first package bodies are soldered onto a second substrate, so as to reduce the warping of the first substrate and increase the pitch of the pads, thereby reducing the probability of welding risks such as short circuits occurring in the chip packaging structure.

[0045] As an optional implementation of the disclosed content of the present application, embodiments of the present application disclose a chip packaging structure, as Figure 2 and Figure 3 shown, Figure 2 is a top view structural schematic diagram of a chip packaging structure disclosed in an embodiment of the present application, Figure 3 and Figure 2 is a cross-sectional structural schematic diagram of the chip packaging structure shown along the cutting line AA. The chip packaging structure includes a plurality of first package bodies 20 and a second substrate 21.

[0046] Among them, the first package body 20 includes a die 10, a first substrate 201, and a first encapsulation layer 202. The die 10 is soldered onto the first substrate 201, and the die 10 is electrically connected to the first substrate 201. The first encapsulation layer 202 is located on the first substrate 201, and the first encapsulation layer 202 wraps the side surface of the die 10.

[0047] A plurality of first package bodies 20 are soldered onto the second substrate 21, and the first substrate 201 is electrically connected to the second substrate 21. The first substrate 201 is at least used to realize the electrical connection between the die 10 and the second substrate 21. The second substrate 21 is at least used to realize the interconnection between the first package bodies 20 and the electrical connection between the first package bodies 20 and other devices such as a printed circuit board.

[0048] In this way, first, since a plurality of first package bodies 20 can be soldered onto the second substrate 21, the difference in area between the first substrate 201 and the die 10 is smaller than the difference in area between the second substrate 21 and the die 10. Thus, the warping of the first substrate 201 after soldering the die 10 can be made smaller, and further, the probability of welding problems such as short circuits occurring between the first package body 20 and the second substrate 21 can be reduced, and further, the probability of welding risks occurring in the chip packaging structure can be reduced.

[0049] Secondly, by first soldering the die 10 onto the first substrate 201 to form the first package body 20 and then soldering a plurality of first package bodies 20 onto the second substrate 21, the pitch of the second pads 203 on the first substrate 201 can be made larger than the pitch of the first pads 100 on the die 10, so as to reduce the probability of welding risks such as short circuits occurring between the first package body 20 and the second substrate 21, and further, the probability of welding risks occurring in the chip packaging structure can be further reduced.

[0050] Moreover, even if there are soldering problems such as short circuits between a certain first package 20 and the second substrate 21, it will not affect the soldering between other first packages 20 and the second substrate 21, which can improve the yield and stability of the chip packaging structure.

[0051] In some embodiments of the present application, as Figure 4 shown, Figure 4 FIG. is a schematic cross-sectional structure diagram of another chip packaging structure disclosed in the embodiments of the present application. The chip packaging structure further includes a second encapsulation layer 210, which is located on the second substrate 21 and wraps the side surface of the first package 20. In this way, a plurality of first packages 20 and the second substrate 21 can form a second package, which can improve the structural stability of the chip packaging structure. Of course, the present application is not limited thereto. In some other embodiments, the chip packaging structure may not include the second encapsulation layer 210 but include a packaging cover, which will not be elaborated herein.

[0052] In some embodiments of the present application, as Figure 3 and Figure 4 shown, one side of the die 10 facing the first substrate 201 has a plurality of first pads 100, the side of the first substrate 201 facing away from the die 10 has a plurality of second pads 203, and the side of the second substrate 21 facing away from the first substrate 201 has a plurality of third pads 211. The pitch of the second pads 203 is greater than the pitch of the first pads 100, and / or the pitch of the third pads 211 is greater than the pitch of the second pads 203.

[0053] In this way, not only can the probability of soldering risks such as short circuits between the first package 20 and the second substrate 21 be reduced by making the pitch of the second pads 203 greater than the pitch of the first pads 100, but also the probability of soldering risks such as short circuits between the second substrate 21 and other devices such as a printed circuit board can be reduced by making the pitch of the third pads 211 greater than the pitch of the second pads 203. Furthermore, the probability of soldering risks in the chip packaging structure can be further reduced.

[0054] Of course, the present application is not limited thereto. In some other embodiments, the pitch of the third pads 211 may also be equal to the pitch of the second pads 203, which will not be elaborated herein.

[0055] In some embodiments of the present application, the first substrate 201 internally has a plurality of first signal lines, the second substrate 21 internally has a plurality of second signal lines, the plurality of first pads 100 are electrically connected to the plurality of second pads 203 through the plurality of first signal lines, the plurality of second pads 203 are electrically connected to the plurality of third pads 211 through the plurality of second signal lines, the width of the second signal lines is greater than the width of the first signal lines, and / or the pitch of the second signal lines is greater than the pitch of the first signal lines.

[0056] It can be understood that when the pitch of the second pads 203 is greater than the pitch of the first pads 100, the number of the second signal lines can be larger, the line width and line pitch of the second signal lines can be larger, so that the number of layers of the second substrate 21 can be reduced, and further the manufacturing process requirements for the second substrate 21 can be reduced, and further the manufacturing cost of the second substrate 21 can be reduced.

[0057] It should be noted that traditional packaging substrates not only need to achieve the interconnection between the dies 10 and the electrical connection between the dies 10 and other devices such as printed circuit boards, but also need to increase the pitch of the pads of the dies 10 to match the lines of other devices such as printed circuit boards. In the embodiments of the present application, by using the first substrate 201 to increase the pitch of the pads of the die 10 and using the second substrate 21 to achieve the interconnection between the dies 10 and the electrical connection between the die 10 and other devices such as printed circuit boards, not only can the lines of the die 10 and other devices such as printed circuit boards be matched, but also the number of signal lines and pads in the packaging substrate, i.e., the second substrate 21, can be reduced, and further the area and manufacturing cost of the packaging substrate, i.e., the second substrate 21, can be reduced.

[0058] In some embodiments of the present application, as Figure 4 shown, the first pads 100, the second pads 203 and the third pads 211 all include solder balls. The pitch of the first pads 100 refers to the distance L1 between the solder balls of adjacent first pads 100. The pitch of the second pads 203 refers to the distance L2 between the solder balls of adjacent second pads 203. The pitch of the third pads 211 refers to the distance L3 between the solder balls of adjacent third pads 211. Of course, the present application is not limited thereto. In some other embodiments, the third pads 211 may not include solder balls, and the pitch of the third pads 211 refers to the distance between adjacent third pads.

[0059] It should be noted that if the third pads 211 include solder balls, the second substrate 21 can be directly soldered to the printed circuit board through the solder balls of the third pads 211. However, if the third pads 211 do not include solder balls, the second substrate 21 needs to be electrically connected to the printed circuit board through a connector.

[0060] In some embodiments of the present application, as Figure 3 and Figure 4 shown, each first package 20 includes a die 10 and a first substrate 201. Of course, the present application is not limited thereto. In some other embodiments, as Figure 5 shown, Figure 5Schematic cross-sectional structure diagram of another chip packaging structure disclosed in the embodiments of the present application. The first package body 20 may further include a plurality of bare chips 10 and a first substrate 201. That is to say, in the embodiments of the present application, the number of bare chips 10 included in the first package body 20 can be set according to actual needs. However, in order to avoid excessive warping of the first substrate 201, the number of bare chips 10 included in the first package body 20 should not be too large. It can be understood that when the first package body 20 includes a plurality of bare chips 10, the first substrate 201 is also used to realize the interconnection between the bare chips 10.

[0061] In some embodiments of the present application, the chip packaging structure may include two, three, four, five or even more first package bodies 20. The multiple first package bodies 20 may be arranged in an array on the second substrate 21 as Figure 2 shown, but the present application is not limited to this. In some other embodiments, such as Figure 6 or Figure 7 shown, Figure 6 Schematic top view structure diagram of another chip packaging structure disclosed in the embodiments of the present application. Figure 7 Schematic top view structure diagram of another chip packaging structure disclosed in the embodiments of the present application. The multiple first package bodies 20 may be arranged non-arrayedly.

[0062] It should be noted that the sizes of the bare chips 10 in each first package body 20 may be the same or different. In the embodiments of the present application, the arrangement form can be set according to the size of the first package body 20, which will not be elaborated here.

[0063] In some embodiments of the present application, the materials of the first substrate 201 and the second substrate 21 both include organic materials. Among them, the second substrate 21 may be an ABF substrate or a PCB substrate, etc. In this way, the first substrate 201 and the second substrate 21 can have good mechanical properties and electrical properties, be easy to process and assemble, and the manufacturing cost is also relatively low. Of course, the present application is not limited to this. In some other embodiments, the material of the first substrate 201 may also be an inorganic material such as glass or silicon.

[0064] In some embodiments of the present application, such as Figure 8 shown, Figure 8 Schematic cross-sectional structure diagram of another chip packaging structure disclosed in the embodiments of the present application. The chip packaging structure further includes a packaging cover 12, which is fixed on the second substrate 21, and the packaging cover 12 and the second substrate 21 enclose an accommodation space, and a plurality of first package bodies 20 are located in this accommodation space.

[0065] Among them, the encapsulation cover 12 is a metal cover, and the encapsulation cover 12 is in contact with the side of the die 10 facing away from the first substrate 201. Moreover, the side of the die 10 facing away from the first substrate 201 can be in contact with the encapsulation cover 12 through a heat-conducting material, so as to transfer the heat generated by the die 10 to the encapsulation cover 12 through the heat-conducting material.

[0066] Of course, the present application is not limited to this. In some other embodiments, such as Figure 9 shown, Figure 9 is a schematic cross-sectional structure diagram of another chip packaging structure disclosed in the embodiments of the present application. The side of the encapsulation cover 12 facing away from the second substrate 21 has a plurality of hollow areas 120. The plurality of hollow areas 120 respectively expose the top surfaces of the dies 10 of the plurality of first packages 20. The hollow areas 120 are used for dissipating heat from the dies 10.

[0067] In this way, the side of the die 10 facing away from the first substrate 201 can be in contact with the radiator through the hollow areas 120, so that the radiator can directly dissipate heat from the die 10, and further improve the heat dissipation effect of the chip packaging structure.

[0068] In some embodiments of the present application, such as Figure 8 and Figure 9 shown, the encapsulation cover 12 includes an encapsulation cover plate 121 and an encapsulation retaining wall 122. The encapsulation retaining wall 122 is fixed on the second substrate 21, and the encapsulation retaining wall 122 is arranged around the plurality of first packages 20. The encapsulation cover plate 121 and the encapsulation retaining wall 122 are integrally formed. In this way, not only can the encapsulation retaining wall 122 be used as a reinforcing rib to suppress the warping of the second substrate 21 and further reduce the soldering risk of the chip packaging structure, but also the encapsulation cover plate 121 and the encapsulation retaining wall 122 can be integrally formed to simplify the manufacturing process.

[0069] Of course, the present application is not limited to this. In some other embodiments, the encapsulation cover plate 121 can also be fixedly connected to the side of the encapsulation retaining wall 122 facing away from the second substrate 21. That is to say, the encapsulation retaining wall 122 can be first fixed on the second substrate 21, and then the encapsulation cover plate 121 can be fixedly connected to the side of the encapsulation retaining wall 122 facing away from the second substrate 21. In this way, the warping of the second substrate 21 can also be further suppressed, and the soldering risk of the chip packaging structure can be further reduced.

[0070] Among them, the encapsulation retaining wall 122 can be fixed on the second substrate 21 by welding or bonding, etc., and the encapsulation cover plate 121 can also be fixedly connected to the side of the encapsulation retaining wall 122 facing away from the second substrate 21 by welding or bonding, etc.

[0071] In some embodiments of the present application, such as Figure 10 and Figure 11 shown,Figure 10 This is a schematic top view of another chip packaging structure disclosed in an embodiment of the present application. Figure 11 This is a schematic cross-sectional view of another chip packaging structure disclosed in an embodiment of the present application. The chip packaging structure further includes a reinforcing rib 22 . The reinforcing rib 22 is fixed on the second substrate 21 , and the reinforcing rib 22 is at least located between adjacent first packaging bodies 20 .

[0072] The reinforcing ribs 22 are made of an inert metal material. They can be secured to the second substrate 21 by welding or bonding. Furthermore, the reinforcing ribs 22 can be located only between adjacent first package bodies 20 or can be positioned around the first package bodies 20. This will not be discussed further here. In this manner, the reinforcing ribs 22 can further suppress warping of the second substrate 21, further reducing soldering risks in the chip packaging structure.

[0073] In some embodiments of the present application, Figure 12 As shown, Figure 12 This is a schematic cross-sectional structure diagram of another chip packaging structure disclosed in an embodiment of the present application. The chip packaging structure also includes a first passive component 23 and / or a second passive component 24. The first passive component 23 is arranged on the first substrate 201, and the first passive component 23 is electrically connected to the first substrate 201. The second passive component 24 is arranged on the second substrate 21, and the second passive component 24 is electrically connected to the second substrate 21.

[0074] The first passive component 23 and the second passive component 24 include capacitors or resistors, etc. Moreover, the first passive component 23 can be located on the side of the first substrate 201 facing toward or away from the second substrate 21 , and the second passive component 24 can also be located on the side of the second substrate 21 facing toward or away from the first substrate 201 .

[0075] In this way, signal interference in the first substrate 201 and the second substrate 21 can be eliminated to the greatest extent, and the signal quality of the chip packaging structure can be improved.

[0076] As another optional implementation of the disclosure of this application, the embodiment of this application also discloses a method for manufacturing a chip packaging structure, such as Figure 13 As shown, Figure 13 This is a flow chart of a method for manufacturing a chip packaging structure disclosed in an embodiment of the present application. The manufacturing method includes:

[0077] S101: Soldering a bare chip onto a first substrate to electrically connect the bare chip to the first substrate, and forming a first packaging layer on the first substrate to wrap around a side surface of the bare chip to form a first package body.

[0078] First, if Figure 14 As shown, Figure 14Schematic cross-sectional structure diagram of another chip packaging structure disclosed in the embodiments of the present application. The die 10 is welded on the first substrate 201, and the die 10 is electrically connected to the first substrate 201. Then, as Figure 15 shown, Figure 15 Schematic cross-sectional structure diagram of another chip packaging structure disclosed in the embodiments of the present application. A first encapsulation layer 202 that wraps the side of the die 10 is formed on the first substrate 201 to form a first encapsulation body 20.

[0079] S102: Weld a plurality of first encapsulation bodies on the second substrate and electrically connect the first substrate to the second substrate.

[0080] As Figure 16 shown, Figure 16 Schematic cross-sectional structure diagram of another chip packaging structure disclosed in the embodiments of the present application. A plurality of first encapsulation bodies 20 are welded on the second substrate 21, and the first substrate 201 of each first encapsulation body 20 is electrically connected to the second substrate 21. Among them, the first substrate 201 is at least used to realize the electrical connection between the die 10 and the second substrate 21; the second substrate 21 is at least used to realize the interconnection between the first encapsulation bodies 20 and the electrical connection between the first encapsulation bodies 20 and other devices such as printed circuit boards.

[0081] Of course, in some other embodiments, a second encapsulation layer 210 that wraps the side of the first encapsulation body 20, reinforcing ribs 22 at least located between adjacent first encapsulation bodies 20, an encapsulation cover 12 surrounding a plurality of first encapsulation bodies 20, etc. can also be formed on the second substrate 21, which will not be elaborated here.

[0082] In this way, first, because a plurality of first encapsulation bodies 20 can be welded on the second substrate 21, compared with the difference in area between the second substrate 21 and the die 10, the difference in area between the first substrate 201 and the die 10 is smaller, so that the warping of the first substrate 201 after welding the die 10 is smaller, and further the probability of welding problems such as short circuits between the first encapsulation body 20 and the second substrate 21 can be reduced, and further the probability of welding risks in the chip packaging structure can be reduced.

[0083] Secondly, first weld the die 10 on the first substrate 201 to form the first encapsulation body 20, and then weld a plurality of first encapsulation bodies 20 on the second substrate 21. By making the pitch of the second pads 203 on the first substrate 201 greater than the pitch of the first pads 100 on the die 10, the probability of welding risks such as short circuits between the first encapsulation body 20 and the second substrate 21 can be reduced, and further the probability of welding risks in the chip packaging structure can be further reduced.

[0084] Moreover, even if there are soldering problems such as short circuits between a certain first package 20 and the second substrate 21, it will not affect the soldering between other first packages 20 and the second substrate 21, which can improve the yield and stability of the chip packaging structure.

[0085] As another optional implementation of the disclosed content of the present application, the embodiments of the present application also disclose an electronic device, including the chip packaging structure disclosed in any of the above embodiments. In this way, the probability of soldering risks such as short circuits in the electronic device can be reduced, and the yield and stability of the electronic device can be improved.

[0086] In some embodiments of the present application, the electronic device further includes a printed circuit board and the like electrically connected to the chip packaging structure. The electronic device can be, for example, a computer server, a cloud server, a distributed server, etc.

[0087] The technical features of the above embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope described in this specification.

[0088] The above embodiments only represent several implementation manners of this specification, and their descriptions are relatively specific and detailed, but they should not be construed as limiting the scope of the patent application. It should be noted that for those of ordinary skill in the art, without departing from the concept of this specification, several modifications and improvements can still be made, and these all belong to the protection scope of this specification. Therefore, the protection scope of the patent of this specification should be subject to the appended claims.

Claims

1. A chip packaging structure, characterized in that, Comprising: A plurality of first encapsulation bodies; the first encapsulation body includes a die, a first substrate, and a first encapsulation layer; The die is soldered on the first substrate, and the die is electrically connected to the first substrate; the first encapsulation layer is located on the first substrate, and the first encapsulation layer wraps the side surface of the die; A second substrate; the plurality of first encapsulation bodies are soldered on the second substrate, and the first substrate is electrically connected to the second substrate; The first substrate is at least used to realize the electrical connection between the die and the second substrate; the second substrate is at least used to realize the interconnection between the first encapsulation bodies and the electrical connection between the first encapsulation body and other devices.

2. The chip packaging structure according to claim 1, wherein The chip packaging structure further includes a second encapsulation layer; the second encapsulation layer is located on the second substrate, and the second encapsulation layer wraps the side surface of the first encapsulation body.

3. The chip package structure according to claim 1, wherein The side of the die facing the first substrate has a plurality of first pads; the side of the first substrate facing away from the die has a plurality of second pads; the side of the second substrate facing away from the first substrate has a plurality of third pads; the pitch of the second pads is greater than the pitch of the first pads; and / or, the pitch of the third pads is greater than the pitch of the second pads.

4. The chip packaging structure according to claim 1, characterized in that, The materials of the first substrate and the second substrate both include organic materials.

5. The chip packaging structure according to claim 1, wherein The chip packaging structure further includes a packaging cover; the packaging cover is fixed on the second substrate, and the packaging cover and the second substrate enclose a receiving space; The plurality of first encapsulation bodies are located in the receiving space; The side of the packaging cover facing away from the second substrate has a plurality of hollowed-out areas; the plurality of hollowed-out areas respectively expose the top surfaces of the plurality of dies; the hollowed-out areas are used for dissipating heat from the dies.

6. The chip packaging structure according to claim 5, wherein The packaging cover includes a packaging cover plate and a packaging retaining wall; the packaging retaining wall is fixed on the second substrate, and the packaging retaining wall surrounds the plurality of first encapsulation bodies; the packaging cover plate is integrally formed with the packaging retaining wall, or the packaging cover plate is fixedly connected to the side of the packaging retaining wall facing away from the second substrate.

7. The chip packaging structure according to claim 1, characterized in that, The chip packaging structure further includes reinforcing ribs; the reinforcing ribs are fixed on the second substrate, and the reinforcing ribs are at least located between adjacent first encapsulation bodies.

8. The chip packaging structure according to claim 1, wherein, The chip packaging structure further includes a first passive device and / or a second passive device; the first passive device is disposed on the first substrate, and the first passive device is electrically connected to the first substrate; the second passive device is disposed on the second substrate, and the second passive device is electrically connected to the second substrate.

9. A method for manufacturing a chip packaging structure, characterized in that, Comprising: Soldering a die on a first substrate, electrically connecting the die to the first substrate, and forming a first encapsulation layer on the first substrate to wrap the side surface of the die to form a first encapsulation body; Soldering a plurality of the first encapsulation bodies on a second substrate, and electrically connecting the first substrate to the second substrate; Wherein, the first substrate is at least used to realize the electrical connection between the die and the second substrate; the second substrate is at least used to realize the interconnection between the first encapsulation bodies and the electrical connection between the first encapsulation body and other devices.

10. An electronic device, characterized in that, Including the chip packaging structure according to any one of claims 1-8.

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