Three-dimensional packaging structure and circuit board assembly

Abstract

The invention relates to a three-dimensional packaging structure and a circuit board assembly. The three-dimensional packaging structure comprises a first substrate, a chip integration unit and a heat dissipation piece. The first substrate comprises first salient points which are used for being electrically connected with the second substrate. The chip integration unit comprises a plurality of functional chips which are sequentially arranged in the first direction, the chip integration unit is located on one side of the first substrate in the thickness direction, and each functional chip comprises a device layer, a back power supply layer, an interconnection layer and a second convex point; the second salient points are at least located between the back power supply layer and the first substrate and between the interconnection layer and the first substrate, and at least one of the back power supply layer and the interconnection layer is connected with the first substrate through the second salient points, so that signals in the at least one of the power supply layer and the interconnection layer are conducted into the first substrate. The heat dissipation piece is at least arranged on the outer side of the chip integration unit in the first direction. The heat dissipation performance, the power supply integrity and the integration density of the three-dimensional packaging structure can be improved.

Description

Technical Field

[0001] This application relates to the technical field of three-dimensional chip packaging, and particularly to a three-dimensional packaging structure and a circuit board assembly. Background Art

[0002] With the rapid development of semiconductor technology, stacked chips (3D ICs), as an advanced integration technology, have gradually become an important solution in fields such as high-performance computing, mobile devices, and artificial intelligence accelerators. Stacked chips integrate multiple chips or wafers in the vertical direction and use technologies such as through-silicon vias (TSVs) to achieve interlayer interconnection, thereby significantly improving system integration, shortening interconnection lengths, and reducing signal transmission delays. Compared with traditional two-dimensional planar packaging, stacked chips can achieve higher functional densities per unit volume, while meeting the requirements of miniaturization, high bandwidth, and low power consumption. Therefore, they are highly favored in scenarios such as data centers, 5G communications, and the Internet of Things.

[0003] In 3D ICs, due to the voltage drop degradation of the top chip and the heat accumulation of the bottom chip caused by chip stacking, the performance of the chips decreases, which limits the improvement of the integration degree, performance, and realization of multiple functions of 3D ICs. Summary of the Invention

[0004] The three-dimensional packaging structure and circuit board assembly provided by the embodiments of this application can improve the heat dissipation performance, power integrity, and integration density of the three-dimensional packaging structure.

[0005] In a first aspect, according to an embodiment of this application, a three-dimensional packaging structure is proposed. The three-dimensional packaging structure includes a first substrate, a chip integration unit, and a heat dissipation component. The first substrate includes first bumps for electrically connecting to a second substrate. The chip integration unit includes multiple functional chips arranged in sequence along a first direction. The chip integration unit is located on one side of the first substrate in the thickness direction. The functional chip includes a device layer, a back power supply layer, an interconnection layer, and second bumps. The back power supply layer, the device layer, and the interconnection layer are stacked and electrically connected along the first direction. In the thickness direction of the first substrate, the second bumps are at least located between both the back power supply layer and the interconnection layer and the first substrate. At least one of the back power supply layer and the interconnection layer is connected to the first substrate through the second bumps, so that signals in at least one of the power supply layer and the interconnection layer are conducted into the first substrate. The heat dissipation component is at least provided on the outer side of the chip integration unit along the first direction.

[0006] According to the first aspect of the embodiment of this application, the chip integration unit includes a first side and a second side opposite to each other along the first direction. The heat dissipation component includes two outer heat dissipation components, and one of the two outer heat dissipation components is provided on the first side, and the other is provided on the second side.

[0007] According to the first aspect of the embodiments of the present application, in the direction from the first side to the second side, the back power supply layer, the device layer, and the interconnection layer of at least some of the multiple functional chips are sequentially arranged.

[0008] According to the first aspect of the embodiments of the present application, the chip integration unit includes a first functional chip and a second functional chip arranged in sequence along a first direction, and at least one of the interconnection layer of the first functional chip and the interconnection layer of the second functional chip is located between the device layer of the first functional chip and the device layer of the second functional chip.

[0009] According to the first aspect of the embodiments of the present application, the chip integration unit further includes a third functional chip located on the side of the second functional chip facing away from the first functional chip, and an interconnection layer of the third functional chip is provided between the device layer of the third functional chip and the device layer of the second functional chip. Alternatively, the interconnection layer of the third functional chip is located on the side of the device layer of the third functional chip facing away from the second functional chip.

[0010] According to the first aspect of the embodiments of the present application, the thermal conductivity of the outer heat dissipation member located on the first side is greater than the thermal conductivity of the outer heat dissipation member located on the second side.

[0011] According to the first aspect of the embodiments of the present application, the heat dissipation member further includes an intermediate heat dissipation member, and the intermediate heat dissipation member is located between two adjacent functional chips.

[0012] According to the first aspect of the embodiments of the present application, a connection layer is provided between the heat dissipation member and the functional chip, and the connection layer includes a connection main body and a support structure, and the support structure is embedded in the connection main body.

[0013] According to the first aspect of the embodiments of the present application, the material of the heat dissipation member includes diamond.

[0014] According to the first aspect of the embodiments of the present application, it further includes a support portion, and a support portion is provided between at least one of the chip integration unit and the heat dissipation member and the first substrate.

[0015] According to the first aspect of the embodiments of the present application, it further includes a packaging layer, and the packaging layer is at least located on the peripheral sides of the heat dissipation member and the chip integration unit.

[0016] According to the first aspect of the embodiments of the present application, the packaging layer includes a first packaging portion and a second packaging portion, the first packaging portion is located on the peripheral sides of the heat dissipation member and the chip integration unit, and the second packaging portion is located on the side of at least one of the heat dissipation member and the chip integration unit facing away from the first substrate.

[0017] In a second aspect, according to the embodiments of the present application, a circuit board assembly is proposed, including: a three-dimensional packaging structure as described in any of the foregoing embodiments and a second substrate, and a first bump of the three-dimensional packaging structure is electrically connected to the second substrate.

[0018] In the stacked power module and circuit board assembly provided by the present application, by disposing the heat dissipation member on the outer side of the chip integration unit along the first direction, the heat dissipation area of the chip integration unit can be increased. At the same time, the external heat dissipation device for dissipating heat from the three-dimensional packaging structure is located at the top of the three-dimensional packaging structure. Through the above settings, the heat dissipation path between all functional chips and the external heat dissipation device can be shortened, the uniformity of the heat dissipation performance of all functional chips can be improved, and thus the heat dissipation performance can be improved. In addition, since the second bumps are disposed between both the back power supply layer and the interconnection layer and the substrate, the back power supply layer can supply power to the functional chips, and the back power supply layer of each functional chip can be directly connected to the first substrate, so as to shorten the electrical connection path between the functional chip and the first substrate, reduce the voltage drop loss, improve the power integrity of the three-dimensional packaging structure, and increase the integration density of the three-dimensional packaging structure. Description of the Drawings

[0019] The features, advantages and technical effects of the exemplary embodiments of the present application will be described below with reference to the drawings.

[0020] Figure 1 An isometric structural schematic diagram of a three-dimensional packaging structure provided by some embodiments of the present application;

[0021] Figure 2 A cross-sectional structural schematic diagram of a three-dimensional packaging structure provided by some embodiments of the present application;

[0022] Figure 3 Another cross-sectional structural schematic diagram of a three-dimensional packaging structure provided by some embodiments of the present application;

[0023] Figure 4 Another cross-sectional structural schematic diagram of a three-dimensional packaging structure provided by some embodiments of the present application;

[0024] Figure 5 Another cross-sectional structural schematic diagram of a three-dimensional packaging structure provided by some embodiments of the present application;

[0025] Figure 6 Another cross-sectional structural schematic diagram of a three-dimensional packaging structure provided by some embodiments of the present application;

[0026] Figure 7 Another cross-sectional structural schematic diagram of a three-dimensional packaging structure provided by some embodiments of the present application;

[0027] Figure 8 Another cross-sectional structural schematic diagram of a three-dimensional packaging structure provided by some embodiments of the present application;

[0028] Figure 9 Another cross-sectional structural schematic diagram of a three-dimensional packaging structure provided by some embodiments of the present application;

[0029] Figure 10 Schematic cross-sectional structure diagram of another three-dimensional packaging structure provided by some embodiments of the present application;

[0030] Figure 11 Schematic cross-sectional structure diagram of another three-dimensional packaging structure provided by some embodiments of the present application;

[0031] Figure 12 Schematic cross-sectional structure diagram of a circuit board assembly provided by some embodiments of the present application.

[0032] Marking description:

[0033] 10. First substrate; 11. First bump; 12. Silicon layer; 13. Wiring layer;

[0034] 20. Chip integration unit; 21. Functional chip; 211. Device layer; 212. Interconnection layer; 2121. Front-end interconnection layer; 2122. Back-end interconnection layer; 213. Second bump; 214. Back power supply layer; S1. First side; S2. Second side; T1. First functional chip; T11. First device layer; T12. First interconnection layer; T2. Second functional chip; T21. Second device layer; T22. Second interconnection layer; T3. Third functional chip; T31. Third device layer; T32. Third interconnection layer;

[0035] 30. Heat dissipation component; 31. Outer heat dissipation component; 32. Intermediate heat dissipation component;

[0036] 40. Connection layer; 41. Connection body; 42. Support structure; 50. Support part; 60. Encapsulation layer; 61. First encapsulation part; 62. Second encapsulation part; 70. Second substrate; 71. Copper pillar bump;

[0037] X. First direction; Z. Thickness direction.

[0038] In the drawings, the same components are denoted by the same reference numerals. The drawings are not drawn to actual scale. Detailed implementation manners

[0039] The features and exemplary embodiments of various aspects of the present invention will be described in detail below. In order to make the objectives, technical solutions and advantages of the present application clearer, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only intended to explain the present application, rather than to limit the present application. For those skilled in the art, the present application can be implemented without some of these specific details. The following description of the embodiments is only intended to provide a better understanding of the present application by showing examples of the present application.

[0040] It should be noted that in this document, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprising", "including" or any other variation thereof are intended to cover non-exclusive inclusion, such that a process, method, article or device comprising a series of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "comprising..." does not exclude the presence of additional identical elements in the process, method, article or device comprising the said element.

[0041] For a better understanding of the present application, on the one hand, the following will describe in detail Figures 1 to 12 a three-dimensional packaging structure and a circuit board assembly according to an embodiment of the present application.

[0042] Figure 1 An axonometric structural schematic diagram of a three-dimensional packaging structure provided by some embodiments of the present application. Figure 2 A cross-sectional structural schematic diagram of a three-dimensional packaging structure provided by some embodiments of the present application.

[0043] As Figure 1 and Figure 2 shown, an embodiment of the present application provides a three-dimensional packaging structure, which includes a first substrate 10, a chip integration unit 20, and a heat dissipation member 30. The first substrate 10 includes first bumps 11 for electrically connecting to a second substrate 70. The chip integration unit 20 includes a plurality of functional chips 21 arranged in sequence along a first direction. The chip integration unit 20 is located on one side of the first substrate 10 in the thickness direction. The functional chip 21 includes a device layer 211, a back power supply layer 214, an interconnection layer 212, and second bumps 213. The back power supply layer 214, the device layer 211, and the interconnection layer 212 are stacked and electrically connected along the first direction. In the thickness direction of the first substrate 10, the second bumps 213 are at least located between both the back power supply layer 214 and the interconnection layer 212 and the first substrate 10. At least one of the back power supply layer 214 and the interconnection layer 212 is connected to the first substrate 10 through the second bumps 213, so that signals in at least one of the power supply layer and the interconnection layer 212 are conducted into the first substrate 10. The heat dissipation member 30 is at least disposed on the outer side of the chip integration unit 20 along the first direction.

[0044] Optionally, the first substrate 10 may include a silicon layer 12. The silicon layer 12 is located between the second substrate 70 and the chip integration unit 20. Circuit interconnection, signal exchange, and mechanical support between the functional chip 21 and the second substrate 70 can be achieved through the bump technology. The silicon layer 12 includes through holes, which can serve as channels for electrical connection. Exemplarily, when the material of the silicon layer 12 is silicon, the through holes are through-silicon vias (TSVs).

[0045] Optionally, the first substrate 10 may further include a wiring layer 13. Exemplarily, the wiring layer 13 may be located between the silicon layer 12 and the second substrate 70, or the wiring layer 13 may be located on the side of the silicon layer 12 facing away from the second substrate 70. Optionally, there may be two wiring layers 13, one of which is located between the silicon layer 12 and the second substrate 70, and the other wiring layer 13 is located on the side of the silicon layer 12 facing away from the second substrate 70. Optionally, the wiring layer 13 may be a redistribution layer (RDL).

[0046] Optionally, the wiring layer 13 located between the silicon layer 12 and the second substrate 70 may be connected through the first bumps 11. Optionally, there may be multiple first bumps 11, and an insulating material may be filled between the multiple first bumps 11. Optionally, the insulating material includes underfill or silicon dioxide. Optionally, the first bumps 11 may be bumps formed by tin-based solder. Most solders are lead-containing solders (such as SnPb). Optionally, appropriate metal elements such as silver, zinc, copper, and bismuth may be added to the Sn-based solder to form a lead-free alloy solder to improve performance, which can meet the mechanical, electrical, and thermal performance requirements of the device. Optionally, the solder includes Sn-Ag-Cu, Sn-Cu, Sn-Ag, Sn-Zn, and Sn-Bi solders.

[0047] The first bumps 11 may be located on the side of the first substrate 10 facing away from the chip integration unit 20, that is, the first bumps 11 are provided on one side of the first substrate 10 along its thickness direction, and the chip integration unit 20 and the heat sink 30 are provided on the other side.

[0048] The first bumps 11 may be welded and connected to the pads on the second substrate 70.

[0049] The chip integration unit 20 includes multiple functional chips 21, and the multiple functional chips 21 may be stacked in a face-to-face (F2F) stacking manner or a face-to-back (F2B) stacking manner.

[0050] The embodiments of the present application do not limit the type of the functional chip 21. Exemplarily, the functional chip 21 may include a memory chip and / or a logic chip. Exemplarily, the device types in the device layer 211 may include fin field-effect transistors or nanosheet field-effect transistors.

[0051] Optionally, multiple stacked functional chips 21 may be of the same type, or may be a stack of multiple types of functional chips 21.

[0052] Optionally, multiple functional chips 21 may be electrically connected to each other, or may be only stacked. Optionally, multiple functional chips 21 may be electrically connected through a stacked interconnection layer 212 to achieve inter-chip interconnection, or may be connected to the circuits in the first substrate through the second bumps 213, and the circuits in the first substrate 10 perform mutual electrical connection.

[0053] The functional chip 21 includes a device layer 211 and an interconnection layer 212. The device layer may include multiple transistors, and the multiple transistors are connected to form a functional circuit. The functional circuit is electrically connected to the device layer 211 of an adjacent functional chip 21 through the interconnection layer 212.

[0054] Optionally, the number of the device layers 211 may include one layer or multiple layers.

[0055] Optionally, the number of the interconnection layers 212 may include one layer or multiple layers.

[0056] The interconnection layer 212 can be used to electrically connect two adjacent functional chips 21, and can also be used to electrically connect two adjacent device layers 211. The interconnection layer 212 can serve as a connection film layer for functional signals to facilitate the transmission of functional signals between the functional chip 21 and the first substrate 10.

[0057] The back power supply layer 214 is used to provide a power connection for the device layer 211. Exemplarily, the back power supply layer 214 can transmit an electrical signal to the transistor.

[0058] Optionally, the back power supply layer 214 may include VDD traces and VSS traces.

[0059] Optionally, when the device layer 211 is multiple layers, the interconnection layer 212 may be located between two adjacent device layers 211 to electrically connect the two device layers 211.

[0060] Optionally, the interconnect layer 212 may include a front-end interconnect layer 2121 and a back-end interconnect layer 2122. The front-end interconnect layer 2121 may be located between the back-end interconnect layer 2122 and the device layer 211. The front-end interconnect layer 2121 may be used to electrically connect the back-end interconnect layer 2122 to the device layer 211, and the back-end interconnect layer 2122 may electrically connect the device layers 211 of two adjacent functional chips 21, thereby realizing inter-chip interconnection. Optionally, the interconnect layer may further include a hybrid bonding layer, and two adjacent functional chips 21 may be connected through the hybrid bonding layer.

[0061] Optionally, the first direction intersects the thickness direction. Optionally, the first direction is perpendicular to the thickness direction.

[0062] Optionally, the back power supply layer 214, the device layer 211, and the interconnect layer 212 are stacked along the first direction, that is, the film layer stacking direction of the functional chip 21 is the first direction.

[0063] The functional chip 21 further includes a second bump 213. In the thickness direction of the first substrate 10, the second bump 213 is at least located between both the back power supply layer 214 and the interconnect layer 212 and the first substrate 10. In other words, the second bump 213 may be provided only between the back power supply layer 214 and the substrate, and between the interconnect layer 212 and the substrate. Of course, the second bump 213 may also be provided between the device layer 211 and the substrate. The second bump 213 may also be provided between the heat sink 30 and the substrate.

[0064] Optionally, the second bump 213 may be electrically connected to the back power supply layer 214, the second bump 213 may also be electrically connected to the interconnect layer 212, and the second bump 213 may further include a plurality of them. A part of the second bumps 213 is electrically connected to the back power supply layer 214, and another part of the second bumps 213 is electrically connected to the interconnect layer 212. It can be understood that when the second bump 213 electrically connects the back power supply layer 214 to the first substrate 10, the power signal in the first substrate can be conducted to the back power supply layer 214 through the second bump 213, and then conducted to the device layer 211 by the back power supply layer; when the second bump 213 electrically connects the interconnect layer 212 to the first substrate 10, the functional signal can be transmitted between the interconnect layer 212 and the first substrate 10.

[0065] The heat sink 30 is at least provided on the outer side of the chip integration unit 20 along the first direction. It can be understood that a plurality of functional chips 21 are arranged in sequence along the first direction to form a chip integration unit 20. This chip integration unit has two opposite side surfaces along the first direction. A heat sink 30 may be provided on one side of one surface facing away from the chip integration unit 20, or heat sinks 30 may be provided on one side of each of the two surfaces facing away from the chip integration unit 20.

[0066] Optionally, the heat dissipation component can also be located outside the chip integration unit 20 along the second direction. That is, multiple functional chips 21 are arranged in sequence along the first direction to form a chip integration unit 20. This chip integration unit has two opposite side surfaces along the first direction and two opposite side surfaces along the second direction. In other words, the orthographic projection of the chip integration unit 20 on the first substrate 10 can be a rectangle or a square, and the heat dissipation component 30 is arranged around the edge of the rectangle.

[0067] Optionally, the heat dissipation component 30 is in contact with the outer surface of the chip integration unit 20 along the first direction; or, the heat dissipation component 30 is spaced from the outer surface of the chip integration unit 20 along the first direction.

[0068] In some examples, the heat dissipation component 30 is a plate-like structure, and the heat generated during the operation of the chip integration unit 20 can be conducted to the outside through the heat dissipation component 30.

[0069] In the three-dimensional packaging structure provided by the embodiments of the present application, by arranging the heat dissipation component 30 outside the chip integration unit 20 along the first direction X, the heat dissipation area of the chip integration unit 20 can be increased. At the same time, the external heat dissipation device for dissipating heat from the three-dimensional packaging structure is located at the top of the three-dimensional packaging structure. Through the above settings, the heat dissipation path between all the functional chips 21 and the external heat dissipation device can be shortened, the uniformity of the heat dissipation performance of all the functional chips 21 can be improved, and thus the heat dissipation performance can be improved. In addition, since the second bump 213 is disposed between both the back power supply layer 214 and the interconnection layer 212 and the substrate, the back power supply layer 214 can supply power to the functional chip 21, and the back power supply layer 214 of each functional chip 21 can be directly connected to the first substrate 10 to shorten the electrical connection path between the functional chip 21 and the first substrate 10, reduce the voltage drop loss, improve the power integrity of the three-dimensional packaging structure, and improve the integration density of the three-dimensional packaging structure.

[0070] In some optional embodiments, as Figure 1 and Figure 2 shown, the chip integration unit 20 includes a first side S1 and a second side S2 opposite to each other along the first direction, and the heat dissipation component 30 includes two outer heat dissipation components 31. One of the two outer heat dissipation components is disposed on the first side S1, and the other is disposed on the second side S2.

[0071] Exemplarily, one outer heat dissipation component 31 is located on the first side S1 of the chip integration unit 20 and is in contact with the surface of the first side S1 of the chip integration unit 20, and the other outer heat dissipation component 31 is located on the second side S2 of the chip integration unit 20 and is in contact with the surface of the second side S2 of the chip integration unit 20.

[0072] In these optional embodiments, by providing outer heat dissipation members 31 on both the first side S1 and the second side S2, it is beneficial to increase the heat dissipation path of the chip integration unit 20, improve the heat dissipation performance of the three-dimensional packaging structure, and thus improve the performance of the functional chip 21.

[0073] Figure 3 Schematic cross-sectional structure diagram of another three-dimensional packaging structure provided by some embodiments of the present application. Figure 4 Schematic cross-sectional structure diagram of another three-dimensional packaging structure provided by some embodiments of the present application.

[0074] In some optional embodiments, as Figures 1 to 4 shown, in the direction from the first side S11 to the second side S22, the back power supply layer 214, the device layer 211, and the interconnection layer 212 of at least some of the plurality of functional chips 21 are sequentially arranged.

[0075] In some examples, in the direction from the first side S1 to the second side S2, the back power supply layer 214, the device layer 211, and the interconnection layer 212 of all the functional chips 21 are sequentially arranged. In other examples, in the direction from the first side S1 to the second side S2, the back power supply layer 214, the device layer 211, and the interconnection layer 212 of a part of the plurality of functional chips 21 are sequentially arranged, and the interconnection layer 212, the device layer 211, and the back power supply layer 214 of the other part of the functional chips 21 are sequentially arranged in the direction from the first side S1 to the second side S2.

[0076] In these optional embodiments, through the above settings, it is beneficial to improve the stacking method of the plurality of functional chips 21 and improve the flexibility of the three-dimensional packaging structure design.

[0077] In some optional embodiments, as Figures 1 to 4 shown, the chip integration unit 20 includes a first functional chip T1 and a second functional chip T2 sequentially arranged in a first direction, and at least one of the interconnection layer 212 of the first functional chip T1 and the interconnection layer 212 of the second functional chip T2 is located between the device layer 211 of the first functional chip T1 and the device layer of the second functional chip T2.

[0078] Exemplarily, the first functional chip T1 includes a first device layer T11 and a first interconnection layer T12, and the second functional chip T2 includes a second device layer T21 and a second interconnection layer T22. In some examples, as Figure 4 shown, a first interconnection layer T12 and a second interconnection layer T22 are provided between the first device layer T11 and the second device layer T21. In other examples, as Figure 3As shown, a first interconnection layer T12 is provided between the first device layer T11 and the second device layer T21, and the second interconnection layer T22 is located on the side of the second device layer T21 facing away from the first device layer T11. In some other examples, a second interconnection layer T22 is provided between the first device layer T11 and the second device layer T21, and the first interconnection layer T12 is located on the side of the first device layer T11 facing away from the second device layer T21.

[0079] The device layer 211 of the first functional chip T1 and the device layer of the second functional chip T2 are connected at least through the interconnection layer 212 of at least one of the first functional chip T1 and the second functional chip T2. It can be understood that the first device layer T11 and the second device layer T21 can be connected only through the interconnection layer 212 located between the first device layer T11 and the second device layer T21, or a part of the functional circuits in the first device layer T11 and the second device layer T21 are connected through the interconnection layer 212 located between the first device layer T11 and the second device layer T21, and the other part of the functional circuits are connected to the wiring layer 13 through the second bump 213, and the interconnection between the first device and the second device is realized by the wiring layer.

[0080] In these alternative embodiments, through the above settings, it is beneficial to improve the layout flexibility of the interconnection layer 212, shorten the distance between the first device layer T11 and the second device layer T21, reduce the resistance between the first device layer T11 and the second device layer T21, and improve the transmission efficiency.

[0081] Figure 5 It is a schematic cross-sectional structure diagram of another three-dimensional packaging structure provided by some embodiments of the present application. Figure 6 It is a schematic cross-sectional structure diagram of another three-dimensional packaging structure provided by some embodiments of the present application. Figure 7 It is a schematic cross-sectional structure diagram of another three-dimensional packaging structure provided by some embodiments of the present application. Figure 8 It is a schematic cross-sectional structure diagram of another three-dimensional packaging structure provided by some embodiments of the present application.

[0082] In some alternative embodiments, as Figure 1 , Figure 2 and Figures 5 to 8 shown, the chip integration unit 20 further includes a third functional chip T3 located on the side of the second functional chip T2 facing away from the first functional chip T1, and an interconnection layer 212 of the third functional chip T3 is provided between the device layer 211 of the third functional chip 21 and the device layer of the second functional chip T2. Alternatively, the interconnection layer 212 of the third functional chip T3 is located on the side of the device layer 211 of the third functional chip 21 facing away from the second functional chip T2.

[0083] Exemplarily, the third functional chip T3 includes a third device layer T31 and a third interconnection layer T32.

[0084] In some examples, such as Figure 5 shown, a first interconnection layer T12 is provided between the first device layer T11 and the second device layer T21, a second interconnection layer T22 is provided between the second device layer T21 and the third device layer T31, and a third interconnection layer T32 is located on the side of the third device layer T31 facing away from the second device layer T21. In other examples, such as Figure 6 shown, a first interconnection layer T12 and a second interconnection layer T22 are provided between the first device layer T11 and the second device layer T21, and a third interconnection layer T32 is provided between the second device layer T21 and the third device layer T31. In other examples, such as Figure 7 shown, a first interconnection layer T12 is provided between the first device layer T11 and the second device layer T21, and a second interconnection layer T22 and a third interconnection layer T32 are provided between the second device layer T21 and the third device layer T31. In still other examples, such as Figure 8 shown, a first interconnection layer T12 and a second interconnection layer T22 are provided between the first device layer T11 and the second device layer T21, and a third interconnection layer T32 is located on the side of the third device layer T31 facing away from the second device layer T21.

[0085] In these alternative embodiments, through the above settings, it is beneficial to increase the arrangement modes of the functional chips, thereby improving the design flexibility of the chip integration unit 2020 and the applicable range of the three-dimensional packaging structure.

[0086] In some alternative embodiments, the thermal conductivity of the outer heat sink 3131 located on the first side S11 is greater than the thermal conductivity of the outer heat sink 31 located on the second side S22.

[0087] The thermal conductivity of the outer heat sink can be tested by the steady-state method, the transient method or other methods. Thermal conductivity refers to the conduction ability of a substance. The higher the thermal conductivity of a substance, the stronger its heat conduction ability and the better its heat dissipation effect.

[0088] As can be seen from the foregoing, at least part of the device layer 211 of the functional chip 21 is disposed close to the first side S1. The functional circuits in the device layer, such as the active layer, have the best working performance within a preset working temperature range. By increasing the thermal conductivity of the heat sink 31 on the outer side of the first side S1, the functional circuits can work within the optimal working temperature, thereby improving the service performance of the functional circuits. The film layer closest to the second side S2 is the interconnection layer 212, which is mainly used to achieve electrical connection. Moreover, the interconnection layer 212 has a relatively large thermal resistance, so that the heat conducted from the interconnection layer 212 to the outer heat sink 31 is lower than the heat conducted from the device layer 211 to the outer heat sink 31. By reducing the thermal conductivity of the heat sink on the outer side of the second side S2, the redundant setting of the heat dissipation performance of the heat sink 31 on the outer side of the second side S2 can be reduced, and the manufacturing cost of the three-dimensional packaging structure can be reduced.

[0089] It can be understood that the thermal conductivity of the heat sink 31 on the outer side of the first side S1 and the thermal conductivity of the heat sink 31 on the outer side of the second side S2 can be adjusted by changing the thickness or material of the heat sinks on both sides.

[0090] Optionally, the functional chip 21 may further include a substrate, which is located between the device layer 211 and the back power supply layer 214, and the device layer may be fabricated on the substrate. In some examples, the heat dissipation performance of the functional chip 21 can also be adjusted by changing the thickness of the substrate. Optionally, the material of the substrate may include silicon.

[0091] Exemplarily, the thickness of the substrate may be 1μm - 50μm.

[0092] Figure 9 FIG. is a schematic cross-sectional structure diagram of another three-dimensional packaging structure provided by some embodiments of the present application.

[0093] In some alternative embodiments, as Figure 9 shown, the heat sink 30 further includes an intermediate heat sink 32, which is located between two adjacent functional chips 21.

[0094] Optionally, the intermediate heat sink 32 may be provided with through holes, and two adjacent functional chips 21 may be electrically connected through the through holes.

[0095] Optionally, a connection layer 40 may be provided between the intermediate heat sink 32 and the functional chip 21. The connection layer can connect the intermediate heat sink 32 and the functional chip 21, thereby reducing the possibility of separation between the intermediate heat sink and the functional chip. Moreover, the connection layer 40 may be provided with a through hole structure for connecting two adjacent functional chips 21, thereby realizing signal interconnection between the two functional chips. Optionally, the connection layer 40 may be a hybrid bonding layer.

[0096] In these alternative embodiments, by providing the intermediate heat sink 32, the heat dissipation effect on the functional chip 21 is further enhanced, the uniformity of the heat dissipation performance of multiple functional chips 21 is improved, and the possibility of performance differentiation among multiple functional chips is reduced, thereby reducing the failure risk caused by thermal stress.

[0097] Figure 10 FIG. 4 is a schematic cross-sectional structure diagram of another three-dimensional packaging structure provided by some embodiments of the present application.

[0098] In some alternative embodiments, as Figure 10 shown, a connection layer 40 is provided between the heat sink 30 and the functional chip 21. The connection layer includes a connection body 41 and a support structure 42, and the support structure is embedded in the connection body 41.

[0099] Optionally, the connection body 41 may be a whole-layer structure, and the support structure 42 is embedded in the connection body. Optionally, the support structure may be pressed into the connection body 41 in a preset temperature environment.

[0100] Optionally, the material of the support structure 42 may be an insulating material.

[0101] Optionally, the connection layer 40 may be a hybrid bonding layer.

[0102] Optionally, a connection layer 40 is provided between the outer heat sink 31 and the functional chip 21; and / or, a connection layer is provided between the intermediate heat sink 32 and the functional chip.

[0103] In these alternative embodiments, by providing the support structure 42, the overall strength of the connection layer 40 is increased, the possibility of separation between the heat sink 30 and the functional chip 21 is reduced, and at the same time, the difference in the thermal expansion coefficients of the heat sink 30 and the functional chip 21 can be compensated by deformation, improving the thermal stress buffer.

[0104] In some alternative embodiments, the material of the heat sink 30 includes diamond. Diamond is a material with a relatively high thermal conductivity among natural substances. At the same time, diamond also has a low dielectric constant, enabling diamond to have a low parasitic capacitance, reducing signal loss during transmission, and improving signal integrity.

[0105] Optionally, the device layer 211 of the functional chip 21 may be formed on a substrate, and the material of the substrate may be silicon. The thermal expansion coefficient of diamond is relatively matched with that of silicon. Therefore, when the temperature changes during service, the thermal stress generated between the functional chip 21 and the heat sink 30 can be reduced, and the possibility of deformation or damage to the functional chip 21 and / or the heat sink 30 due to the difference in thermal expansion is reduced, improving the reliability of the three-dimensional packaging structure.

[0106] In some alternative embodiments, asFigure 2 As shown, the three-dimensional packaging structure further includes a support portion 50, and a support portion 50 is provided between at least one of the chip integration unit 20 and the heat dissipation member 30 and the first substrate 10.

[0107] Optionally, the support portion 50 and the second bump 213 may be arranged side by side.

[0108] Optionally, the material of the support portion 50 and the material of the second bump 213 may be the same, that is, the support portion and the second bump 213 may be formed by the same process.

[0109] Exemplarily, the support portion 50 may be a bump structure that does not serve as an electrical connection between the chip integration unit 20 and the first substrate 10 or between the second bump 213 and the first bump 11.

[0110] In some examples, a support portion 50 is provided between the chip integration unit 20 and the first substrate 10; exemplarily, a support portion 50 is provided between the device layer 211 and the first substrate 10; and / or, a support portion 50 is provided between the interconnection layer 212 and the first substrate 10. Specifically, a support portion 50 is provided between the transistor layer and the first substrate 10; and / or, a support portion 50 is provided between the power supply layer and the first substrate 10.

[0111] In some examples, a support portion 50 is provided between the heat dissipation member 30 and the first substrate 10; exemplarily, a support portion 50 is provided between the outer heat dissipation member 31 and the first substrate 10; and / or, a support portion is provided between the intermediate heat dissipation member 32 and the first substrate.

[0112] In some other examples, a support portion 50 is provided between the chip integration unit 20 and the first substrate 10, and a support portion 50 is provided between the heat dissipation member 30 and the first substrate.

[0113] Optionally, the number of the support portions 50 may be one or more.

[0114] Optionally, the dimensions of the support portion along the side-by-side direction of the support portion and the second bump 213 may be the same or different.

[0115] In some examples, the support portion 50 may be grounded. Exemplarily, a grounded support portion 50 is provided between two second bumps 213 for transmitting different signals, and the support portion may serve as a shielding structure to shield the mutual interference of signals between the two second bumps 213 for transmitting different signals. Optionally, the different signals may include a constant signal and a non-constant signal. For example, a voltage constant signal and a voltage non-constant signal.

[0116] In these optional embodiments, by providing the support portion 50, it is beneficial to increase the support performance between the chip integration unit 20 and / or the heat dissipation member 30 and the first substrate 10, reduce the risk that the chip integration unit 20 and / or the heat dissipation member 30 squeeze the second bump 213 or even cause deformation of the second bump 213 due to their own weights, improve the connection reliability between the second bump 213 and the first bump 11, and thus improve the reliability of the three-dimensional packaging structure.

[0117] Figure 12 FIG. is a schematic cross-sectional structure view of another three-dimensional packaging structure provided by some embodiments of the present application.

[0118] In some optional embodiments, as Figure 12 shown, it further includes a packaging layer 60, and the packaging layer 60 is at least located on the peripheral sides of the heat dissipation member 30 and the chip integration unit 20.

[0119] Optionally, the material of the packaging layer includes epoxy resin (Epoxy Molding Compound, EMC). Optionally, the packaging layer 60 may further include a heat-conducting material, such as a nano material. Exemplarily, the nano material is used as a heat-conducting filler and incorporated into the epoxy resin matrix to form a high heat-conducting composite plastic packaging material. The nano material may include metals (Ag, Cu), carbon-based materials (graphene, CNTs, diamond), and ceramics (BN, AlN, Al2O3).

[0120] Optionally, when preparing the packaging layer 60, the chip integration unit 20 and the heat dissipation member 30 mounted on the first substrate 10 may be placed in a packaging mold, the heated packaging material is injected into the packaging mold and cured, and after demolding, the preparation of the packaging layer 60 is completed.

[0121] It can be understood that the chip integration unit 20 may include a first side S1 and a second side S2 facing away from each other in a first direction, and at least one of the first side S1 and the second side S2 is used to provide the heat dissipation member 30. The chip integration unit 20 may further include a third side and a fourth side facing away from each other in a second direction. The packaging layer 60 may be located on the third side and the fourth side and on the side of the heat dissipation member 30 facing away from the chip integration unit 20.

[0122] Optionally, the packaging layer 60 may cover the side of the chip integration unit facing away from the first substrate 10.

[0123] Optionally, the packaging layer 60 may further cover the side of the heat dissipation member facing away from the first substrate.

[0124] Optionally, the packaging layer may expose the surface of the side of the chip integration unit 20 facing away from the first substrate 10.

[0125] Optionally, the packaging layer 60 may expose the surface of the side of the heat dissipation member 30 facing away from the first substrate 10.

[0126] In these optionally implemented embodiments, by providing the encapsulation layer 60, it is beneficial to mechanically protect and environmentally isolate the chip integration unit 20 and the heat dissipation member 30, thereby reducing the possibility of damage to the heat dissipation member 30 and the chip integration unit 20 caused by external forces and external impurities, and improving the stability and reliability of the chip integration unit.

[0127] In some optionally implemented embodiments, as Figure 11 shown, the encapsulation layer 60 includes a first encapsulation portion 61 and a second encapsulation portion 62. The first encapsulation portion is located on the peripheral side of the heat dissipation member 30 and the chip integration unit 20, and the second encapsulation portion is located on the side of at least one of the heat dissipation member and the chip integration unit facing away from the first substrate 10.

[0128] Optionally, the first encapsulation portion 61 and the second encapsulation portion 62 can be of the same material structure. The first encapsulation portion and the second encapsulation portion 62 can be of different materials. Exemplarily, the thermal conductivity of the second encapsulation portion 62 is greater than that of the first encapsulation portion 61.

[0129] Optionally, the second encapsulation portion can protrude from the first encapsulation portion 61 in a direction away from the first substrate 10.

[0130] Optionally, the second encapsulation portion 62 can also cover the side of the first encapsulation portion facing away from the first substrate 10.

[0131] Optionally, the elastic modulus of the second encapsulation portion 62 can be less than that of the first encapsulation portion 61, such that the second encapsulation portion 62 is not easily deformed, thereby reducing the possibility of encapsulation failure caused by local thinning of the thickness of the second encapsulation portion 62.

[0132] Optionally, a hole structure can be provided on the surface of the second encapsulation portion facing away from the first substrate 10, and a heat-conducting material can be provided in the hole structure. Optionally, the hole structure can include blind holes or through holes.

[0133] In a second aspect, an embodiment of the present application provides a circuit board assembly, including the three-dimensional encapsulation structure in any of the foregoing implementation manners and a second substrate 70, and the first bump 11 of the three-dimensional encapsulation structure is electrically connected to the second substrate.

[0134] It should be noted that the circuit board assembly provided by the embodiment of the present application has the beneficial effects of the three-dimensional encapsulation structure in any of the foregoing implementation manners. For specific content, please refer to the description of the beneficial effects of the three-dimensional encapsulation structure above. The embodiment of the present application will not repeat it here.

[0135] In some embodiments, the second substrate 70 may include a rigid organic substrate. The organic substrate is based on a composite of organic resin and glass fiber or an organic film, and is realized through multi-layer wiring and multi-layer lamination methods. It has the characteristics of good electrical insulation performance, low dielectric constant, small mass, and low manufacturing cost.

[0136] Optionally, the second substrate 70 may include copper pillar bumps 71. The copper pillar bumps are composed of copper pillars and solder caps. The copper pillars provide mechanical support and electrical connection, and the solder caps interconnect the second substrate 70 with other electronic devices through welding.

[0137] Although the present application has been described with reference to the preferred embodiments, various improvements can be made thereto and components thereof can be replaced with equivalents without departing from the scope of the present application. In particular, as long as there is no structural conflict, the technical features mentioned in each embodiment can be combined in any manner. The present application is not limited to the specific embodiments disclosed herein, but includes all technical solutions falling within the scope of the claims.

Claims

1. A three-dimensional packaging structure, characterized in that, Comprising: A first substrate, including first bumps for electrically connecting to a second substrate; A chip integration unit, including a plurality of functional chips arranged in sequence along a first direction. The chip integration unit is located on one side of the first substrate in the thickness direction. The functional chip includes a device layer, a back power supply layer, an interconnection layer, and second bumps. The back power supply layer, the device layer, and the interconnection layer are stacked and electrically connected along the first direction. In the thickness direction of the first substrate, the second bumps are at least located between both the back power supply layer and the interconnection layer and the first substrate. At least one of the back power supply layer and the interconnection layer is connected to the first substrate through the second bumps, so that signals in at least one of the power supply layer and the interconnection layer are conducted into the first substrate; A heat dissipation member, at least provided on the outer side of the chip integration unit along the first direction.

2. The three-dimensional packaging structure according to claim 1, wherein, The chip integration unit includes a first side and a second side opposite to each other along the first direction. The heat dissipation member includes two outer heat dissipation members, one of the two outer heat dissipation members is provided on the first side, and the other is provided on the second side.

3. The three-dimensional packaging structure according to claim 2, wherein In the direction from the first side to the second side, the back power supply layer, the device layer, and the interconnection layer of at least some of the plurality of functional chips are arranged in sequence.

4. The three-dimensional packaging structure according to claim 3, wherein, The chip integration unit includes a first functional chip and a second functional chip arranged in sequence along the first direction. At least one of the interconnection layer of the first functional chip and the interconnection layer of the second functional chip is located between the device layer of the first functional chip and the device layer of the second functional chip.

5. The three-dimensional packaging structure according to claim 4, wherein The chip integration unit further includes a third functional chip located on the side of the second functional chip facing away from the first functional chip. The interconnection layer of the third functional chip is provided between the device layer of the third functional chip and the device layer of the second functional chip; or, The interconnection layer of the third functional chip is located on the side of the device layer of the third functional chip facing away from the second functional chip.

6. The three-dimensional packaging structure according to claim 3, wherein The thermal conductivity of the outer heat dissipation member located on the first side is greater than that of the outer heat dissipation member located on the second side.

7. The three-dimensional packaging structure according to claim 1, characterized in that The heat dissipation member further includes an intermediate heat dissipation member, and the intermediate heat dissipation member is located between two adjacent functional chips.

8. The three-dimensional packaging structure according to claim 1, characterized in that, A connection layer is provided between the heat dissipation member and the functional chip. The connection layer includes a connection main body and a support structure, and the support structure is embedded in the connection main body.

9. The three-dimensional packaging structure according to claim 1, wherein The material of the heat dissipation member includes diamond.

10. The three-dimensional packaging structure according to claim 1, characterized in that, Further including a support portion, the support portion is provided between at least one of the chip integration unit and the heat dissipation member and the first substrate.

11. The three-dimensional packaging structure according to claim 1, characterized in that, Further including a packaging layer, the packaging layer is at least located on the peripheral side of the heat dissipation member and the chip integration unit.

12. The three-dimensional packaging structure according to claim 11, characterized in that, The packaging layer includes a first packaging portion and a second packaging portion. The first packaging portion is located on the peripheral side of the heat dissipation member and the chip integration unit, and the second packaging portion is located on the side of at least one of the heat dissipation member and the chip integration unit facing away from the first substrate.

13. A circuit board assembly, characterized in that, Comprising: The three-dimensional packaging structure according to any one of claims 1 to 12; A second substrate, wherein the first bumps of the three-dimensional packaging structure are electrically connected to the second substrate.

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