Package substrate, electronic device, circuit board and electronic equipment

Abstract

The embodiment of the invention relates to the technical field of electronic equipment, in particular to a packaging substrate, an electronic device, a circuit board and electronic equipment. The embodiment of the invention aims to solve the problem that the structure on the circuit board is complex. According to the packaging substrate, the electronic device, the circuit board and the electronic equipment provided by the embodiment of the invention, the electronic elements are arranged in the board body, so that the number of the electronic elements on the circuit board and winding resources are reduced, the structure on the circuit board is simplified, and simple and miniaturized design is facilitated. Besides, a third connecting part is arranged on the second surface, the electronic element is connected with the third connecting part, and the circuit on the substrate can be selectively connected with or disconnected from the third connecting part according to application requirements, so that the electronic element can be selected or bypassed.

Description

Technical Field

[0001] Embodiments of the present application relate to the technical field of electronic devices, and particularly to a packaging substrate, an electronic device, a circuit board, and an electronic device. Background Art

[0002] An electronic device generally includes a circuit board. An electronic device is disposed on a substrate of the circuit board. The electronic device includes a packaging substrate and a chip disposed on the packaging substrate. The chip is connected to a circuit on the substrate through the packaging substrate. Electronic components (such as resistors, inductors, etc.) are disposed on the substrate of the circuit board. The electronic components are electrically connected to the chip to assist the chip in working. However, the electronic components are disposed on the substrate of the circuit board, resulting in a complex structure of the circuit board and affecting the design of simplicity and miniaturization. Summary of the Invention

[0003] Embodiments of the present application provide a packaging substrate, an electronic device, a circuit board, and an electronic device, which can reduce the number of devices on the circuit board, simplify the structure of the circuit board, and facilitate the design of simplicity and miniaturization.

[0004] In a first aspect, an embodiment of the present application provides a packaging substrate, including: a board body, a conductive part, and an electronic component. A first connection part is disposed on a first surface of the board body. The first connection part can be connected to a chip. A second connection part is disposed on a second surface of the board body. The second connection part can be connected to a substrate. The first surface and the second surface are disposed opposite to each other. The conductive part is disposed in the board body. One end of the conductive part is connected to the first connection part, and the other end of the conductive part is connected to the second connection part. The electronic component is disposed in the board body, and the electronic component is disposed at an interval from the conductive part. A third connection part is further disposed on the second surface of the board body. One end of the electronic component is connected to the third connection part.

[0005] Through the above arrangement, the electronic component is disposed in the board body, reducing the number of electronic components and wiring resources on the circuit board, simplifying the structure on the circuit board, and facilitating the design of simplicity and miniaturization.

[0006] In addition, a third connection part connected to the electronic component is disposed on the second surface of the board body. The circuit on the substrate can be selectively connected or not connected to the third connection part according to application requirements to implement the selection or bypass of the electronic component.

[0007] In some embodiments that may include the above embodiments, one end of the electronic component is connected to the conductive part to realize the connection between the electronic component and the chip. The other end of the electronic component is connected to the third connection part. The third connection part can be connected to a ground network or a power network, so that the third connection part has a preset potential. With such an arrangement, the electronic component can assist the chip in working to improve the performance of the electronic device. The third connection part can also be left floating. With such an arrangement, the electronic component does not participate in the operation of the signal link, avoiding signal loss.

[0008] In some embodiments that may include the above embodiments, one end of the electronic component is configured to have a preset potential and can be connected to the ground circuit on the package substrate, so that one end of the electronic component is at zero potential; it can also be connected to the circuit connecting the power supply in the package substrate, so that the other end of the electronic component has a certain potential. The other end of the electronic component is connected to the third connection part, and the third connection part can be connected to the second connection part through the circuit on the substrate to realize the connection between the electronic component and the chip. With such an arrangement, the electronic component is connected to the signal link, which can assist the chip to work and improve the performance of the electronic device; the third connection part can also be configured to have a preset potential. With such an arrangement, the electronic component does not affect the signal quality, and the chip can be connected to the electronic component corresponding to the function of the electronic device integrated on the substrate.

[0009] In some embodiments that may include the above embodiments, the conductive part includes a first conductive part and a second conductive part. The first conductive part and the second conductive part are arranged at intervals. There are two first connection parts and two second connection parts. One end of the first conductive part is connected to one first connection part, the other end of the first conductive part is connected to one second connection part, one end of the second conductive part is connected to the other first connection part, and the other end of the second conductive part is connected to the other second connection part; the electronic component includes a first electronic component and a second electronic component. The first electronic component is arranged corresponding to and at intervals from the first conductive part, and the second electronic component is arranged corresponding to and at intervals from the second conductive part. With such an arrangement, the conductive part and the electronic component respectively correspond to the two signal channels for transmitting differential signals.

[0010] In some embodiments that may include the above embodiments, the board body includes a plurality of conductive layers and a plurality of dielectric layers, and the plurality of conductive layers and the plurality of dielectric layers are arranged in an alternating laminated manner; the electronic component includes an inductor, and the inductor includes a first coil and a second coil arranged in series. At least part of the first coil is located in one conductive layer, and at least part of the second coil is located in another conductive layer. The coils in different layers are connected through package via vias. With such an arrangement, the inductor in the package substrate can be wound with multiple layers of wire, reducing the winding area and saving the internal space of the package substrate. In addition, the inductor is arranged inside the board body, realizing self-shielding, avoiding the risk of EMI introduced by the inductor, and eliminating the need for an additional shielding cavity compared with integrating the inductor on the substrate.

[0011] In some embodiments that may include the above embodiments, the board body includes a first board body, an intermediate board body, and a second board body arranged in a laminated manner. Both the first board body and the second board body include a plurality of conductive layers and a plurality of dielectric layers. The intermediate board body is located between the first board body and the second board body, and the thickness of the intermediate board body is greater than the thicknesses of the first board body and the second board body. It is the thickest dielectric layer near the longitudinal middle position of the board body, and the solid electronic component can be arranged inside the intermediate board body. With such an arrangement, the dielectric layers in the package substrate are fully utilized, saving the space inside the package substrate.

[0012] In a second aspect, an embodiment of the present application further provides an electronic device, including: a chip and the encapsulation substrate described above. The chip is disposed on the first surface and is electrically connected to the first connection portion.

[0013] The electronic device provided by the embodiment of the present application includes the encapsulation substrate in any of the above embodiments. Therefore, both can solve the same technical problems and achieve the same technical effects.

[0014] In a third aspect, an embodiment of the present application further provides a circuit board, including: a substrate and the electronic device described above. The electronic device is disposed on the circuit board.

[0015] The circuit board provided by the embodiment of the present application includes the electronic device in any of the above embodiments. Therefore, both can solve the same technical problems and achieve the same technical effects.

[0016] In a fourth aspect, an embodiment of the present application further provides an electronic device, including: a battery and the circuit board described above. The battery is electrically connected to the circuit board.

[0017] The electronic device provided by the embodiment of the present application includes the circuit board in any of the above embodiments. Therefore, both can solve the same technical problems and achieve the same technical effects. Description of the Drawings

[0018] Figure 1 is a circuit diagram of a DC bias circuit in the related art;

[0019] Figure 2 is a schematic structural diagram of a choke inductor of a DC bias circuit disposed on a circuit board by winding;

[0020] Figure 3 is a schematic structural diagram of a choke inductor of a DC bias circuit disposed on a circuit board by surface mount devices;

[0021] Figure 4 is a schematic structural diagram of an electronic device provided by an embodiment of the present application;

[0022] Figure 5 is a schematic structural diagram of an encapsulation substrate provided by an embodiment of the present application;

[0023] Figure 6 is a schematic diagram of the circuit connection inside and on the substrate of the encapsulation substrate provided by an embodiment of the present application Figure 1 ;

[0024] Figure 7 is a schematic diagram of the circuit connection inside and on the substrate of the encapsulation substrate provided by an embodiment of the present application Figure 2 ;

[0025] Figure 8 Schematic diagram of the internal and on-board circuit connections of the packaging substrate provided by the embodiments of the present application Figure 3 ;

[0026] Figure 9 Schematic diagram of the internal and on-board circuit connections of the packaging substrate provided by the embodiments of the present application Figure 4 ;

[0027] Figure 10 Schematic diagram of the internal and on-board circuit connections of the packaging substrate provided by the embodiments of the present application Figure 5 ;

[0028] Figure 11 Schematic diagram of the internal and on-board circuit connections of the packaging substrate provided by the embodiments of the present application Figure 6 ;

[0029] Figure 12 Schematic diagram of the internal structure of the board body of the packaging substrate provided by the embodiments of the present application;

[0030] Figure 13 Schematic diagram of the internal and on-board circuit connections of the packaging substrate provided by the embodiments of the present application Figure 7 ;

[0031] Figure 14 is Figure 13 Insertion loss diagram of the signal of the corresponding circuit board;

[0032] Figure 15 is Figure 13 Return loss diagram of the signal of the corresponding circuit board;

[0033] Figure 16 Schematic diagram of the internal and on-board circuit connections of the packaging substrate provided by the embodiments of the present application Figure 8 ;

[0034] Figure 17 is Figure 16 Insertion loss diagram of the signal of the corresponding circuit board;

[0035] Figure 18 is Figure 16 Return loss diagram of the signal of the corresponding circuit board;

[0036] Figure 19 Schematic diagram of the internal structure connection of the packaging substrate provided by the embodiments of the present application;

[0037] Figure 20 Schematic diagram of the internal structure of the first and second electronic components of the packaging substrate provided by the embodiments of the present application;

[0038] Figure 21Schematic diagram of the board structure of the packaging substrate provided by the embodiment of the present application;

[0039] Figure 22 Schematic diagram of the structure of internal electronic components of the packaging substrate provided by the embodiment of the present application Figure 1 ;

[0040] Figure 23 Schematic diagram of the structure of internal electronic components of the packaging substrate provided by the embodiment of the present application Figure 2 ;

[0041] Figure 24 Schematic diagram of the structure of internal electronic components of the packaging substrate provided by the embodiment of the present application Figure 3 .

[0042] Description of reference numerals: 10: DC bias circuit; 11: first RF port; 12: second RF port; 13: DC bias port; 14: choke inductor; 15: DC blocking capacitor; 16: chip; 161: RF chip; 17: antenna; 20: circuit board; 21: substrate; 30: electronic device; 31: packaging substrate; 40: housing; 50: battery; 60: electronic device; 311: board body; 312: conductive part; 313: electronic component; 32: first connection part; 33: second connection part; 34: third connection part; 35: fourth connection part; 141: inductor; 3121: first conductive part; 3122: second conductive part; 3131: first electronic component; 3132: second electronic component; 321: one first connection part; 322: the other first connection part; 331: one second connection part; 332: the other second connection part; 341: one third connection part; 342: the other third connection part; 313a: first coil; 313b: second coil; 311a: first board body; 311b: intermediate board body; 311c: second board body; 3111: conductive layer; 3112: dielectric layer; 3133: solid electronic component. Detailed implementation manners

[0043] To make the objectives, technical solutions, and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are some, but not all, of the embodiments of the present application. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present application without creative efforts shall fall within the protection scope of the present application.

[0044] Hereinafter, terms such as "first", "second", etc. are for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, features defined with "first", "second", etc. may explicitly or implicitly include one or more such features.

[0045] In addition, in the embodiments of the present application, orientation terms such as "upper", "lower", "left", "right", "horizontal", and "vertical" are defined relative to the orientation in which the components in the drawings are schematically placed. It should be understood that these directional terms are relative concepts, which are used for relative description and clarification and can change accordingly with the change of the orientation in which the components in the drawings are placed.

[0046] In the embodiments of the present application, unless otherwise clearly specified and limited, the term "connection" should be understood in a broad sense. For example, "connection" can be a fixed connection, an electrical connection, or a detachable connection, or integrated; it can be directly connected or indirectly connected through an intermediate medium.

[0047] Please refer to Figure 1 , when the electronic device communicates (such as when sending text messages or making phone calls through a mobile phone), the radio frequency signal is transmitted to the antenna 17 through the radio frequency chip 161, and the antenna 17 converts the radio frequency signal into an electromagnetic wave in free space and transmits it to the base station. Since the signal output by the radio frequency chip 161 may include a direct current signal in addition to the radio frequency signal, in order to separate the radio frequency signal and the direct current signal in the signal, the radio frequency chip 161 and the antenna 17 are generally connected through a direct current bias circuit 10 (Bias-Tee), where the direct current bias circuit 10 includes a blocking capacitor 15, a choke inductor 14, a first radio frequency port 11, a second radio frequency port 12, and a direct current bias port 13. One end of the blocking capacitor 15 is connected to the second radio frequency port 12, and the other end of the blocking capacitor 15 is connected to the first radio frequency port 11 and one end of the choke inductor 14. The other end of the choke inductor 14 is connected to the direct current bias port 13. The first radio frequency port 11 is used to connect the radio frequency chip 161, the second radio frequency port 12 is used to connect the antenna 17, and the direct current bias port 13 is used to connect the direct current network, and the direct current network may include a power network and a ground network. During operation, the signal is input from the first radio frequency port 11, the radio frequency signal in the signal is transmitted to the antenna 17 through the blocking capacitor 15, and the direct current signal in the signal is blocked by the blocking capacitor 15 and grounded or flows into the power supply through the choke inductor 14 to prevent the direct current component in the signal from affecting the operation of the antenna 17.

[0048] In some related technologies, as Figure 2 shown, Figure 1The choke inductor 14 in the DC bias circuit 10 shown is disposed on the circuit board 20. Correspondingly, the choke inductor 14, the line connecting the first RF port 11 and the choke inductor 14, the line connecting the second RF port 12 and the choke inductor 14, and the line connecting the DC bias port 13 and the choke inductor 14 can all be formed by the circuit patterns on the circuit board 20. Exemplarily, the circuit board 20 includes a metal layer, and after the metal layer is patterned, circuit patterns are formed, that is, the choke inductor 14 is formed.

[0049] In an implementation manner where the signal includes differential signals, there are two choke inductors 14, two first RF ports 11, and two second RF ports 12. One port of the RF chip 161 is connected to one end of a second RF port 12 and a choke inductor 14 through a first RF port 11. The other port of the RF chip 161 is connected to one end of another second RF port 12 and another choke inductor 14 through another first RF port 11. The two second RF ports 12 are both connected to the antenna 17, and the other ends of the two choke inductors 14 are both connected to the same DC bias port 13. The signals sent by the two ports of the RF chip 161 have a certain phase difference.

[0050] In other related technologies, such as Figure 3 As shown, the circuit board 20 includes a substrate 21, and electronic devices 30 and a choke inductor 14 disposed on the circuit board 20. The electronic device 30 includes an RF chip 161 and a package substrate 31. The RF chip 161 is packaged on the package substrate 31. The package substrate 31 is electrically connected to the circuit on the substrate 21. The choke inductor 14 includes a chip inductor and is disposed on the substrate 21 through a surface mount device and is electrically connected to the package substrate 31 through the circuit on the substrate 21 to realize the electrical connection between the choke inductor 14 and the RF chip 161.

[0051] Figure 2 and Figure 3 In the related technology shown, the DC bias circuit 10 (as Figure 1 shown) is disposed on the substrate 21 of the circuit board 20, such that there are many devices and lines on the circuit board 20, resulting in a complex structure of the circuit board 20.

[0052] An embodiment of the present application provides an electronic device 60, which may include a mobile phone, a tablet computer, a smart watch, and wearable devices, etc. The embodiment does not limit the electronic device 60. This embodiment will take the electronic device 60 as a mobile phone as an example for introduction. It can be understood that this embodiment is not limited thereto, and the electronic device 60 may also be other devices.

[0053] Please refer to Figure 4, in this embodiment, the electronic device 60 includes a housing 40, a circuit board 20 disposed within the housing 40, and a battery 50 disposed within the housing 40. The battery 50 is electrically connected to the circuit board 20. The circuit board 20 includes a substrate 21 and electronic components 30 disposed on the substrate 21. The electronic components 30 are electrically connected to the circuit on the substrate 21. Exemplarily, the electronic components 30 may include radio frequency electronic components, charging management electronic components, audio decoding electronic components, etc. The electronic components 30 include a chip 16 and a package substrate 31. The chip 16 is mounted on the package substrate 31, and the package substrate 31 is connected to the circuit on the substrate 21 to achieve electrical connection between the chip 16 and the circuit board 20. Exemplarily, in an implementation where the electronic components 30 include radio frequency electronic components, the chip 16 may include a radio frequency chip, and a radio frequency signal can be sent to the Figure 1 antenna 17 shown to achieve signal transmission. In an implementation where the electronic components 30 include charging management electronic components, the chip 16 may include a charging management chip, and a control signal can be sent to the battery 50 through the charging management chip to achieve the function of controlling the charging speed of the battery 50; in an implementation where the electronic components 30 include audio decoding electronic components, the chip 16 may include an audio decoding chip, and an analog audio signal can be sent to the speaker of the electronic device 60 through the audio decoding chip to achieve the function of playing music.

[0054] Please refer to Figure 5 , in the embodiment of the present application, the package substrate 31 includes a board body 311. The board body 311 includes a first surface ( Figure 5 the upper surface in Figure 5 ) and a second surface ( the lower surface in ) which are oppositely arranged. A first connection portion 32 is disposed on the first surface, and a second connection portion 33 is disposed on the second surface.

[0055] In the above implementation, the first connection portion 32 may include a first pad disposed on the first surface, and the first connection portion 32 may be connected to Figure 4The chip 16 shown is soldered. Of course, the first connection portion 32 may also include a metal layer or a metal block provided on the first surface, and the embodiments of the present application do not limit the first connection portion 32; the second connection portion 33 is connected to the substrate 21 to achieve electrical connection between the chip 16 and the circuit on the substrate 21. Exemplarily, the second connection portion 33 may include a metal layer on the second surface and a second pad provided on the second surface. Correspondingly, a third pad is provided on the substrate 21, and the second pad and the third pad are soldered. It can be understood that during soldering, solder is formed between the first connection portion 32 and the chip 16, and then the solder is heated to form solder balls connecting the first connection portion 32 and the chip 16; solder is formed between the second connection portion 33 and the third pad, and then the solder is heated to form solder balls connecting the second connection portion 33 and the third pad.

[0056] The packaging substrate 31 in the embodiments of the present application further includes a conductive portion 312. The conductive portion 312 is disposed inside the plate body 311. One end ( Figure 5 the top end in) of the conductive portion 312 is connected to the first connection portion 32, and the other end ( Figure 5 the bottom end in) of the conductive portion 312 is connected to the second connection portion 33. The electrical connection between the first connection portion 32 and the second connection portion 33 is achieved through the conductive portion 312. A via hole is provided on the plate body 311. The via hole may penetrate the first connection portion 32 and the second connection portion 33. Correspondingly, the conductive portion 312 may include a metal sidewall provided on the inner wall of the via hole. One end of the metal sidewall is connected to the first connection portion 32, and the other end of the metal sidewall is connected to the second connection portion 33 to achieve electrical connection between the first connection portion 32 and the second connection portion 33; of course, the conductive portion 312 may also include a solid via hole, that is, a metal column. One end of the metal column is connected to the first connection portion 32, and the other end of the metal column is connected to the second connection portion 33. The first connection portion 32 and the second connection portion 33 achieve electrical connection through the metal column.

[0057] The packaging substrate 31 in the embodiments of the present application further includes an electronic component 313. The electronic component 313 is disposed inside the plate body 311, and the electronic component 313 is disposed at an interval from the conductive portion 312. The embodiments of the present application do not limit the electronic component 313. The electronic component 313 may include an inductor, a capacitor, a resistor, etc. It can be understood that the number and functions of the electronic components 313 can be reasonably set according to the functions and structures of the electronic device 30. In the implementation manner where there are multiple electronic components 313, the functions of each electronic component 313 may be the same or different.

[0058] In the encapsulation substrate 31 in the embodiment of the present application, the first connection portion 32 is disposed on the first surface of the board body 311, the second connection portion 33 is disposed on the second surface of the board body 311, the conductive portion 312 is disposed within the board body 311, one end of the conductive portion 312 is connected to the first connection portion 32, and the other end of the conductive portion 312 is connected to the second connection portion 33; the electronic component 313 is disposed within the board body 311, and the electronic component 313 is disposed at an interval from the conductive portion 312. A third connection portion 34 is further disposed on the second surface of the board body 311, and one end of the electronic component 313 is connected to the third connection portion 34. It can be understood that the structures of the third connection portion 34 and the second connection portion 33 may be substantially the same, and will not be elaborated herein.

[0059] Compared with the case where the electronic component 313 is disposed on the substrate 21 of the circuit board 20, in the embodiment of the present application, the electronic component 313 is disposed within the board body 311 of the encapsulation substrate 31, which can reduce the number of electronic components 313 on the circuit board 20, simplify the circuit on the circuit board 20, and facilitate a simple and miniaturized design; a third connection portion 34 connected to the electronic component 313 is disposed on the second surface of the board body 311, and the circuit on the substrate 21 can be selectively connected or not connected to the third connection portion 34 according to application requirements to implement the selection or bypass of the electronic component 313.

[0060] Continue to refer to Figure 5 , in some implementation manners, the electronic component 313 is not connected to Figure 4 the chip 16 shown, that is to say, the electronic component 313 is not connected to the chip 16, the conductive portion 312, the first connection portion 32, and the second connection portion 33; correspondingly, the electronic component 313 can be connected to the circuit on the substrate 21. Exemplarily, a third connection portion 34 is disposed on the second surface of the board body 311, and the third connection portion 34 is connected to both the electronic component 313 and the circuit on the substrate 21. In this way, the electronic component 313 can assist the circuit on the substrate 21 to work and play a role corresponding to the circuit function.

[0061] Please refer to Figure 6, in some embodiments, a third connection portion 34 connected to the electronic component 313 is provided on the second surface, and the other end of the third connection portion 34 is connected to the circuit on the substrate 21. The other end of the electronic component 313 can be configured to have a preset potential. Exemplarily, the other end of the electronic component 313 can be connected to the ground network or the power network. It can be understood that the other end of the electronic component 313 is connected to the ground network, that is, the other end of the electronic component 313 is connected to the grounding circuit on the package substrate 31, so that the other end of the electronic component 313 is at zero potential; where the grounding circuit can be a line or structure for grounding on the package substrate 31. The other end of the electronic component 313 is connected to the power network, that is, the other end of the electronic component 313 is connected to the circuit connecting the power supply in the package substrate 31, so that the other end of the electronic component 313 has a certain potential; generally, there are lines or structures connecting the power supply in the package substrate 31 to supply power to the chip 16, and correspondingly, the other end of the electronic component 313 can be connected to the lines or structures connecting the power supply. In this way, the electronic component 313 can assist the circuit on the substrate 21 to work and play a role corresponding to the circuit function.

[0062] Continue to refer to Figure 6 , in the implementation where the electronic device 30 (such as Figure 4 shown) is a radio frequency electronic device and the electronic component 313 is an inductor 141, the radio frequency chip 161 is connected to the first connection portion 32 to realize the connection between the radio frequency chip 161 and the package substrate 31; the package substrate 31 is connected to the circuit on the substrate 21 through the second connection portion 33 and finally connected to the antenna 17 to realize the connection between the radio frequency chip 161 and the antenna 17. The inductor 141 is connected to the circuit on the substrate 21 to assist the circuit to realize the corresponding function.

[0063] In some implementation manners, the electronic component 313 is connected to the chip 16. Please refer to Figure 7 , in some embodiments, one end of the electronic component 313 can be configured to have a preset potential. For example, one end of the electronic component 313 can be connected to the ground network or the power network in the package substrate 31; the other end of the electronic component 313 is connected to the third connection portion 34.

[0064] In some embodiments, the third connection portion 34 can be connected to the second connection portion 33 through the circuit on the substrate 21 to realize the connection between the electronic component 313 and the chip 16. With such a setting, the electronic component is connected to the signal link, can assist the chip to work, and improve the performance of the electronic device. Continue to refer to Figure 7 , in the electronic device 30 (such as Figure 4As shown, it is a radio frequency electronic device. In the implementation of the electronic component 313 as the inductor 141, the radio frequency chip 161 is connected to the first connection portion 32 to realize the connection between the radio frequency chip 161 and the packaging substrate 31; the packaging substrate 31 is connected to the circuit on the substrate 21 through the second connection portion 33 and finally connected to the antenna 17 to realize the connection between the radio frequency chip 161 and the antenna 17. In the implementation of focusing on high-frequency signals, the inductor 141 has a good effect on biasing the DC component. One end of the inductor 141 is connected to the third connection portion 34, and the third connection portion 34 is connected to the second connection portion 33 to realize the connection between the inductor 141 and the radio frequency chip 161; the other end of the inductor 141 is configured to have a preset potential. That is, the inductor can deliver the DC signal to the ground network or the power network to eliminate the DC signal, thereby avoiding the influence of the DC signal on the operation of the antenna.

[0065] In some embodiments, the third connection portion 34 can be configured to have a preset potential. Exemplarily, the third connection portion 34 can be connected to the ground network or the power network on the substrate 21. With such a setting, the electronic component does not affect the signal quality, and the chip can be connected to the electronic component corresponding to the function of the electronic device integrated on the substrate.

[0066] Please refer to Figure 8 , in the implementation of focusing on low-frequency signals, the area of the inductor 141 wound inside the package is limited, the inductance value of the inductor 141 is small, and the effect of the inductor 141 on biasing the DC component is poor. The third connection portion 34 is connected to the ground network or the power network (bypass inductor 141). In this way, it is avoided that the inductor delivers part of the low-frequency radio frequency signal to the ground network or the power network, resulting in radio frequency signal loss.

[0067] It can be understood that in the implementation of the bypass inductor 141, the target networks connected to both ends of the inductor 141 are the same. In the implementation where one end of the inductor 141 inside the package is configured as the ground network, the third connection portion 34 is connected to the ground network on the substrate 21; in the implementation where one end of the inductor 141 inside the package is configured as the power network, the third connection portion 34 is connected to the same power network on the substrate 21 to ensure that the voltages at both ends of the inductor 141 are the same, and to avoid grounding one end of the inductor 141 and connecting the other end to the power network, resulting in a voltage generated in the path of the inductor 141 and causing a short circuit between the power supply and the ground.

[0068] Please refer to Figure 9 , in other embodiments, one end of the electronic component 313 can be connected to the conductive portion 312 to realize the connection between the electronic component 313 and the chip 16; the other end of the electronic component 313 is connected to the third connection portion 34.

[0069] In some embodiments, the third connection portion 34 may be connected to a ground network or a power network, such that the third connection portion 34 has a preset potential. With such an arrangement, the electronic component can assist the chip in operating, so as to improve the performance of the electronic device.

[0070] Continuing to refer to Figure 9 , in an implementation manner where the electronic device 30 (as shown in Figure 4 ) is a radio frequency electronic device and the electronic component 313 is an inductor 141, the radio frequency chip 161 is connected to the first connection portion 32 to achieve the connection between the radio frequency chip 161 and the package substrate 31; the package substrate 31 is connected to the circuit on the substrate 21 through the second connection portion 33 and finally connected to the antenna 17 to achieve the connection between the radio frequency chip 161 and the antenna 17. In an implementation manner where the signal focuses on high-frequency signals, the inductor 141 has a good effect on biasing the DC component. One end of the inductor 141 is connected to the radio frequency chip 161 through the conductive portion 312, and the other end is connected to the ground network or the power network on the substrate 21 through the second connection portion 33 to achieve the function of biasing the DC signal component of the inductor 141, that is, the inductor can deliver the DC signal to the ground network or the power network to eliminate the DC signal, thereby avoiding the DC signal from affecting the operation of the antenna.

[0071] In some embodiments, the third connection portion 34 may be left floating, that is to say, the third connection portion 34 is not connected to the circuit on the substrate. With such an arrangement, the electronic component does not participate in the operation of the signal link, avoiding signal loss.

[0072] Please refer to Figure 10 , in an implementation manner where the signal focuses on low-frequency signals, the area of the in-package wirewound inductor 141 is limited, the inductance value of the inductor 141 is small, and the inductor 141 has a poor effect on biasing the DC component. The third connection portion 34 is left floating (bypassing the inductor 141). In this way, it is avoided that the inductor delivers part of the low-frequency radio frequency signal to the ground network or the power network, resulting in radio frequency signal loss.

[0073] Please refer to Figure 11 , in other embodiments, one end of the electronic component 313 may be connected to the first connection portion 32 to achieve the connection between the electronic component 313 and the chip 16, or a fourth connection portion 35 is provided on the first surface, and the electronic component 313 is connected to the chip 16 through the fourth connection portion 35. The structure of the fourth connection portion 35 is substantially the same as that of the first connection portion 32 and will not be elaborated herein. In this way, the electronic component can assist the chip in operating, so as to improve the performance of the electronic device.

[0074] It can be understood that the signal may be a single-ended signal or a differential signal. Since both signal lines are used for signal transmission in differential transmission, the two transmitted signals have the same amplitude and a certain phase difference, and two signal channels and DC bias circuits 10 are correspondingly provided. Please refer toFigure 12 In an implementation where the signal includes differential signals, the conductive part 312 includes a first conductive part 3121 and a second conductive part 3122. The first conductive part 3121 and the second conductive part 3122 are arranged at intervals. Both the first connection part 32 and the second connection part 33 are two. One end of the first conductive part 3121 is connected to a first connection part 321, and the other end of the first conductive part 3121 is connected to a second connection part 331. One end of the second conductive part 3122 is connected to another first connection part 322, and the other end of the second conductive part 3122 is connected to another second connection part 332. The electronic component 313 includes a first electronic component 3131 and a second electronic component 3132. The first electronic component 3131 is arranged corresponding to and at intervals from the first conductive part 3121, and the second electronic component 3132 is arranged corresponding to and at intervals from the second conductive part 3122. The third connection part 34 includes two. The first electronic component 3131 is connected to a third connection part 341, and the second electronic component 3132 is connected to another third connection part 342. In this way, the conductive part and the electronic component respectively correspond to the two signal channels for transmitting differential signals.

[0075] It can be understood that the first electronic component 3131 and the second electronic component 3132 may include at least one of a resistor, an inductor, and a capacitor, and the first electronic component 3131 and the second electronic component 3132 may be the same or different.

[0076] Please refer to Figure 13 In some implementations, one end of the first electronic component 3131 is configured to have a preset potential, and the other end is connected to a third connection part 341; one end of the second electronic component 3132 is configured to have a preset potential, and the other end is connected to another third connection part 342.

[0077] In some embodiments, the two third connection parts 34 (341 and 342) are correspondingly connected to the two second connection parts 33 (331 and 332) through the circuit on the substrate 21. With such an arrangement, the first electronic component 3131 and the second electronic component 3132 are connected to the signal link, which can assist the chip to work and improve the performance of the electronic device.

[0078] Continue to refer to Figure 13, in an implementation where the signal includes a differential signal and the signal focuses on high-frequency signals, and both the first electronic component 3131 and the second electronic component 3132 include an inductor 141, the inductor 141 has a good effect on biasing the DC component. At this time, the two third connection parts 34 (341 and 342) are correspondingly connected to the two second connection parts 33 (331 and 332) on the substrate 21 to realize the connection between the inductor 141 and the signal path. That is, the two inductors 141 can respectively deliver the DC signals in the corresponding signal paths to the ground network or the power supply network to eliminate the DC signals, thereby avoiding the influence of the DC signals on the antenna operation.

[0079] Please refer to Figure 14 , Figure 14 for Figure 13 the signal insertion loss (Insertion Loss, abbreviated as IL) diagram of the corresponding circuit board 20. The abscissa represents the frequency of the signal, and the ordinate represents the insertion loss of the signal; the solid line is the curve corresponding to the embodiment of the present application, and the dotted line is the curve corresponding to the circuit board 20 with only a signal path inside the package substrate 31 in the related art. When the frequency is 1.8 GHz - 10 GHz, the two curves coincide highly. Specifically, when the frequency is 5.71 GHz, the insertion loss corresponding to the embodiment of the present application is -2.30 dB, and the insertion loss corresponding to the related art is -2.41 dB, and the data difference is small. It shows that in the high-frequency band, the inductor 141 has almost no influence on the high-frequency radio frequency signal component. When the frequency is less than 1.8 GHz, the curve corresponding to the embodiment of the present application drops, indicating that the DC signal component in the signal is output from the DC bias port 13 through the inductor 141, which is consistent with the purpose to be achieved by the embodiment of the present application. It shows that in an implementation where the signal includes a differential signal and the signal includes a high-frequency signal, the inductor 141 located inside the package substrate 31 can both bias the DC signal component in the signal path and has no influence on the high-frequency component in the signal path.

[0080] Please refer to Figure 15 , Figure 15 for Figure 13The signal return loss (Return Loss, abbreviated as RL) diagram of the corresponding circuit board 20. The abscissa represents the frequency of the signal, and the ordinate represents the return loss of the signal; the solid line is the curve corresponding to the embodiment of the present application, and the dashed line is the curve corresponding to the circuit board with only signal paths inside the package substrate 31. In the related art, the DC bias circuit 10 of the RF signal usually requires the return loss of the signal to be less than -10 dB. When the return loss corresponding to the embodiment of the present application is -10 dB, the covered frequency band is 0.85 GHz - 10 GHz, meeting the index requirements, and the signal path can be used normally. Similarly, when the return loss corresponding to the embodiment of the present application is -15 dB, the covered frequency band is 1.22 GHz - 4.39 GHz. It can be understood that for the frequency band requirements above 10 GHz, it can be optimized by integrating small inductors or by reducing the coupling capacitance, including increasing the wire spacing of the winding inductor 141 in the package substrate 31, and increasing the size of the anti-pad of the inductor 141; for the frequency band requirements below 0.85 GHz, it can be achieved by increasing the length of the winding inductor 141 in the package substrate 31, but limited by the size of the package substrate 31, the inductor 141 needs to be bypassed at lower frequencies, and a large inductor is integrated on the circuit board 20 to solve the problem.

[0081] In some implementation manners, the two third connection parts 34 (341 and 342) are configured to have a preset potential. Exemplarily, they can be connected to the ground network or the power network on the substrate 21. With such a setting, the first electronic component 3131 and the second electronic component 3132 do not affect the signal quality, and the chip can be connected to the electronic components corresponding to the functions of the electronic devices integrated on the substrate.

[0082] Please refer to Figure 16 , in the implementation manner where the signal includes differential signals and the signal focuses on low-frequency signals, and both the first electronic component 3131 and the second electronic component 3132 include inductors, the area of the inductor wound inside the package is limited, the inductance value of the inductor is small, and the effect of the inductor biasing the DC component is poor. At this time, the two third connection parts 34 can be connected to the ground network or the power network on the substrate 21. It can be understood that the target networks connected to both ends of the two inductors are kept consistent, which will not be elaborated here. In this way, it is avoided that the two inductors send some low-frequency RF signals in the corresponding signal paths to the ground network or the power network, resulting in RF signal loss.

[0083] Please refer to Figure 17 , Figure 17 For Figure 16The signal insertion loss diagram of the corresponding circuit board 20. The abscissa represents the frequency of the signal, and the ordinate represents the insertion loss of the signal; the solid line is the curve corresponding to the embodiment of the present application, and the dashed line is the curve corresponding to the circuit board with only signal paths inside the package substrate 31. The two curves are almost the same. Specifically, when the frequency is 6.00 GHz, the insertion loss corresponding to the embodiment of the present application is -1.05 dB, and the insertion loss corresponding to the related art is -1.04 dB, and the data difference is small. The signal insertion loss curve corresponding to the embodiment of the present application is smooth, indicating that there is no stub effect on the signal path. That is to say, when the inductor 141 in the embodiment of the present application is in a non-operating state, even if the inductor 141 is connected to the signal path, the transmission of the signal is not affected by the branch connected to the inductor 141.

[0084] Please refer to Figure 18 , Figure 18 is Figure 16 The signal return loss diagram of the corresponding circuit board 20. The abscissa represents the frequency of the signal, and the ordinate represents the return loss of the signal; the solid line is the curve corresponding to the embodiment of the present application, and the dashed line is the curve corresponding to the circuit board with only signal paths inside the package substrate 31. The curve corresponding to the embodiment of the present application coincides highly with the curve corresponding to the related art. Specifically, when the frequency is 6.00 GHz, the return loss corresponding to the embodiment of the present application is -19.39 dB, and the return loss corresponding to the related art is -19.64 dB, and the data difference is small. It shows that in the implementation where the signal includes differential signals and low-frequency signals, the inductor 141 located inside the package substrate 31 hardly affects the signal quality.

[0085] Please refer to Figure 19 , in other implementation manners, one end of the first electronic component 3131 is connected to the first conductive part 3121, and the other end is connected to a third connection part 341; one end of the second electronic component 3132 is connected to the second conductive part 3122, and the other end is connected to another third connection part 342.

[0086] In some embodiments, the two third connection parts 34 (341 and 342) can be connected to the ground network or the power supply network, so that the two third connection parts 34 (341 and 342) have a preset potential. With such a setting, the first electronic component 3131 and the second electronic component 3132 can assist the chip to work, so as to improve the performance of the electronic device.

[0087] In an implementation where the signal includes a differential signal and the signal focuses on high-frequency signals, and both the first electronic component 3131 and the second electronic component 3132 include inductors, the effect of the inductor biasing the DC component is relatively good. At this time, the two third connection parts 34 (341 and 342) are connected to the ground network or the power supply network through the lines on the substrate 21. That is, the two inductors can respectively deliver the DC signals in the corresponding signal paths to the ground network or the power supply network to eliminate the DC signals, thereby avoiding the influence of the DC signals on the operation of the antenna.

[0088] In some embodiments, the two third connection parts 34 (341 and 342) are left floating, that is to say, neither of the two third connection parts 34 (341 and 342) is connected to the circuit on the substrate. With such a setting, the first electronic component 3131 and the second electronic component 3132 do not participate in the operation of the signal link, avoiding signal loss.

[0089] In an implementation where the signal includes a differential signal and the signal focuses on low-frequency signals, and both the first electronic component 3131 and the second electronic component 3132 include inductors, the area of the inductor wound inside the package is limited, the inductance value of the inductor is small, and the effect of the inductor biasing the DC component is relatively poor. At this time, the two third connection parts 34 (341 and 342) are left floating. In this way, it is avoided that the two inductors deliver some low-frequency RF signals in the corresponding signal paths to the ground network or the power supply network, resulting in RF signal loss.

[0090] Please refer to Figure 20 , in an implementation where both the first electronic component 3131 and the second electronic component 3132 are inductors, the first electronic component 3131 and the second electronic component 3132 can be arranged in a direction perpendicular to the plate body 311. That is to say, in the plane parallel to the plate body 311, the projections of the first electronic component 3131 and the second electronic component 3132 at least partially overlap; of course, the first electronic component 3131 and the second electronic component 3132 can also be arranged in a direction parallel to the plate body 311. In this way, the space occupied by the first electronic component 3131 and the second electronic component 3132 can be reduced, saving the internal space of the package substrate 31.

[0091] Please refer to Figure 21, in some implementations, the board body 311 includes a first board body 311a, an intermediate board body 311b, and a second board body 311c that are stacked. The intermediate board body 311b is located between the first board body 311a and the second board body 311c, and the thickness of the intermediate board body 311b is greater than the thicknesses of the first board body 311a and the second board body 311c. It can be understood that multiple conductive layers 3111 and multiple dielectric layers 3112 in the board body 311 are alternately stacked. The intermediate board body 311b is the thickest dielectric layer 3112 near the longitudinal middle position of the board body 311. Both the first board body 311a and the second board body 311c include multiple conductive layers 3111 and multiple dielectric layers 3112. The electronic component 313 can be disposed in the conductive layer 3111 or in the dielectric layer 3112. The embodiments of the present application do not limit the setting position of the electronic component 313.

[0092] In the implementation where the electronic component 313 is disposed in the dielectric layer 3112, the electronic component 313 includes a physical electronic component 3133. Since the thickness of the intermediate board body 311b is greater than that of other dielectric layers 3112, the physical electronic component 3133 can be disposed in the intermediate board body 311b. In some embodiments, one pin of the physical electronic component 3133 is connected to the conductive part 312, and the other pin is connected to the third connection part 34. In other embodiments, one pin of the physical electronic component 3133 can be configured to have a preset potential, and the other pin is connected to the third connection part 34. It can be understood that the intermediate board body 311b can include multiple physical electronic components 3133, and the multiple physical electronic components 3133 are spaced apart. The multiple physical electronic components 3133 can be the same or different. In this way, the dielectric layer is fully utilized, and the internal space of the packaging substrate is saved.

[0093] In some implementations, at least one conductive layer 3111 in the board body 311 is grounded, and at least one conductive layer 3111 is connected to a target power supply. In the implementation where one end of the electronic component 313 is configured to have a preset potential, one end of the electronic component 313 can be connected to the conductive layer 3111 having the preset potential in the board body 311.

[0094] In the above implementation, there is at least one grounded conductive layer 3111 and vias surrounding the electronic component 313, realizing self-shielding of the electronic component 313. Compared with integrating the electronic component 313 on the substrate 21, there is no need to additionally provide a shielding cavity for the electronic component 313, avoiding the EMI risk introduced by the electronic component 313.

[0095] Continue to refer to Figure 21, in some implementations, the board body 311 includes a plurality of conductive layers 3111 and a plurality of dielectric layers 3112, and the plurality of conductive layers 3111 and the plurality of dielectric layers 3112 are alternately stacked. The electronic component 313 includes an inductor 141. The inductor 141 includes a first coil 313a and a second coil 313b arranged in series. At least a part of the first coil 313a is located in one conductive layer 3111, and at least a part of the second coil 313b is located in another conductive layer 3111. It can be understood that, in some implementations, the first coil 313a and the second coil 313b are located in different layers, and the coils in different layers are connected through encapsulated via holes for layer change. In this way, the inductance value of the inductor can be adjusted by changing the winding length of the first coil and the second coil, which is convenient for realizing the function of the inductor biasing the DC signal. In addition, the inductor is arranged inside the board body 311, realizing self-shielding, avoiding the EMI risk introduced by the inductor, and eliminating the need for an additional shielding cavity compared with integrating the inductor on the substrate.

[0096] Please refer to Figure 22 , in some implementations, in the plane parallel to the board body 311, the projection of the first coil 313a is located within the projection of the second coil 313b. It can be understood that the present application embodiment does not limit the winding directions of the first coil 313a and the second coil 313b. Taking Figure 22 the shown orientation as an example, the first coil 313a with a clockwise winding direction is connected to the second coil 313b with a clockwise winding direction through an encapsulated via hole for layer change. Taking Figure 23 the shown orientation as an example, the first coil 313a with a counterclockwise winding direction is connected to the second coil 313b with a counterclockwise winding direction through an encapsulated via hole for layer change. It can be understood that the positional relationship between the first coil 313a and the second coil 313b further includes that in the plane parallel to the board body 311, at least a part of the projection of the first coil 313a may overlap with at least a part of the projection of the second coil 313b. In this way, the inductor in the encapsulated substrate can be multi-layer wound, reducing the winding area of each layer and saving the internal space of the encapsulated substrate.

[0097] Please refer to Figure 24 , in other implementations, the first coil 313a and the second coil 313b are located in the same layer, that is to say, the first coil 313a and the second coil 313b are located in the same plane parallel to the board body 311. Taking Figure 24Taking the shown orientation as an example, the first coil 313a is wound counterclockwise, and the second coil 313b is wound clockwise. One end of the first coil 313a is connected to one end of the second coil 313b. The other end of the first coil 313a and the other end of the second coil 313b are respectively used as the two ends of the winding inductor 141. It can be understood that this embodiment is not limited thereto. The winding directions of the first coil 313a and the second coil 313b can be other combinations. Exemplarily, the winding direction of the first coil 313a can include clockwise, and the winding direction of the second coil 313b can include counterclockwise. The combination of the first coil 313a and the second coil 313b can include two clockwise-wound coils, two counterclockwise-wound coils, etc. In this way, the inductance value can be adjusted by changing the winding lengths of the first coil 313a and the second coil 313b, facilitating the realization of the function of the inductor biasing the DC signal.

[0098] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the embodiments of the present application, rather than to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements on some or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. An encapsulation substrate, characterized in that, Comprising: A plate body, on the first surface of the plate body there is a first connection part, on the second surface of the plate body there is a second connection part, and the first surface and the second surface are oppositely arranged; A conductive part, the conductive part is arranged in the plate body, one end of the conductive part is connected to the first connection part, and the other end of the conductive part is connected to the second connection part; An electronic component, the electronic component is arranged in the plate body, and the electronic component is arranged at an interval from the conductive part; There is a third connection part on the second surface, and the electronic component is connected to the third connection part.

2. The encapsulated substrate according to claim 1, wherein One end of the electronic component is connected to the conductive part, and the other end of the electronic component is connected to the third connection part.

3. The encapsulation substrate according to claim 1, wherein One end of the electronic component is configured to have a preset potential, and the other end of the electronic component is connected to the third connection part.

4. The encapsulation substrate according to any one of claims 1 to 3, characterized in that, The conductive part includes a first conductive part and a second conductive part, the first conductive part and the second conductive part are arranged at an interval, both the first connection part and the second connection part are two, one end of the first conductive part is connected to one of the first connection parts, the other end of the first conductive part is connected to one of the second connection parts, one end of the second conductive part is connected to the other first connection part, and the other end of the second conductive part is connected to the other second connection part; The electronic component includes a first electronic component and a second electronic component, the first electronic component is arranged corresponding to and at an interval from the first conductive part, and the second electronic component is arranged corresponding to and at an interval from the second conductive part; The third connection part includes two, the first electronic component is connected to one third connection part, and the second electronic component is connected to the other third connection part.

5. The encapsulation substrate according to any one of claims 1-4, characterized in that The electronic component includes at least one of an inductor, a capacitor, and a resistor.

6. The encapsulation substrate according to any one of claims 1-5, characterized in that, The plate body includes a plurality of conductive layers and a plurality of dielectric layers, and the plurality of conductive layers and the plurality of dielectric layers are alternately stacked; the electronic component includes an inductor, and the inductor includes a first coil and a second coil arranged in series, at least part of the first coil is located in one of the conductive layers, and at least part of the second coil is located in another conductive layer.

7. The encapsulated substrate according to claim 6, wherein In a plane parallel to the plate body, the projection of the first coil is located within the projection of the second coil.

8. The encapsulated substrate according to any one of claims 1-5, characterized in that, The plate body includes a first plate body, an intermediate plate body, and a second plate body which are stacked, the intermediate plate body is located between the first plate body and the second plate body, the thickness of the intermediate plate body is greater than the thicknesses of the first plate body and the second plate body, and the electronic component is arranged in the intermediate plate body.

9. An electronic device, characterized in that, Comprising: A chip and the packaging substrate according to any one of claims 1-8, the chip is arranged on the first surface, and the chip is electrically connected to the first connection part.

10. A circuit board, characterized in that, Comprising: A substrate and the electronic device according to claim 9, the electronic device is arranged on the substrate.

11. An electronic device, characterized in that, Comprising: A battery and the circuit board according to claim 10, the battery is electrically connected to the circuit board.

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