Test structure of wafer, test wafer and preparation method of test wafer

Abstract

The invention relates to a wafer test structure, a test wafer and a preparation method of the test wafer. The test structure comprises a test part located on the first side of the wafer and two test ports located at the two ends of the test part. Wherein the testing part comprises at least one characteristic line and at least two testing lines, and the testing lines are connected end to end through the characteristic lines; the width of the characteristic line is different from that of the test line; each test port is used for being connected with time domain reflection equipment, receiving a test signal transmitted by the time domain reflection equipment and receiving a reflection signal formed after the test signal is reflected by the characteristic line; wherein the test signal and the reflection signal are jointly used for determining electrical parameters of the characteristic line. Through the test structure, whether the wafer breaks and fails can be judged.

Description

Technical Field

[0001] The present application relates to the technical field of wafer thinning, and particularly to a test structure of a wafer, a test wafer, and a method for manufacturing a test wafer. Background Art

[0002] Wafer thinning is a key step in the back-end process of semiconductor manufacturing. Through precise grinding technology, the back surface of the wafer is gradually thinned to reach a predetermined thickness specification. This can not only reduce the chip thickness and package size but also improve the heat dissipation effect and overall performance of the chip.

[0003] However, since the thinning process significantly reduces the wafer thickness, thereby increasing its brittleness, when the process parameters do not match during the thinning process, the wafer will break or fail. Summary of the Invention

[0004] Based on this, it is necessary to provide a test structure of a wafer, a test wafer, and a method for manufacturing a test wafer that can test the fracture failure of a wafer for the above technical problems.

[0005] In a first aspect, the present application provides a test structure of a wafer, including: a test portion located on a first side of the wafer, and two test ports located at both ends of the test portion; wherein,

[0006] The test portion includes at least one feature line and at least two test lines, and each of the test lines is connected end to end through the feature line; the width of the feature line is different from the width of the test line;

[0007] Each of the test ports is used to connect to a time domain reflectometry device, and is used to receive a test signal emitted by the time domain reflectometry device, and receive a reflected signal formed after the test signal is reflected by the feature line; wherein, the test signal and the reflected signal are jointly used to determine the electrical parameters of the feature line.

[0008] In one embodiment, the test structure includes:

[0009] An adhesion layer, located on the first side of the wafer, the first side and the second side of the wafer are opposite sides, and the second side is the side of the wafer to be thinned;

[0010] A conductive layer, located on the side of the adhesion layer away from the wafer.

[0011] In one embodiment, the test portion includes at least two sub-test portions connected in sequence, each of the sub-test portions respectively includes at least one of the feature lines and at least two test lines, and any two adjacent sub-test portions are connected through the test lines, and the distances between the feature lines of different sub-test portions and the center of the wafer are different; wherein,

[0012] The first end of the first sub - test part is connected to one of the test ports, and the second end of the last sub - test part is connected to the other test port.

[0013] In one embodiment, the at least two sub - test parts include a first sub - test ring and a second sub - test ring arranged concentrically, and the center of the first sub - test ring and the second sub - test ring is the center of the wafer; wherein, the distance between the first sub - test ring and the wafer is between two - fifths and three - fifths of the radius of the wafer; the distance between the second sub - test ring and the wafer is between seven - tenths and nine - tenths of the radius of the wafer.

[0014] In a second aspect, the present application provides a test wafer, which includes a wafer and the test structure of the wafer in any one of the above embodiments.

[0015] In a third aspect, the present application provides a method for preparing a test wafer, and the method includes:

[0016] Providing a wafer;

[0017] Forming an adhesion layer on the first side of the wafer by using a mask; wherein, the mask includes a test part pattern and two test port patterns located at both ends of the test part, the first side and the second side of the wafer are opposite sides, and the second side is the side of the wafer to be thinned.

[0018] Forming a conductive layer on the side of the adhesion layer away from the wafer by using a mask to form a test structure; wherein, the test structure includes a test part and two test ports located at both ends of the test part, the test part includes at least one feature line and at least two test lines, and each test line is connected end to end through the feature line; the width of the feature line is different from the width of the test line.

[0019] Each test port is used to be connected to a time - domain reflectometry device, and is used to receive a test signal emitted by the time - domain reflectometry device, and receive a reflected signal formed after the test signal is reflected by the feature line; wherein, the test signal and the reflected signal are jointly used to determine the electrical parameters of the feature line.

[0020] In a fourth aspect, the present application provides a method for thinning and testing a wafer, which is applied to the test wafer in the above - mentioned embodiments, and the method includes:

[0021] Obtaining the initial electrical parameters of the test structure on the test wafer;

[0022] Obtaining the test electrical parameters of the test structure after the second side of the test wafer is thinned.

[0023] Determine the thinning test result of the test wafer according to the initial electrical parameters and the test electrical parameters.

[0024] In one embodiment, the thinning process includes a mechanical thinning process, and the test electrical parameters include mechanical test electrical parameters; wherein, the obtaining of the test electrical parameters of the test structure after thinning the second side of the test wafer includes:

[0025] Form a first protective layer on a side of the test structure away from the test wafer.

[0026] Perform a mechanical thinning process on the second side of the test wafer.

[0027] Remove the first protective layer and obtain the mechanical test electrical parameters after the mechanical thinning process of the test wafer.

[0028] In one embodiment, the thinning process includes a chemical polishing process, and the test electrical parameters include chemical test electrical parameters; wherein, the obtaining of the test electrical parameters of the test structure after thinning the second side of the test wafer includes:

[0029] Form a second protective layer on a side of the test structure away from the test wafer.

[0030] Perform a chemical polishing process on the second side of the test wafer.

[0031] Remove the second protective layer and obtain the chemical test electrical parameters after the chemical polishing process of the test wafer.

[0032] In one embodiment, the test structure includes a first sub-test ring and a second sub-test ring; the method further includes:

[0033] In the case where the thinning process result is that the first sub-test ring fails, adjust the first working parameter of the thinning process.

[0034] In the case where the thinning process result is that the second sub-test ring fails, adjust the second working parameter of the thinning process.

[0035] Wherein, the first working parameter is different from the second working parameter.

[0036] The above-mentioned test structure of the wafer, test wafer, preparation method of the test wafer, and thinning test method of the wafer include a test part located on the first side of the wafer and two test ports located at both ends of the test part. The test part includes at least one characteristic line and at least two test lines. Each of the test lines is connected end to end through the characteristic line. The width of the characteristic line is different from the width of the test line, and thus the impedance of the characteristic line is different from the impedance of the test line. A time domain reflectometry device can send a test signal to the test structure through the test port. Since the impedance of the characteristic line is different from that of the test line, when the test signal passes through the characteristic line, a reflected signal will be generated due to reflection. In applications, test signals can be sent to the test structure on the wafer before and after wafer thinning respectively. By comparing whether the reflected signals of the characteristic lines obtained before and after wafer thinning change, it can be determined whether the wafer has fractured and failed. Description of the Drawings

[0037] To more clearly illustrate the technical solutions in the embodiments of the present application or in the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the following drawings are only some embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0038] Figure 1 Structural schematic diagram of the test structure of the wafer in one embodiment;

[0039] Figure 2 Cross-sectional schematic diagram of the test wafer in one embodiment;

[0040] Figure 3 Structural schematic diagram of the test structure of the wafer in another embodiment;

[0041] Figure 4 Flow schematic diagram of the preparation method of the test wafer in one embodiment;

[0042] Figure 5 Flow schematic diagram of the thinning test method of the wafer in one embodiment;

[0043] Figure 6 Flow schematic diagram of step S502 in one embodiment;

[0044] Figure 7 Flow schematic diagram of step S502 in another embodiment;

[0045] Figure 8 Flow schematic diagram of the thinning test method of the wafer in another embodiment;

[0046] Figure 9Waveform diagram of the reflected signal when the test structure is intact in an embodiment;

[0047] Figure 10 Waveform diagram of the reflected signal when there is a break near the position of the first characteristic line in an embodiment;

[0048] Figure 11 Waveform diagram of the reflected signal when there is a break near the position of the fourth characteristic line in an embodiment. Detailed implementation manners

[0049] To facilitate the understanding of this application, the following will provide a more comprehensive description of this application with reference to the relevant attached drawings. Embodiments of this application are given in the drawings. However, this application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, these embodiments are provided to make the disclosure of this application more thorough and comprehensive.

[0050] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the technical field to which this application belongs. The terms used in the description of this application herein are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0051] It can be understood that the terms "first", "second", etc. used in this application can be used herein to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish one element from another.

[0052] Spatial relationship terms such as "under", "below", "lower", "beneath", "above", "upper", etc. can be used herein to describe the relationship between an element or feature shown in the drawings and other elements or features. It should be understood that in addition to the orientations shown in the drawings, spatial relationship terms also include different orientations of the devices during use and operation. For example, if the device in the attached drawings is flipped, the element or feature described as "under other elements" or "beneath it" or "under it" will be oriented "above" other elements or features. Therefore, the exemplary terms "under" and "below" can include both the upper and lower orientations. In addition, the device can also include other orientations (such as rotating 90 degrees or other orientations), and the spatial description terms used herein are correspondingly interpreted.

[0053] It should be noted that when an element is considered to be "connected" to another element, it can be directly connected to the other element or connected to the other element through an intermediate element. In addition, for the "connection" in the following embodiments, if there is a transmission of electrical signals or data between the connected objects, it should be understood as "electrically connected", "communicatively connected", etc.

[0054] As used herein, the singular forms "a", "an" and "the" may also include the plural forms unless the context clearly dictates otherwise. It should also be understood that the terms "comprises / comprising", "has" etc. specify the presence of the stated features, integers, steps, operations, components, parts, or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, components, parts, or combinations thereof. At the same time, the term "and / or" used in this specification includes any and all combinations of the related listed items.

[0055] As described in the background section, wafer thinning is a key step in the back-end process of semiconductor manufacturing. Through precise grinding technology, the back side of the wafer is gradually thinned to achieve the predetermined thickness specification, which can not only reduce the chip thickness and package size, but also improve the chip's heat dissipation effect and overall performance. In the post-Moore era, due to the limitations of lithography technology and the physical properties of materials, it has become extremely difficult to continue shrinking the transistor size. Therefore, advanced packaging technology is urgently needed, and wafer thinning technology has become even more important. According to Moore's Law, the number of transistors on an integrated circuit doubles every 18 months. The size of transistors on the chip is getting smaller and the price is getting cheaper. However, in recent years, due to the limitations of lithography technology and the physical properties of materials, it has become extremely difficult to continue shrinking the transistor size, and Moore's Law is about to face failure. The high-density advanced packaging technology of chips is considered an important means to break through Moore's Law and further improve chip performance. In the process of semiconductor manufacturing, the wafer thinning process is an essential part of achieving advanced packaging and high-performance devices. However, in order to ensure the quality and reliability of the wafer, defect detection must be carried out during the thinning process to identify defects that may affect the performance of subsequent processes and the final product. Since the thinning process significantly reduces the wafer thickness, it increases its brittleness. When the process parameters do not match during the thinning process, the wafer will break or fail. Technicians can avoid further processing of defective wafers by detecting defects in advance, thereby reducing material waste and production costs.

[0056] In the related art, a method for defect detection of a wafer is to make polarized light incident obliquely on the wafer after the light is polarized by a polarizer, and use a CCD imaging device to capture the scattered light. Based on the obtained P-polarized light component image and S-polarized light component image, the intensity of the polarized light component and the polarization direction as the ratio of them are calculated. According to the images obtained by shooting in the state where no stress is applied to the wafer and in the state where a static stress as a tensile stress is applied to the surface on the light-irradiated side of the wafer by applying a static load to the wafer, the intensity of the polarized light component and the polarization direction are calculated, and the defects are detected and classified by comparing with a specified threshold. Although this method can perform quality management on wafer inspection defects, it is necessary to scan each position of the wafer with polarized light, the time for detecting faults is too long, it cannot be detected efficiently, the technical implementation is complex, the equipment cost and maintenance cost are relatively high, and it is necessary to support software for data analysis, which increases the complexity and dependence of the technical implementation. At the same time, this detection method has certain requirements for the flatness or material uniformity of the wafer surface, and its applicability needs to be further verified.

[0057] Another method for defect detection of a wafer in the related art is to obtain a target image through the graphic data system (GDS) information of a specific layout in a semiconductor wafer. Among them, the target image includes a first profile having a first pattern corresponding to the specific layout. According to the first profile, image-based alignment is performed to collect an original image from the semiconductor wafer. The semiconductor wafer is analyzed by measuring the original image, thereby providing a diagnostic result. This method requires equipment such as an electron microscope, the technical implementation is complex, the equipment cost and maintenance cost are relatively high, and it requires a supporting database for data analysis, with high labor costs and high complexity of technical implementation.

[0058] Based on the above technical problems, in an exemplary embodiment, please refer to Figure 1 , the present application provides a test structure 20 of a wafer, including: a test part located on the first side of the wafer 10, and two test ports 21 located at both ends of the test part; wherein, the test part includes at least one feature line 22 and at least two test lines 23, and each test line 23 is connected end to end through the feature line 22; the width of the feature line 22 is different from the width of the test line 23; each test port 21 is used to connect to a time domain reflectometry device, and is used to receive a test signal emitted by the time domain reflectometry device and receive a reflected signal formed after the test signal is reflected by the feature line 22; wherein, the test signal and the reflected signal are jointly used to determine the electrical parameters of the feature line 22.

[0059] It can be understood that the test structure 20 provided by the present application can be formed on the first side surface of the wafer 10. Before the second side of the wafer is thinned, the transmitting probe and the receiving probe of the time-domain reflection device can be respectively connected to the two test ports 21 of the test structure 20. A test signal is sent to the test structure 20 by the transmitting probe, and the reflected signal after the test signal passes through the test section is received through the receiving probe. In the present application, the material of the characteristic line is the same as that of the test line, but the width of the characteristic line 22 is different from the width of the test line 23. Exemplarily, as Figure 1 shown in, the width of the characteristic line 22 is smaller than the width of the test line 23. Therefore, the impedance of the characteristic line 22 will be greater than the impedance of the test line 23. Furthermore, the waveform of the reflected signal passing through the characteristic line 22 appears as a wave peak. In the case where the test section includes multiple characteristic lines 22, due to the position difference of the characteristic lines 22, the transmission time of their reflected waves is also different, thereby realizing the mapping relationship between different wave peaks and the characteristic lines 22 on the test structure 20. In one example, the line width of the test line 23 can be between 50 µm and 1000 µm, the line width of the characteristic line 22 can be 0.2 - 0.4 times the line width of the test line 23, the shape of the test port 21 can be circular, the diameter of the test port 21 can be 1.2 - 1.5 times the line width of the test line 23, and the distance between the two test ports 21 can be between 400 µm and 1000 µm.

[0060] In the application, during the process of thinning the second side of the wafer 10, it may occur that the wafer breaks and fails during the thinning process due to inappropriate thinning process parameters. Therefore, after the second side of the wafer 10 is thinned, the transmitting / receiving probe and the grounding probe of the time-domain reflection device can be respectively connected to the corresponding two test ports 21 in the test structure 20 again. A test signal is sent to the test structure 20 again by the transmitting / receiving probe, and the reflected signal after the test signal passes through the test section is received through the transmitting / receiving probe. It can be understood that if the wafer 10 breaks during the thinning process, the test section on the first side of the wafer 10 will also break, which is specifically manifested as a steep peak with an increased impedance in the reflected signal. By comparing the waveforms of the reflected signals before and after the wafer 10 is thinned, it can be determined whether the wafer 10 breaks and fails during the thinning process.

[0061] The above-mentioned test structure of the wafer includes a test section located on the first side of the wafer, and two test ports located at both ends of the test section. The test section includes at least one characteristic line and at least two test lines. Each of the test lines is connected end to end through the characteristic line. The width of the characteristic line is different from the width of the test line, and thus the impedance of the characteristic line is different from the impedance of the test line. The time domain reflectometry device can send a test signal to the test structure through the test port. Since the impedance of the characteristic line is different from that of the test line, when the test signal passes through the characteristic line, a reflected signal will be generated due to reflection. In application, the test signal can be sent to the test structure on the wafer before and after wafer thinning respectively. By comparing whether the reflected signal of the characteristic line obtained before and after wafer thinning changes, it can be determined whether the wafer has cracked and failed.

[0062] In an exemplary embodiment, please refer to Figure 2 , the test structure 20 includes an adhesion layer 201 and a conductive layer 202. The adhesion layer 201 is located on the first side of the wafer 10. The first side of the wafer 10 and the second side of the wafer 10 are opposite sides, and the second side is the side of the wafer to be thinned. The conductive layer 202 is located on the side of the adhesion layer 201 away from the wafer 10.

[0063] In application, when preparing the test wafer, a mask can be prepared in advance. The mask includes a test section pattern and two test port patterns located at both ends of the test section. First, the wafer 10 is provided. Then, one or more layers of an adhesion layer 201 composed of chromium (Cr) and titanium (Ti) can be uniformly deposited on the first side of the wafer 10 by using the prepared mask in advance. Among them, the deposition method includes but is not limited to physical vapor deposition (PVD), chemical vapor deposition (CVD), or other appropriate deposition techniques. In one example, the thickness of the adhesion layer 201 can be between 30 nm and 1000 nm to provide the adhesion, conductivity, and / or corrosion resistance required for the test structure 20. Then, the mask can be used again to uniformly deposit a conductive layer 202 on the side of the adhesion layer 201 away from the wafer 10 by physical vapor deposition, electroplating, electroless plating, or other appropriate deposition techniques, and thus the test structure 20 can be formed. The material of the conductive layer 202 includes but is not limited to one or more of (Au), silver (Ag), and copper (Cu). The thickness of the conductive layer 202 can be between 50 µm and 2000 µm to provide the required conductivity and solderability.

[0064] In an exemplary embodiment, please refer to Figure 3, the test department includes at least two sub - test departments connected in sequence. Each sub - test department respectively includes at least one feature line 22 and at least two test lines 23. Any two adjacent sub - test departments are connected by a test line 23. The distances between the feature lines of different sub - test departments and the center of the wafer are different; among them, the first end of the first sub - test department is connected to a test port, and the second end of the last sub - test department is connected to another test port.

[0065] In one example, each sub - test department can be a concentric ring with a notch. The centers of each sub - test department and the center of the wafer 10 have the same projection on the plane where the wafer is located. Different sub - test departments are sequentially connected by test lines 23. Among them, the innermost sub - test department, the sub - test department with the smallest distance from the center of the wafer 10 is connected to a test port 21, and the outermost sub - test department, the sub - test department with the largest distance from the center of the wafer 10 is connected to another test port 21.

[0066] In an exemplary embodiment, please continue to refer to Figure 3 , at least two sub - test departments include a first sub - test ring and a second sub - test ring arranged concentrically. The centers of the first sub - test ring and the second sub - test ring are the center of the wafer; among them, the distance between the first sub - test ring and the wafer is between two - fifths and three - fifths of the wafer radius; the distance between the second sub - test ring and the wafer is between seven - tenths and nine - tenths of the wafer radius.

[0067] Exemplarily, both the first sub - test ring and the second sub - test ring respectively include three feature lines 22 and four test lines 23, and the first sub - test ring and the second sub - test ring are connected by test lines 23. Among them, the first sub - test ring has a first feature line 22 - 1, a second feature line 22 - 2, and a third feature line 22 - 3, and the second sub - test ring has a fourth feature line 22 - 4, a fifth feature line 22 - 5, and a sixth feature line 22 - 6. The test port 21 connected to the first sub - test ring is used to connect to the transmitting / receiving probe of the time - domain reflectometry device, and the test port 21 connected to the second sub - test ring is used to connect to the ground probe of the time - domain reflectometry device; or, the test port 21 connected to the first sub - test ring is used to connect to the ground probe of the time - domain reflectometry device, and the test port 21 connected to the second sub - test ring is used to connect to the transmitting / receiving probe of the time - domain reflectometry device.

[0068] In an exemplary embodiment, the present application provides a test wafer. The test wafer includes a wafer and the test structure of the wafer in any of the above - mentioned embodiments. At the same time, please refer to Figure 4 , the present application also provides a preparation method for a test wafer. The preparation method for a test wafer includes steps S401 to S403.

[0069] S401: Provide a wafer.

[0070] S402: Form an adhesion layer on the first side of the wafer using a mask.

[0071] Among them, the mask includes a test section pattern and two test port patterns located at both ends of the test section. The test section pattern further includes at least one feature line pattern and at least two test line patterns. The first side and the second side of the wafer 10 are opposite sides, and the second side is the side of the wafer to be thinned. The adhesion layer 201 includes, but is not limited to, chromium (Cr) and titanium (Ti). The thickness of the adhesion layer 201 can be between 30 nm and 1000 nm to provide the adhesion, conductivity, and corrosion resistance required for the test structure 20.

[0072] S403: Form a conductive layer on the side of the adhesion layer away from the wafer using a mask to form a test structure.

[0073] Since the mask includes a test section pattern and two test port patterns located at both ends of the test section, the prepared test structure has a test section corresponding to the pattern on the mask and two test ports 21 located at both ends of the test section. The test section includes at least one feature line 22 and at least two test lines 23. Each test line 23 is connected end to end through the feature line 22; the width of the feature line 22 is different from the width of the test line 23; each test port 21 is used to connect to a time domain reflectometry device, and is used to receive the test signal emitted by the time domain reflectometry device and receive the reflected signal formed after the test signal is reflected by the feature line. The test signal and the reflected signal are jointly used to determine the electrical parameters of the feature line. Among them, the material of the conductive layer 202 includes, but is not limited to, one or more of (Au), silver (Ag), and copper (Cu). The thickness of the conductive layer 202 can be between 50 µm and 2000 µm to provide the required conductivity and solderability.

[0074] In an exemplary embodiment, please refer to Figure 5 , the present application provides a wafer thinning test method, which is applied to the test wafer in the above embodiment. The wafer thinning test method includes steps S501 to S503.

[0075] S501: Obtain the initial electrical parameters of the test structure on the test wafer.

[0076] In an example, please refer to Figure 3, the test section includes a first sub-test loop and a second sub-test loop that are connected in sequence and concentrically arranged. The first sub-test loop has a first characteristic line 22-1, a second characteristic line 22-2, and a third characteristic line 22-3. The second sub-test loop has a fourth characteristic line 22-4, a fifth characteristic line 22-5, and a sixth characteristic line 22-6. The test port 21 connected to the first sub-test loop is used to connect to the transmit / receive probe of the time domain reflectometry device, and the test port 21 connected to the second sub-test loop is used to connect to the ground probe of the time domain reflectometry device. This example and the following examples all use Figure 3 The test structure shown is used as an example for illustration. Before the wafer thinning starts, connect the transmit / receive probe of the time domain reflectometry device to the test port 21 connected to the first sub-test loop, and connect the ground probe of the time domain reflectometry device to the test port 21 connected to the second sub-test loop, thereby forming a test loop.

[0077] Next, turn on the time domain reflectometry device. The transmit / receive probe sends a test signal to the test structure 20, and at the same time receives the reflected signal of the test structure through the transmit / receive probe. Since the width of the characteristic line 22 is narrower than that of the test line 23, its impedance is larger, which causes the waveform reflected by the characteristic line 22 to present a peak. Also, due to the different positions of the characteristic lines 22, the transmission times of the reflected waves of the characteristic lines 22 are not the same, thus realizing the mapping relationship between different peaks on the reflected signal and the characteristic lines 22.

[0078] S502: Obtain the test electrical parameters of the test structure after thinning the second side of the test wafer.

[0079] After obtaining the reflected signal before wafer thinning, the reflected signal before wafer thinning can be saved. At the same time, disconnect the connection between the test structure 20 and the time domain reflectometry device, and thin the second side of the test wafer. After the thinning process is completed, the transmit / receive probe of the time domain reflectometry device can be connected to the test port 21 connected to the first sub-test loop again, and the ground probe of the time domain reflectometry device can be connected to the test port 21 connected to the second sub-test loop to form a test loop. Then, turn on the time domain reflectometry device. The transmit / receive probe sends the same test signal to the test structure 20, and at the same time receives the reflected signal of the test structure through the transmit / receive probe.

[0080] S503: Determine the thinning test result of the test wafer according to the initial electrical parameters and the test electrical parameters.

[0081] It can be understood that during the wafer thinning process, if the wafer breaks, the test structure attached to the wafer will also have an open circuit, which is manifested as a sharp peak with an increased impedance in the waveform of the reflected signal. Therefore, by comparing the waveforms of the reflected signals before and after wafer thinning, it can be determined whether the wafer has broken during the thinning process.

[0082] In an exemplary embodiment, the thinning process includes a mechanical thinning process, and the test electrical parameters include mechanical test electrical parameters. Refer to Figure 6 , step S502, obtaining the test electrical parameters of the test structure after thinning the second side of the test wafer, including steps S601 to S603.

[0083] S601: Form a first protective layer on the side of the test structure away from the test wafer.

[0084] Before thinning the test wafer, a first protective layer can be formed on the side of the test structure away from the test wafer to prevent the test structure 20 from being open-circuited due to reasons other than wafer fracture during the mechanical thinning process of the wafer. In one example, the material of the first protective layer can be polyimide, polyethylene, acrylic polymer, polyester polymer, epoxy, polyurethane, etc.

[0085] S602: Perform a mechanical thinning process on the second side of the test wafer.

[0086] In this embodiment, the sandpaper used for the mechanical thinning process can be between 600 and 4000 mesh, the grinding feed rate can be between 0.05 mm / min and 1 mm / min each time, the polishing particles used can be diamond, alumina, silicon carbide particles, etc., and the particle size can be between 0.5 μm and 5 μm. The relative movement mode between the sandpaper and the wafer during the mechanical thinning process is completed by an automatic or semi-automatic grinding machine, where the grinding pressure range is 0.2 MPa to 10 MPa and the grinding speed is 200 rpm to 3000 rpm to ensure that the wafer reaches the predetermined final thickness.

[0087] S603: Remove the first protective layer and obtain the mechanical test electrical parameters after mechanically thinning the test wafer.

[0088] After the mechanical thinning process is completed, the first protective layer on the surface of the test structure can be removed. The transmitting / receiving probe of the time domain reflectometry device and the test port 21 connected to the first sub-test loop can be connected again, and the grounding probe of the time domain reflectometry device and the test port 21 connected to the second sub-test loop can be connected to form a test loop. Then, turn on the time domain reflectometry device, the transmitting / receiving probe sends the same test signal to the test structure 20, and at the same time, the reflected signal of the test structure is received through the transmitting / receiving probe, that is, the mechanical test electrical parameters.

[0089] In an exemplary embodiment, the thinning process includes a chemical polishing process, and the test electrical parameters include chemical test electrical parameters. Refer to Figure 7, Step S502, obtaining the test electrical parameters of the test structure after thinning the second side of the test wafer, including steps S701 to S703.

[0090] S701: Form a second protective layer on the side of the test structure away from the test wafer.

[0091] Before thinning the test wafer, a second protective layer can be formed on the side of the test structure away from the test wafer to prevent the test structure 20 from being open-circuited due to reasons other than wafer fracture during the chemical mechanical polishing process of the wafer. In one example, the material of the second protective layer can be polyimide, polyethylene, acrylic polymer, polyester polymer, epoxy, polyurethane, etc.

[0092] S702: Perform chemical mechanical polishing on the second side of the test wafer.

[0093] Specifically, the chemical mechanical polishing treatment is chemical mechanical polishing. The polishing abrasive grains of the chemical mechanical polishing liquid used in the chemical mechanical polishing treatment are silica, alumina, cerium oxide, etc., and their particle size distribution is between 20 nm and 100 nm, which is used to provide mechanical polishing effect. The solvent of the chemical mechanical polishing liquid is water or organic solvents such as ethanol, acetone, ethyl acetate, etc., and the pH value of the chemical mechanical polishing liquid is between 9 - 12. The process of the chemical mechanical polishing treatment includes setting the rotation speed of the polishing machine, where the rotation speed of the carrier plate is 30 rpm to 3000 rpm, and the rotation speed of the polishing head is 30 rpm to 200 rpm to generate relative movement and achieve uniform polishing. The process of the chemical mechanical polishing treatment also includes setting the polishing pressure, that is, the pressure applied by the polishing head to the wafer is 5 kPa to 5000 kPa to control the polishing rate and the uniformity of the wafer surface. The polishing time can be between 5 min and 60 min according to the polishing requirements and the wafer material.

[0094] S703: Remove the second protective layer and obtain the chemical test electrical parameters after chemical mechanical polishing of the test wafer.

[0095] After the chemical mechanical polishing treatment is completed, the second protective layer on the surface of the test structure can be removed. The transmitting / receiving probe of the time domain reflectometry device can be connected to the test port 21 connected to the first sub-test loop again, and the grounding probe of the time domain reflectometry device can be connected to the test port 21 connected to the second sub-test loop to form a test circuit. Then, turn on the time domain reflectometry device. The transmitting / receiving probe sends the same test signal to the test structure 20, and at the same time, receives the reflected signal of the test structure through the transmitting / receiving probe, that is, the chemical test electrical parameters.

[0096] In an exemplary embodiment, please refer to Figure 8The test structure includes a first sub-test loop and a second sub-test loop; the wafer thinning test method further includes step S801 and step S802.

[0097] S801: When the thinning process result shows that the first sub-test loop fails, adjust the first working parameter of the thinning process.

[0098] As described in the above embodiments, the reflected signal includes the reflected waves of each characteristic line. Due to the different positions of each characteristic line 22, the transmission times of the reflected waves of each characteristic line 22 are also different. The transmission time of the reflected wave of the characteristic line 22 closer to the transmitting / receiving probe is shorter. If the test structure fails, the shape of the reflected wave of the characteristic line after the failure point on the test structure will be different from the shape of the reflected wave of the corresponding characteristic line before wafer thinning. Exemplarily, if a break occurs in the test structure between the third characteristic line 22-3 and the fourth characteristic line 22-4, the reflected waves of the fourth characteristic line 22-4, the fifth characteristic line 22-5, and the sixth characteristic line 22-6 will be different from the shapes of the reflected waves of the fourth characteristic line 22-4, the fifth characteristic line 22-5, and the sixth characteristic line 22-6 before wafer thinning. Therefore, the specific failure position of the wafer can be determined by comparing the waveforms of the reflected signals before and after wafer thinning.

[0099] If the first sub-test loop fails after the wafer is mechanically thinned, the first working parameters such as the grinding pressure of the grinding machine, the mesh number of the grinding sandpaper, and the grinding feed rate can be adjusted; if the first sub-test loop fails after the wafer is chemically polished, the first working parameters such as the polishing pressure of the polishing machine can be adjusted.

[0100] S802: When the thinning process result shows that the second sub-test loop fails, adjust the second working parameter of the thinning process.

[0101] If the second sub-test loop fails after the wafer is mechanically thinned, the second working parameters such as the grinding speed of the grinding machine, the type of polishing particles, and the particle diameter can be adjusted; if the second sub-test loop fails after the wafer is chemically polished, the second working parameters such as the type of abrasive grains, the abrasive grain size of the chemical mechanical polishing liquid, the polishing speed of the polishing machine, and the polishing time can be adjusted.

[0102] It should be understood that although Figures 4 - 8 the steps in the flowchart of Figures 4 - 8At least a part of the steps therein may include multiple steps or multiple stages, and these steps or stages are not necessarily executed and completed at the same moment, but can be executed at different moments. The execution order of these steps or stages is not necessarily sequential, but can be executed alternately or in turns with at least a part of other steps or steps or stages in other steps.

[0103] In a detailed embodiment, refer to Figure 3 , taking the test section including a first sub-test ring and a second sub-test ring that are sequentially connected and concentrically arranged as an example. The first sub-test ring has a first characteristic line 22-1, a second characteristic line 22-2, and a third characteristic line 22-3. The second sub-test ring has a fourth characteristic line 22-4, a fifth characteristic line 22-5, and a sixth characteristic line 22-6. The test port 21 connected to the first sub-test ring is used to connect to the transmit / receive probe of the time domain reflectometry device, and the test port 21 connected to the second sub-test ring is used to connect to the ground probe of the time domain reflectometry device.

[0104] First, use a pre-prepared mask and deposit a 120-nm chromium (Cr) adhesion layer uniformly on the first side of the wafer by chemical vapor deposition technology; then, on top of the adhesion layer, deposit a conductive layer composed of gold (Au) uniformly by electroplating deposition technology, and the thickness of the conductive layer is 300 µm to provide the required conductivity and solderability. The final formed test structure is shaped as Figure 3 shown, where the test line width is 180 µm, the wafer diameter is 20 mm, the diameter of the first sub-test ring is 0.5 of the wafer diameter, and the diameter of the second sub-test ring is 0.8 of the wafer diameter; there are three characteristic lines on each of the first sub-test ring and the second sub-test ring, and the line width of the characteristic lines is 100 µm.

[0105] After that, connect the transmit / receive probe of the time domain reflectometry device to the test port 21 connected to the first sub-test ring, and connect the ground probe of the time domain reflectometry device to the test port 21 connected to the second sub-test ring, and then obtain the waveform of the reflected signal as shown in Figure 9 as the control group for subsequent tests. The waveform of the reflected signal will clearly reflect the condition of each characteristic line. By observing the waveform of each characteristic line, the information of each characteristic line can be obtained. In Figure 9 , a1 is the reflected wave of the first characteristic line 22-1, b1 is the reflected wave of the second characteristic line 22-2, c1 is the reflected wave of the third characteristic line 22-3, d1 is the reflected wave of the fourth characteristic line 22-4, e1 is the reflected wave of the fifth characteristic line 22-5, and f1 is the reflected wave of the sixth characteristic line 22-6.

[0106] After that, a first protective layer of polyimide is used to protect the test structure. Then, mechanical grinding is performed successively with 1200-mesh and 2000-mesh sandpapers, controlling the chip grinding amount to be 0.05 mm each time. The polishing particles are diamond particles with a particle size of 2 μm. The grinding pressure range is adjusted to 1 MPa and the grinding speed is 200 rpm. After the mechanical thinning process is completed, the first protective layer is removed, and the thinned wafer is detected again. The transmitting / receiving probe of the time-domain reflectometry device is connected to the test port 21 connected to the first sub-test loop, and the grounding probe of the time-domain reflectometry device is connected to the test port 21 connected to the second sub-test loop. Then, as shown in Figure 10 the waveform of the reflected signal is obtained. In Figure 10 , a2 is the reflected wave of the first characteristic line 22-1, b2 is the reflected wave of the second characteristic line 22-2, c2 is the reflected wave of the third characteristic line 22-3, d2 is the reflected wave of the fourth characteristic line 22-4, e2 is the reflected wave of the fifth characteristic line 22-5, and f2 is the reflected wave of the sixth characteristic line 22-6. By comparing Figure 9 and Figure 10 , it can be seen that the main failure point is near the position of the first characteristic line 22-1, indicating that the possible failure reason may be excessive pressure applied during mechanical grinding or too large a diameter of the polishing particles. Take the same batch of the same wafers to remake the test structure, repeat the above steps, and adjust the mechanical grinding pressure to 0.5 MPa and the grinding particle diameter to 1 μm. Test again to obtain the waveform of the reflected signal after wafer thinning, and there is no obvious abnormality.

[0107] Continue to carry out the chemical mechanical polishing process. Use a second protective layer of polyimide organic film to protect the test structure on the first side of the wafer, and then perform chemical mechanical polishing. The abrasive grains of the polishing liquid are silica with a particle size distribution between 20 nm and 100 nm. The solvent of the chemical polishing liquid is acetone and the pH value of the chemical mechanical polishing liquid is adjusted to around 10. Set the rotation speed of the polishing machine carrier plate to 2000 rpm and the rotation speed of the polishing head to 100 rpm to generate relative movement and achieve uniform polishing. The pressure applied by the polishing head to the wafer is 3000 KPa, and the polishing time is set to 30 min. After the chemical mechanical polishing process is completed, remove the second protective layer, and then connect the transmitting / receiving probe of the time-domain reflectometry device to the test port 21 connected to the first sub-test loop, and connect the grounding probe of the time-domain reflectometry device to the test port 21 connected to the second sub-test loop. Then, as shown in Figure 11 the waveform of the reflected signal is obtained. In Figure 11 , a3 is the reflected wave of the first characteristic line 22-1, b3 is the reflected wave of the second characteristic line 22-2, c3 is the reflected wave of the third characteristic line 22-3, d3 is the reflected wave of the fourth characteristic line 22-4, e3 is the reflected wave of the fifth characteristic line 22-5, and f3 is the reflected wave of the sixth characteristic line 22-6. CompareFigure 9 and Figure 11 It can be seen that the main failure point is near the position of the fourth characteristic line 22-4, indicating that the possible failure reason may be that the rotational speed of chemical mechanical polishing is too high or the polishing time is too long. Take the same batch of the same wafers to remake the test structure, repeat the above steps, set the rotational speed of the carrier plate to 1000 rpm, the rotational speed of the polishing head to 100 rpm, and the polishing time to 20 min. Test the waveform of the reflected signal after wafer thinning again, and there is no obvious abnormality. Thus, the iteration of the wafer thinning process parameters is realized, and the yield of wafer thinning is improved.

[0108] The wafer thinning test method of the present application can detect the position of defects generated during wafer thinning, and take repair and correction measures in a timely manner by adjusting the working parameters of the grinding machine or polishing machine, and evaluate the reliability in the semiconductor production process. During the detection process, the reflected signal can be detected online. When a fault occurs, the position and failure mode of the fault can be determined in a timely manner. Compared with the traditional electronic material verification and failure analysis, it can greatly reduce the experimental time, find the risk points of wafer devices, and support the reliability design of electronic components. This invention has application requirements for product development units, third-party evaluation agencies, and product application units, and can generate huge economic value.

[0109] In an exemplary embodiment, the present application further provides a wafer thinning test device, which includes: a first acquisition module, a second acquisition module, and a first determination module. Among them,

[0110] The first acquisition module is used to acquire the initial electrical parameters of the test structure on the test wafer.

[0111] The second acquisition module is used to acquire the test electrical parameters of the test structure after thinning the second side of the test wafer.

[0112] The first determination module is used to determine the thinning test result of the test wafer according to the initial electrical parameters and the test electrical parameters.

[0113] In an exemplary embodiment, the thinning process includes a mechanical thinning process, and the test electrical parameters include mechanical test electrical parameters; among them, the second acquisition module includes: a first protection sub-module, a first thinning sub-module, and a first test sub-module. Among them,

[0114] The first protection sub-module is used to form a first protective layer on the side of the test structure away from the test wafer.

[0115] The first thinning sub-module is used to perform a mechanical thinning process on the second side of the test wafer.

[0116] The first test sub-module removes the first protective layer and obtains the mechanical test electrical parameters after the test wafer is mechanically thinned.

[0117] In an exemplary embodiment, the thinning process includes a chemical polishing process, and the test electrical parameters include chemical test electrical parameters; wherein, the second acquisition module includes a second protection sub-module, a first polishing sub-module, and a second test sub-module. Among them,

[0118] The second protection sub-module is used to form a second protective layer on the side of the test structure away from the test wafer.

[0119] The first polishing sub-module is used to perform a chemical polishing process on the second side of the test wafer.

[0120] The second test sub-module is used to remove the second protective layer and obtain the chemical test electrical parameters after the test wafer is chemically polished.

[0121] In an exemplary embodiment, the test structure includes a first sub-test ring and a second sub-test ring; the wafer thinning test device further includes a first regulation module and a second regulation module.

[0122] The first regulation module is used to adjust the first working parameter of the thinning process when the thinning result of the first sub-test ring fails;

[0123] The second regulation module is used to adjust the second working parameter of the thinning process when the thinning result of the second sub-test ring fails;

[0124] Among them, the first working parameter is different from the second working parameter.

[0125] For the specific limitations of the wafer thinning test device, reference can be made to the limitations of the wafer thinning test method in the above text, which will not be elaborated here. Each module in the above wafer thinning test device can be implemented in whole or in part by software, hardware, and their combination. The above modules can be embedded in or independent of the processor in the computer device in the form of hardware, or stored in the memory of the computer device in the form of software, so that the processor can call and execute the operations corresponding to the above modules. It should be noted that the division of modules in the embodiments of the present application is illustrative, only a logical function division, and there may be other division methods in actual implementation.

[0126] In an embodiment, a computer device is provided, including a memory and a processor, and a computer program is stored in the memory. When the processor executes the computer program, the steps of the wafer thinning test method in any one of the above embodiments are implemented.

[0127] Those of ordinary skill in the art can understand that all or part of the processes in the methods of the above embodiments can be completed by instructing relevant hardware through a computer program. The computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above methods. Among them, any reference to a memory, storage, database, or other medium used in the embodiments provided in the present application can include at least one of non-volatile and volatile memories. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, or optical memory, etc. Volatile memory can include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM), etc.

[0128] In the description of this specification, the description referring to terms such as "some embodiments", "other embodiments", "ideal embodiments", etc. means that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic description of the above terms does not necessarily refer to the same embodiment or example.

[0129] The technical features of the above embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered to be within the scope described in this specification.

[0130] The above-described embodiments merely represent several implementation manners of the present application. The description is relatively specific and detailed, but it should not be construed as a limitation on the scope of the invention patent. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present application, several modifications and improvements can still be made, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application shall be subject to the appended claims.

Claims

1. A test structure for a wafer, characterized in that, Comprising: A test section located on the first side of the wafer, and two test ports located at both ends of the test section; wherein, The test section includes at least one characteristic line and at least two test lines, and each of the test lines is connected end to end through the characteristic line; the width of the characteristic line is different from the width of the test line; Each of the test ports is used to connect to a time domain reflectometry device, and is used to receive a test signal emitted by the time domain reflectometry device, and receive a reflected signal formed after the test signal is reflected by the characteristic line; wherein, the test signal and the reflected signal are jointly used to determine the electrical parameters of the characteristic line.

2. The test structure of the wafer according to claim 1, wherein The test structure includes: An adhesion layer located on the first side of the wafer, the first side and the second side of the wafer are opposite sides, and the second side is the side of the wafer to be thinned; A conductive layer located on the side of the adhesion layer away from the wafer.

3. The test structure of the wafer according to claim 1, wherein The test section includes at least two sub-test sections connected in sequence, and each of the sub-test sections respectively includes at least one of the characteristic lines and at least two test lines, and any two adjacent sub-test sections are connected through the test lines, and the distances between the characteristic lines of different sub-test sections and the center of the wafer are different; wherein, The first end of the first sub-test section is connected to one of the test ports, and the second end of the last sub-test section is connected to the other test port.

4. The test structure of a wafer according to claim 3, characterized in that, The at least two sub-test sections include a first sub-test ring and a second sub-test ring arranged concentrically, and the centers of the first sub-test ring and the second sub-test ring are the center of the wafer; wherein, the distance between the first sub-test ring and the wafer is between two-fifths and three-fifths of the radius of the wafer; the distance between the second sub-test ring and the wafer is between seven-tenths and nine-tenths of the radius of the wafer.

5. A test wafer, characterized in that, The test wafer includes a wafer and a test structure of the wafer as described in any one of claims 1-4.

6. A method for preparing a test wafer, characterized in that, The method includes: Providing a wafer; Forming an adhesion layer on the first side of the wafer by using a mask; wherein, the mask includes a test section pattern and two test port patterns located at both ends of the test section, the first side and the second side of the wafer are opposite sides, and the second side is the side of the wafer to be thinned; Forming a conductive layer on the side of the adhesion layer away from the wafer by using a mask to form a test structure; Wherein, the test structure includes a test section and two test ports located at both ends of the test section, the test section includes at least one characteristic line and at least two test lines, and each of the test lines is connected end to end through the characteristic line; the width of the characteristic line is different from the width of the test line; each of the test ports is used to connect to a time domain reflectometry device, and is used to receive a test signal emitted by the time domain reflectometry device, and receive a reflected signal formed after the test signal is reflected by the characteristic line; the test signal and the reflected signal are jointly used to determine the electrical parameters of the characteristic line.

7. A thinning test method for a wafer, characterized in that, Applied to the test wafer as described in claim 5, the method includes: Obtaining the initial electrical parameters of the test structure on the test wafer; Obtain the test electrical parameters of the test structure after the second side of the test wafer is thinned; Determine the thinning test result of the test wafer according to the initial electrical parameters and the test electrical parameters.

8. The thinning test method for a wafer according to claim 7, wherein The thinning process includes a mechanical thinning process, and the test electrical parameters include mechanical test electrical parameters; wherein, obtaining the test electrical parameters of the test structure after the second side of the test wafer is thinned includes: Form a first protective layer on the side of the test structure away from the test wafer; Perform a mechanical thinning process on the second side of the test wafer; Remove the first protective layer and obtain the mechanical test electrical parameters after the test wafer is mechanically thinned.

9. The thinning test method for a wafer according to claim 7, wherein The thinning process includes a chemical polishing process, and the test electrical parameters include chemical test electrical parameters; wherein, obtaining the test electrical parameters of the test structure after the second side of the test wafer is thinned includes: Form a second protective layer on the side of the test structure away from the test wafer; Perform a chemical polishing process on the second side of the test wafer; Remove the second protective layer and obtain the chemical test electrical parameters after the test wafer is chemically polished.

10. The thinning test method for a wafer according to any one of claims 7 to 9, characterized in that, The test structure includes a first sub-test ring and a second sub-test ring; the method further includes: Adjust the first working parameter of the thinning process when the thinning process result is that the first sub-test ring fails; Adjust the second working parameter of the thinning process when the thinning process result is that the second sub-test ring fails; Wherein, the first working parameter is different from the second working parameter.

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