Integrated circuit package with packaged resistor

Abstract

The invention relates to an integrated circuit package with a packaged resistor. An integrated circuit (IC) package (800) includes: a package resistor (802) having a first terminal and a second terminal; and an IC (816) separate from and coupled to the packaged resistor (802). The IC (816) includes sensing circuitry (866) having a first terminal (868) and a second terminal (869). The first terminal (868) of the sensing circuitry (866) is coupled to the first terminal of the packaged resistor (802). The second terminal (869) of the sensing circuitry (866) is coupled to the second terminal of the packaged resistor (802).

Description

[0001] Cross - Reference to Related Applications

[0002] This application claims priority to U.S. Provisional Application No. 63 / 626,217, filed on January 29, 2024, titled "ANALOG OUTPUT CURRENT SENSOR WITH INTEGRATED SHUNT RESISTOR AND DYNAMIC TEMPERATURE DRIVER CORRECTION", Attorney Docket No. T104079US01, which is hereby incorporated by reference in its entirety. Technical Field

[0003] This application generally relates to integrated circuit packages, and more particularly, to an integrated circuit package having a packaged resistor. Background Art

[0004] Many sensing circuits for sensing current or voltage are subject to errors or system limitations such as aging, stress-induced errors. Thus, the initial design or calibration of such sensing circuits ultimately results in less accurate results and may even exceed the target tolerance. Example sensing circuits can include a sensing resistor and an integrated circuit (IC) having a sense amplifier. When the IC and the sensing resistor are mounted to a printed circuit board (PCB), the PCB traces between the sensing resistor and the IC can cause additional errors or limitations. Summary of the Invention

[0005] In an example, an integrated circuit (IC) package includes: a packaged resistor having a first terminal and a second terminal; and an IC separated from and coupled to the packaged resistor. The IC includes a sensing circuit system having a first terminal and a second terminal. The first terminal of the sensing circuit system is coupled to the first terminal of the packaged resistor. The second terminal of the sensing circuit system is coupled to the second terminal of the packaged resistor.

[0006] In another example, an IC package includes: a lead frame that includes an integrated lead frame resistor having a first terminal and a second terminal; and an IC on the lead frame resistor. The IC has a first terminal coupled to the first terminal of the lead frame resistor and a second terminal coupled to the second terminal of the lead frame resistor. In yet another example, an IC package includes: a packaged resistor having a first terminal and a second terminal; and an IC. The IC includes: an amplifier; and a calibration controller. The amplifier has a first terminal coupled to the first terminal of the packaged resistor and a second terminal coupled to the second terminal of the packaged resistor. The amplifier includes an adjustable circuitry configured to adjust a gain of the amplifier. The adjustable circuitry has an input. The calibration controller includes a gain control circuitry having an output coupled to the input of the adjustable circuitry, the gain control circuitry being configured to provide a calibration setting at the output in response to a digital temperature code. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 is a diagram showing an example system.

[0008] Figure 2 is a diagram showing another example system.

[0009] Figure 3 is a top view of a printed circuit board having an example integrated circuit (IC) package.

[0010] Figure 4A is a perspective top view of an example IC package.

[0011] Figure 4B is Figure 4A a perspective bottom view of an example IC package of

[0012] Figure 5A is Figure 4A and 4B a first cross-sectional view of an example IC package of

[0013] Figure 5B is Figure 4A and 4B a second cross-sectional view of an example IC package of

[0014] Figure 5C is a first cross-sectional view of another example IC package.

[0015] Figure 5D is Figure 5C a second cross-sectional view of an example IC package of

[0016] Figure 6A is Figure 4A and 4B a bottom side view of an exemplary IC package.

[0017] Figure 6B is Figure 4A and 4B an internal view of an exemplary IC package.

[0018] Figure 6C is an internal view of another exemplary IC package.

[0019] Figure 6D is an internal view of another exemplary IC package.

[0020] Figure 7A is an exemplary graph showing the resistance of an exemplary lead frame resistor varying with temperature.

[0021] Figure 7B is an exemplary graph showing the system gain of an exemplary sensing circuit system varying with temperature.

[0022] Figure 7C is another exemplary graph showing the system gain of an exemplary sensing circuit system varying with temperature.

[0023] Figure 8 is a diagram of an exemplary IC package.

[0024] Figure 9 is a diagram of an exemplary sensing circuit calibration technique.

[0025] Figure 10 is a diagram of another exemplary IC package. DETAILED DESCRIPTION

[0026] The same reference numerals or other reference indicators are used in the drawings to denote the same or similar features. These features may be the same or similar in function and / or structure.

[0027] Figure 1 is a diagram showing an exemplary system 100. In different instances, system 100 is part of an overcurrent protection system, a battery management system, a power telemetry system, a motor or solenoid control system, or other system. As shown, system 100 includes an electrical device 102, an integrated circuit (IC) package 110, and a controller 132. In different instances, the electrical device 102 can be a battery, a motor, a solenoid, a telemetry device, a power conditioning device, or other electrical device. In Figure 1 the instance of, the electrical device 102 has a first terminal 104, a second terminal 106, and a third terminal 108. The IC package 110 has a first terminal 112, a second terminal 114, and a third terminal 116. The controller 132 has a first terminal 134 and a second terminal 136.

[0028] In Figure 1 an example of, the IC package 110 includes a package resistor 118 and a sensing circuitry 124. The package resistor 118 has a first terminal 120 and a second terminal 122. The sensing circuitry 124 has a first terminal 126, a second terminal 128, and a third terminal 130. In some examples, the sensing circuitry 124 is part of the IC. In some examples, the package resistor 118 is a lead frame resistor separated from the IC.

[0029] As used herein, a "lead frame" refers to the support and connection structure of an IC. For example, the support and connection structure can include a support platform for the IC, bond pads for connecting to corresponding bond pads of the IC, and external terminals for each corresponding bond pad. The external terminals are used to couple the bond pads of the lead frame and the corresponding bond pads of the IC to an external circuitry. In other examples, the lead frame omits at least some of the bond pads such that the bond pads of the IC are directly coupled to the external terminals via bond wires. As an alternative, the lead frame can include some bond pads for some of the external terminals but not all of the external terminals. The IC bond pads or the lead frame bond pads are sometimes referred to herein as "internal terminals" or simply "terminals".

[0030] As used herein, a "lead frame resistor" refers to a resistive material that is part of or integrated with a lead frame. In some examples, the lead frame resistor is a resistance between at least two spaced-apart connection points or bond pads of the lead frame. The resistive material can be integrated with the support platform of the lead frame or separated from the support platform and / or the external terminals of the lead frame.

[0031] As used herein, a "package resistor" is a lead frame resistor, an on-chip resistor, or an off-chip resistor that is embedded within the encapsulation material of the IC package 110 and separated from the IC and the lead frame. In different examples, the materials, sizes, and locations of the off-chip resistors vary. The overall volume of the encapsulation of the IC package can be adjusted as needed to accommodate the off-chip resistor.

[0032] In Figure 1 an example of, a first terminal 104 of the electrical device 102 is coupled to a first terminal 112 of the IC package 110. A second terminal 106 of the electrical device 102 is coupled to a second terminal 114 of the IC package 110. A third terminal 116 of the IC package 110 is coupled to a first terminal 134 of the controller 132. A second terminal 136 of the controller 132 is coupled to a third terminal 108 of the electrical device 102.

[0033] The first terminal 112 of the IC package 110 is coupled to the first terminal 120 of the package resistor 118 and the first terminal 126 of the sensing circuitry 124. The second terminal 114 of the IC package 110 is coupled to the second terminal 122 of the package resistor 118 and the second terminal 128 of the sensing circuitry 124. The third terminal 130 of the sensing circuitry 124 is coupled to the third terminal 116 of the IC package 110.

[0034] In some examples, the electrical device 102 is configured to: receive a control signal CS1 at the third terminal 108; and perform an operation in response to the control signal CS1. During operation of the electrical device 102, a current ISNS flows from the first terminal 104 and through the package resistor 118. In Figure 1 examples, the current ISNS flows back to the second terminal 106 of the electrical device 102. In other examples, the current ISNS flows to a ground terminal. In either case, the current ISNS is monitored by the sensing circuitry 124. In some examples, the sensing circuitry 124 monitors the current ISNS by monitoring the voltage drop across the package resistor 118. In such examples, the sensing circuitry 124 is configured to: receive a first voltage level at the first terminal 126; receive a second voltage level at the second terminal 128; and provide a current sense signal S1_ISNS at the third terminal 130 in response to the first voltage level and the second voltage level. The controller 132 is configured to: receive the sense signal S1_ISNS at the first terminal 134; and adjust the control signal CS1 in response to the current sense signal S1_ISNS. In some examples, the process of using the package resistor 118 and the sensing circuitry 124 to monitor the current ISNS, provide the current sense signal S1_ISNS to the controller 132, and adjust the control signal CS1 of the electrical device 102 is repeated to provide continuous overcurrent protection, continuous battery management, continuous power telemetry, continuous motor control, continuous solenoid control, continuous power regulation, or other system operations.

[0035] Using the IC package 110 and the package resistor 118 avoids an external sense resistor, which in some applications can cause resistor selection, procurement, and printed circuit board (PCB) layout issues. In some examples, the sensing circuitry 124 can include adjustable components (also referred to as an adjustable circuit system) and a calibration controller, where the calibration operation accounts for errors introduced by the package resistor 118. Such errors can be due to resistor value drift of the package resistor 118 with temperature.

[0036] Figure 2 is a diagram illustrating another example system 200. In Figure 2In an example, system 200 includes motor 250, IC package 110A, and controller 232. Motor 250 is an example of the electrical device 102 in Figure 1 . In some examples, motor 250 is a three-phase motor. IC package 110A is an example of the IC package 110 in Figure 1 . Controller 232 is an example of the controller 132 in Figure 1 .

[0037] In Figure 2 's example, IC package 110A has the first terminal 112, the second terminal 114, and the third terminal 116 described in Figure 1 . As shown, IC package 110A includes resistor RS1 and sensing circuitry 124. Resistor RS1 is an example of the packaged resistor 118 in Figure 1 .

[0038] In Figure 2 's example, controller 232 has a first terminal 234, second terminals 236A to 236C, a third terminal 238, and a fourth terminal 240. The first terminal 234 is an example of the first terminal 134 in Figure 1 . The second terminals 236A to 236C are corresponding examples of the second terminal 136 in Figure 1 . The third terminal 238 is a power supply terminal that can be included together with the controller 132 in Figure 1 . The fourth terminal 240 is a ground terminal that can be included together with the controller 132 in Figure 1 .

[0039] In Figure 2In an example, the controller 232 includes switches S1 to S6 and control logic 251. Each of the switches S1 to S6 has a corresponding first terminal, a corresponding second terminal, and a corresponding control terminal. The control logic 251 has a first terminal 252, a second terminal 253, a third terminal 254, a fourth terminal 256, a fifth terminal 258, a sixth terminal 260, a seventh terminal 262, and an eighth terminal 264. The first terminal 252 of the control logic 251 is coupled to the first terminal 234 of the controller 232. The second terminal 253 of the control logic 251 receives a control signal CS_IN. In some examples, the control signal CS_IN may include motor speed, rotation direction, motor position, and / or other control parameters. The third terminal 254 of the control logic 251 is coupled to the control terminal of the switch S1. The fourth terminal 256 of the control logic 251 is coupled to the control terminal of the switch S2. The fifth terminal 258 of the control logic 251 is coupled to the control terminal of the switch S3. The sixth terminal 260 of the control logic 251 is coupled to the control terminal of the switch S4. The seventh terminal 262 of the control logic 251 is coupled to the control terminal of the switch S5. The eighth terminal 264 of the control logic 251 is coupled to the control terminal of the switch S6.

[0040] In Figure 2 an example, the first terminals of switches S1, S3, and S5 are coupled to the third terminal 238 of the controller 232. The second terminal of the switch S1 is coupled to the first terminal of the switch S2 and the second terminal 236A of the controller 232. The second terminal of the switch S3 is coupled to the first terminal of the switch S4 and the second terminal 236B of the controller 232. The second terminal of the switch S5 is coupled to the first terminal of the switch S6 and the second terminal 236C of the controller 232. The second terminals of switches S2, S4, and S6 are coupled to the fourth terminal 240 of the controller 232.

[0041] In Figure 2In an example, the controller 232 is configured to: receive a power supply voltage (VDD) at a third terminal 238; receive a current sense signal S1_ISNS; and provide current to second terminals 236A to 236C in response to the operation of VDD, S1_ISNS, CS_IN, and control logic 251. In some examples, the control logic 251 is configured to: receive S1_ISNS at a first terminal 252; receive CS_IN at a second terminal 253; and provide switch control signals CS_S1, CS_S2, CS_S3, CS_S4, CS_S5, and CS_S6 at third terminal 254, fourth terminal 256, fifth terminal 258, sixth terminal 260, seventh terminal 262, and eighth terminal 264 in response to S1_ISNS and CS_IN. In some examples, the control logic 251 is configured to: send pulse width modulation (PWM) signals to switches S1 to S6 to sequentially control the on / off states of the switches, thereby causing rotation of the motor 250. In some examples, the control logic 251 is configured to: monitor S1_ISNS and other sensor inputs; and change the frequency and / or duty cycle of the PWM signals to switches S1 to S6 to regulate the movement of the motor 250.

[0042] In Figure 2 an example, an IC package 110A provides a current sense signal S1_ISNS for current passing through RS1 and second terminal 236C. In some examples, there may be a second IC package for providing a second current sense signal S2_ISNS (not shown) for current passing through RS2 and second terminal 236B. Additionally, there may be a third IC package for providing a third current sense signal S3_ISNS (not shown) for current passing through RS3 and second terminal 236A. In such an example, the controller 232 and the control logic 251 may include additional terminals for receiving the second current sense signal S2_ISNS and the third current sense signal S3_ISNS. In such an example, the control logic 251 may be configured to: receive S1_ISNS at a first terminal 252; receive S2_ISNS; receive S3_ISNS; and provide switch control signals CS_S1, CS_S2, CS_S3, CS_S4, CS_S5, and CS_S6 at third terminal 254, fourth terminal 256, fifth terminal 258, sixth terminal 260, seventh terminal 262, and eighth terminal 264 in response to S1_ISNS, S2_ISNS, S3_ISNS, and CS_IN.

[0043] Using IC package 110A and resistor RS1 avoids an external sense resistor, which can pose resistor selection, procurement, and PCB layout issues. In some instances, the sense circuitry 124 of IC package 110A can include adjustable components and a calibration controller, where the calibration operation accounts for errors introduced by the package resistor 118. Such errors can be due to resistor value drift of the package resistor 118 caused by temperature and / or aging.

[0044] Figure 3 is a top view 300 of a PCB 302 with an example IC package 304. IC package 304 is Figure 1 the IC package 110 in Figure 2 or an instance of the IC package 110A in Figure 3 In an instance of, IC package 304 has a length X and a width Y. In different instances, the dimensions of IC package 304 can vary. Using IC package 304 avoids an external sense resistor on, for example, PCB 302, which reduces the layout size of the sense circuitry on PCB 302. The use of IC package 304 can also provide benefits such as eliminating resistor selection, simplifying PCB trace layout, and reducing sense errors due to the trace length between the resistor and the sense circuitry. Using a package resistor (e.g., Figure 1 the package resistor 118 in Figure 2 or the resistor RS1 in Figure 1 and 2 ), the current sense circuitry of IC package 304 (e.g.,

[0045] Figure 4A is a perspective top side view 400 of an example IC package 402. IC package 402 is Figure 1 the IC package 110 in Figure 2 or an instance of the IC package 110A in Figure 3 or the IC package 304 in Figure 4A In an instance of, various terminals 404 of IC package 402 are shown.

[0046] Figure 4B is Figure 4A a perspective bottom side view 410 of the example IC package 402. In the perspective bottom side view 410, more terminals 404 are shown. Additionally, an exposed portion of the lead frame 412 is shown. In different instances, the number of terminals 404, the size of the lead frame 412, and the amount of the lead frame 412 that is exposed can vary.

[0047] Figure 5A is Figure 4A and 4B A first cross-sectional view 500 of an exemplary IC package 402. In the first cross-sectional view 500, the lead frame layer 502, the IC 504, bond pads 508A to 508C, bond wires 506A to 506C, and the encapsulant 510 of the IC package 402 can be seen. The lead frame layer 502 includes a first lead frame portion 503A, a second lead frame portion 503B, and a third lead frame portion 503C. The first lead frame portion 503A has a bond pad, including bond pad 508A, and is separated from the second lead frame portion 503B in the first cross-sectional view 500. The second lead frame portion 503B also includes a bond pad, including bond pad 508B. The third lead frame portion 503C also includes a bond pad, including bond pad 508C, and is separated from the second lead frame portion 503B in the first cross-sectional view 500. As shown, the IC 504 has bond pads 507A, 507B, and 507C. The bond pad 507A of the IC 504 is coupled to the bond pad 508A of the first lead frame portion 503A through a corresponding bond wire 506A. The bond pad 507B of the IC 504 is coupled to the bond pad 508B of the second lead frame portion 503B through a corresponding bond wire 506B. The bond pad 507C of the IC 504 is coupled to the bond pad 508C of the third lead frame portion 503C through a corresponding bond wire 506C.

[0048] In different instances, the number and arrangement of the bond pads of the lead frame layer 502 can vary. Regardless of the number and arrangement of the bond pads of the lead frame layer 502, the encapsulant 510 is used to cover the bond pads of the lead frame layer 502, the bond pads of the IC 504 (not shown), and the bond wires coupling the bond pads of the lead frame layer 502 to the corresponding bond pads of the IC 504. In Figure 5A an instance, the second lead frame portion 503B can provide a support platform for the IC 504 and a lead frame resistor. In different instances, the width W of the second lead frame portion 503B can vary, which can change the current density and / or resistivity of the associated lead frame resistor.

[0049] Figure 5B is Figure 4A and 4B A second cross-sectional view 520 of an exemplary IC package 402. In the second cross-sectional view 520, the second lead frame portion 503B, the IC 504, and the encapsulant 510 of the IC package 402 can be seen. In Figure 5A and 5BIn an example, the second lead frame portion 503B or a part of the second lead frame portion 503B serves as a lead frame resistor and a support platform for the IC 504.

[0050] Figure 5C is a first cross-sectional view 530 of another example IC package 531. Since an off-chip resistor 542 is used instead of a lead frame resistor, Figure 5C and 5D the IC package 531 of Figure 4B is different from the IC package 402 of Figure 5A and 5B the IC package 510 of. In the first cross-sectional view 530, the lead frame layer 532, the IC 534, the bond pads 538A to 538E, the bond wires 536A to 536E, the off-chip resistor 542, and the encapsulant 540 of the IC package 531 can be seen. The lead frame layer 532 includes a first lead frame portion 533A, a second lead frame portion 533B, and a third lead frame portion 533C. The first lead frame portion 533A has bond pads, including the bond pads 538A and 538B, and is separated from the second lead frame portion 533B in the first cross-sectional view 530. The second lead frame portion 533B also includes bond pads, including the bond pad 538C. The third lead frame portion 533C also includes bond pads, including the bond pads 538D and 538E, and is separated from the second lead frame portion 533B in the first cross-sectional view 530.

[0051] As shown, the IC 534 has bond pads 537B, 537C, and 537D. The bond pad 537B of the IC 534 is coupled to the bond pad 538B of the first lead frame portion 533A via the corresponding bond wire 536A. The bond pad 537C of the IC 534 is coupled to the bond pad 538C of the second lead frame portion 533B via the corresponding bond wire 536C. The bond pad 537D of the IC 534 is coupled to the bond pad 538D of the third lead frame portion 533C via the corresponding bond wire 536D. In different examples, the number and arrangement of the bond pads of the lead frame layer 532 can vary. Regardless of the number and arrangement of the bond pads of the lead frame layer 532, some encapsulant 540 is used to cover the bonding pads of the lead frame layer 532, the bond pads (not shown) of the IC 534, and the bond wires coupling the bond pads of the lead frame layer 532 to the corresponding bond pads of the IC 534.

[0052] In Figure 5C an example, the second lead frame portion 533B can provide a support platform for the IC 534 but does not provide a lead frame resistor. Instead, an off-chip resistor 542 is included. In Figure 5CIn an example, the external resistor 542 is suspended in the encapsulant 540 and has: a first terminal 537A coupled to the bond pad 538A of the lead frame layer 532 using a bond wire 536A; and a second terminal 537E coupled to the bond pad 538E of the lead frame layer 532 using a bond wire 536E.

[0053] In some examples, the external resistor 542 can be placed in position after some encapsulant 540 covers the IC 534, the bond pads 538B, 538C, and 538D, and the corresponding bond wires 536B, 536C, and 536D and is at least partially cured. Then, the external resistor 542 and the bond wires 536A and 536E can be added, and more encapsulant 540 can be added to cover the external resistor 542, the bond pads 538A and 538E, and the bond wires 536A and 536E.

[0054] Figure 5D is Figure 5C A second cross-sectional view 550 of an example IC package 531. In the second cross-sectional view 550, the second lead frame portion 503B of the IC package 531, the IC 534, the external resistor 542, and the encapsulant 540 can be seen. In Figure 5C and 5D In an example, the second lead frame portion 503B serves as a support platform for the IC 534, and the external resistor 542 serves as an encapsulated resistor for current sensing operation or other operations of the IC 534.

[0055] Figure 6A is Figure 4A and 4B A bottom view 600 of an example IC package 402. As shown, the IC package 402 includes various external terminals 404 labeled as terminals 1 to 14. Terminal 1 is the SH+ terminal. Terminal 2 is the IN+ terminal. Terminal 7 is the IS- terminal. Terminal 8 is the SH- terminal. Terminal 9 is the IN- terminal. Terminal 10 is the output (OUT) terminal. Terminal 14 is the IS+ terminal. In different examples, terminals 3 to 6 and terminals 11 to 13 can have different functions or no functions. Additionally, in different examples, the functions of each of terminals 1 to 13 can vary.

[0056] Figure 6B is Figure 4A and 4B An internal view 610 of an example IC package 402. In Figure 6B is shown Figure 6A the IC 611 and the external terminals 404 described in Figure 1 and 2 The sensing circuitry 124 in Figure 5A and5B Examples of ICs related to IC 504 in. As shown, the SH+ terminal is coupled to the IS+ terminal at the terminal or region 615A of the lead frame via the first bonding wire 614. The SH- terminal is coupled to the IS- terminal at the terminal or region 615B of the lead frame via the second bonding wire 616. The other external terminals 404 of the IC package 402 are coupled to the corresponding bonding pads 613 of the IC 611 via corresponding bonding wires (shown but not individually labeled). In other examples, the lead frame (e.g., including a first lead frame sub-part 612A, a second lead frame sub-part 612B, and a third lead frame sub-part 612C) may include bonding pads, external terminals, and conductive traces between the bonding pads and the external terminals. In such examples, the bonding wires may be coupled between the bonding pads of the IC and the bonding pads of the lead frame. As an alternative, some bonding wires may directly couple the bonding pads of the IC to the external terminals of the lead frame, while other bonding wires may couple the bonding pads of the IC to the bonding pads of the lead frame (the bonding pads of the lead frame are coupled to the corresponding external terminals via conductive traces). In Figure 6B the example of, the first bonding wire 614 includes three bonding wires, and the second bonding wire 616 includes three bonding wires. In other examples, the first bonding wire 614 and / or the second bonding wire 616 may include more or fewer bonding wires. The IN+ terminal, IN- terminal, and OUT terminal are coupled to the corresponding bonding pads 613 of the IC 611.

[0057] In Figure 6B the example of, the IS+ terminal and the IS- terminal are coupled to the lead frame resistor. In Figure 6B the example of, the lead frame includes a first lead frame sub-part 612A, a second lead frame sub-part 612B, and a third lead frame sub-part 612C. In Figure 6B the example of, the first lead frame sub-part 612A, the second lead frame sub-part 612B, and the third lead frame sub-part 612C may be Figure 5A and 5B a part of the second lead frame portion 503B in. The first lead frame sub-part 612A includes the IS+ terminal. The third lead frame sub-part 612C includes the IS- terminal. The second lead frame sub-part 612B forms a lead frame resistor between the first lead frame sub-part 612A and the third lead frame sub-part 612C. In Figure 6BIn an example, the second lead frame sub - part 612B is shown with a dashed line to represent the second lead frame sub - part 612B below the IC 611. In some examples, the second lead frame sub - part 612B is narrower than the first lead frame sub - part 612A and the third lead frame sub - part 612C, and can provide support for the IC 611. In some examples, the lead frame resistor is at least integrated with the second lead frame sub - part 612B and includes resistive material between the positions where the first bonding wire 614 and the second bonding wire 616 contact the lead frame. In Figure 6B an example, the lead frame resistor includes the second lead frame sub - part 612B, some of the first lead frame sub - part 612A (where the first bonding wire 614 is coupled to the lead frame), and some of the third lead frame sub - part 612C (where the second bonding wire 616 is coupled to the lead frame). In other words, the first bonding wire 614 and the second bonding wire 616 establish voltage sense points that determine where the voltage difference across the lead frame is sensed.

[0058] When current passes through the lead frame resistor of the IC package 402, a voltage is generated across its ends. The first bonding wire 614 connects the sense point on the lead frame to the SH + terminal. The second bonding wire 616 connects the sense point on the lead frame to the SH - terminal. In Figure 6B an example, the SH + terminal is externally coupled to the IN + terminal (e.g., via the first trace of the PCB), and the SH - terminal is externally coupled to the IN - terminal (e.g., via the second trace of the PCB) to provide the voltage across the lead frame resistor to the PCB. Bonding wires connect the IN + and IN - pins to the corresponding bond pads of the IC 611, enabling the current sensing circuitry of the IC 611 to sense the voltage generated across the lead frame resistor. In other examples, the first bonding wire 614 and the second bonding wire 616 can directly couple the lead frame to the IN + / IN - terminals (instead of coupling the lead frame to the SH + / SH - terminals, coupling the SH + terminal to the IN +, and coupling the SH - terminal to the IN - terminal). As another alternative, the IC die can be directly coupled to the lead frame. As another alternative, the package resistor can be a on - chip resistor. In such an example, the on - chip resistor can carry a current density higher than the target threshold.

[0059] In some examples, the current sensing circuitry of the IC 611 includes a current sensing amplifier that is configured to: amplify the voltage difference; and output the amplified result as an output voltage VOUT to the OUT terminal. Assuming the gain of the current sensing amplifier is Gain Amp (V / V), then the gain of the current sensing circuitry can be Gain CS = R shunt*Gain amp (V / A). For example, if the packaged resistor has a value of 0.4 mOhm and the gain of the current sensing amplifier is 50 V / V, then the gain of the current sensing circuit system is 20 mV / A (0.4 m X 50). In this example, if a current of 10 A passes through the lead frame, the voltage generated across the two ends is 4 mV (0.4 m X 10). The current sensing amplifier senses this voltage and amplifies it with a gain of 50 V / V to obtain an output voltage VOUT of 0.2 V (0.4 m X 50 V / V). As an alternative, the output can be calculated by multiplying the input current by the current sensor system gain (e.g., 10 A X 20 mV / A = 0.2 V). In some examples, the REF terminal can be used to add an offset VREF to the output voltage VOUT, which enables the measurement of both positive and negative currents. In such examples, the gain of the current sensing circuit system is VOUT = R shunt *Gain CS + VREF. For example, if the current is -10 A and VREF is set to 2 V, then Vout = -10 A * 20 mV / A + 2 V = 1.8 V.

[0060] Figure 6C is an internal view 620 of another example IC package 602. The IC package 602 is Figure 1 the IC package 110 in Figure 2 the IC package 110A in Figure 3 or an example of the IC package 304 in Figure 6C In the example of Figure 6C , the IC package 602 includes an IC 621 and a lead frame, and the lead frame includes a first lead frame sub - part 622A, a second lead frame sub - part 622B, and a third lead frame sub - part 622C. In Figure 5A and 5B , the first lead frame sub - part 622A, the second lead frame sub - part 622B, and the third lead frame sub - part 622C can be part of the second lead frame portion 503B in Figure 6C . Compared with the IC package 402, the IC package 602 has the same terminals, but for the IC package 602, the SH + and IN + terminals are combined, and the SH - and IN - terminals are combined. Combining the SH + and IN + terminals and combining the SH - and IN - terminals as in Figure 6C reduces the packaging cost and simplifies the PCB layout. The first lead frame sub - part 622A includes the IS + terminal. The third lead frame sub - part 622C includes the IS - terminal. The second lead frame sub - part 622B forms a lead frame resistor between the first lead frame sub - part 622A and the third lead frame sub - part 622C.

[0061] InFigure 6B In the example, a part of the second lead frame sub - part 622B is shown by a dashed line to represent some of the second lead frame sub - parts 622B under the IC621. In some examples, the second lead frame sub - part 622B is narrower than the first lead frame sub - part 622A and the third lead frame sub - part 622C, and can provide support for the IC 621. The Figure 6C lead frame of Figure 6B is compared with the Figure 6B lead frame. The first lead frame sub - part 622A is elongated compared to the first lead frame sub - part 612A, the second lead frame sub - part 622B is elongated compared to the second lead frame sub - part 612B, and the third lead frame sub - part 622C is elongated compared to the third lead frame sub - part 612C. Using the elongated lead frame sub - parts, the resistance of the lead frame and the total gain (in mV / A) of the current sensing operation can be increased.

[0062] Figure 6D is an internal view 630 of another example IC package 632. The IC package 632 is an example of the IC package 110 in Figure 1 , the IC package 110A in Figure 2 or the IC package 304 in Figure 3 . In the example of Figure 6D , the IC package 632 includes an IC 641 and a lead frame. The lead frame includes a first lead frame sub - part 642A, a second lead frame sub - part 642B, a third lead frame sub - part 642C, a fourth lead frame sub - part 642D, and a fifth lead frame sub - part 642E. In the example of Figure 6D , the first lead frame sub - part 642A, the second lead frame sub - part 642B, the third lead frame sub - part 642C, the fourth lead frame sub - part 642D, and the fifth lead frame sub - part 642E can be a part of the second lead frame portion 503B in Figure 5A and 5B . The first lead frame sub - part 642A includes the IS + terminal. The fifth lead frame sub - part 642E includes the IS - terminal. The second lead frame sub - part 642B is located between the first lead frame sub - part 642A and the third lead frame sub - part 642C. The fourth lead frame sub - part 642D is located between the fifth lead frame sub - part 642E and the third lead frame sub - part 642C. The third lead frame sub - part 642C is located between the second lead frame sub - part 642B and the fourth lead frame sub - part 642D. The third lead frame sub - part 642C forms a lead frame resistor between the second lead frame sub - part 642B and the fourth lead frame sub - part 642D.

[0063] In Figure 6DIn an example, a part of the third lead frame sub - portion 642C is shown by a dashed line to represent some of the third lead frame sub - portions 642C under the IC641. In some examples, the second lead frame sub - portion 622B is narrower than the second lead frame sub - portion 642B and the fourth lead frame sub - portion 642D, and can provide support for the IC 641. The second lead frame sub - portion 642B and the fourth lead frame sub - portion 642D are wider than the third lead frame sub - portion 642C and narrower than the first lead frame sub - portion 642A and the fifth lead frame sub - portion 642E. Compared with Figure 6C the IC package 602, Figure 6D the IC package 632 has the same terminals, and the lead frame has additional sub - portions or levels (e.g., five levels or sub - portions instead of Figure 6B and 6C the three in). By using additional levels or sub - portions, the resistivity of the lead frame and the total gain (in mV / A) of the current sensing operation can be adjusted. In different examples, the number, length, and cross - sectional area of the levels or sub - portions of the lead frame can vary, which affects the resistivity, current density, and thermal characteristics.

[0064] In some examples, the package resistor of the IC package serves as a shunt resistor in a current input - voltage output analog current sensor system. The current sensor IC (e.g., Figure 1 and 2 the sensing circuitry 124 in, Figure 5A and 5B the IC504 in, Figure 6C the IC 611 in or Figure 6D the IC 641 in) generates a voltage at its output, and the voltage amplifies the current passing through its lead frame with a trans - impedance gain (V / A). In some examples, the package resistor is part of a lead frame having target parameters (e.g., resistivity, current density, and / or thermal characteristics), and the current sensor IC die is located on the lead frame. In some examples, the current sensor IC uses a mixed - signal circuitry to address the problems caused by using a package resistor with a significant positive temperature coefficient. In some examples, the lead frame is made of a copper alloy, the IC die is located on the lead frame, and is connected to the terminals of the package (e.g., Figures 6A - 6D the terminals in). In some examples, the encapsulant (e.g., Figure 5A and 5B the encapsulant 510 in) is a black molding compound that covers the IC, the bonding wires, and at least some of the package resistors.

[0065] In the described examples, current passes through the package resistor via the IS + terminal and the IS - terminal. In the narrow part of the lead frame (e.g.,Figure 6B the second lead frame portion 612B in Figure 6C the second lead frame portion 622B in Figure 6D or the third lead frame portion 642C in Figures 6A - 6D form a packaged resistor. In some instances,

[0066] each of the IC packages 402, 602, 632 of

[0067] Figure 7A can include terminals for power and ground. As an alternative, a REF terminal can be included to support negative current measurement.

[0068] Figure 7B is a graph 700 showing the variation of the resistance of an example lead frame resistor with temperature. In some instances, the lead frame material (at least a portion of which forms the packaged resistor) is composed of a copper alloy material. In such instances, the temperature coefficient can be approximately 4000 ppm / C (0.4% / C). Thus, the resistance varies with temperature and is proportional to temperature. The line 704 in graph 700 shows a shunt resistance of 0.4 mΩ, and the temperature coefficient (0.4% / C) can vary from -55 to 170 C. In some scenarios, the lead frame can have a tolerance of + / - 20%. In graph 700, the line 702 shows a shunt resistance of 0.48 mΩ (0.4 Ω + 20%) varying with temperature, and the line 706 shows a shunt resistance of 0.32 mΩ (0.4 Ω - 20%) varying with temperature. In other instances, the temperature coefficients of the packaged resistors can vary.

[0068] Figure 7B is a graph 710 showing the variation of the system gain of an example sensing circuit system with temperature. The line 714 in graph 710 shows how temperature affects Figure 7A the total system gain (in mV / A) of a 0.4 mΩ shunt resistor of Figure 7A In some scenarios, the lead frame can have a tolerance of + / - 20%. Thus, the line 712 shows the gain of a 0.48 mΩ (0.4 Ω + 20%) shunt resistance varying with temperature, and the line 716 shows the gain of a 0.32 mΩ (0.4 Ω - 20%) shunt resistance varying with temperature.

[0069] In Figure 7A the example, the value of the packaged resistor can vary from 0.27 mΩ to 0.64 mΩ, and the total gain can vary from 13.6 mV / A to 32 mV / A over a temperature range (e.g., -55 °C to 176 °C). This drift of the gain over the temperature range can cause a significant error in the output voltage VOUT of the current sensing circuit system. For example, if the input current into the current sensing circuit system is 10 A, and the current sensing circuit system has a gain of 20 mV / A (0.4 mOhm × 50 V / V), and VREF is 2 V, then the output voltage VOUT is 2.2 V (10 A × 20 mV / A + 2 V). However, if the packaged resistor value reaches 0.64 mΩ at 170 °C, and the current sensor gain reaches 32 mV / A, then the output voltage VOUT of the current sensing circuit system becomes 2.32 V (10 A × 32 mV / A + 2 V) at 170 °C.

[0070] In some examples, the current sensing circuit system provides dynamic gain / offset calibration. In some examples, the dynamic gain / offset calibration is based on: detecting the temperature of the packaged resistor; and modifying the voltage gain (in V / V) of the current sensing amplifier. Figure 7C FIG. 720 is a graph showing the system gain of another example sensing circuit system varying with temperature. Using the dynamic gain / offset calibration as shown in FIG. 720, the effect of the shunt resistor change is reduced or eliminated, and the total gain of the current sensor (in mV / A) remains constant over the temperature range. Specifically, line 724 shows the dynamic adjustment of the gain of a 0.4 mΩ shunt resistor with temperature. Line 722 shows the gain of a 0.48 mΩ (0.4 Ω + 20%) shunt resistor with temperature. Line 726 shows the dynamic adjustment of the gain of a 0.32 mΩ (0.4 Ω - 20%) shunt resistor with temperature.

[0071] Figure 8 FIG. is of an example IC package 800. The IC package 800 includes a packaged resistor 802, a first bond wire 804, an SH+ terminal 806, an IN+ terminal 808, a second bond wire 810, an SH- terminal 812, an IN- terminal 814, and an IC 816. The packaged resistor 802 is Figure 1 the packaged resistor 118 in Figure 2 the resistor RS1 in Figure 5A and 5B a part of the lead frame layer 502 or the second lead frame portion 503B in Figure 6B the second lead frame portion 612B in Figure 6C the second lead frame portion 622B in Figure 6DAn example of the third lead frame portion 642C in. The SH+ terminal 806 is Figures 6A - 6D An example of the SH+ terminal in. The IN+ terminal 808 is Figures 6A - 6D An example of the IN+ terminal in. The SH- terminal 812 is Figures 6A - 6D An example of the SH- terminal in. The IN- terminal 814 is Figures 6A - 6D An example of the IN- terminal in. The first bonding wire 804 is Figure 6B An example of the first bonding wire 614 in. The second bonding wire 810 is Figure 6B An example of the second bonding wire 616 in. The IC 816 is Figure 1 and 2 The sensing circuit system 124 in, Figure 5A and 5B The IC 504 in, Figure 5C and 5D The IC 534 in, Figure 6B The IC 611 in, Figure 6C The IC 621 in or Figure 6D An example of the IC 641 in.

[0072] In Figure 8 the example of, the IC 816 has a first terminal 818, a second terminal 820, a third terminal 822, and a fourth terminal 824. In some examples, the first terminal 818 of the IC 816 is coupled to the IN+ terminal 808 of the IC package 800. The second terminal 820 of the IC 816 is coupled to the IN- terminal 812 of the IC package 800. The third terminal 822 of the IC 816 is coupled to the OUT terminal (not shown) of the IC package 800.

[0073] In Figure 8 the example of, the IC 816 includes a temperature sensor circuit system 830, a calibration controller 846, and a current sensing amplifier circuit system 866. The temperature sensor circuit system 830 has a terminal 832. In some examples, the temperature sensor circuit system 830 includes current sources 834 and 836, transistors BP1 and BP2, and an analog-to-digital converter (ADC) 838 in the shown arrangement. The ADC 838 has a first terminal 840, a second terminal 842, and a third terminal 844. In Figure 8 the example of, the ADC 838 includes a finite state machine (FSM) 845.

[0074] The calibration controller 846 has a first terminal 848, a second terminal 850, and a third terminal 852. In some examples, the calibration controller 846 includes gain code control logic 854 and offset code control logic 860 in the illustrated arrangement, which can be implemented as digital logic circuitry, for example. The gain code control logic 854 has a first terminal 856 and a second terminal 858. The offset code control logic 860 has a first terminal 862 and a second terminal 864.

[0075] The current sense amplifier circuitry 866 has a first terminal 868, a second terminal 869, a third terminal 870, a fourth terminal 871, a fifth terminal 872, and a sixth terminal 874. In some examples, the current sense amplifier circuitry 866 includes an operational amplifier 876, resistors R1p, R1n, R2p, and R2n, and adjustable resistors RadjP and RadjN in the illustrated arrangement. Each of the resistors R1p, R1n, R2p, and R2n has a respective first terminal and a respective second terminal. Each of the adjustable resistors RadjP and RadjN has a respective first terminal, a respective second terminal, and a respective control terminal. The operational amplifier 876 has a first (non-inverting or “+”) terminal 878, a second (inverting or “−”) terminal 880, and a third terminal 882.

[0076] In Figure 8 an example, a first side of the package resistor 802 is coupled to the SH+ terminal 806 of the IC package 800 via a first bond wire 804. In some examples, a conductive side or target portion of a package resistor (e.g., a lead frame resistor) can be considered a terminal of the package resistor. In other words, a conductive side or target portion of a package resistor that is used to electrically couple the package resistor to another component can be considered a terminal of the package resistor. For example, each package resistor can have two conductive sides or target portions that serve as terminals. The SH+ terminal 806 is coupled to the IN+ terminal 808 of the IC package 800. The IN+ terminal 808 is coupled to the first terminal 818 of the IC 816. A second side of the package resistor 802 is coupled to the SH− terminal 812 of the IC package 800 via a second bond wire 810. The SH− terminal 812 is coupled to the IN− terminal 814 of the IC package 800. The IN− terminal 814 is coupled to the second terminal 820 of the IC 816.

[0077] The first terminal 868 of the current sensing amplifier circuit system 866 is coupled to the first terminal 818 of the IC 816 and the first terminal of the resistor R1p. The second terminal of the resistor R1p is coupled to the first terminal of the adjustable resistor RadjP and the first terminal 878 of the operational amplifier 876. The second terminal of the adjustable resistor RadjP is coupled to the first terminal of the resistor R2p. The second terminal of the resistor R2p is coupled to the sixth terminal 874 of the current sensing amplifier circuit system 866 and the fourth terminal 824 of the IC 816.

[0078] The second terminal 869 of the current sensing amplifier circuit system 866 is coupled to the second terminal 820 of the IC 816 and the first terminal of the resistor R1n. The second terminal of the resistor R1n is coupled to the first terminal of the adjustable resistor RadjN and the second terminal 880 of the operational amplifier 876. The second terminal of the adjustable resistor RadjN is coupled to the first terminal of the resistor R2n. The second terminal of the resistor R2n is coupled to the third terminal 882 of the operational amplifier 876, the sixth terminal 874 of the current sensing amplifier circuit system 866, and the fourth terminal 824 of the IC 816.

[0079] In Figure 8 the example, the first terminal of the transistor BP1 is coupled to the current source 834 and the first terminal 840 of the ADC 838. The second terminal of the transistor BP1 is coupled to the ground or a ground terminal. The first terminal of the transistor BP2 is coupled to the current source 836 and the second terminal 842 of the ADC 838. The control terminals of the transistors BP1 and BP2 are coupled together. The third terminal 844 of the ADC 838 is coupled to the terminal 832 of the temperature sensor circuit system 830. In other examples, the temperature sensor circuit system may be different from Figure 8 the example.

[0080] The first terminal 848 of the calibration controller 846 is coupled to the terminal 832 of the temperature sensor circuit system 830. The second terminal 850 of the calibration controller 846 is coupled to the control terminals of the resistors RadjP and RadjN. The third terminal 852 of the calibration controller 846 is coupled to the control terminals of the resistors RadjP and RadjN. The first terminal 856 of the gain code control logic 854 is coupled to the first terminal 848 of the calibration controller 846. The second terminal 858 of the gain code control logic 854 is coupled to the first terminal 862 of the offset code control logic 860 and the second terminal 850 of the calibration controller 846. The second terminal 864 of the offset code control logic 860 is coupled to the third terminal 852 of the calibration controller 846.

[0081] IC 816 is used for: receiving a current sense differential voltage between a first terminal 818 of IC 816 and a second terminal 820 of IC 816 in response to a current through the sense resistor 802; and providing VOUT at a third terminal 822 of IC 816 in response to the current sense differential voltage, the operation of the temperature sensor circuitry 830, the operation of the calibration controller 846, and the operation of the current sense amplifier circuitry 866. In some instances, IC 816 is used for: receiving a reference voltage VREF at a fourth terminal 824; and adjusting VOUT at the third terminal 822 in response to the current sense differential voltage, the operation of the temperature sensor circuitry 830, the operation of the calibration controller 846, the operation of the current sense amplifier circuitry 866, and VREF (e.g., VOUT = R shunt *Gain CS +VREF).

[0082] The temperature sensor circuitry 830 is used for: providing a differential voltage in response to the ambient temperature; providing a digital temperature code at a third terminal 844 of the ADC 838 in response to a differential voltage applied across a first terminal 840 and a second terminal 842 of the ADC 838; and providing the digital temperature code to a terminal 832 of the temperature sensor circuitry 830.

[0083] The calibration controller 846 is used for: receiving a digital code at a first terminal 848; providing a gain control code at a second terminal 850 in response to the digital temperature code and the operation of the gain code control logic 854; and providing an offset control code at a third terminal 852 in response to the gain control code and the operation of the offset code control logic 860. In some instances, the gain code control logic 854 is used for: receiving the digital temperature code (representing the temperature of the sense resistor); applying the digital temperature code to a math engine (as Figure 9 shown); and calculating the gain control code in response to the digital temperature code and the operation of the math engine. In some instances, the gain control code adjusts the value of a tunable resistor such that the gain of the current sense operation varies as a negative curve with temperature, as in the instance of Figure 7C shown. In some instances, the offset code control logic 860 is used for: receiving the gain control code; and adjusting the offset control code in response to the gain control code.

[0084] The current sensing amplifier circuit system 866 is configured to: receive a current sensing differential voltage across a first terminal 868 and a second terminal 869; receive a gain control code at a third terminal 870; receive an offset control code at a fourth terminal 871; and provide VOUT at a fifth terminal 872 in response to the current sensing differential voltage, the gain control code, the offset control code, the arrangement of resistors R1p, RadjP, R2p, R1n, RadjN, and R2n, and the operation of the operational amplifier 876. In some examples, the current sensing amplifier circuit system 866 is configured to: receive VREF at a sixth terminal 874; and adjust VOUT at the fifth terminal 872 in response to VREF, the current sensing differential voltage, the gain control code, the offset control code, the arrangement of resistors R1p, RadjP, R2p, R1n, RadjN, and R2n, and the operation of the operational amplifier 876.

[0085] Figure 9 FIG. 900 is a diagram of an example sensing circuit calibration technique. In Figure 9 this example, FIG. 900 includes a temperature sensor circuit system 830, a subtraction block 902, a first multiplier block 908, a temperature coefficient (TC) correction block 916, a first summing block 924, a second multiplier block 932, a second summing block 940, a gain adjustment (R2G) block 948, and an offset adjustment (G2O) block 956.

[0086] The temperature sensor circuit system 830 has a terminal 832. The subtraction block 902 has a first terminal 904, a second terminal 906, and a third terminal 907. The first multiplier block 908 has a first terminal 910, a second terminal 912, and a third terminal 914. The TC correction block 916 has a first terminal 918, a second terminal 920, and a third terminal 922. The first summing block 924 has a first terminal 926, a second terminal 928, and a third terminal 930. The second multiplier block 932 has a first terminal 934, a second terminal 936, and a third terminal 938. The second summing block 940 has a first terminal 942, a second terminal 944, and a third terminal 946. The R2G block 948 has a first terminal 950, a second terminal 952, and a third terminal 954. The G2O block 956 has a first terminal 958, a second terminal 960, and a third terminal 962.

[0087] The terminal 832 of the temperature sensor circuit system 830 is coupled to the first terminal 904 of the subtraction block 902 and the first terminal 918 of the TC correction block 916. The third terminal 907 of the subtraction block 902 is coupled to the first terminal of the first multiplier block 908. The third terminal 914 of the first multiplier block 908 is coupled to the first terminal 926 of the first summing block 924. The second terminal 928 of the first summing block 924 is coupled to the third terminal 922 of the TC correction block 916. The third terminal 930 of the first summing block 924 is coupled to the first terminal 934 of the second multiplier block 932. The third terminal 938 of the second multiplier block 932 is coupled to the first terminal 942 of the second summing block 940. The third terminal 946 of the second summing block 940 is coupled to the first terminal 950 of the R2G block 948. The third terminal 954 of the R2G block 948 is coupled to the control terminals of the adjustable resistors (e.g., adjustable resistors RadjP and RadjN) and the first terminal 958 of the G2O block 956. The third terminal 962 of the G2O block 956 is coupled to the control terminals of the adjustable resistors (e.g., adjustable resistors RadjP and RadjN).

[0088] In some instances, a lead frame having a shunt resistor (e.g., package resistor 802), bond wires, package pins, and / or PCB traces converts an input current into a differential voltage and then provides the differential voltage to the Vinp / Vinn bond pads of the IC (e.g., the first terminal 818 and the second terminal 820 herein). In some instances, the IC 816 includes an amplifier (e.g., operational amplifier 876) that converts the input differential voltage into a single-ended voltage (e.g., VOUT herein). In different instances, the amplifier topology and feedback arrangement can vary. Regardless of the specific amplifier topology and feedback arrangement, the amplifier is used to gain the differential voltage to an output voltage. In Figure 8 the instance of Amp Gain = R2 / R1.

[0089] In Figure 8 the instance of Figure 8In the example, a portion of each of the adjustable resistors RadjP and RadjN on the right side of the tap is in series with the corresponding R2 resistors (R2p and R2n), so each R2 value can be considered as (R2 + Radj_right). A portion of the adjustable resistors RadjP and RadjN on the left side of the tap is in series with the corresponding R1 resistors (R1p and R1n), so each R1 value can be considered as (R1 + Radj_left). Thus, the gain of the amplifier in this architecture is (R2 + Radj_right) / (R1 + Radj_left).

[0090] The gain control code moves the tap equally left and right for both the adjustable resistors RadjP and RadjN and changes the gain of the amplifier. Depending on the architecture of the current sense amplifier circuit system 866, the gain adjustment can vary. Regardless of such variation, the calibration controller 846 can provide a digital gain control code for gain adjustment.

[0091] In some examples, due to semiconductor manufacturing processes, the resistor network of the current sense amplifier circuit system 866 may have inherent mismatches. An example mismatch may be approximately + / -0.2%. To account for resistor mismatches and associated output errors, the calibration controller 846 can provide an offset control code. As the gain control code changes the values of the adjustable resistors RadjP and RadjN, and subsequently the gain of the amplifier, the offset error of the amplifier also changes due to the variation of the resistor network. Thus, the calibration controller 846 can determine an offset control code to change the values of the resistors in the resistor network to account for the mismatch.

[0092] In some examples, the offset control code moves the tap on the adjustable resistors RadjP and RadjN independently of the gain control code. In some examples, when the tap moves to the left for RadjP, the tap moves to the right for the adjustable resistor RadjN. This effectively changes the contribution of each adjustable resistor to the R2 and R1 resistors on the P side and N side, with the aim of maintaining a target R2 / R1 ratio on the P side and N side resistors. Depending on the architecture of the current sense amplifier circuit system 866, the offset correction can vary. Regardless of such variation, the calibration controller 846 can provide a digital offset control code for offset adjustment.

[0093] In some examples, the temperature sensor circuit system 830 is an on-chip temperature sensor with a mixed-signal circuit system for converting the IC temperature to a digital temperature code. The digital temperature code is then sent to the calibration controller 846, which can dynamically adjust the gain control code and the offset control code.

[0094] In Figure 9In an example, the temperature sensor circuit system 830 is configured to: provide a digital temperature code (TemperatureCode) at terminal 832 in response to the ambient temperature. The subtraction block 902 is configured to: receive the digital temperature code at a first terminal 904; receive the room temperature code at a second terminal 906; and provide a relative temperature value (e.g., ΔT = digital temperature code minus room temperature code) at a third terminal 907 in response to the digital temperature code and the room temperature code. The first multiplier block 908 is configured to: receive the relative temperature value at a first terminal 910; receive the TC value of the package resistor at a second terminal 912; and provide a first multiplication result (e.g., ΔT*TC) at a third terminal 914 in response to the relative temperature value and the temperature coefficient of the package resistor. The TC correction block 916 is configured to: receive the digital temperature code at a first terminal 918; receive the piecewise linear (PWL) segment or polynomial coefficients at a second terminal 920; and provide a corrected digital temperature code at a third terminal 922 in response to the digital temperature code and the PWL segment or polynomial coefficients. The first summing block 924 is configured to: receive the first multiplication result at a first terminal 926; receive the corrected digital temperature code at a second terminal 928; and provide a first sum value (e.g., (ΔT*TC) COR , where (ΔT*TC) COR is a corrected sum value that takes into account the TC variation).

[0095] The second multiplier block 932 is configured to: receive the first sum result at a first terminal 934; receive the package resistor value at a second terminal 936; and provide a second multiplication result at a third terminal 938 in response to the first sum result and the package resistor value at room temperature (R ROOM ). In some examples, the second multiplication result is given as: R ROOM *(ΔT*TC) COR . The second summing block 940 is configured to: receive the second multiplication result at a first terminal 942; receive R ROOM ; and provide a second sum result at a third terminal 946 in response to the second multiplication result and R ROOM . In some examples, the second sum result is given as: R ROOM *(1+(ΔT*TC) COR)。The R2G block 948 is configured to: receive a second summation result at a first terminal 950; receive a PWL segment or polynomial coefficients at a second terminal 952; and provide a gain control code (GainCode) at a third terminal 954 in response to the second summation result and the PWL segment / polynomial coefficients. The G2O block 956 is configured to: receive the gain control code at a first terminal 958; receive the PWL segment / polynomial coefficients at a second terminal 960; and provide an offset control code (OffsetCode) at a third terminal 962 in response to the gain control code and the PWL segment / polynomial coefficients.

[0096] In some examples, a temperature sensor circuit system (such as temperature sensor circuit system 830) includes bipolar transistors (such as transistors BP1 and BP2), an ADC (such as ADC 838), and a control digital state machine (such as FSM 845). The ADC receives the Vbe voltage difference (dVbe) between bipolar transistors with different current densities as its input. This dVbe value is proportional to temperature and can be reliably used to sense temperature. In some examples, the bipolar transistors can also be used to generate a reference voltage (VREF BP ) for the ADC, and the reference voltage remains constant within a temperature range within a threshold tolerance. In these examples, the ADC uses the dVbe voltage and VREF BP to generate a digital temperature code (TemperatureCode = A * dVbe / Vref + B, where A and B are temperature sensor gain and offset fine-tuning values that can be programmed during production to achieve a target digital code output) proportional to the ratio of dVbe and VREF BP . In other examples, a temperature sensor circuit system (such as temperature sensor circuit system 830) can use other techniques to generate a digital temperature code proportional to the die temperature. If the IC is placed on top of a lead frame resistor, the temperature of the IC and thus the output of the temperature sensor circuit system is equal to the temperature of the lead frame resistor within a reasonable tolerance.

[0097] In some examples, the digital temperature code is used as an input to a calibration controller, which can use Figure 9The techniques described obtain a gain control code and an offset control code. To account for variations in the temperature coefficient of the packaged resistor, TC correction is applied (e.g., TC correction block 916). In some instances, the TC variance that varies with temperature is non-linear. In such instances, the TC correction applies non-linear correction. In some instances, the TC correction models the error caused by the TC variation and applies correction based on the digital temperature code. In some instances, the TC correction uses a piecewise linear function to model the non-linear TC error function. In other instances, the TC correction uses a polynomial function that best approximates the error function. Regardless of the specific technique used, some predetermined inputs can be applied. For example, the PWL function can be implemented using slopes in predetermined segments within the operating temperature range of the device. The segment slopes of the PWL function can be configured and programmed during production based on the characterization of the packaged resistor. As another example, the coefficient terms of the polynomial function can be fine-tuned based on the characteristics of the packaged resistor.

[0098] In some instances, the R2G block 948 can use a piecewise linear approximation of a function that defines the relationship between the value of the packaged resistor at a particular temperature and the digital gain code required to achieve a target voltage gain at that temperature. In other instances, the R2G block 948 can use a higher-order polynomial to define the relationship between the value of the packaged resistor at a particular temperature and the digital gain code required to achieve a target voltage gain at that temperature. In some instances, the R2G function is based on the architecture of the current sensor such that no adjustment of segments (in the piecewise linear case) or coefficients (in the polynomial case) is required. In other instances, the R2G function can be pre-determined and programmed.

[0099] In some instances, the G2O block 956 is implemented using a piecewise linear approximation of a function that defines how the offset error of the amplifier varies as its gain changes in relation to temperature. In other instances, the G2O block 956 is implemented using a higher-order polynomial that models the same function. Since the amplifier gain varies according to the gain control code, the gain control code from the R2G block 948 can be used as an input to the G2O block 956, which determines the offset control code that minimizes the offset error. The digital offset code is then output to the adjustable resistor to equalize the ratio of the p-side resistor and the n-side resistor, thereby minimizing the offset error of the amplifier output.

[0100] In some instances, the current sensing circuitry (e.g., Figure 1 and 2 the sensing circuitry 124 in Figure 5A and 5B the IC 504 in Figure 6B the IC 611 in Figure 6Cthe IC 621 in Figure 6D the IC 641 in or Figure 8 the IC 816) in maintains a constant total gain (e.g., in mV / A) over a temperature range and minimizes the offset error over the temperature range. In an example scenario, as the temperature increases, the resistance of the package resistor increases, and the voltage difference generated across the terminals of the current sensing circuit system for the same current increases. In such a scenario, the output of the current sensing circuit system (e.g., VOUT herein) increases due to the change in the package resistor value and represents an incorrect current sensing value.

[0101] To minimize such error, a temperature sensor circuit system (e.g., temperature sensor circuit system 830) detects the increase in temperature and provides a digital temperature code proportional to the temperature to a calibration controller 846. The calibration controller 846 uses the digital temperature code and various pre-programmed value inputs (e.g., PWL segments or polynomial coefficient terms) to determine a gain control code that adjusts the value of a tunable resistor in the resistor network of the amplifier to reduce the gain of the amplifier. Through calibration, the total system gain (in mV / A) remains constant, resulting in VOUT remaining constant as if the value of the package resistor had not changed with temperature. Additionally, when the package resistor value changes, an offset error is introduced at the output of the amplifier due to the mismatch contributions of the P-side and N-side resistors changing with the change in gain (such that the ratio of the P-side to the N-side is different with the change in gain). Therefore, the calibration controller 846 can also provide an offset correction code to adjust the tunable resistor to equalize the P-side and N-side resistor ratios and eliminate the offset error.

[0102] Figure 10 is a diagram of an example IC package 1000. The IC package 1000 includes a package resistor 1002, a first bond wire 1004, an IN+ terminal 1008, a second bond wire 1010, an IN− terminal 1014, and an IC 1016. The package resistor 1002 is Figure 1 the package resistor 118 in Figure 2 the resistor RS1 in Figure 5A and 5B a portion of the lead frame layer 502 or the second lead frame section 503B in Figure 6B the second lead frame section 612B in Figure 6C the second lead frame section 622B in or Figure 6D an instance of the third lead frame section 642C in. The IN+ terminal 1008 is Figures 6A - 6D an instance of the IN+ terminal in Figures 6A - 6D The IN− terminal 1014 is Figure 6BAn example of the first bonding wire 614 in. The second bonding wire 1010 is Figure 6B An example of the second bonding wire 616 in. The IC 1016 is Figure 1 and 2 The sensing circuit system 124 in Figure 5A and 5B The IC 504 in Figure 5C and 5D The IC 534 in Figure 6B The IC 611 in Figure 6C The IC 621 in or Figure 6D An example of the IC 641 in.

[0103] In Figure 10 the example of, the IC 1016 has a first terminal 1018, a second terminal 1020, and a third terminal 1022. In some examples, the first terminal 1018 of the IC 1016 is coupled to the IN+ terminal 1008 of the IC package 1000. The second terminal 1020 of the IC 816 is coupled to the IN- terminal 1014 of the IC package 1000. The third terminal 1022 of the IC 1016 is coupled to an output terminal (not shown) of the IC package 1000.

[0104] In Figure 10 the example of, the first side of the package resistor 1002 is coupled to the IN+ terminal 1008 of the IC package 1000 via the first bonding wire 1004. The IN+ terminal 1008 is coupled to the first terminal 1018 of the IC 1016. The second side of the package resistor 1002 is coupled to the IN- terminal 1014 of the IC package 1000 via the second bonding wire 1010. The IN- terminal 1014 is coupled to the second terminal 1020 of the IC 1016.

[0105] In Figure 10 the example of, the IC 1016 includes an ADC 1030. The ADC 1030 has a first terminal 1032, a second terminal 1034, and a third terminal 1036. The first terminal 1032 of the ADC 1030 is coupled to the first terminal 1018 of the IC 1016. The second terminal 1034 is coupled to the second terminal 1020 of the IC 1016. The third terminal 1036 of the ADC 1030 is coupled to the third terminal 1022 of the IC 1016. In different examples, the ADC topology may vary.

[0106] The IC package 1000 is used to receive the current ISNS through the package resistor 1002. The current ISNS causes a differential voltage (Vinp - Vinn) across the package resistor 1002. The Vinp voltage is provided to the first terminal 1032 of the ADC 1030 via the first bonding wire 1004, the IN+ terminal 1008 of the IC package 1000, and the first terminal 1018 of the IC 1016. The Vinn voltage is provided to the second terminal 1034 of the ADC 1030 via the second bonding wire 1010, the IN+ terminal 1014 of the IC package 1000, and the second terminal 1020 of the IC 1016. The ADC 1030 is configured to: receive Vinp at the first terminal 1032; receive Vinn at the second terminal 1034; and provide a digital code at the third terminal 1036 in response to the difference between Vinp and Vinn. Using Figure 10 the IC package 1000, a controller (e.g., Figure 1 the controller 132 in Figure 2 or the controller 232 in Figure 1 ) or other circuitry receives the digital code and interprets the digital code as a current sense signal (e.g., S1_ISNS in

[0107] In some instances, an IC package (e.g., Figure 1 the IC package 110 in Figure 2 the IC package 110A in Figure 3 the IC package 304 in Figure 4A , 4B 5A, 5B, 6A, and 6B, the IC package 402 in Figure 5C and 5D the IC package 531 in Figure 6C the IC package 602 in Figure 6D the IC package 632 in Figure 8 the IC package 800 in Figure 10 or the IC package 1000 in Figure 1 the package resistor 118 in Figure 2 RS1 in Figure 5C and 5D the package resistor 542 in Figure 6B the lead frame resistor integrated with the second lead frame sub - part 612B in Figure 6C the lead frame resistor integrated with the second lead frame sub - part 622B in Figure 6D the lead frame resistor integrated with the third lead frame sub - part 642C in Figure 8 the package resistor 802 in Figure 10 the package resistor 1002 inFigure 1 the first terminal 120 in Figure 2 or 5C the relevant terminals in 5D, 6B, 6C, 6D, 8, and 10) and a second terminal (e.g., Figure 1 the second terminal 122 in Figure 2 or 5C the relevant terminals in 5D, 6B, 6C, 6D, 8, and 10); and an IC (e.g., Figure 5A and 5B the IC 504 in Figure 5C and 5D the IC 534 in Figure 6B the IC 611 in Figure 6C the IC 621 in Figure 6D the IC 641 in Figure 8 the IC 816 in Figure 10 or the IC1016 in Figure 1 and 2 the sensing circuit system 124 in Figure 8 the current sensing amplifier circuit system 866 in Figure 10 or the ADC 1030 in Figure 1 which has a first terminal (e.g., Figure 2 the first terminal 126 in 8 or Figure 1 the second terminal 128 in Figure 2 or 8 the relevant terminals in 10). The first terminal of the sensing circuit system is coupled to the first terminal of the packaged resistor. The second terminal of the sensing circuit system is coupled to the second terminal of the packaged resistor.

[0108] In some instances, the IC has a first terminal (e.g., Figure 8 the first terminal 818 in Figure 8 and a second terminal (e.g., Figure 8 one of the first bonding wires 804 in Figure 8 ). The first terminal of the IC is coupled to the first terminal of the packaged resistor via a first bonding wire (e.g., Figure 8 one of the second bonding wires 810 in Figure 8The second bond wire 810) is coupled to the second terminal of the packaged resistor.

[0109] In some instances, the packaged resistor is a lead frame resistor (e.g., integrated with the second lead frame portion 503B in Figure 5A and 5B integrated with the second lead frame sub - portion 612B in Figure 6B integrated with the second lead frame sub - portion 622B in Figure 6C and integrated with the third lead frame sub - portion 642C in Figure 6D ). In such instances, the IC package includes a lead frame having a first lead frame sub - portion (e.g., the first lead frame sub - portion 612A in Figure 6B or the first lead frame sub - portion 622A in Figure 6C ), a second lead frame sub - portion (e.g., the second lead frame sub - portion 612B in Figure 6B or the second lead frame sub - portion 622B in Figure 6C ), and a third lead frame sub - portion (e.g., the third lead frame sub - portion 612C in Figure 6B or the third lead frame sub - portion 622C in Figure 6C ). The second lead frame sub - portion is located between the first lead frame sub - portion and the third lead frame sub - portion. The third lead frame sub - portion forms the lead frame resistor. In some instances, the second lead frame sub - portion is narrower than the first lead frame sub - portion and the third lead frame sub - portion.

[0110] In other instances, the IC package includes a lead frame having a first lead frame sub - portion (e.g., the first lead frame sub - portion 642A in Figure 6D ), a second lead frame sub - portion (e.g., the second lead frame sub - portion 642B in Figure 6D ), a third lead frame sub - portion (e.g., the third lead frame sub - portion 642C as in Figure 6D ), a fourth lead frame sub - portion (e.g., the fourth lead frame sub - portion 642D in Figure 6D ), and a fifth lead frame sub - portion (e.g., the fifth lead frame sub - portion 642E in Figure 6D ). The second lead frame sub - portion is located between the first lead frame sub - portion and the third lead frame sub - portion. The fourth lead frame sub - portion is located between the third lead frame sub - portion and the fifth lead frame sub - portion. The third lead frame sub - portion forms the lead frame resistor. In some instances, the second lead frame sub - portion and the fourth lead frame sub - portion are narrower than the first lead frame sub - portion and the fifth lead frame sub - portion, and the third lead frame sub - portion is narrower than the second lead frame sub - portion and the fourth lead frame sub - portion.

[0111] In some instances, the sensing circuit system includes a temperature sensor circuit system (e.g., Figure 8 and 9 the temperature sensor circuit system 830 in Figure 8 ), a current sense amplifier having adjustable resistors (e.g., Figure 8 the adjustable resistors RadjP and RadjN in Figure 9 ), and a calibration controller coupled to the temperature sensor circuit system and the adjustable resistors (e.g., the calibration controller 846 in Table 8, or Figure 9 the related components / operations in Figure 9 ). The temperature sensor circuit system is configured to provide a digital temperature code proportional to the temperature of the package resistor (e.g., Figure 8 the TemperatureCode in Figure 9 ). The calibration controller is configured to: receive the digital temperature code; determine a gain adjustment in response to the digital temperature code (e.g., using the gain code control logic 854 or Figure 9 the related operations in

[0112] In some instances, the IC package includes: a lead frame having an integrated lead frame resistor, the lead frame resistor having a first terminal (e.g., Figure 6B the first terminal 615A in Figure 6B ), and a second terminal (e.g., Figure 6B the second terminal 615B in [[ID=26 ); and an IC on the lead frame resistor (e.g., ​ the IC 611 in ​ the second terminal 820 in ​ ), and includes a sensing circuit system (e.g., ​ and 2 the sensing circuit system 124 in ​in the current sensing amplifier circuit system 866), the sensing circuit system having a first terminal (e.g., ​ the first terminal 126 in ​ the first terminal 868 of the current sensing amplifier circuit system 866 in ​ the second terminal 128 in ​ the second terminal 869 of the current sensing amplifier circuit system 866 in ​ the third terminal 130 in ​ the third terminal 872 of the current sensing amplifier circuit system 866 in

[0113] In some instances, the sensing circuit system includes an ADC (e.g., ​ the ADC 1030 in ​ which is configured to provide a digital output in response to a voltage difference across a lead frame resistor. In some instances, the sensing circuit system includes a current sensing circuit system that includes a temperature sensor circuit system (e.g., ​ the temperature sensor circuit system 830 in ​ a current sensing amplifier having an adjustable resistor (e.g.,

[0114] the current sensing amplifier circuit system 866 in

[0115] and a calibration controller coupled to the temperature sensor circuit system and the adjustable resistor (e.g., ​ the package resistor 118 in ​ RS1 in ​ and 5D the package resistor 542 in ​ a lead frame resistor integrated with the second lead frame sub - part 612B in ​ a lead frame resistor integrated with the second lead frame sub - part 622B in ​The lead frame resistor integrated in the third lead frame sub - part 642C in, ​ the packaged resistor 802 in, or ​ the packaged resistor 1002 in); and an IC. The IC includes: an amplifier (e.g., ​ the current sensing amplifier circuit system 866 in), and a calibration controller (e.g., ​ the calibration controller 846 in). The amplifier has a first terminal coupled to the first terminal of the packaged resistor (e.g., ​ the first terminal 868 of the current sensing amplifier circuit system 866 in), and has a second terminal coupled to the second terminal of the packaged resistor (e.g., ​ the second terminal 869 of the current sensing amplifier circuit system 866 in). The amplifier includes an adjustable circuit system (e.g., ​ the adjustable resistors RadjP and RadjN in), which is configured to adjust the gain of the amplifier. The adjustable circuit system has an input (e.g., ​ the corresponding control terminals of the adjustable resistors RadjP and RadjN in). The calibration controller includes a gain control circuit system (e.g., ​ the gain code control logic 854 in, or ​ the related components / operations in), and the gain control circuit system has an output coupled to the input of the adjustable circuit system (e.g., ​ the second terminal 858 in). The gain control circuit system is configured to provide a calibration setting at the output in response to a digital temperature code ( ​ the TemperatureCode in).

[0116] In some instances, the IC includes: a temperature sensor circuit system (e.g., ​ the temperature sensing circuit system 830 in), which has an output coupled to the input of the gain control circuit system (e.g., ​ the first terminal 856 of the gain code control logic 854 in) (e.g., ​ the terminal 832 in); a current sensing amplifier (e.g., ​ the current sensing amplifier circuit system 866 in), which has adjustable resistors (e.g., ​ the adjustable resistors RadjP and RadjN in); and a calibration controller (e.g., ​ the calibration controller 846 in), which is coupled to the temperature sensor circuit system and the adjustable resistors. The temperature sensor circuit system is configured to provide a digital temperature code.

[0117] In some instances, the calibration controller (e.g., ​ the calibration controller 846 in, or ​The relevant components / operations therein include an offset control circuit system (e.g., ​ the offset code control logic 860 in ​ ), and the calibration controller is configured to correct based on the temperature coefficient and determine the calibration settings based on the operation of the offset control circuit system. In some instances, the operation of the offset control circuit system includes receiving a gain control code and adjusting the offset control code in response to the gain control code.

[0118] In some instances, the calibration controller (e.g., ​ the calibration controller 846 in ​ ), or the relevant components / operations therein) is configured to determine the calibration settings based on a piecewise linear function or a polynomial function. In some instances, the calibration controller is configured to determine the calibration settings based on the room temperature value and the value of the package resistor at the room temperature value.

[0119] In this specification, the term "coupled" may encompass a connection, communication, or signal path that supports a functional relationship consistent with this specification. For example, if device A generates a signal to control device B to perform an action, then: (a) in a first instance, device A is coupled to device B through a direct connection; or (b) in a second instance, device A is coupled to device B through an intermediate component C, but the intermediate component C does not change the functional relationship between device A and device B, such that device B is controlled by device A via the control signal generated by device A.

[0120] Additionally, in this specification, the recitation of "based on" means "at least partially based on". Thus, if X is based on Y, then X may depend on Y and any number of other factors.

[0121] A device "configured to" perform a task or function may be configured (e.g., programmed and / or hardwired) by the manufacturer to perform the function, and / or may be configured (or reconfigured) by the user after manufacture to perform the function and / or other additional or alternative functions. The configuration may be by programming the firmware and / or software of the device, by the construction and / or layout of the hardware components and interconnections of the device, or a combination thereof.

[0122] As used herein, the terms "terminal", "node", "interconnect", "lead", and "pin" may be used interchangeably. Unless specifically stated to the contrary, these terms are generally used to mean the interconnection between device elements, circuit elements, integrated circuits, devices or other electronic devices or semiconductor components and / or conductors, or their ends.

[0123] Circuits or devices described herein as including particular components may in fact be adapted to be coupled to those components to form the described circuitry or device. For example, a structure described as including one or more semiconductor elements (e.g., transistors), one or more passive elements (e.g., resistors, capacitors, and / or inductors), and / or one or more sources (e.g., voltage and / or current sources) may in fact include only semiconductor elements within a single physical device (e.g., a semiconductor die and / or an integrated circuit (IC) package) and may be adapted to be coupled to at least some of the passive elements and / or sources, such as during manufacture or after manufacture, e.g., by an end user and / or a third party, to form the described structure.

[0124] Although the use of particular transistors is described herein, other transistors (or equivalent devices) may alternatively be used with little or no change to the rest of the circuitry. For example, field effect transistors (“FETs”) (e.g., NFETs or PFETs), bipolar junction transistors (BJTs - e.g., NPN transistors or PNP transistors), insulated gate bipolar transistors (IGBTs), and / or junction field effect transistors (JFETs) may be used in place of or in combination with the devices described herein. The transistors may be depletion mode devices, drain extended devices, enhancement mode devices, native transistors, or other types of device structure transistors. Additionally, the devices may be implemented in or on a silicon substrate (Si), a silicon carbide substrate (SiC), a gallium nitride substrate (GaN), or a gallium arsenide substrate (GaAs).

[0125] The control terminal of a transistor, as well as its first and second terminals, may be referred to in the claims. In the context of an FET, the control terminal is the gate, and the first and second terminals are the drain and source. In the context of a BJT, the control terminal is the base, and the first and second terminals are the collector and emitter.

[0126] As used herein, an FET being “on” means that there is a conductive channel in the FET and a drain current can flow through the FET. As used herein, an FET being “off” means that a conducting channel does not exist, and thus a drain current does not flow through the FET. However, an “off” FET may have a current flowing through the body diode of the transistor.

[0127] The circuits described herein can be reconfigured to include additional or different components to provide functionality that is at least partially similar to the functionality available prior to component replacement. Unless otherwise indicated, a component shown as a resistor generally represents any one or more elements coupled in series and / or in parallel to provide the amount of impedance represented by the shown resistor. For example, a resistor or capacitor shown and described herein as a single component can alternatively be multiple resistors or capacitors coupled in parallel between the same nodes. For example, a resistor or capacitor shown and described herein as a single component can actually be multiple resistors or capacitors coupled in series between the same two nodes as the single resistor or capacitor.

[0128] Although some of the elements of the described examples are included in an integrated circuit and other elements are external to the integrated circuit, in other examples, additional or fewer features can be incorporated into the integrated circuit. Additionally, some or all of the features described as external to the integrated circuit can be included in the integrated circuit, and / or some of the features described as internal to the integrated circuit can be incorporated external to the integrated circuit. As used herein, the term "integrated circuit" means one or more circuits that: (i) are incorporated in / on a semiconductor substrate; (ii) are incorporated in a single semiconductor package; (iii) are incorporated into the same module; and / or (iv) are incorporated in / on the same printed circuit board.

[0129] The use of the phrase "ground" in the foregoing description includes chassis ground, earth ground, floating ground, virtual ground, digital ground, common ground, and / or any other form of ground connection applicable to or suitable for the teachings of this specification. In this specification, unless otherwise indicated, "about," "substantially," or "essentially" in front of a parameter means within + / - 10% of the stated parameter, or, if the parameter is zero, within a reasonable value that is approximately zero.

[0130] Within the scope of the claims, the described examples can be modified, and other examples are possible.

Claims

1. An integrated circuit (IC) package, comprising: A packaged resistor having a first terminal and a second terminal; And An IC separated from and coupled to the packaged resistor, the IC comprising: A sensing circuit system having a first terminal and a second terminal, the first terminal of the sensing circuit system being coupled to the first terminal of the packaged resistor, and the second terminal of the sensing circuit system being coupled to the second terminal of the packaged resistor.

2. The IC package according to claim 1, wherein the IC has a first terminal and a second terminal, the first terminal of the IC being coupled to the first terminal of the packaged resistor via a first bonding wire, and the second terminal of the IC being coupled to the second terminal of the packaged resistor via a second bonding wire.

3. The IC package according to claim 1, wherein the IC has a first terminal and a second terminal, the first terminal of the IC being coupled to the first terminal of the packaged resistor via a plurality of first bonding wires, and the second terminal of the IC being coupled to the second terminal of the packaged resistor via a plurality of second bonding wires.

4. The IC package according to claim 1, wherein the packaged resistor is a lead frame resistor.

5. The IC package according to claim 4, further comprising a lead frame, the lead frame including a first lead frame sub - part, a second lead frame sub - part, and a third lead frame sub - part, the second lead frame sub - part being located between the first lead frame sub - part and the third lead frame sub - part, and the third lead frame sub - part forming the lead frame resistor.

6. The IC package according to claim 5, wherein the second lead frame sub - part is narrower than the first lead frame sub - part and the third lead frame sub - part.

7. The IC package according to claim 4, further comprising a lead frame, the lead frame including a first lead frame sub - part, a second lead frame sub - part, a third lead frame sub - part, a fourth lead frame sub - part, and a fifth lead frame sub - part, the second lead frame sub - part being located between the first lead frame sub - part and the third lead frame sub - part, the fourth lead frame sub - part being located between the third lead frame sub - part and the fifth lead frame sub - part, the third lead frame sub - part forming the lead frame resistor, the second lead frame sub - part and the fourth lead frame sub - part being narrower than the first lead frame sub - part and the fifth lead frame sub - part, and the third lead frame sub - part being narrower than the second lead frame sub - part and the fourth lead frame sub - part.

8. The IC package according to claim 1, wherein the sensing circuit system includes a temperature sensor circuit system, a current sensing amplifier having an adjustable resistor, and a calibration controller coupled to the temperature sensor circuit system and the adjustable resistor, the temperature sensor circuit system being configured to provide a digital temperature code proportional to the temperature of the package resistor, and the calibration controller being configured to: Receive the digital temperature code; Determine a gain adjustment in response to the digital temperature code; Determine an offset adjustment in response to the gain adjustment; and Provide a control signal to the adjustable resistor in response to the gain adjustment and the offset adjustment.

9. The IC package according to claim 8, wherein the sensing circuit system is configured to: Receive a current sensing signal using the package resistor; and Output an amplified current sensing signal based on the received current sensing signal and the calibration of the adjustable resistor by the calibration controller.

10. An integrated circuit (IC) package, comprising: A lead frame including an integrated lead frame resistor having a first terminal and a second terminal; And An IC on the lead frame resistor, the IC having a first terminal coupled to the first terminal of the lead frame resistor and a second terminal coupled to the second terminal of the lead frame resistor.

11. The IC package according to claim 10, wherein the IC has a third terminal and includes a sensing circuit system having a first terminal, a second terminal, and a third terminal, the first terminal of the IC being coupled to the first terminal of the sensing circuit system, the second terminal of the IC being coupled to the second terminal of the sensing circuit system, and the third terminal of the IC being coupled to the third terminal of the sensing circuit system.

12. The IC package according to claim 10, wherein the lead frame includes a first lead frame sub - part, a second lead frame sub - part, and a third lead frame sub - part, the second lead frame sub - part being located between the first lead frame sub - part and the third lead frame sub - part, the second lead frame sub - part forming the lead frame resistor, and the second lead frame sub - part being narrower than the first lead frame sub - part and the third lead frame sub - part.

13. The IC package according to claim 11, wherein the sensing circuit system includes an analog - to - digital converter (ADC) configured to provide a digital output in response to a voltage difference across the lead frame resistor.

14. The IC package according to claim 11, wherein the sensing circuit system includes a current sensing circuit system, the current sensing circuit system including a temperature sensor circuit system, a current sensing amplifier having an adjustable resistor, and a calibration controller coupled to the temperature sensor circuit system and the adjustable resistor.

15. The IC package according to claim 14, wherein the temperature sensor circuitry is configured to provide a digital temperature code proportional to the temperature of the lead frame resistor, and the calibration controller is configured to: receive the digital temperature code; determine a gain adjustment in response to the digital temperature code; determine an offset adjustment in response to the gain adjustment; and provide a control signal to the adjustable resistor in response to the gain adjustment and the offset adjustment.

16. An integrated circuit (IC) package comprising: a package resistor having a first terminal and a second terminal; and an IC including: an amplifier having a first terminal coupled to the first terminal of the package resistor and a second terminal coupled to the second terminal of the package resistor, the amplifier including adjustable circuitry configured to adjust the gain of the amplifier, the adjustable circuitry having an input; and a calibration controller including gain control circuitry having an output coupled to the input of the adjustable circuitry, the gain control circuitry being configured to provide a calibration setting at the output in response to a digital temperature code.

17. The IC package according to claim 16, wherein the IC includes temperature sensor circuitry having an output coupled to the input of the gain control circuitry, the temperature sensor circuitry being configured to provide the digital temperature code.

18. The IC package according to claim 16, wherein the calibration controller includes offset control circuitry, and the calibration controller is configured to determine the calibration setting based on temperature coefficient correction and based on the operation of the offset control circuitry, the operation of the offset control circuitry including receiving a gain control code and adjusting an offset control code in response to the gain control code.

19. The IC package according to claim 16, wherein the calibration controller is configured to determine the calibration setting based on a piecewise linear function or a polynomial function.

20. The IC package according to claim 16, wherein the calibration controller is configured to determine the calibration setting based on a room temperature value and a package resistor value at the room temperature value.

Images