Semiconductor device

Abstract

The semiconductor device of the present invention controls on-off transition of a semiconductor element through a simple structure. The semiconductor device includes: a second semiconductor element connected in parallel with a first semiconductor element; a source semiconductor element; a common semiconductor element; a source-sink connection semiconductor element connected between the gate terminal of the first semiconductor element and the gate terminal of the second semiconductor element; and a control circuit for controlling transition of on-off states of the source semiconductor element, the sink semiconductor element, and the source-sink connection semiconductor element such that the first semiconductor element and the second semiconductor element are switched to the on state in this order. The second semiconductor element and the first semiconductor element are switched to an off state in this order.

Description

Technical Field

[0001] The technology disclosed in the specification of the present application relates to semiconductor devices. Background Art

[0002] In the past, as power elements for inverter devices for driving electric motors, etc., IGBTs (Insulated Gate Bipolar Transistors) or MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) made of inexpensive Si (silicon) have generally been used.

[0003] On the other hand, in recent years, the use of high-efficiency power elements made of wide-bandgap semiconductors, namely SiC (silicon carbide) or GaN (gallium nitride), has been increasing. Here, wide-bandgap semiconductors generally refer to semiconductors having a bandgap width of about 2 eV or more, and known ones include group 3 nitrides such as gallium nitride (GaN), group 2 oxides such as zinc oxide (ZnO), group 2 chalcogenides such as zinc selenide (ZnSe), diamond, and silicon carbide.

[0004] However, wide-bandgap semiconductors are relatively expensive, and therefore, they have not been popularized in consumer equipment that emphasizes cost. Therefore, for applications such as the drive motor of a compressor of a household air conditioner that uses low current for a long time, a parallel circuit composed of a small-sized SiC-MOSFET and a Si-IGBT connected in parallel has been proposed for use in products (for example, refer to Patent Document 1). With such a product, cost reduction due to the small size of the SiC-MOSFET and efficiency improvement (i.e., reduction of loss) due to the good DC characteristics of the SiC-MOSFET at low current can be expected. Prior Art Documents Patent Documents

[0005] Patent Document 1: Japanese Patent No. 6919292 Gazette Summary of the Invention Technical Problem to be Solved by the Invention

[0006] In order to balance efficiency improvement and cost reduction, it is necessary to reduce the element size of the SiC-MOSFET. However, when the element size of the SiC-MOSFET is reduced, the amount of current that can flow (permissible current) becomes low. Therefore, it is necessary to control the gate drive circuit in an appropriate order so that not only the SiC-MOSFET becomes in an on state, so that a large current does not flow only through the SiC-MOSFET and cause damage.

[0007] On the other hand, for the above control, a gate drive circuit for each element and a logic circuit for controlling the turn-on and turn-off state transitions of each element at separate timings are required, which may increase the circuit scale, and the timing control of the turn-on and turn-off state transitions becomes complicated, possibly leading to malfunction of the system.

[0008] The technology disclosed in the specification of the present application is completed in view of the above problems, and is a technology for controlling the turn-on and turn-off state transitions of semiconductor elements with a simple structure and suppressing damage to the semiconductor elements. Technical means for solving technical problems

[0009] The semiconductor device according to the first aspect of the technology disclosed in the specification of the present application includes: a first semiconductor element; a second semiconductor element connected in parallel with the first semiconductor element; a first source semiconductor element connected between a first power supply potential and the gate terminal of the first semiconductor element; a first sink semiconductor element connected between a reference potential and the gate terminal of the second semiconductor element; a source-sink connection semiconductor element connected between the gate terminal of the first semiconductor element and the gate terminal of the second semiconductor element; and a control circuit for controlling the turn-on and turn-off state transitions of the first source semiconductor element, the first sink semiconductor element, and the source-sink connection semiconductor element so that the conduction states are transferred in the order of the first semiconductor element and the second semiconductor element, and the turn-off states are transferred in the order of the second semiconductor element and the first semiconductor element. Advantages of the invention

[0010] According to at least the first aspect of the technology disclosed in the specification of the present application, the turn-on and turn-off state transitions of each semiconductor element can be controlled with a simple circuit structure including a source-sink connection semiconductor element, and damage to the semiconductor elements can be suppressed.

[0011] In addition, the objects, features, aspects, and advantages related to the technology disclosed in the specification of the present application will become clearer through the following detailed description and drawings. Description of the drawings

[0012] Figure 1 It is a diagram showing an example of the operation of an Si element and the operation of an SiC element. Figure 2 It is a diagram showing an example of a drive circuit for driving an Si element and an SiC element. Figure 3 It is a diagram schematically showing an example of the circuit structure of the semiconductor device according to the embodiment. Figure 4 It is a diagram showing examples of the operations of the Si element and the SiC element according to the embodiment. Figure 5 It is a diagram schematically showing an example of the circuit structure of the semiconductor device according to the embodiment. Figure 6 It is a diagram showing an example of the rise of the gate voltage of the SiC-MOSFET and the decrease of the gate-source voltage VGS of the MOSFET for source-drain connection. Figure 7 It is a diagram schematically showing a modified example of the circuit structure of the semiconductor device according to the embodiment. Figure 8 It is a diagram schematically showing an example of the circuit structure of the semiconductor device according to the embodiment. Figure 9 It is a diagram schematically showing an example of the circuit structure of the semiconductor device according to the embodiment. Figure 10 It is a diagram showing examples of the operations of the Si element and the SiC element according to the embodiment. Figure 11 It is a diagram schematically showing an example of the circuit structure of the semiconductor device according to the embodiment. Figure 12 It is a diagram showing examples of the operations of the Si element and the SiC element according to the embodiment. Figure 13 It is a diagram schematically showing an example of the circuit structure of the semiconductor device according to the embodiment. Figure 14 It is a diagram schematically showing an example of the circuit structure of the semiconductor device according to the embodiment. Figure 15 It is a diagram showing an example of the DC characteristics of the MOSFET. Figure 16 It is a diagram schematically showing an example of the circuit structure of the semiconductor device according to the embodiment. Figure 17 It is a diagram showing examples of the operations of the Si-IGBT and the SiC-MOSFET. Figure 18 It is a diagram showing an example of a drive circuit having a general parallel connection circuit. Figure 19 It is a diagram schematically showing an example of the circuit structure of the semiconductor device according to the embodiment. Figure 20 It is a diagram showing examples of the operations of the Si element and the SiC element according to the embodiment. Figure 21This is a diagram showing an example of a structure in which the gate of a SiC-MOSFET and a common-use MOSFET are connected via a common-use diode. Figure 22 This is a diagram showing examples of the operations of Si elements and SiC elements according to the embodiment. Detailed Embodiment

[0013] Hereinafter, the embodiment will be described with reference to the drawings. In the following examples, although detailed features and the like are shown for the purpose of explaining the present technology, these features are exemplary, and not all of these features are necessary for implementing the embodiment.

[0014] In addition, the drawings are generally represented, and for convenience of explanation, structures are appropriately omitted or simplified in the drawings. In addition, the mutual relationships of the sizes and positions of the structures shown in different drawings are not necessarily correctly described and can be changed as appropriate. In addition, for ease of understanding the content of the embodiment, shading may sometimes be added to a top view or the like that is not a cross-sectional view.

[0015] In addition, in the following description, the same reference numerals are used to illustrate the same structural elements, and their names and functions are also assumed to be the same. Therefore, in order to avoid duplication, detailed descriptions of them are sometimes omitted.

[0016] Furthermore, in the description described in the specification of the present application, when a structural element is described as "including", "containing", or "having", etc., unless otherwise specified, it is not an exclusive expression excluding the existence of other structural elements.

[0017] Furthermore, even when ordinal numbers such as "first" or "second" are used in the description described in the specification of the present application, these terms are used for ease of understanding the content of the embodiment, and the content of the embodiment is not limited to the order and the like resulting from these ordinal numbers.

[0018] <Embodiment 1> Hereinafter, the semiconductor device according to the present embodiment will be described. For ease of explanation, first, the structure of a semiconductor device known to the inventor will be described.

[0019] In order to achieve both efficiency improvement and cost reduction, it is necessary to reduce the element size of the SiC-MOSFET. In this case, when the element size of the SiC-MOSFET becomes small, the current that can flow becomes low. Therefore, in the gate drive circuit, it is necessary to control in an appropriate order so that not only the SiC-MOSFET becomes in an on state, so that a large current does not flow only through the SiC-MOSFET and cause damage.

[0020] Figure 1This is a diagram showing examples of the operations of Si elements and SiC elements.

[0021] As Figure 1 shown in the example, considering the timing (rise time) at which the Si element transitions to the on state, the rise of the gate output of the SiC element with respect to the input signal is delayed by a time D1 compared to the gate output of the Si element. Further, considering the timing (fall time) at which the SiC element transitions to the off state, the fall of the gate output of the Si element is delayed by a time D2 with respect to the gate output of the SiC element.

[0022] Consequently, the current in the Si element is equivalent to the total current immediately after rising, and then decreases as it is shunted to the SiC element with a delayed rise according to the characteristics of the element, and again becomes equivalent to the total current after the fall of the SiC element.

[0023] To perform the above control, a gate drive circuit for each element and a logic circuit for controlling the turn-on and turn-off of each element at separate timings are required.

[0024] Figure 2 This is a diagram showing an example of a drive circuit for driving Si elements and SiC elements. As Figure 2 shown in the example, the drive circuit 100 includes a control signal generation circuit 12 that receives an input signal, a gate drive circuit 14 that inputs a control signal 12A from the control signal generation circuit 12, and a gate drive circuit 16 that inputs a control signal 12B from the control signal generation circuit 12. An Si-IGBT 20 to which a gate signal is input to a gate terminal 20A from the gate drive circuit 14 and an SiC-MOSFET 22 to which a gate signal is input to a gate terminal 22A from the gate drive circuit 16 are connected to the drive circuit 100.

[0025] When it becomes Figure 2 the circuit configuration shown, the circuit scale increases and the timing control of its turn-on and turn-off state transitions becomes complex, and there is a possibility of malfunction in the system.

[0026] <Regarding the structure of the semiconductor device> Figure 3 This is a diagram schematically showing an example of the circuit structure of the semiconductor device according to the present embodiment. As Figure 3As shown in the example, the drive circuit 100A in the semiconductor device includes: a source MOSFET 24 connected between the gate terminal 20A for conducting and turning off control of the Si-IGBT 20 (hereinafter also referred to as the Si element), which is the first semiconductor element, and the potential VCC; a sink MOSFET 26 connected between the gate terminal 22A for conducting and turning off control of the SiC-MOSFET 22 (hereinafter also referred to as the SiC element), which is the second semiconductor element with a current capacity lower than that of the first semiconductor element, and the reference potential VNC; a source-drain connecting MOSFET 28 connected between the gate terminals of both the Si element and the SiC element (i.e., connected between the gate terminal 20A for conducting and turning off control of the Si-IGBT 20 and the gate terminal 22A for conducting and turning off control of the SiC-MOSFET 22); and a control circuit 30 that causes these MOSFETs (the source MOSFET 24, the sink MOSFET 26, and the source-drain connecting MOSFET 28) to transfer between the conducting and non-conducting states in a specified order. A parallel connection circuit 200 is connected to the drive circuit 100A. The parallel connection circuit 200 is a circuit in which the Si-IGBT 20, which is the first semiconductor element, and the SiC-MOSFET 22, which is the second semiconductor element with a current capacity lower than that of the first semiconductor element, are connected in parallel.

[0027] In the parallel connection circuit 200, the collector terminal of the Si-IGBT 20 is connected to the drain terminal of the SiC-MOSFET 22, and the emitter terminal of the Si-IGBT 20 is connected to the source terminal of the SiC-MOSFET 22.

[0028] The control circuit 30 is commonly connected to the gate terminal 24A of the source MOSFET 24 and the gate terminal 26A of the sink MOSFET 26, and is connected to the gate terminal 28A of the source-drain connecting MOSFET 28 and the reference potential VNC.

[0029] In the conduction operation (transfer to the conduction state) based on the control signal (input signal) from an external controller (not shown here) of this semiconductor device, in order to prevent all currents from flowing through the smaller-sized SiC element and damaging it, it is necessary to first make the Si element, which can conduct a large current, perform the conduction operation, and then delay for a specified time to make the smaller-sized SiC element perform the conduction operation. Conversely, in the turn-off operation (transfer to the turn-off state) based on the control signal (input signal) from an external controller (not shown here) of this semiconductor device, it is necessary to first make the SiC element perform the turn-off operation. Hereinafter, the detailed order will be described.

[0030] Figure 41 and 2 are diagrams showing examples of the operation of the Si device and the operation of the SiC device according to this embodiment.

[0031] like Figure 4 As shown in the example, when an input signal related to the conduction operation (conduction signal) is input to the control circuit 30, the control circuit 30 inputs an L-level signal to the gate terminal 28A of the source-sink connection MOSFET 28 for a predetermined time (time T1) to cause the source-sink connection MOSFET 28 to perform a turn-off operation, thereby disconnecting the gate terminal 20A for on / off control of the Si-IGBT 20 and the gate terminal 22A for on / off control of the SiC-MOSFET 22. The timing for inputting the L-level signal to the gate terminal 28A of the source-sink connection MOSFET 28 can be set to the detection of the rising edge of the input signal (conduction signal).

[0032] Afterwards, the source MOSFET 24 and sink MOSFET 26, whose gates are linked, perform opposite transitions. Specifically, in the source MOSFET 24, the signal input to the gate terminal 24A thereof changes from an L-level signal to an H-level signal, thereby delaying the transition from the off-state to the on-state with a time delay of T2. Meanwhile, the signal input to the gate terminal 26A of the sink MOSFET 26 changes from an H-level signal to an L-level signal, thereby delaying the transition from the on-state to the off-state with a time delay of T2.

[0033] As a result, the gate of the Si-IGBT 20 is charged, and the Si-IGBT 20 turns on before the SiC-MOSFET 22. Meanwhile, the source-sink MOSFET 28 turns off, so the gate of the SiC-MOSFET 22 is disconnected from the gate of the Si-IGBT 20, and no charging occurs.

[0034] Then, when an H-level signal is input to gate terminal 28A of source-sink MOSFET 28, turning on source-sink MOSFET 28, gate terminal 20A for on / off control of Si-IGBT 20 and gate terminal 22A for on / off control of SiC-MOSFET 22 are connected. This starts charging the gate of SiC-MOSFET 22, and SiC-MOSFET 22 turns on with a delay of time T3 relative to Si-IGBT 20.

[0035] Next, when an input signal related to the shutdown operation (shutdown signal) is input to the control circuit 30, the control circuit 30 inputs an L-level signal to the gate terminal 28A of the source-sink connection MOSFET 28 for a predetermined time (time T4), causing the source-sink connection MOSFET 28 to perform a shutdown operation, thereby disconnecting the gate terminal 20A for on / off control of the Si-IGBT 20 and the gate terminal 22A for on / off control of the SiC-MOSFET 22. The timing for inputting the L-level signal to the gate terminal 28A of the source-sink connection MOSFET 28 can be set to the detection of the falling edge of the input signal (shutdown signal).

[0036] Afterwards, the source MOSFET 24 and sink MOSFET 26, whose gates are linked to each other, perform opposite transitions. Specifically, in the source MOSFET 24, the signal input to its gate terminal 24A changes from an H-level signal to an L-level signal, causing a delay of time T5 and transitioning from on-state to off-state. Meanwhile, the signal input to its gate terminal 26A changes from an L-level signal to an H-level signal, causing a delay of time T5 and transitioning from off-state to on-state.

[0037] As a result, the gate of SiC-MOSFET 22 is discharged, and SiC-MOSFET 22 turns off before Si-IGBT 20. Meanwhile, since source-sink MOSFET 28 turns off, the gate of Si-IGBT 20 is disconnected from the gate of SiC-MOSFET 22, and no discharge occurs.

[0038] Then, when an H-level signal is input to gate terminal 28A of source-sink MOSFET 28, turning on source-sink MOSFET 28, gate terminal 20A for on / off control of Si-IGBT 20 and gate terminal 22A for on / off control of SiC-MOSFET 22 are connected. Discharge of the gate of Si-IGBT 20 then begins, and Si-IGBT 20 turns off with a delay of time T6 relative to SiC-MOSFET 22.

[0039] As described above, the transition between the on / off states of Si and SiC devices can be controlled using a simpler circuit configuration. Specifically, the delay in the on / off operation of Si and SiC devices can be controlled using a simple circuit configuration, without requiring separate gate drive circuits for each Si and SiC device to delay the on / off operation.

[0040] <Implementation Method 2> A semiconductor device according to this embodiment will be described. In the following description, structural elements that are the same as those described in the above-described embodiments are denoted by the same reference numerals and illustrated, and their detailed descriptions are appropriately omitted.

[0041] <Regarding the structure of the semiconductor device> Figure 5 is a diagram schematically showing an example of the circuit structure of the semiconductor device according to the embodiment. As Figure 5 shown in the example, the drive circuit 100A in the semiconductor device includes: a source MOSFET 24 connected between the gate terminal 20A for controlling the conduction and cutoff of the Si element and the potential VCC; a sink MOSFET 26 connected between the gate terminal 22A for controlling the conduction and cutoff of the SiC element and the reference potential VNC; a source-drain connection MOSFET 28 connected between the gate terminals of both the Si element and the SiC element (that is, connected between the gate terminal 20A for controlling the conduction and cutoff of the Si-IGBT 20 and the gate terminal 22A for controlling the conduction and cutoff of the SiC-MOSFET 22); and a control circuit 30 that causes these MOSFETs (the source MOSFET 24, the sink MOSFET 26, and the source-drain connection MOSFET 28) to transfer between conduction and cutoff states in a predetermined order. A parallel connection circuit 200 is connected to the drive circuit 100A.

[0042] Figure 5 In the structure shown, when an N-channel MOSFET is applied to the source-drain connection MOSFET 28, in order to charge the gate of the SiC-MOSFET 22, the control circuit 30 causes the source-drain connection MOSFET 28 to transfer to the conduction state.

[0043] At this time, in order to cause the source-drain connection MOSFET 28 to transfer to the conduction state, the power supply voltage applied to the gate of the source-drain connection MOSFET 28 is the potential VCC. Since the potential VCC is equal to the gate voltage of the Si-IGBT 20, when the source-drain connection MOSFET 28 transfers to the conduction state and the gate voltage of the SiC-MOSFET 22 rises, the gate-source voltage VGS of the source-drain connection MOSFET 28 decreases as the gate voltage of the SiC-MOSFET 22 rises. In order for the MOSFET to transfer to the conduction state, the gate-source voltage VGS needs to be above the gate threshold Vth. Therefore, before the gate voltage of the SiC-MOSFET 22 reaches the potential VCC, the source-drain connection MOSFET 28 transfers to the cutoff state.

[0044] Figure 6 This is a diagram showing an example of the rise of the gate voltage of the SiC-MOSFET 22 and the decrease in the gate-source voltage VGS of the source-drain connection MOSFET 28. As Figure 6 shown in the example, when the gate-source voltage VGS of the source-drain connection MOSFET 28 is lower than the gate threshold Vth, the source-drain connection MOSFET 28 transitions to the off state. Therefore, the rise of the gate voltage of the SiC-MOSFET 22 is restricted and does not rise to the potential VCC.

[0045] As a result, the gate voltage of the SiC-MOSFET 22 becomes low, which may lead to deterioration of DC characteristics (and reduction of conduction ability, etc.).

[0046] Figure 7 This is a diagram schematically showing a modified example of the circuit structure of the semiconductor device according to the present embodiment. As Figure 7 shown in the example, the semiconductor device includes: a Si-IGBT 20; a parallel connection circuit 200 in which the SiC-MOSFET 22 is connected in parallel; a source MOSFET 24 connected between the gate terminal 20A for controlling the conduction and cutoff of the Si element and the potential VCC; a drain MOSFET 26 connected between the gate terminal 22A for controlling the conduction and cutoff of the SiC element and the reference potential VNC; a source-drain connection MOSFET 28 that connects between the gate terminals of both the Si element and the SiC element (i.e., between the gate terminal 20A for controlling the conduction and cutoff of the Si-IGBT 20 and the gate terminal 22A for controlling the conduction and cutoff of the SiC-MOSFET 22); a source MOSFET 32 connected between the gate terminal 28A for controlling the conduction and cutoff of the source-drain connection MOSFET 28 and the potential VCC2; a drain MOSFET 34 connected between the gate terminal 28A for controlling the conduction and cutoff of the source-drain connection MOSFET 28 and the reference potential VNC; a control circuit 30A that causes these MOSFETs (the source MOSFET 24, the drain MOSFET 26, the source-drain connection MOSFET 28, the source MOSFET 32, and the drain MOSFET 34) to transfer between the conduction and cutoff states in a prescribed order; and an internal power supply circuit 50 that outputs the potential VCC and the potential VCC2. The drive circuit 100B includes the source MOSFET 24, the drain MOSFET 26, the source-drain connection MOSFET 28, the source MOSFET 32, the drain MOSFET 34, the control circuit 30A, and the internal power supply circuit 50. Here, the potential VCC2 is set to a voltage higher than the potential VCC. In addition, the source-drain connection MOSFET 28 is, for example, an N-channel MOSFET.

[0047] Figure 7In the structure shown, the power supply voltage output from the internal power supply circuit 50 is a dual system of the potential VCC and the potential VCC2. As the power supply for the pre-stage circuit (the circuit composed of the source MOSFET 32 and the drain MOSFET 34) that supplies the gate voltage to the gate terminal 28A for controlling the conduction and cutoff of the source-drain connection MOSFET 28, the potential VCC2 is used.

[0048] By adopting such a circuit structure, the source MOSFET 32 functions as an element for charging the gate of the source-drain connection MOSFET 28, and the drain MOSFET 34 functions as an element for discharging the gate of the source-drain connection MOSFET 28. Thus, even if the gate voltage of the SiC-MOSFET 22 rises, the gate-source voltage VGS of the source-drain connection MOSFET 28 can be ensured to be above the threshold voltage. Therefore, the gate of the SiC-MOSFET 22 can be sufficiently charged, and the deterioration of the DC characteristics can be suppressed.

[0049] <Embodiment 3> The semiconductor device according to the present embodiment will be described. In addition, in the following description, the same reference numerals are assigned to the structural elements that are the same as those described in the above-described embodiments, and their detailed descriptions are appropriately omitted.

[0050] <Regarding the Structure of the Semiconductor Device> Figure 8 is a diagram schematically showing an example of the circuit structure of the semiconductor device according to the embodiment. As Figure 8 shown in the example, the drive circuit 100C in the semiconductor device includes: a source MOSFET 24 connected between the gate terminal 20A for controlling the conduction and cutoff of the Si element and the potential VCC; a drain MOSFET 26 connected between the gate terminal 22A for controlling the conduction and cutoff of the SiC element and the reference potential VNC; a source-drain connection MOSFET 128 connected between the gate terminals of both the Si element and the SiC element (that is, connected between the gate terminal 20A for controlling the conduction and cutoff of the Si-IGBT 20 and the gate terminal 22A for controlling the conduction and cutoff of the SiC-MOSFET 22); and a control circuit 30 that causes these MOSFETs (the source MOSFET 24, the drain MOSFET 26, and the source-drain connection MOSFET 128) to perform conduction and cutoff state transitions in a specified order. A parallel connection circuit 200 is connected to the drive circuit 100C.

[0051] Figure 8In the structure shown, the source-drain connection MOSFET 128 is formed by connecting an N-channel MOSFET 128A and a P-channel MOSFET 128B in parallel. In addition, an inverter 128C is connected between the gate terminal of the N-channel MOSFET 128A and the gate terminal of the P-channel MOSFET 128B. Further, a gate voltage can be applied to the source-drain connection MOSFET 128 so that both the SiC-MOSFET 22 and the Si-IGBT 20 perform conduction operations or turn-off operations (i.e., their conduction operations and turn-off operations are synchronized).

[0052] According to this structure, when the gate voltage of the SiC-MOSFET 22 rises and the N-channel MOSFET 128A of the source-drain connection MOSFET 128 is in an off state, the P-channel MOSFET 128B can also be in an on state. Thus, the gate voltage of the SiC-MOSFET 22 can be sufficiently charged without using an additional power supply circuit, and therefore, deterioration of DC characteristics can be suppressed.

[0053] <Embodiment 4> The semiconductor device according to the present embodiment will be described. In the following description, structural elements that are the same as those described in the above-described embodiments are denoted by the same reference numerals for illustration, and their detailed descriptions are appropriately omitted.

[0054] <Regarding the structure of the semiconductor device> Figure 9 is a diagram schematically showing an example of the circuit structure of the semiconductor device according to the embodiment. As Figure 9 shown in the example, the drive circuit 100D in the semiconductor device includes: a source MOSFET 24 connected between the gate terminal 20A for controlling conduction and turn-off of the Si element and the potential VCC; a sink MOSFET 26 connected between the gate terminal 22A for controlling conduction and turn-off of the SiC element and the reference potential VNC; a source-drain connection resistor 228 connected between the gate terminals of both the Si element and the SiC element (i.e., between the gate terminal 20A for controlling conduction and turn-off of the Si-IGBT 20 and the gate terminal 22A for controlling conduction and turn-off of the SiC-MOSFET 22); and a control circuit 30 that causes these MOSFETs (source MOSFET 24, sink MOSFET 26) to perform conduction and turn-off state transitions in a prescribed order. A parallel connection circuit 200 is connected to the drive circuit 100D.

[0055] Figure 9In the structure shown, the gate input of the source MOSFET 24 and the gate input of the sink MOSFET 26 are not linked, and they transfer from the off state to the on state and from the on state to the off state separately at different timings.

[0056] Figure 10 FIG. is a diagram showing examples of the operations of the Si element and the SiC element according to the present embodiment.

[0057] As Figure 9 shown in the example, when an input signal (turn-on signal) related to the turn-on operation is input to the control circuit 30, the source MOSFET 24 changes the signal input to the gate terminal 24A of the source MOSFET 24 from an L-level signal to an H-level signal, thereby transferring from the off operation to the on operation. In addition, the signal input to the gate terminal 26A of the sink MOSFET 26 changes from an H-level signal to an L-level signal, so that the sink MOSFET 26 transfers from the on operation to the off operation after a delay time T10.

[0058] Thereby, the gate of the Si-IGBT 20 is charged, and the Si-IGBT 20 starts the turn-on operation earlier than the SiC-MOSFET 22. After that, the charging of the gate of the SiC-MOSFET 22 starts, and the SiC-MOSFET 22 starts the turn-on operation after a delay time T10 compared to the Si-IGBT 20.

[0059] Next, when an input signal (turn-off signal) related to the turn-off operation is input to the control circuit 30, the sink MOSFET 26 changes the signal input to the gate terminal 26A of the sink MOSFET 26 from an L-level signal to an H-level signal, thereby transferring from the off operation to the on operation. In addition, the signal input to the gate terminal 24A of the source MOSFET 24 changes from an H-level signal to an L-level signal, so that the source MOSFET 24 transfers from the on operation to the off operation after a delay time T12.

[0060] Thereby, the gate of the SiC-MOSFET 22 is discharged, and the SiC-MOSFET 22 starts the turn-off operation earlier than the Si-IGBT 20. After that, the discharging of the gate of the Si-IGBT 20 starts, and the Si-IGBT 20 starts the turn-off operation after a delay time T12 compared to the SiC-MOSFET 22.

[0061] According to this structure, a circuit for driving the source-drain connected MOSFET 28 is not required. Therefore, the turn-on and turn-off control of the Si-IGBT 22 and the SiC-MOSFET 22 can be performed with a simple structure.

[0062] <Embodiment 5> A semiconductor device according to this embodiment will be described. In the following description, structural elements identical to those described in the above-described embodiments are denoted by the same reference numerals and illustrated, and detailed descriptions thereof are appropriately omitted.

[0063] <Regarding the structure of the semiconductor device> Figure 11 is a diagram schematically showing an example of the circuit structure of the semiconductor device according to the embodiment. As Figure 11 shown in the example, the drive circuit 100E in the semiconductor device includes: a source MOSFET 24 connected between the gate terminal 20A for controlling conduction and cutoff of the Si element and the potential VCC; a sink MOSFET 26 connected between the gate terminal 22A for controlling conduction and cutoff of the SiC element and the reference potential VNC; a source-sink connection MOSFET 28 connecting between the gate terminals of both the Si element and the SiC element (that is, connecting between the gate terminal 20A for controlling conduction and cutoff of the Si-IGBT 20 and the gate terminal 22A for controlling conduction and cutoff of the SiC-MOSFET 22); a control circuit 30 that causes these MOSFETs (the source MOSFET 24, the sink MOSFET 26, and the source-sink connection MOSFET 28) to perform conduction and cutoff state transitions in a prescribed order; a Si-IGBT gate voltage monitor 40 that detects the gate voltage of the Si-IGBT 20; and a SiC-MOSFET gate voltage monitor 42 that detects the gate voltage of the SiC-MOSFET 22. A parallel connection circuit 200 is connected to the drive circuit 100E.

[0064] Figure 11 In the structure shown, the control circuit 30 can control the timing of the state transition of the one that performs the state transition later (from the on state to the off state, or from the off state to the on state) between the Si-IGBT 20 and the SiC-MOSFET 22 based on the gate voltage of the Si-IGBT 20 detected by the Si-IGBT gate voltage monitor 40 and the gate voltage of the SiC-MOSFET 22 detected by the SiC-MOSFET gate voltage monitor 42.

[0065] In the case of a circuit structure other than this, for example, in the on state, the source-drain connection MOSFET 28 is set to the off state to charge the gate of the Si-IGBT 20, and the Si-IGBT 20 is set to the on state to start charging the gate of the SiC-MOSFET 22. Therefore, a certain margin is set for the time until the source-drain connection MOSFET 28 is set to the on state again, so that the SiC-MOSFET 22 does not become conductive before the Si-IGBT 20.

[0066] In this case, the time during which the SiC-MOSFET 22, which is effective for efficiency improvement, is in the on state may be shortened.

[0067] Therefore, by monitoring the gate voltage of the Si-IGBT 20 with the Si-IGBT gate voltage monitor 40 and immediately changing the source-drain connection MOSFET 28 to the on state at the moment when the conduction operation of the Si-IGBT 20 is confirmed, the gate charging of the SiC-MOSFET 22 can be started quickly, thereby improving the system efficiency.

[0068] Figure 12 It is a diagram showing an example of the operation of the Si element and the operation of the SiC element according to the present embodiment.

[0069] As Figure 12 As shown in the example in [ ], by monitoring the gate voltage of the Si-IGBT 20 with the Si-IGBT gate voltage monitor 40 and immediately changing the source-drain connection MOSFET 28 to the on state at the moment (X1) when the conduction operation of the Si-IGBT 20 is confirmed (that is, minimizing the time difference between X1 and X2), the gate charging (conduction operation) of the SiC-MOSFET 22 can be started quickly.

[0070] Similarly, by monitoring the gate voltage of the SiC-MOSFET 22 with the SiC-MOSFET gate voltage monitor 42 and immediately changing the source-drain connection MOSFET 28 to the on state at the moment (X3) when the conduction operation of the SiC-MOSFET 22 is confirmed (that is, minimizing the time difference between X3 and X4), the gate discharge (turn-off operation) of the Si-IGBT 20 can be started quickly.

[0071] <Embodiment 6> The semiconductor device according to the present embodiment will be described. In the following description, the same reference numerals are given to the structural elements that are the same as those described in the above embodiments, and the detailed description thereof is appropriately omitted.

[0072] <Regarding the structure of the semiconductor device> Figure 13 is a diagram schematically showing an example of the circuit structure of a semiconductor device according to an embodiment. As Figure 13 shown in the example, the drive circuit 100F in the semiconductor device includes: a source MOSFET 24 connected between the gate terminal 20A for controlling conduction and cutoff of the Si element and the potential VCC2; a sink MOSFET 26 connected between the gate terminal 22A for controlling conduction and cutoff of the SiC element and the reference potential VNC; a source-drain connection MOSFET 28 connecting between the gate terminals of both the Si element and the SiC element (that is, connecting between the gate terminal 20A for controlling conduction and cutoff of the Si-IGBT 20 and the gate terminal 22A for controlling conduction and cutoff of the SiC-MOSFET 22); a control circuit 30 that causes these MOSFETs (the source MOSFET 24, the sink MOSFET 26, and the source-drain connection MOSFET 28) to transfer between conduction and cutoff states in a prescribed order; and an internal power supply circuit 52 connected to the control circuit 30 and the source MOSFET 24, inputting the potential VCC to the control circuit 30 and inputting the potential VCC2 to the source MOSFET 24. However, the potential VCC2 is set to a voltage higher than the potential VCC, and may be the same potential as the Figure 7 shown potential VCC2, or may be a different potential. In addition, a parallel connection circuit 200 is connected to the drive circuit 100F.

[0073] Figure 3 In the circuit structure shown, the gate voltage of the SiC-MOSFET 22 is provided via the source-drain connection MOSFET 28, and thus, it may be lower than the gate voltage of the Si-IGBT 20. As a result, the DC characteristics may deteriorate, leading to a decrease in the operation efficiency.

[0074] Therefore, Figure 13 in the structure shown, it can be boosted to a potential VCC2 higher than the potential VCC by the internal power supply circuit 52 and then supplied to the source MOSFET 24, which can increase the gate voltage of the SiC-MOSFET 22. Thereby, deterioration of the DC characteristics can be suppressed and the operation efficiency can be maintained.

[0075] <Embodiment 7> The semiconductor device according to the present embodiment will be described. In addition, in the following description, structural elements identical to those described in the above-described embodiments are denoted by the same reference numerals and illustrated, and detailed descriptions thereof are appropriately omitted.

[0076] <Regarding the structure of the semiconductor device> Figure 14 is a diagram schematically showing an example of the circuit structure of the semiconductor device according to the embodiment. As Figure 14 shown in the example, the drive circuit 100G in the semiconductor device includes: a source MOSFET 24 connected between the gate terminal 20A for controlling conduction and cutoff of the Si element and the potential VCC2; a sink MOSFET 26 connected between the gate terminal 22A for controlling conduction and cutoff of the SiC element and the reference potential VNC; a source-sink connection MOSFET 28 connecting between the gate terminals of both the Si element and the SiC element (that is, connecting between the gate terminal 20A for controlling conduction and cutoff of the Si-IGBT 20 and the gate terminal 22A for controlling conduction and cutoff of the SiC-MOSFET 22); a control circuit 30 that causes these MOSFETs (the source MOSFET 24, the sink MOSFET 26, and the source-sink connection MOSFET 28) to transfer between conduction and cutoff states in a specified order; an internal power supply circuit 52 connected to the control circuit 30 and the source MOSFET 24, inputting the potential VCC to the control circuit 30 and inputting the potential VCC2 to the source MOSFET 24; and a current detection circuit 54 that detects the current value in the emitter terminal of the Si-IGBT 20. Here, it is assumed that the potential VCC2 is a voltage higher than the potential VCC. In addition, a parallel connection circuit 200 is connected to the drive circuit 100G.

[0077] The current detection circuit 54 feeds back the detected current value to the control circuit 30. Then, the control circuit 30 can control whether to boost the potential VCC to the potential VCC2 in the internal power supply circuit 52 and input it to the source MOSFET 24 based on the magnitude of the current value input from the current detection circuit 54. Specifically, the control circuit 30 can boost the potential VCC to the potential VCC2 in the internal power supply circuit 52 and input it to the source MOSFET 24 only when the magnitude of the current value input from the current detection circuit 54 is larger than a predetermined threshold.

[0078] Figure 15 is a diagram showing an example of the DC characteristics of the MOSFET. As Figure 15 shown in the example, as the voltage value rises, the decrease in the current value becomes significant (deterioration of the DC characteristics can be observed).

[0079] According to this structure, the current consumption in the internal power supply circuit 52 can be reduced, and the deterioration of the DC characteristics can be suppressed while maintaining the operation efficiency.

[0080] <Embodiment 8> A semiconductor device according to this embodiment will be described. In the following description, structural elements identical to those described in the above-described embodiments are denoted by the same reference numerals and illustrated, and their detailed descriptions are appropriately omitted.

[0081] <Regarding the structure of the semiconductor device> Figure 16 FIG. is a diagram schematically showing an example of the circuit structure of the semiconductor device according to the embodiment. Figure 16 The structure shown, for example, is a circuit for inverter driving a motor for rotating a compressor of an air conditioner.

[0082] As Figure 16 shown in the example, in this circuit, two parallel connection circuits 200 are connected in series to a load 2000 such as a motor, and a plurality of series-connected parallel connection circuits 200 are connected in parallel. A drive circuit 1000 for driving the gates is connected to each parallel connection circuit 200. The drive circuit 1000 is, for example, drive circuit 100A, drive circuit 100B, drive circuit 100C, drive circuit 100D, drive circuit 100E, drive circuit 100F, drive circuit 100G, etc.

[0083] Figure 16 In the circuit shown, as Figure 17 shown, dv / dt is generated by one of the switches of Si-IGBT 20 and SiC-MOSFET 22, and due to this dv / dt, current sometimes flows through the parasitic capacitance between C-G or D-G of the semiconductor element in the off state. Then, the gate voltage of the semiconductor element in the off state is charged, and it may inadvertently transition to the on state and become an abnormal state. In addition, Figure 17 FIG. is a diagram showing an example of the operation of Si-IGBT 20 and SiC-MOSFET 22.

[0084] To prevent such malfunction, generally the following method is adopted: In order to reduce the impedance between the gate and the reference potential to quickly attract this current, an additional sink MOSFET is arranged, and the additional sink MOSFET is transferred to the on state after the normal off state transition of the semiconductor element.

[0085] Figure 18 FIG. is a diagram showing an example of a drive circuit having a general parallel connection circuit. As Figure 18As shown in the example, the drive circuit 100H includes: a control signal generation circuit 12 that receives an input signal; a gate drive circuit 14 that receives a control signal 12A from the control signal generation circuit 12; a gate drive circuit 16 that receives a control signal 12B from the control signal generation circuit 12; a sink MOSFET 13 connected between the gate terminal 20A and the reference potential VNC; and a sink MOSFET 15 connected between the gate terminal 22A and the reference potential VNC. The Si-IGBT 20 that receives a gate signal at the gate terminal 20A from the gate drive circuit 14 and the SiC-MOSFET 22 that receives a gate signal at the gate terminal 22A from the gate drive circuit 16 are connected to the drive circuit 100H.

[0086] Figure 18 In the structure shown, the gate drive circuit 14 of the Si-IGBT 20 and the gate drive circuit 16 of the SiC-MOSFET 22 are separated. Therefore, a dual system of additional sink MOSFETs (sink MOSFET 13 and sink MOSFET 15) is required. As a result, the circuit scale increases.

[0087] Figure 19 It is a diagram schematically showing an example of the circuit structure of the semiconductor device according to the embodiment. Figure 19 As shown in the example, the drive circuit 100J in the semiconductor device includes: a source MOSFET 24 connected between the gate terminal 20A for conducting and turning off the Si-IGBT 20 and the potential VCC; a sink MOSFET 26 connected between the gate terminal 22A for conducting and turning off the SiC-MOSFET 22 and the reference potential VNC; a source-drain connection MOSFET 28 that connects between the gate terminals of both the Si element and the SiC element (that is, connects between the gate terminal 20A for conducting and turning off the Si-IGBT 20 and the gate terminal 22A for conducting and turning off the SiC-MOSFET 22); a sink MOSFET 13A connected between the gate terminal 20A and the reference potential VNC; and a control circuit 30 that causes these MOSFETs (source MOSFET 24, sink MOSFET 26, source-drain connection MOSFET 28, sink MOSFET 13A) to transfer between conduction and non-conduction states in a specified order. A parallel connection circuit 200 is connected to the drive circuit 100J.

[0088] According to Figure 19In the structure shown, the gate terminals 20A and 22A are connected by the source-drain connection using MOSFET 28. Therefore, by disposing one additional drain MOSFET 13A for either the gate of the Si-IGBT 20 or the gate of the SiC-MOSFET 22, the same effect as Figure 18 can be obtained.

[0089] Figure 20 FIG. is a diagram showing examples of the operations of the Si element and the SiC element according to the present embodiment.

[0090] As Figure 20 shown in the example, when an input signal (turn-on signal) related to the turn-on operation is input to the control circuit 30, the drain MOSFET 13A transitions to the off state. After an input signal (turn-off signal) related to the turn-off operation is input to the control circuit 30, the drain MOSFET 13A further transitions to the on state after the Si-IGBT 20 transitions to the off state. Thereby, the gate potential of the Si-IGBT 20 can be maintained at the reference potential VNC.

[0091] <Embodiment 9> The semiconductor device according to the present embodiment will be described. In the following description, structural elements that are the same as those described in the above-described embodiments are denoted by the same reference numerals and illustrated, and detailed descriptions thereof are appropriately omitted.

[0092] <Regarding the Structure of the Semiconductor Device> Figure 19 In the structure shown, the drain MOSFET 13A is connected to the gate of the Si-IGBT 20 that first transitions to the on state. In this case, the gate of the SiC-MOSFET 22 and the drain MOSFET 13A may be connected via a drain diode. Figure 21 FIG. is a diagram showing an example of a structure in which the gate of the SiC-MOSFET 22 and the drain MOSFET 13A are connected via a drain diode 113. In addition, Figure 21 in, the anode of the drain diode 113 is on the gate side of the SiC-MOSFET 22.

[0093] In the case where the drain diode 113 is not provided, a source-drain connection MOSFET 28 is provided in the path where current converges from the gate of the SiC-MOSFET 22 via the drain MOSFET 13A, and thus, the current converging ability may be affected.

[0094] Therefore, by providing the drain diode 113 and converging current in parallel through two paths, the current converging ability can be improved.

[0095] As Figure 22As shown in the example, the gate of the Si-IGBT20 that first transitions to the on state is charged first. Therefore, the reason for providing the common-use diode 113 without directly connecting it through wiring is to prevent the charging of the gate of the SiC-MOSFET22 that will later transition to the on state at this time. In the case where the common-use diode 113 is not provided, in the Figure 22 state of Y, the gate of the SiC-MOSFET22 is charged. In addition, Figure 22 is a diagram showing an example of the operation of the Si element and the operation of the SiC element according to the present embodiment.

[0096] <Regarding the effects produced by the above-described multiple embodiments> Next, examples of the effects produced by the above-described multiple embodiments are shown. In addition, in the following description, the effects are described based on the specific structures shown in the examples in the above-described multiple embodiments. However, within the range where the same effects are produced, they can be replaced with other specific structures shown in the examples in the present specification. That is, hereinafter, for convenience, sometimes only one of the corresponding specific structures is representatively described, but it can also be replaced with other specific structures corresponding to the representatively described specific structure.

[0097] In addition, this replacement can also span multiple embodiments. That is, it is also possible to combine the respective structures exemplified in different embodiments to produce the same effect.

[0098] According to the embodiments described above, the semiconductor device includes a first semiconductor element, a second semiconductor element, a first source semiconductor element, a first drain semiconductor element, a source-drain connection semiconductor element, and a control circuit 30. Here, the first semiconductor element corresponds to, for example, a Si-IGBT 20 or the like. In addition, the second semiconductor element corresponds to, for example, a SiC-MOSFET 22 or the like. In addition, the first source semiconductor element corresponds to, for example, a source MOSFET 24 or the like. In addition, the first drain semiconductor element corresponds to, for example, a drain MOSFET 26 or the like. In addition, the source-drain connection semiconductor element corresponds to, for example, a source-drain connection MOSFET 28, a source-drain connection MOSFET 128, or the like. The SiC-MOSFET 22 is connected in parallel with the Si-IGBT 20. The source MOSFET 24 is connected between the first power supply potential (for example, potential VCC) and the gate terminal 20A of the Si-IGBT 20. The drain MOSFET 26 is connected between the reference potential VNC and the gate terminal 22A of the SiC-MOSFET 22. The source-drain connection MOSFET 28 is connected between the gate terminal 20A of the Si-IGBT 20 and the gate terminal 22A of the SiC-MOSFET 22. The control circuit 30 controls the transition of the on / off states of the source MOSFET 24, the drain MOSFET 26, and the source-drain connection MOSFET 28 so that the on state is transferred in the order of the Si-IGBT 20 and the SiC-MOSFET 22, and the off state is transferred in the order of the SiC-MOSFET 22 and the Si-IGBT 20.

[0099] According to this structure, the transition of the on / off states of the Si element and the SiC element can be controlled by a simple circuit structure including the source-drain connection semiconductor element.

[0100] In addition, in the case where other structures exemplified in the present application specification are appropriately added to the above structure, that is, in the case where other structures not mentioned in the present application specification are appropriately added as the above structure, the same effect can also be obtained.

[0101] In addition, according to the embodiments described above, the control circuit 30 causes the Si-IGBT 20 to transition to the on state by turning off the source-drain connection MOSFET 28, and then causes the SiC-MOSFET 22 to transition to the on state by turning on the source-drain connection MOSFET 28. In addition, the control circuit 30 causes the SiC-MOSFET 22 to transition to the off state by turning off the source-drain connection MOSFET 28, and then causes the SiC-MOSFET 22 to transition to the off state by turning on the source-drain connection MOSFET 28. According to this structure, the transition of the on / off states of the Si element and the SiC element can be controlled by a simple circuit structure including the source-drain connection semiconductor element. Specifically, the control for generating a delay in the on / off operations of the Si element and the SiC element can be performed by a simple circuit structure without separately providing a gate drive circuit for generating a delay in the on / off operations for the Si element and the SiC element.

[0102] In addition, according to the embodiments described above, the semiconductor device includes a second source semiconductor device and a second drain semiconductor device. Here, the second source semiconductor element corresponds to, for example, the source MOSFET 32 or the like. In addition, the second drain semiconductor element corresponds to, for example, the drain MOSFET 34 or the like. The source MOSFET 32 is connected to the gate terminal 28A of the source-drain connection MOSFET 28. In addition, the source MOSFET 32 charges the gate of the source-drain connection MOSFET 28. The drain MOSFET 34 is connected to the gate terminal 28A of the source-drain connection MOSFET 28. In addition, the drain MOSFET 34 discharges the gate of the source-drain connection MOSFET 28. The source-drain connection MOSFET 28 is an N-channel MOSFET. In addition, the source-drain connection MOSFET 28 is connected to the potential VCC via the source MOSFET 24. In addition, the source-drain connection MOSFET 28 is connected to a second power supply potential (for example, the potential VCC2), which is higher than the potential VCC, via the source MOSFET 32. According to this structure, even when the source-drain connection semiconductor element is an N-channel MOSFET, the gate voltage of the SiC-MOSFET 22 can be charged to the potential VCC. Therefore, it is possible to suppress the gate voltage of the SiC-MOSFET 22 from becoming insufficient and suppress the deterioration of the DC characteristics.

[0103] In addition, according to the embodiment described above, the source-drain connection MOSFET 128 is a component obtained by connecting an N-channel MOSFET 128A and a P-channel MOSFET 128B in parallel. Then, the N-channel MOSFET 128A and the P-channel MOSFET 128B are connected between the gate terminal 20A of the Si-IGBT 20 and the gate terminal 22A of the SiC-MOSFET 22. In addition, the on-state and off-state of the Si-IGBT 20 and the SiC-MOSFET 22 are synchronized with each other. According to this structure, when the N-channel MOSFET 128A of the source-drain connection MOSFET 128 is in the off state when the gate voltage of the SiC-MOSFET 22 rises, the P-channel MOSFET 128B can also be in the on state. Thereby, the gate voltage of the SiC-MOSFET 22 can be sufficiently charged without using an additional power supply circuit, and thus, the deterioration of the DC characteristics can be suppressed.

[0104] In addition, according to the embodiment described above, the semiconductor device includes a first gate voltage detector and a second gate voltage detector. Here, the first gate voltage detector corresponds to, for example, the Si-IGBT gate voltage monitor 40 or the like. In addition, the second gate voltage detector corresponds to, for example, the SiC-MOSFET gate voltage monitor 42 or the like. The Si-IGBT gate voltage monitor 40 detects the gate voltage of the Si-IGBT 20 as the first gate voltage. The SiC-MOSFET gate voltage monitor 42 detects the gate voltage of the SiC-MOSFET 22 as the second gate voltage. Then, the control circuit 30 controls the switching timing of the one that performs the on / off state transition later between the Si-IGBT 20 and the SiC-MOSFET 22 based on the first gate voltage and the second gate voltage. According to this structure, at the moment (X1) when the conduction operation of the Si-IGBT 20 is confirmed, the source-drain connection MOSFET 28 is immediately switched to the on state, so that the gate charging of the SiC-MOSFET 22 can be started quickly. In addition, at the moment (X3) when the turn-off operation of the SiC-MOSFET 22 is confirmed, the source-drain connection MOSFET 28 is immediately switched to the on state, so that the gate discharge of the Si-IGBT 20 can be started quickly.

[0105] In addition, according to the embodiment described above, the semiconductor device includes an internal power supply circuit 52, which is connected to the potential VCC and can output a potential VCC2 higher than the potential VCC. Then, the source MOSFET 24 is connected between the internal power supply circuit 52 and the gate terminal 20A of the Si-IGBT 20. According to this structure, the potential can be boosted to a potential VCC2 higher than the potential VCC by the internal power supply circuit 52 and then supplied to the source MOSFET 24, and the gate voltage of the SiC-MOSFET 22 can be increased. Thereby, the deterioration of the DC characteristics can be suppressed and the operation efficiency can be maintained.

[0106] In addition, according to the embodiment described above, the semiconductor device includes a current detection circuit 54 that detects the current flowing through the parallel connection circuit 200, and the parallel connection circuit includes the Si-IGBT 20 and the SiC-MOSFET 22. Then, the control circuit 30 controls whether to output the potential VCC or the potential VCC2 from the internal power supply circuit 52 to the source MOSFET 24 according to the value of the current detected by the current detection circuit 54. According to this structure, the current consumption in the internal power supply circuit 52 can be reduced, the deterioration of the DC characteristics can be suppressed, and the operation efficiency can be maintained.

[0107] In addition, according to the embodiment described above, the semiconductor device includes a third sink semiconductor element connected between the gate terminal 20A of the Si-IGBT 20 and the reference potential VNC. Here, the third sink semiconductor element corresponds to, for example, the sink MOSFET 13A or the like. Then, the control circuit 30 sets the sink MOSFET 13A to the on state after the off state transition of the Si-IGBT 20 and keeps the gate potential of the Si-IGBT 20 at the reference potential VNC. According to this structure, the number of semiconductor elements for keeping the gate potential of the Si-IGBT 20 at the reference potential VNC can be set to one, so the expansion of the circuit scale can be suppressed.

[0108] In addition, according to the embodiment described above, the semiconductor device includes a sink diode 113 connected between the gate terminal 22A of the SiC-MOSFET 22 and the sink MOSFET 13A. According to this structure, the current sinking ability for maintaining the off state can be improved.

[0109] In addition, according to the embodiments described above, a plurality of parallel connection circuits 200 in which Si-IGBTs 20 and SiC-MOSFETs 22 are connected in parallel are connected in series and in parallel. Then, a drive circuit 1000 is connected to each of the parallel connection circuits 200. The drive circuit 1000 includes a source MOSFET 24, a sink MOSFET 26, a source-sink connection MOSFET 28, and a control circuit 30. According to this structure, in a semiconductor device including a plurality of parallel connection circuits 200, the drive circuit 1000 corresponding to each of the parallel connection circuits 200 has a simple circuit structure including a source-sink connection semiconductor element, so that the transition of the conduction and cutoff states of the Si element and the SiC element can be effectively controlled.

[0110] In addition, according to the embodiments described above, the semiconductor device includes: an Si-IGBT 20; an SiC-MOSFET 22 connected in parallel with the Si-IGBT 20; a source MOSFET 24 connected between the potential VCC and the gate terminal 20A of the Si-IGBT 20; a sink MOSFET 26 connected between the reference potential VNC and the gate terminal 22A of the SiC-MOSFET 22; a source-sink connection resistor 228 connected between the gate terminal 20A of the Si-IGBT 20 and the gate terminal 22A of the SiC-MOSFET 22; and a control circuit 30 that controls the transition of the conduction and cutoff states of the source MOSFET 24 and the sink MOSFET 26 so as to transition to the conduction state in the order of the Si-IGBT 20 and the SiC-MOSFET 22, and transition to the cutoff state in the order of the SiC-MOSFET 22 and the Si-IGBT 20.

[0111] According to this structure, the transition of the conduction and cutoff states of the Si element and the SiC element can be controlled by a simple structure without controlling the gate drive of the source-sink connection semiconductor element.

[0112] In addition, according to the embodiments described above, the gate terminal of the source MOSFET 24 and the gate terminal of the sink MOSFET 26 are connected to the control circuit 30. According to this structure, the gate voltage of the source MOSFET 24 and the gate voltage of the sink MOSFET 26 can be controlled, and the transition of the conduction and cutoff states of the Si-IGBT 20 and the SiC-MOSFET 22 can be controlled.

[0113] In addition, according to the embodiments described above, the SiC-MOSFET 22 is a semiconductor device composed of a wide-bandgap semiconductor. The allowable current of the SiC-MOSFET 22 is lower than that of the Si-IGBT 20. With this structure, by using a semiconductor device composed of a wide-bandgap semiconductor, it is possible to achieve cost reduction due to small size and improvement in efficiency (i.e., reduction in loss) due to good DC characteristics at low current.

[0114] <Modifications of the Multiple Embodiments Described Above> In the multiple embodiments described above, the materials, materials, dimensions, shapes, relative arrangement relationships, or implementation conditions of each structural element may sometimes be described, but these are all examples in all aspects and are not restrictive.

[0115] Therefore, it can be considered that countless modifications and equivalent inventions not described in this example can be envisioned within the technical scope disclosed in this application specification. For example, it is assumed to include cases where at least one structural element is modified, added, or omitted, and cases where at least one structural element in at least one embodiment is extracted and combined with the structural elements of other embodiments.

[0116] In addition, in at least one of the embodiments described above, when a material name or the like is described without special specification, unless there is a contradiction, it is assumed that other additives, such as alloys, are included in the material.

[0117] In addition, unless there is a contradiction, when a structural element described as having "one" in the embodiments described above, the structural element may also have "one or more".

[0118] In addition, each structural element in the embodiments described above is a conceptual unit, and within the technical scope disclosed in this application specification, there are cases where one structural element is composed of multiple structures, cases where one structural element corresponds to a part of a certain structure, and cases where multiple structural elements are included in one structure.

[0119] In addition, each structural element in the embodiments described above, as long as it performs the same function, includes structures or shapes with other structures.

[0120] In addition, the descriptions in this application specification are for reference for all purposes related to this technology and are not considered to be prior art content.

[0121] Hereinafter, each aspect of the present disclosure will be summarized and described as an appendix.

[0122] (Appendix 1) A semiconductor device, comprising: The first semiconductor element; The second semiconductor element, which is connected in parallel with the first semiconductor element; The first source semiconductor element, which is connected between the first power supply potential and the gate terminal of the first semiconductor element; The first drain semiconductor element, which is connected between the reference potential and the gate terminal of the second semiconductor element; The source-drain connection semiconductor element, which is connected between the gate terminal of the first semiconductor element and the gate terminal of the second semiconductor element; and A control circuit for controlling the transfer of the on-off states of the first source semiconductor element, the first drain semiconductor element, and the source-drain connection semiconductor element so that the conduction states are transferred in the order of the first semiconductor element and the second semiconductor element, and the off states are transferred in the order of the second semiconductor element and the first semiconductor element.

[0123] (Supplementary Note 2) The semiconductor device according to Supplementary Note 1, The control circuit transfers the first semiconductor element to the on state by setting the source-drain connection semiconductor element to the off state, and then transfers the second semiconductor element to the on state by setting the source-drain connection semiconductor element to the on state, And the control circuit transfers the second semiconductor element to the off state by setting the source-drain connection semiconductor element to the off state, and then transfers the second semiconductor element to the off state by setting the source-drain connection semiconductor element to the on state.

[0124] (Supplementary Note 3) The semiconductor device according to Supplementary Note 1 or 2 further includes: The second source semiconductor element, which is connected to the gate terminal of the source-drain connection semiconductor element and charges the gate of the source-drain connection semiconductor element; and The second drain semiconductor element, which is connected to the gate terminal of the source-drain connection semiconductor element and discharges the gate of the source-drain connection semiconductor element, The source-drain connection semiconductor element is an N-channel MOSFET, Connected to the first power supply potential via the first source semiconductor element, Connected to the second power supply potential, which is higher than the first power supply potential, via the second source semiconductor element.

[0125] (Supplementary Note 4) The semiconductor device according to any one of Supplementary Notes 1 to 3, The semiconductor element for source-drain connection is an element obtained by connecting an N-channel MOSFET and a P-channel MOSFET in parallel, The N-channel MOSFET and the P-channel MOSFET are connected between the gate terminal of the first semiconductor element and the gate terminal of the second semiconductor element, The on-state and off-state of the first semiconductor element and the second semiconductor element are synchronized with each other.

[0126] (Supplementary Note 5) The semiconductor device according to any one of Supplementary Notes 1 to 4 further includes: A first gate voltage detector that detects the gate voltage of the first semiconductor element as a first gate voltage; and A second gate voltage detector that detects the gate voltage of the second semiconductor element as a second gate voltage, The control circuit controls the transfer timing of the one of the first semiconductor element and the second semiconductor element that undergoes the on-off state transition later based on the first gate voltage and the second gate voltage.

[0127] (Supplementary Note 6) The semiconductor device according to any one of Supplementary Notes 1 to 5 Further includes an internal power supply circuit that is connected to the first power supply potential and can output a second power supply potential higher than the first power supply potential, The first source semiconductor element is connected between the internal power supply circuit and the gate terminal of the first semiconductor element.

[0128] (Supplementary Note 7) The semiconductor device according to Supplementary Note 6 Further includes a current detection circuit that detects the current flowing through the parallel connection circuit including the first semiconductor element and the second semiconductor element, The control circuit controls whether to output the first power supply potential or the second power supply potential from the internal power supply circuit to the first source semiconductor element according to the value of the current detected by the current detection circuit.

[0129] (Supplementary Note 8) The semiconductor device according to any one of Supplementary Notes 1 to 7 Further includes a third drain semiconductor element that is connected between the gate terminal of the first semiconductor element and the reference potential, After the turn-off state transition of the first semiconductor element, the control circuit sets the third shared semiconductor element to the on state and maintains the gate potential of the first semiconductor element at the reference potential.

[0130] (Supplementary Note 9) The semiconductor device as described in Supplementary Note 8, further includes a shared diode connected between the gate terminal of the second semiconductor element and the third shared semiconductor element.

[0131] (Supplementary Note 10) The semiconductor device as described in any one of Supplementary Notes 1 to 9, performs series connection and parallel connection on a plurality of parallel connection circuits in which the first semiconductor element and the second semiconductor element are connected in parallel, and a drive circuit is connected to each of the parallel connection circuits, and the drive circuit includes the first source semiconductor element, the first shared semiconductor element, the source-shared connection semiconductor element, and the control circuit.

[0132] (Supplementary Note 11) A semiconductor device, comprising: a first semiconductor element; a second semiconductor element connected in parallel with the first semiconductor element; a first source semiconductor element connected between a first power supply potential and the gate terminal of the first semiconductor element; a first shared semiconductor element connected between a reference potential and the gate terminal of the second semiconductor element; a source-shared connection resistor connected between the gate terminal of the first semiconductor element and the gate terminal of the second semiconductor element; and a control circuit that controls the turn-on and turn-off state transitions of the first source semiconductor element and the first shared semiconductor element so that the conduction states are transferred in the order of the first semiconductor element and the second semiconductor element, and the turn-off states are transferred in the order of the second semiconductor element and the first semiconductor element.

[0133] (Supplementary Note 12) The semiconductor device as described in any one of Supplementary Notes 1 to 11, the gate terminals of the first source semiconductor element and the first shared semiconductor element are connected to the control circuit.

[0134] (Supplementary Note 13) The semiconductor device as described in any one of Supplementary Notes 1 to 12, the second semiconductor element is a semiconductor element made of a wide bandgap semiconductor, The allowable current of the second semiconductor element is lower than that of the first semiconductor element. Reference Designations

[0135] 12 Control signal generation circuit 12A Control signal 12B Control signal 13 Common-use MOSFET 13A Common-use MOSFET 15 Common-use MOSFET 14 Gate drive circuit 16 Gate drive circuit 20 Si-IGBT 20A Gate terminal 22 SiC-MOSFET 22A Gate terminal 24 Source-use MOSFET 24A Gate terminal 26 Common-use MOSFET 26A Gate terminal 28 Source-drain connection-use MOSFET 28A Gate terminal 30 Control circuit 30A Control circuit 32 Source-use MOSFET 34 Common-use MOSFET 40 Si-IGBT Gate voltage monitor 42 SiC-MOSFET Gate voltage monitor 50 Internal power supply circuit 52 Internal power supply circuit 54 Current detection circuit 100 Drive circuit 100A Drive circuit 100B Drive circuit 100C Drive circuit 100D Drive circuit 100E Drive circuit 100F Drive circuit 100G Drive circuit 100H Drive circuit 100J Drive circuit 113 Common-use diode 128 Source-drain connection-use MOSFET 128A N-channel MOSFET 128B P-channel MOSFET 128C Inverter 200 Parallel connection circuit 228 Resistor for source-drain connection 1000 Driver circuit 2000 Load

Claims

1. A semiconductor device, characterized in that, Comprising: A first semiconductor element; A second semiconductor element, which is connected in parallel with the first semiconductor element; A first source semiconductor element, which is connected between a first power supply potential and the gate terminal of the first semiconductor element; A first sink semiconductor element, which is connected between a reference potential and the gate terminal of the second semiconductor element; A source-sink connection semiconductor element, which is connected between the gate terminal of the first semiconductor element and the gate terminal of the second semiconductor element; And A control circuit, which is used to control the conduction and cutoff state transitions of the first source semiconductor element, the first sink semiconductor element, and the source-sink connection semiconductor element, so that the conduction states are transferred in the order of the first semiconductor element and the second semiconductor element, and the cutoff states are transferred in the order of the second semiconductor element and the first semiconductor element.

2. The semiconductor device according to claim 1, characterized in that The control circuit makes the first semiconductor element transfer to the conduction state by setting the source-sink connection semiconductor element to the cutoff state, and then makes the second semiconductor element transfer to the conduction state by setting the source-sink connection semiconductor element to the conduction state, And, the control circuit makes the second semiconductor element transfer to the cutoff state by setting the source-sink connection semiconductor element to the cutoff state, and then makes the second semiconductor element transfer to the cutoff state by setting the source-sink connection semiconductor element to the conduction state.

3. The semiconductor device according to claim 1 or 2, wherein Further comprising: A second source semiconductor element, which is connected to the gate terminal of the source-sink connection semiconductor element and charges the gate of the source-sink connection semiconductor element; And A second sink semiconductor element, which is connected to the gate terminal of the source-sink connection semiconductor element and discharges the gate of the source-sink connection semiconductor element, The source-sink connection semiconductor element is an N-channel MOSFET, Connected to the first power supply potential via the first source semiconductor element, Connected to a second power supply potential, which is higher than the first power supply potential, via the second source semiconductor element.

4. The semiconductor device according to claim 1 or 2, characterized in that The source-sink connection semiconductor element is an element obtained by connecting an N-channel MOSFET and a P-channel MOSFET in parallel, The N-channel MOSFET and the P-channel MOSFET are connected between the gate terminal of the first semiconductor element and the gate terminal of the second semiconductor element, The conduction states and cutoff states of the first semiconductor element and the second semiconductor element are synchronized with each other.

5. The semiconductor device according to claim 1 or 2, characterized in that, Further comprising: A first gate voltage detector, which detects the gate voltage of the first semiconductor element as a first gate voltage; And A second gate voltage detector that detects the gate voltage of the second semiconductor element as a second gate voltage. The control circuit controls the transfer timing of the one of the first semiconductor element and the second semiconductor element that undergoes a conduction-off state transition based on the first gate voltage and the second gate voltage.

6. The semiconductor device according to claim 1 or 2, characterized in that It further includes an internal power supply circuit that is connected to the first power supply potential and can output a second power supply potential higher than the first power supply potential. The first source semiconductor element is connected between the internal power supply circuit and the gate terminal of the first semiconductor element.

7. The semiconductor device according to claim 6, characterized in that It further includes a current detection circuit that detects the current flowing through a parallel connection circuit including the first semiconductor element and the second semiconductor element. The control circuit controls whether to output the first power supply potential or the second power supply potential from the internal power supply circuit to the first source semiconductor element according to the value of the current detected by the current detection circuit.

8. The semiconductor device according to claim 1 or 2, characterized in that It further includes a third sink semiconductor element that is connected between the gate terminal of the first semiconductor element and the reference potential. The control circuit sets the third sink semiconductor element to a conductive state after the off state transition of the first semiconductor element and keeps the gate potential of the first semiconductor element at the reference potential.

9. The semiconductor device according to claim 8, characterized in that It further includes a sink diode that is connected between the gate terminal of the second semiconductor element and the third sink semiconductor element.

10. The semiconductor device according to claim 1 or 2, characterized in that A plurality of parallel connection circuits in which the first semiconductor element and the second semiconductor element are connected in parallel are connected in series and in parallel. For each of the parallel connection circuits, a drive circuit is connected, and the drive circuit includes the first source semiconductor element, the first sink semiconductor element, the source-sink connection semiconductor element, and the control circuit.

11. A semiconductor device, characterized in that, Comprising: A first semiconductor element; A second semiconductor element that is connected in parallel with the first semiconductor element; A first source semiconductor element that is connected between a first power supply potential and the gate terminal of the first semiconductor element; A first sink semiconductor element that is connected between a reference potential and the gate terminal of the second semiconductor element; A source-sink connection resistor that is connected between the gate terminal of the first semiconductor element and the gate terminal of the second semiconductor element; And A control circuit that controls the transition of the conduction and cutoff states of the first source semiconductor element and the first sink semiconductor element so that the conduction states are transferred in the order of the first semiconductor element and the second semiconductor element, and the cutoff states are transferred in the order of the second semiconductor element and the first semiconductor element.

12. The semiconductor device according to claim 1, 2, or 11, wherein the gate terminals of the first source semiconductor element and the first sink semiconductor element are connected to the control circuit.

13. The semiconductor device according to claim 1, 2, or 11, wherein the second semiconductor element is a semiconductor element made of a wide bandgap semiconductor, and the allowable current amount of the second semiconductor element is lower than the allowable current amount of the first semiconductor element.

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