Dual-mode electrosurgical high-frequency voltage inverter and feed-forward predictive control method thereof

Abstract

The invention discloses a dual-mode electrosurgical high-frequency voltage inverter and a feed-forward predictive control method thereof, and belongs to the technical field of power electronic circuits. The voltage inverter comprises a first capacitor, a second capacitor, a first switch tube, a second switch tube, a third switch tube, a fourth switch tube, a blocking capacitor, a high-frequency boosting transformer and a multi-channel interleaved parallel structure. The channel interleaving parallel structure comprises an interleaving parallel structure first switch tube, an interleaving parallel structure second switch tube and an interleaving parallel structure first filter inductor; the invention discloses double working modes of an electrosurgical high-frequency voltage inverter, which not only widens the voltage gain, but also improves the efficiency of the inverter when the two working modes are switched. The invention further provides a feed-forward predictive control method, the duty ratio can be rapidly calculated through predictive control, the dynamic response speed is increased, and the control precision of the output power is improved through power feedback control.

Description

Technical Field

[0001] The present invention relates to the technical field of power electronic circuits, and particularly relates to a dual-mode electrosurgical high-frequency voltage inverter and a feed-forward predictive control method therefor. Background Art

[0002] An electrosurgical generator is a medical device that uses the thermal effect of high-frequency alternating current for surgical cutting and tissue coagulation. Compared with a traditional mechanical scalpel, the electrosurgical generator has the advantages of fast cutting speed and good blood coagulation effect. The output current frequency range of the electrosurgical generator usually ranges from 200 kHz to 5 MHz to avoid stimulating muscles or nerves with low-frequency current. However, during a surgical operation, the load impedance of biological tissue will change widely and rapidly with the surgical time and site. In addition, different electrosurgical operations have different requirements for the output power, which requires further broadening the output voltage range of the electrosurgical generator to meet different surgical needs, while the traditional electrosurgical generator is difficult to meet a wide output voltage range.

[0003] To achieve an ideal treatment effect, the electrosurgical generator needs to maintain a constant power output when the load impedance changes widely. However, improper power control will lead to problems such as accidental burns, tissue carbonization, and tissue adhesion. Therefore, precise control of the output power is the key to the electrosurgical generator achieving an ideal surgical treatment effect. At the same time, the electrosurgical generator needs to have a high dynamic response to cope with the wide range of changes in the load impedance. Summary of the Invention

[0004] The purpose of the present invention is to overcome the defects in the above background art. The present invention proposes a dual-mode electrosurgical high-frequency voltage inverter and a feed-forward predictive control method therefor. The voltage inverter not only broadens the voltage gain but also improves the inverter efficiency. The control method uses predictive control to quickly calculate the duty cycle, improves the dynamic response, and improves the control accuracy of the output power through power feedback control.

[0005] The present invention adopts the following technical solutions to solve the above technical problems:

[0006] A dual-mode electrosurgical high-frequency voltage inverter, characterized in that the voltage inverter includes a first capacitor C1, a second capacitor C2, a first switching tube Q a , a second switching tube Q b , a third switching tube Q c , a fourth switching tube Q d , a DC-blocking capacitor C b , a high-frequency step-up transformer T r , a load resistor R L and a multi-channel interleaved parallel structure;

[0007] The interleaved parallel structure includes the first switching transistor Q of the interleaved parallel structure 1i , the second switching transistor Q of the interleaved parallel structure 2i , and the first filter inductor L of the interleaved parallel structure 1i , where i = 1, 2,..., N (N is an integer greater than or equal to 1), and i is the number of channels of the interleaved parallel structure.

[0008] One end of the first capacitor C1 is connected to the positive terminal of the DC voltage source, the other end is connected to one end of the second capacitor C2, the other end of the second capacitor C2 is connected to the negative terminal of the DC voltage source, the source of the first switching transistor Q a is connected to the source of the second switching transistor Q b , the drain of the first switching transistor Q a is connected to the connection point of the first capacitor C1 and the second capacitor C2, the drain of the second switching transistor Q b is connected to the connection point of the third switching transistor Q c and the fourth switching transistor Q d , the source of the third switching transistor Q c is connected to the drain of the fourth switching transistor Q d , the drain of the third switching transistor Q c is connected to the positive terminal of the DC voltage source and one end of the first capacitor C1, the source of the fourth switching transistor Q d is connected to the negative terminal of the DC voltage source and the other end of the second capacitor C2;

[0009] The specific interleaved parallel structure is as follows:

[0010] In the interleaved parallel structure of the i-th channel, the source of the first switching transistor Q of the interleaved parallel structure 1i is connected to the drain of the second switching transistor Q of the interleaved parallel structure 2i , the drain of the first switching transistor Q of the interleaved parallel structure 1i is connected to the drain of the third switching transistor Q c , the positive terminal of the DC voltage source, and one end of the first capacitor C1, the source of the second switching transistor Q of the interleaved parallel structure 2i is connected to the source of the fourth switching transistor Q d , the negative terminal of the DC voltage source, and the other end of the second capacitor C2;

[0011] One end of the first filter inductor L of the interleaved parallel structure 1i is connected to the connection point of the first switching transistor Q of the interleaved parallel structure 1i and the second switching transistor Q of the interleaved parallel structure 2i , and the other end of the first filter inductor L of the interleaved parallel structure 1i is connected to one end of the DC-blocking capacitor C b , and one end of the DC-blocking capacitor C bThe other end is connected to the same-named end of the primary winding of the high-frequency step-up transformer T r ; The different-named end of the primary winding of the high-frequency step-up transformer T r is connected to the third switching tube Q c and the connection point of the fourth switching tube Q d ; The secondary winding of the high-frequency step-up transformer T r is connected in parallel with the output capacitor C o and the load resistor R L .

[0012] Furthermore, when the switching frequency of the voltage inverter is f s , if an output cycle has N s switching cycles, then the output voltage frequency f o is f s / N s .

[0013] Furthermore, the voltage inverter has two operating modes:

[0014] When the inverter is in operating mode one, the first switching tube Q a and the second switching tube Q b are always on, and the third switching tube Q c and the fourth switching tube Q d are always off; when the inverter is in operating mode two, the first switching tube Q a and the second switching tube Q b are always off, and the third switching tube Q c and the fourth switching tube Q d conduct complementarily and the switching frequency is always f o .

[0015] Furthermore, the driving signal switching frequency of the first switching tube Q 1i of the interleaved parallel structure and the second switching tube Q 2i of the interleaved parallel structure is always f s ; Inside each channel, the driving signal of the first switching tube Q 1i of the interleaved parallel structure is complementary to the driving signal of the second switching tube Q 2i of the interleaved parallel structure. Between the interleaved parallel structures of adjacent channels, the driving signals between the first switching tubes Q 1i of each interleaved parallel structure are staggered by 360 / i degrees, and the driving signals between the second switching tubes Q 2i of each interleaved parallel structure are staggered by 360 / i degrees, where i = 1, 2,..., N (N is an integer greater than or equal to 1), and i is the number of channels of the interleaved parallel structure.

[0016] Furthermore, the selection of the two operating modes of the voltage inverter is specifically as follows:

[0017] Under the same load impedance and output power, compare the efficiency of the inverter in two operating modes, and select the operating mode with better efficiency on the premise that the total harmonic content of the output voltage and the output current ripple meet the requirements;

[0018] The switching between the two operating modes of the voltage inverter is specifically as follows:

[0019] When the inverter switches from operating mode one to operating mode two, control the duty cycle of the driving signals of the first switching transistor Q a and the second switching transistor Q b to decrease from 1 to 0, so that the first switching transistor and the second switching transistor are converted from the conducting state to the off state, and control the duty cycle of the driving signals of the third switching transistor Q c and the fourth switching transistor Q d to increase from 0 to the corresponding duty cycle, so that the third switching transistor and the fourth switching transistor are converted from the off state to the complementary conducting state, and complete the switching of the inverter from operating mode one to operating mode two; when the inverter switches from operating mode two to operating mode one, control the duty cycle of the driving signals of the first switching transistor Q a and the second switching transistor Q b to increase from 0 to 1, so that the first switching transistor and the second switching transistor are converted from the off state to the conducting state, and control the duty cycle of the driving signals of the third switching transistor Q c and the fourth switching transistor Q d to decrease to 0, so that the third switching transistor and the fourth switching transistor are converted from the complementary conducting state to the off state, and complete the switching of the inverter from operating mode two to operating mode one.

[0020] Furthermore, all the switching transistors in the voltage inverter are composed of a unidirectional switching transistor and a diode in reverse parallel. The capacitance values of the first capacitor C1 and the second capacitor C2 are equal, and all the interleaved parallel structure first filter inductors L 1i have equal inductance values.

[0021] Furthermore, the first switching transistor Q a , the second switching transistor Q b , the third switching transistor Q c , the fourth switching transistor Q d , the interleaved parallel structure first switching transistor Q 1i , and the interleaved parallel structure second switching transistor Q 2i are connected in parallel with a parasitic body diode and a junction capacitance. The anode of the parasitic body diode is connected to the source electrode of the switching transistor, and the cathode of the parasitic body diode is connected to the drain electrode of the switching transistor.

[0022] A feedforward predictive control method for a dual-mode electro-surgical high-frequency voltage inverter, and the feedforward predictive control method specifically includes the following steps:

[0023] Step 1: Define the voltage across the load resistor as the output voltage v o , and the current flowing through the load resistor as the output current i o . Sample the output voltage v o and the output current i o respectively;

[0024] Step 2: Multiply the output voltage v o at each sampling moment by the corresponding output current i o to obtain the instantaneous output power p o :

[0025] p o = v o i o (1)

[0026] Step 3: Calculate the average output power P o :

[0027]

[0028] where T o is the output voltage period;

[0029] Step 4: Calculate the duty cycle D of Q 1i ;

[0030] The closed-loop of the dual-mode electro-surgical high-frequency voltage inverter adopts a feed-forward type duty cycle prediction control method with power compensation, which includes two parts: feed-forward type duty cycle prediction control and power compensation control. Among them, the feed-forward type duty cycle prediction control is further divided into calculating the predicted duty cycle D e through the predicted duty cycle expression and the fuzzy control duty cycle D t obtained by fuzzy control.

[0031] Calculate the predicted duty cycle D e through the predicted duty cycle expression, and its expression is:

[0032]

[0033] where P ref is the reference power, V in is the input voltage, and n is the transformer turns ratio;

[0034] Taking working mode 2 as an example, define the starting moment of an output voltage period as t = 0. During the positive half-cycle of the output voltage, when the switch Q 1i is turned on, the inductor current i Li-p rises linearly; when the switch Q 1i is turned off, the inductor current i Li-pIf it decreases linearly, the inductor current \(i\) in the \((k + 1)\)-th switching period Li-p has the time-domain expression as follows:

[0035]

[0036] Similarly, in the negative half-cycle of the output voltage, the inductor current \(i\) in the \((k + 1)\)-th switching period Li-n has the time-domain expression as follows:

[0037]

[0038] where \(I\) L is the average value of the single-phase inductor current, \(V\) o is the average value of the output voltage, \(L\) is the inductance value, \(T\) s is the switching period, and \(D\) is the duty cycle of \(Q\) 1i ;

[0039] When the polarity of the output voltage is positive, sample the peak value \(i\) Li-p of the inductor current \(i\) in the positive half-cycle Lp and the power reference value \(P\) ref to obtain the fuzzy control duty cycle \(D\) t through fuzzy control; when the polarity of the output voltage is negative, sample the valley value \(i\) Li-n of the inductor current \(i\) in the negative half-cycle Lv and the power reference value \(P\) ref to obtain the fuzzy control duty cycle \(D\) t through fuzzy control;

[0040] Take the difference between the duty cycle \(D\) e obtained from the predicted duty cycle formula and the fuzzy control duty cycle \(D\) t obtained through fuzzy control, and then compare them through hysteresis control to obtain the duty cycle \(D\) h ; The specific assignment method: Take the difference between \(D\) e and \(D\) t . If \(|D\) e - D\) t | is less than the allowable difference \(de\), assign the selection signal \(sel\) to 0; if \(|D\) e - D\) t | is greater than the allowable difference \(de\), assign the selection signal \(sel\) to 1; when \(sel = 0\), it indicates that the load resistance \(R\) L changes slightly. At this time, assign \(D\) h to \(D\) e ; when \(sel = 0\), it indicates that the load resistance \(R\) L changes greatly, then assign \(D\) h to \(D\) t ;

[0041] The power feedback control calculates the power reference value \(P\) refThe error ΔP from the average output power P o is adjusted by the controller to obtain the compensated duty cycle ΔD. The final duty cycle D is obtained by adding the duty cycle D h and the compensated duty cycle ΔD obtained from the power compensation.

[0042] Compared with the prior art, the present invention adopts the above technical solutions and has the following beneficial effects:

[0043] (1) A dual-mode electro-surgical high-frequency voltage inverter and its feed-forward predictive control method proposed by the present invention. The dual-mode electro-surgical high-frequency voltage inverter can output any desired waveform to meet different electro-surgical operation requirements.

[0044] (2) A dual-mode electro-surgical high-frequency voltage inverter and its feed-forward predictive control method proposed by the present invention. The dual-mode electro-surgical high-frequency voltage inverter has two operating modes. While switching between the two operating modes, the voltage gain is broadened and the inverter efficiency is improved.

[0045] (3) A dual-mode electro-surgical high-frequency voltage inverter and its feed-forward predictive control method proposed by the present invention. The feed-forward predictive control method of the dual-mode electro-surgical high-frequency voltage inverter includes a duty cycle prediction control strategy with power compensation, which can achieve the goal of high-dynamic characteristic power control when the load impedance changes instantaneously and improve the accuracy of constant power control. Brief Description of the Drawings

[0046] Figure 1 is a topological schematic diagram of the dual-mode electro-surgical high-frequency voltage inverter of the present invention;

[0047] Figure 2 is the working waveform diagram of the first operating mode in the electro-surgical high-frequency voltage inversion topology of the present invention;

[0048] Figure 3 is the working waveform diagram of the second operating mode in the electro-surgical high-frequency voltage inversion topology of the present invention;

[0049] Figure 4 is the single-channel equivalent circuit diagram of the first operating mode in the electro-surgical high-frequency voltage inversion topology of the present invention;

[0050] Figure 5 is the single-channel equivalent circuit diagram of the second operating mode in the electro-surgical high-frequency voltage inversion topology of the present invention;

[0051] Figure 6 is the main working waveform diagram of the electro-surgical high-frequency voltage inverter of the present invention;

[0052] Figure 7 is the working waveform simulation diagram of the electro-surgical high-frequency voltage inversion topology of the present invention;

[0053] Figure 8 It is the logic diagram of the switching tube drive signal of the dual-mode electro-surgical high-frequency voltage inverter of the present invention;

[0054] Figure 9 It is the simulation diagram of the dual-mode smooth switching waveform of the present invention;

[0055] Figure 10 It is the schematic diagram of the feedforward prediction control strategy of the present invention;

[0056] Figure 11 It is the logic diagram of the fuzzy control of the present invention;

[0057] Figure 12 It is the D of the present invention h Value flow chart; Detailed implementation manners

[0058] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0059] A dual-mode electro-surgical high-frequency voltage inverter, as Figure 1 shown, includes a first capacitor C1, a second capacitor C2, a first switching tube Q a , a second switching tube Q b , a third switching tube Q c , a fourth switching tube Q d , a DC-blocking capacitor C b , a high-frequency step-up transformer T r , a load resistor R L and a multi-channel interleaved parallel structure. The interleaved parallel structure of each channel includes an interleaved parallel structure first switching tube Q 1i , an interleaved parallel structure second switching tube Q 2i , an interleaved parallel structure first filter inductor L 1i , where i = 1, 2,..., N, and N is the total number of channels of the interleaved parallel structure. One end of the first capacitor C1 is connected to the positive terminal of the DC voltage source, the other end of the first capacitor C1 is connected to one end of the second capacitor C2, the other end of the second capacitor C2 is connected to the negative terminal of the DC voltage source, the source of the first switching tube Q a is connected to the source of the second switching tube Q b , the drain of the first switching tube Q a is connected to the connection point of the first capacitor C1 and the second capacitor C2, and the drain of the second switching tube Q b is connected to the connection point of the third switching tube Q c and the fourth switching tube Qd The connection point, the third switching transistor Q c The source electrode of is connected to the drain electrode of the fourth switching transistor Q d The drain electrode of the third switching transistor Q c The drain electrode of is connected to the positive terminal of the DC voltage source and one end of the first capacitor C1. The source electrode of the fourth switching transistor Q d The source electrode of is connected to the negative terminal of the DC voltage source and the other end of the second capacitor C2; In the interleaved parallel structure of the i-th channel, the source electrode of the first interleaved parallel switching transistor Q 1i Is connected to the drain electrode of the second interleaved parallel switching transistor Q 2i The drain electrode of the first interleaved parallel switching transistor Q 1i Is connected to the drain electrode of the third switching transistor Q c The drain electrode of, the positive terminal of the DC voltage source, and one end of the first capacitor C1. The source electrode of the second interleaved parallel switching transistor Q 2i Is connected to the source electrode of the fourth switching transistor Q d The source electrode of, the negative terminal of the DC voltage source, and the other end of the second capacitor C2; One end of the first interleaved parallel filter inductor L 1i Is connected to the connection point between the first interleaved parallel switching transistor Q 1i And the second interleaved parallel switching transistor Q 2i The other end of the first interleaved parallel filter inductor L 1i Is connected to one end of the DC-blocking capacitor C b The other end of the DC-blocking capacitor C b Is connected to the same-named end of the primary winding of the RF transformer T r The primary winding of the high-frequency step-up transformer T r The opposite-named end of the primary winding is connected to the connection point between the third switching transistor Q c And the fourth switching transistor Q d The secondary winding of the high-frequency step-up transformer T r Is connected in parallel with the output capacitor C o And the load resistor R L .

[0060] When the switching frequency of the inverter is f s Let an output period have N s Switching cycles, then the output voltage frequency f o Is f s / N s . This inverter has two operating modes; When the inverter is in operating mode one, the first switching transistor Q a , the second switching transistor Q b Are always on, and the third switching transistor Q c , the fourth switching transistor Q d Are always off; When the inverter is in operating mode two, the first switching transistor Q a, the second switching transistor Q b is always turned off, and the third switching transistor Q c , the fourth switching transistor Q d are always complementary-conducted and the switching frequency is always f o . For the interleaved parallel structure of the first switching transistor Q of all channels 1i , the second switching transistor Q of the interleaved parallel structure 2i , the switching frequency of the driving signal is always f s ; inside each channel, the driving signal of the first switching transistor Q of the interleaved parallel structure 1i is complementary to the driving signal of the second switching transistor Q of the interleaved parallel structure 2i . Among the interleaved parallel structures of adjacent channels, the driving signals between the first switching transistors Q of each interleaved parallel structure 1i are staggered by 360 / i degrees, and the driving signals between the second switching transistors Q of each interleaved parallel structure 2i are staggered by 360 / i degrees. Figure 2 is the positive half-cycle working waveform diagram of the first working mode in the electro-surgical high-frequency voltage inversion topology of the present invention. Figure 3 is the positive half-cycle working waveform diagram of the second working mode in the electro-surgical high-frequency voltage inversion topology of the present invention. Figure 4 is the single-channel equivalent circuit diagram of the first working mode in the electro-surgical high-frequency voltage inversion topology of the present invention. Figure 5 is the single-channel equivalent circuit diagram of the second working mode in the electro-surgical high-frequency voltage inversion topology of the present invention.

[0061] In the first working mode, the duty cycle D determines the polarity of the output voltage of the inverter. Therefore, within one output cycle T o , by making the duty cycle D periodically change symmetrically about D = 0.5 (the duty cycle D1 in the positive half-cycle + the duty cycle D2 in the negative half-cycle = 1), the voltage inversion function can be achieved. In the second working mode, by making the duty cycle D periodically change symmetrically about D = 0.5 (the duty cycle D1 in the positive half-cycle + the duty cycle D2 in the negative half-cycle = 1) and the switching transistors Q c and Q d being complementary-conducted, the high-frequency voltage inversion can be achieved. Therefore, by controlling the inverter to output a positive-polarity voltage in the first N s / 2 cycles; controlling to output a negative-polarity voltage in the subsequent N s / 2 cycles, a square-wave output voltage waveform with positive and negative symmetry can be achieved. Figure 6 is the main working waveform diagram of the electro-surgical high-frequency voltage inverter. Figure 7 is the working waveform simulation diagram of the electro-surgical high-frequency voltage inverter topology of the present invention.

[0062] By adopting the above inverter and using the interleaved parallel structure, the output voltage and current ripples can be reduced; by switching between two modes, the output voltage gain is broadened and the efficiency is improved.

[0063] Furthermore, the capacitance values of the first capacitor C1 and the second capacitor C2 at the input end are equal, and the inductance values of all interleaved parallel structure first filter inductors L 1i are equal.

[0064] Furthermore, the first switching transistor Q a , the second switching transistor Q b , the third switching transistor Q c , the fourth switching transistor Q d , the first switching transistor Q of the interleaved parallel structure 1i , and the second switching transistor Q of the interleaved parallel structure 2i are connected in parallel with a parasitic diode and a junction capacitance. The anode of the parasitic diode is connected to the source electrode of the switching transistor, and the cathode of the parasitic diode is connected to the drain electrode of the switching transistor.

[0065] Based on the above inverter, under the same load impedance and output power, compare the efficiency of the inverter in two operating modes, and select the operating mode with better efficiency on the premise that the total harmonic content of the output voltage and the output current ripple meet the requirements; when the inverter switches from operating mode one to operating mode two, control the duty cycle of the drive signals of the first switching transistor Q a and the second switching transistor Q b to decrease from 1 to 0, so that the first switching transistor and the second switching transistor are converted from the conducting state to the off state, and control the duty cycle of the drive signals of the third switching transistor Q c and the fourth switching transistor Q d to increase from 0 to the corresponding duty cycle, so that the third switching transistor and the fourth switching transistor are converted from the off state to the complementary conducting state, and complete the switching of the inverter from operating mode one to operating mode two. When the inverter switches from operating mode two to operating mode one, control the duty cycle of the drive signals of the first switching transistor Q a and the second switching transistor Q b to increase from 0 to 1, so that the first switching transistor and the second switching transistor are converted from the off state to the conducting state, and control the duty cycle of the drive signals of the third switching transistor Q c and the fourth switching transistor Q d to decrease to 0, so that the third switching transistor and the fourth switching transistor are converted from the complementary conducting state to the off state, and complete the switching of the inverter from operating mode two to operating mode one. The relationship between the drive signals of the switching transistors is as Figure 8 shown. Figure 9 is the simulation diagram of the dual-mode smooth switching waveform of the present invention. It can be seen that when the load resistance changes from 200 Ω to 1000 Ω, the inverter switches from operating mode one to operating mode two; when the load resistance changes from 1000 Ω to 200 Ω, the inverter switches from operating mode two to operating mode one. During the dual-mode switching, not only the voltage gain is broadened, but also the efficiency of the inverter is improved.

[0066] Figure 10 is a schematic diagram of the feedforward predictive control strategy of the present invention. By sampling the output voltage v o and the output current i o , the appropriate predicted duty cycle D is directly calculated through the duty cycle prediction formula e ; when the polarity of the output voltage is positive, the peak inductor current i Lp and the power reference value P ref are subjected to fuzzy control to obtain the fuzzy control duty cycle D t ; when the polarity of the output voltage is negative, the valley inductor current i Lv and the power reference value P ref are subjected to fuzzy control to obtain the fuzzy control duty cycle D t . The duty cycle D obtained from the predicted duty cycle formula e and the fuzzy control duty cycle D obtained through fuzzy control t are subtracted, and then the duty cycle D is obtained through hysteresis control comparison h . In the power loop, the power error e p is adjusted by PI to compensate for the duty cycle error ΔD of the prediction model, and D h and ΔD are added to obtain the final duty cycle D. Finally, the drive signals of Q 1i and Q 2i are obtained by PWM modulation. Figure 11 shows the logic diagram of fuzzy control. First is the fuzzification process. Different fuzzy subsets of the inductor current and the power reference value are defined. The peak inductor current i Lp (valley inductor current i Lv ) and the power reference value p ref are used as input quantities to obtain the membership degrees of the corresponding fuzzy subsets, while the duty cycle d is used as the output quantity. Then, the fuzzy logic rules corresponding to different combinations of fuzzy subsets are established, that is, different combinations of fuzzy subsets result in different fuzzy logic rules. Secondly, fuzzy logic reasoning is performed on those with membership degrees greater than 0, and then the total output d of the fuzzy logic reasoning is obtained t . Finally, d t is defuzzified to obtain the fuzzy control duty cycle D under this operating condition t . Figure 12 shows the flowchart of the value taking of the duty cycle D h . D e is subtracted from D t . If |D e - D t | is less than the difference allowance de, the selection signal sel is assigned a value of 0; if |D e - D t | is greater than the difference allowance de, the selection signal sel is assigned a value of 1; when sel is 0, it indicates that the load resistance RL The change is small, and at this time D h is assigned to D e ; when sel is 0, it indicates that the load resistance R L has a large change, then D h is assigned to D t .

[0067] Adding a DC-blocking capacitor to the primary side of the high-frequency step-up transformer can avoid the harm of human tissues from the DC component and achieve electrical isolation to ensure safety. No capacitor or only a small capacitor is added to the output side. When the load impedance changes and the output voltage needs to be adjusted to achieve constant power control, the inertial effect of the capacitor on its adjustment speed can be effectively avoided.

[0068] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements on some or all of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A dual-mode electrosurgical high-frequency voltage inverter, characterized in that, The voltage inverter includes a first capacitor C1, a second capacitor C2, a first switching transistor Q a , a second switching transistor Q b , a third switching transistor Q c , a fourth switching transistor Q d , a DC-blocking capacitor C b , a high-frequency boost transformer T r , a load resistor R L and a multi-channel interleaved parallel structure; The interleaved parallel structure includes a first switch tube Q of the interleaved parallel structure 1i , a second switch tube Q of the interleaved parallel structure 2i , a first filter inductor L of the interleaved parallel structure 1i , where i = 1, 2,..., N (N is an integer greater than or equal to 1), and i is the number of channels of the interleaved parallel structure; One end of the first capacitor C1 is connected to the positive terminal of the DC voltage source, and the other end is connected to one end of the second capacitor C2. The other end of the second capacitor C2 is connected to the negative terminal of the DC voltage source. The source of the first switch transistor Q a is connected to the source of the second switch transistor Q b . The drain of the first switch transistor Q a is connected to the connection point of the first capacitor C1 and the second capacitor C2. The drain of the second switch transistor Q b is connected to the connection point of the third switch transistor Q c and the fourth switch transistor Q d . The source of the third switch transistor Q c is connected to the drain of the fourth switch transistor Q d . The drain of the third switch transistor Q c is connected to the positive terminal of the DC voltage source and one end of the first capacitor C1. The source of the fourth switch transistor Q d is connected to the negative terminal of the DC voltage source and the other end of the second capacitor C2; The interleaved parallel structure is specifically as follows: In the interleaved parallel structure of the i-th channel, the source electrode of the first switching transistor Q of the interleaved parallel structure 1i is connected to the drain electrode of the second switching transistor Q of the interleaved parallel structure 2i ; the drain electrode of the first switching transistor Q of the interleaved parallel structure 1i is connected to the drain electrode of the third switching transistor Q c , the positive terminal of the DC voltage source, and one end of the first capacitor C1; the source electrode of the second switching transistor Q of the interleaved parallel structure 2i is connected to the source electrode of the fourth switching transistor Q d , the negative terminal of the DC voltage source, and the other end of the second capacitor C2; The first filter inductor L of the interleaved parallel structure 1i has one end connected to the connection point of the first switch Q 1i and the second switch Q 2i of the interleaved parallel structure. The other end of the first filter inductor L 1i is connected to one end of the DC-blocking capacitor C b . The other end of the DC-blocking capacitor C b is connected to the same-named terminal of the primary winding of the high-frequency boost transformer T r . The different-named terminal of the primary winding of the high-frequency boost transformer T r is connected to the connection point of the third switch Q c and the fourth switch Q d . The secondary winding of the high-frequency boost transformer T r is connected in parallel with the output capacitor C o and the load resistor R L .

2. The dual-mode electrosurgical high-frequency voltage inverter according to claim 1, wherein The switching frequency of the voltage inverter is f s When, let an output period have N s switching cycles, then the output voltage frequency f o is f s / N s .

3. A dual-mode electrosurgical high-frequency voltage inverter according to claim 1, characterized in that, The voltage inverter has two operating modes: When the inverter is in operating mode one, the first switching transistor Q a and the second switching transistor Q b are always conducting, and the third switching transistor Q c and the fourth switching transistor Q d are always turned off; when the inverter is in operating mode two, the first switching transistor Q a and the second switching transistor Q b are always turned off, and the third switching transistor Q c and the fourth switching transistor Q d conduct complementarily and the switching frequency is always f o .

4. A dual-mode electrosurgical high-frequency voltage inverter according to claim 1, wherein The first switching transistor Q of the interleaved parallel structure 1i and the second switching transistor Q of the interleaved parallel structure 2i always have a driving signal switching frequency of f s ; within each channel, the driving signal of the first switching transistor Q of the interleaved parallel structure 1i is complementary to the driving signal of the second switching transistor Q of the interleaved parallel structure 2i ; between the interleaved parallel structures of adjacent channels, the driving signals between the first switching transistors Q of each interleaved parallel structure 1i are staggered by 360 / i degrees, and the driving signals between the second switching transistors Q of each interleaved parallel structure 2i are staggered by 360 / i degrees, where i = 1, 2,..., N (N is an integer greater than or equal to 1), and i is the number of channels of the interleaved parallel structure.

5. A dual-mode electrosurgical high-frequency voltage inverter according to claim 3, wherein The selection of the two operating modes of the voltage inverter is specifically as follows: Under the same load impedance and output power, compare the efficiencies of the inverter in the two operating modes. On the premise that the total harmonic content of the output voltage and the output current ripple meet the requirements, select the operating mode with better efficiency; The switching of the two operating modes of the voltage inverter is specifically as follows: When the inverter switches from operating mode one to operating mode two, control the first switching transistor Q a and the second switching transistor Q b so that the duty cycle of the driving signal decreases from 1 to 0, causing the first and second switching transistors to change from the conducting state to the off state. Control the third switch Q c and the fourth switching transistor Q d so that the duty cycle of the driving signal increases from 0 to the corresponding duty cycle, causing the third and fourth switching transistors to change from the off state to the complementary conducting state, thus completing the switching of the inverter from operating mode one to operating mode two; when the inverter switches from operating mode two to operating mode one, control the first switching transistor Q a and the second switching transistor Q b so that the duty cycle of the driving signal increases from 0 to 1, causing the first and second switching transistors to change from the off state to the conducting state. Control the third switching transistor Q c and the fourth switching transistor Q d so that the duty cycle of the driving signal decreases to 0, causing the third and fourth switching transistors to change from the complementary conducting state to the off state, thus completing the switching of the inverter from operating mode two to operating mode one.

6. The dual-mode electrosurgical high-frequency voltage inverter according to claim 1, characterized in that, All the switching tubes in the voltage inverter are composed of a unidirectional switching tube and a diode in reverse parallel. The capacitance values of the first capacitor C1 and the second capacitor C2 are equal, and all the interleaved parallel structure first filter inductors L 1i have equal inductance values.

7. A dual-mode electrosurgical high-frequency voltage inverter according to claim 1, characterized in that, The first switching transistor Q a , the second switching transistor Q b , the third switching transistor Q c , the fourth switching transistor Q d , the first switching transistor Q of the interleaved parallel structure 1i , the second switching transistor Q of the interleaved parallel structure 2i are connected in parallel with a parasitic diode and a junction capacitance. The anode of the parasitic diode is connected to the source electrode of the switching transistor, and the cathode of the parasitic diode is connected to the drain electrode of the switching transistor.

8. A feedforward predictive control method for a dual-mode electrosurgical high-frequency voltage inverter, characterized in that, The feedforward predictive control method for the dual-mode electrosurgical high-frequency voltage inverter is applied to the dual-mode electrosurgical high-frequency voltage inverter as described in any one of claims 1-7. The feedforward predictive control method specifically includes the following steps: Step 1: Define the voltage across the load resistor as the output voltage v o , and the current flowing through the load resistor as the output current i o . Sample the output voltage v o and the output current i o respectively; Step 2: Multiply the output voltage v o at each sampling moment by the corresponding output current i o to obtain the instantaneous output power p o : p o = v o i o (1) Step 3: Calculate the average output power P o : where T o is the output voltage period; Step 4: Calculate the duty cycle D of 1i ; The closed-loop of the dual-mode electrosurgical high-frequency voltage inverter adopts a feedforward type duty cycle prediction control method with power compensation, which includes two parts: feedforward type duty cycle prediction control and power compensation control. Among them, the feedforward type duty cycle prediction control is further divided into calculating the predicted duty cycle D through the predicted duty cycle expression e and the fuzzy control duty cycle D obtained by fuzzy control t ; Calculate the predicted duty cycle D through the predicted duty cycle expression e , and its expression is: Among them, P ref is the reference power, V in is the input voltage, and n is the transformer turns ratio; Taking operating mode 2 as an example, define the starting moment of an output voltage period as t = 0. During the positive half-cycle of the output voltage, when the switching transistor Q 1i conducts, the inductor current i Li-p rises linearly; when the switching transistor Q 1i turns off, the inductor current i Li-p falls linearly. Then, the time-domain expression of the inductor current i Li-p in the (k + 1)-th switching period is: Similarly, in the negative half-cycle of the output voltage, the inductor current i in the (k + 1)-th switching period Li-n has the following time-domain expression: Among them, I L is the average value of single-phase inductor current, V o is the average value of output voltage, L is the inductance value of the inductor, T s is the switching period and D is the Q 1i duty cycle; When the polarity of the output voltage is positive, sample the peak value i Li-p of the inductance current i Lp in the positive half cycle and the power reference value P ref to obtain the fuzzy control duty cycle D t through fuzzy control; when the polarity of the output voltage is negative, sample the valley value i Li-n of the inductance current i Lv in the negative half cycle and the power reference value P ref to obtain the fuzzy control duty cycle D t through fuzzy control; The duty cycle D obtained from the predicted duty cycle formula e and the fuzzy control duty cycle D obtained through fuzzy control t are subtracted, and then the duty cycle D is obtained through hysteresis control comparison h ; Specific assignment method: Subtract D e from D t . If |D e - D t | is less than the allowable difference de, the selection signal sel is assigned 0; if |D e - D t | is greater than the allowable difference de, the selection signal sel is assigned 1; when sel is 0, it indicates that the load resistance R L changes less. At this time, assign D h to D e ; when sel is 0, it indicates that the load resistance R L changes more, then assign D h to D t . Power feedback control calculates the power reference value P ref The error ΔP with the average output power P o After being adjusted by the controller, the compensated duty cycle ΔD is obtained. The compensated duty cycle ΔD obtained from the duty cycle D h and the power compensation are added together to obtain the final duty cycle D.

Images