Dual-band low-noise class-F voltage-controlled oscillator chip

Abstract

The invention belongs to the technical field of integrated circuits, and particularly relates to a dual-band low-noise class-F voltage-controlled oscillator. The circuit structure of the frequency source comprises an F-type voltage-controlled oscillator, a high-frequency output buffer and a low-frequency output buffer. The continuous tuning signal and the discrete tuning signal are input into the F-class voltage-controlled oscillator, the F-class voltage-controlled oscillator adjusts the frequency and phase of an output signal according to the input signal, outputs a high-frequency signal to the high-frequency output buffer and outputs a low-frequency signal to the low-frequency output buffer, the high-frequency output buffer outputs a high-frequency clock signal, and the low-frequency output buffer outputs a low-frequency clock signal. The low-frequency output buffer outputs a low-frequency clock signal. On the basis of an inductance-capacitance oscillator, an on-chip transformer is adopted to replace an inductor in a resonant cavity, electromagnetic energy conversion is reduced, the energy utilization rate is improved, higher harmonics are introduced into the resonant cavity, and phase noise is reduced; and the resonant fundamental wave and the introduced higher harmonic signal respectively pass through a buffer to realize the output of a dual-band signal.

Description

Technical Field

[0001] The present invention belongs to the technical field of integrated circuits, and in particular relates to a dual-band low-noise Class F voltage-controlled oscillator. Background Art

[0002] Voltage-controlled oscillators (VCOs) are crucial in modern communications systems and are widely used in phase-locked loops, clock generation, and frequency synthesis. Their performance in wireless communications and high-speed data transmission directly impacts system stability and signal quality. The VCO's frequency-tunable nature makes it a core component in multi-band communications equipment, providing crucial support for achieving high-precision and high-performance frequency control. However, traditional VCO structures have significant drawbacks, including a narrow output frequency band, high phase noise, and a large circuit area. These shortcomings limit their flexible application in multi-band communication systems while also increasing system power consumption and cost, impacting overall performance and affordability.

[0003] To address these shortcomings, the present invention proposes a dual-band, low-noise Class-F voltage-controlled oscillator. This design not only achieves dual-band coverage, significantly expanding the frequency range, but also effectively reduces phase noise. Furthermore, by optimizing the circuit structure, it reduces circuit area and improves energy efficiency, providing an optimal solution for highly integrated, low-power communication devices. Summary of the Invention

[0004] The object of the present invention is to provide a dual-band low-noise Class-F voltage-controlled oscillator for use in the 24 GHz ISM band and the E band.

[0005] The present invention proposes a dual-band, low-noise Class F voltage-controlled oscillator for use in the 24 GHz ISM band and E band. Its circuit structure includes a Class F voltage-controlled oscillator, a high-frequency output buffer, and a low-frequency output buffer. A continuous tuning signal and a discrete tuning signal are input to the Class F voltage-controlled oscillator. The Class F voltage-controlled oscillator adjusts the frequency and phase of the output signal based on the input signals, outputs a high-frequency signal to the high-frequency output buffer, and outputs a low-frequency signal to the low-frequency output buffer. The high-frequency output buffer then outputs a high-frequency clock signal, while the low-frequency output buffer outputs a low-frequency clock signal.

[0006] In the present invention, the Class F voltage-controlled oscillator comprises a pair of cross-coupled transistors serving as negative resistance transistors, connected between the cross-coupled transistors via a center-tapped on-chip transformer serving as a load. The on-chip transformer and gate capacitor array form a low-frequency resonant cavity, while the on-chip transformer and drain capacitor array form a high-frequency resonant cavity. The capacitor array comprises a tuning unit and a capacitor unit, wherein the tuning unit comprises a capacitor pair consisting of two common-source and common-drain transistors, with the source and drain connected and connected to the output of a frequency controller.

[0007] In the present invention, the capacitor unit includes a fixed capacitor, an NMOS transistor, a resistor, and an inverter. When the enable signal is at a high level, the NMOS transistor is turned off, and the side of the fixed capacitor connected to the transistor is biased at a high level, which is equivalent to disconnecting from the resonant cavity; when the enable signal is at a low level, the NMOS transistor is turned on, and the side of the fixed capacitor connected to the transistor is biased at a low level, which is equivalent to connecting to the resonant cavity.

[0008] In the present invention, the high-frequency buffer adopts a fully differential common-source amplifier structure, in which the transistor pairs are cross-coupled through neutralization capacitors to improve the stability of the buffer; the buffers are coupled in the form of transformers between stages to increase the bandwidth of the buffer.

[0009] The class-F voltage-controlled oscillator designed in the present invention uses an on-chip transformer as a load, and at the same time forms a resonant cavity with two capacitor arrays at the gate terminal and the drain terminal, thereby enhancing the energy of high-order harmonics in the resonant cavity, realizing the extraction of high-order harmonics, reducing phase noise, improving energy utilization efficiency and occupying a small area; through high-frequency and low-frequency buffers, the extraction and amplification of the fundamental wave and high-order signals of the class-F voltage-controlled oscillator are realized, and high-power output in the 24GHz ISM band and E band is achieved. Description of the Drawings

[0010] Figure 1 It is a schematic structural diagram of a dual-band low-noise class-F voltage-controlled oscillator.

[0011] Figure 2 It is a schematic circuit diagram of a class-F voltage-controlled oscillator.

[0012] Figure 3 It is a schematic diagram of the drain capacitor array.

[0013] Figure 4 It is a schematic diagram of the gate capacitor array.

[0014] Figure 5 It is a schematic circuit diagram of the capacitor unit.

[0015] Figure 6 It is a schematic circuit diagram of the tuning unit.

[0016] Figure 7 It is a schematic circuit diagram of the high-frequency output buffer Detailed Embodiments

[0017] The present invention will be described in more detail below with reference to the drawings. In the various drawings, like elements are denoted by like reference numerals. For the sake of clarity, the various parts in the drawings are not drawn to scale. In addition, some well-known parts may not be shown in the figures.

[0018] Numerous specific details of the present invention are described hereinafter, such as the structure, materials, dimensions, processing techniques and technologies of the device, in order to understand the present invention more clearly. However, as those skilled in the art can understand, the present invention can be implemented without these specific details.

[0019] Figure 1 Schematic diagram showing a class-F voltage-controlled oscillator structure with dual-band and low noise of the present invention.

[0020] As Figure 1 shown, a class-F voltage-controlled oscillator 100 with dual-band and low noise in the present invention includes: a class-F voltage-controlled oscillator 101, a high-frequency output buffer 102, and a low-frequency output buffer 103. The analog-domain voltage signal VTUNE serves as the control signal for the class-F voltage-controlled oscillator 101, enabling the class-F voltage-controlled oscillator 101 to generate continuous frequency adjustment, thereby changing the output frequencies of the VH signal and the VL signal. The multi-bit binary control signal CTRLD generated by the digital module serves as the control word for the drain capacitance array of the class-F voltage-controlled oscillator 101, enabling the class-F voltage-controlled oscillator 101 to output a discrete frequency signal VH, which generates a signal VOUTH as the output of the system after passing through the high-frequency output buffer 102. The multi-bit binary control signal CTRLG generated by the digital module serves as the control word for the gate capacitance array of the class-F voltage-controlled oscillator 101, enabling the class-F voltage-controlled oscillator 101 to output a discrete frequency signal VL, which generates a signal VOUTL as the output of the system after passing through the low-frequency output buffer 103.

[0021] Figure 2 Schematic diagram showing the circuit of the class-F voltage-controlled oscillator of the present invention.

[0022] As Figure 2As shown in the figure, the schematic diagram of the class F voltage-controlled oscillator circuit of the present invention includes a drain capacitance array 201, a gate capacitance array 202, transistors M1 and M2, inductors Lp and Ls, and a resistor R. The N-bit digital code CTRLD<1:N> controls the drain capacitance array 201 to generate different on-capacitances and incorporate them into the resonator cavity. The M-bit digital code CTRLG<1:M> controls the source capacitance array 202 to generate different on-capacitances and incorporate them into the resonator cavity. The analog-domain voltage signal VTUNE controls the source capacitance array 202 to generate different capacitance values and incorporate them into the resonator cavity. The drain of transistor M1 is connected to the port of the drain capacitance array 201 and the negative port of inductor Lp, and serves as the output signal VHP at the same time. The source of transistor M1 is connected to resistor R and the source of transistor M2. The gate of transistor M1 is connected to the positive port of inductor Ls and the port of the gate capacitance array 202, and serves as the output signal VLN at the same time. The drain of transistor M2 is connected to the port of the drain capacitance array 201 and serves as the output signal VHN at the same time. The source of transistor M2 is connected to resistor R and the source of transistor M1. The gate of transistor M2 is connected to the negative port of inductor Ls and the port of the gate capacitance array 202, and serves as the output signal VLP at the same time. The center tap of inductor Lp is connected to power supply VDD, the positive port is connected to the drain of M2, and the negative port is connected to the drain of M1. The center tap of inductor Ls is connected to power supply VB, the positive port is connected to the gate of M1, and the negative port is connected to the gate of M2. The coupling coefficient between inductor Lp and inductor Ls is Km. The positive end of resistor R is connected to the sources of M1 and M2, and the negative end of resistor R is grounded.

[0023] As Figure 3 shown, the schematic diagram of the drain capacitance array in the present invention.

[0024] As Figure 3 shown, the schematic diagram of the drain capacitance array of the present invention includes N capacitance units 301: capacitance unit 1, capacitance unit 2,..., capacitance unit N. The digital control signal CTRLD<1> controls the on and off of capacitance unit 1, and capacitance unit 1 is connected to the resonator cavity through output ports VHP and VHN. The digital control signal CTRLD<2> controls the on and off of capacitance unit 2, and capacitance unit 2 is connected to the resonator cavity through output ports VHP and VHN,..., the digital control signal CTRLD <n>Control the turning on and off of the capacitive unit N, and the capacitive unit N is connected to the resonator through the output ports VHP and VHN.

[0025] Figure 4 Show a schematic diagram of the gate capacitor array of the present invention.

[0026] As Figure 4 shown, the schematic diagram of the gate capacitor array in the present invention includes a tuning unit 302 and M capacitive units 301. The analog domain voltage signal VTUNE is used as the control voltage of the tuning unit 302 to generate a continuous capacitance change value, which is connected to the resonator through the two output ports VLP and VLN. The digital domain voltage signal CTRLG<1> is used as the control voltage of the capacitive unit 1 to generate a discrete capacitance change value, which is connected to the resonator through the two output ports VLP and VLN. The digital domain voltage signal CTRLG<2> is used as the control voltage of the capacitive unit 2 to generate a discrete capacitance change value, which is connected to the resonator through the two output ports VLP and VLN... The digital domain voltage signal CTRLG <m>As the control voltage of the capacitor unit M generates discrete capacitance change values, it is connected to the resonant cavity through two output ports VLP and VLN.

[0027] Figure 5 The circuit schematic diagram of the capacitor unit of the present invention is shown.

[0028] As Figure 5 shown, the circuit schematic diagram of the capacitor unit in the present invention includes an inverter N1, capacitors C1 and C2, a transistor M1, and resistors R1 and R2. The enable signal EN is connected to the input terminal of the inverter N1, and the output terminal of the inverter N1 is connected to the gate of the transistor M1. The drain of the transistor M1 is connected to the capacitor C1 and the resistor R1. The other end of the capacitor C1 serves as the output VP, and the other end of the resistor R1 is connected to the enable signal EN. The source of the transistor M1 is connected to the capacitor C2 and the resistor R2. The other end of the capacitor C2 serves as the output VN, and the other end of the resistor R2 is connected to the enable signal EN.

[0029] Figure 6 The circuit schematic diagram of the tuning unit of the present invention is shown.

[0030] As Figure 6 shown, the circuit schematic diagram of the tuning unit of the present invention includes two transistors M1 and M2. The input signal VTUNE is connected to the source of the transistor M1, the source of the transistor M2, the drain of the transistor M1, and the drain of the transistor M2. The gate of the transistor M1 is connected to the resonant cavity as the VP port, and the gate of the transistor M2 is connected to the resonant cavity as the VN port.

[0031] Figure 7 The circuit schematic diagram of the high-frequency output buffer of the present invention is shown.

[0032] As Figure 7 As shown, the circuit schematic diagram of the high-speed output buffer of the present invention includes four transistors M1, M2, M3, M4, six capacitors C1, C2, C3, C4, C5, C6, four inductors L1, L2, L3, L4, and two resistors R1, R2. The input signal VHP is connected to the capacitor C1, and the other end of the capacitor C1 is connected to the positive terminal of the resistor R1. The negative terminal of the resistor R1 is connected to the input signal VB1. The input signal VHN is connected to the capacitor C2, and the other end of the capacitor C2 is connected to the positive terminal of the resistor R2. The negative terminal of the resistor R2 is connected to the input signal VB1. The gate of the transistor M1 is connected to the positive terminal of the capacitor C3 and the positive terminal of the resistor R1. The negative terminal of the capacitor C3 is connected to the drain of the transistor M2. The source of the transistor M1 is grounded. The gate of the transistor M2 is connected to the positive terminal of the capacitor C4 and the positive terminal of the resistor R2. The negative terminal of the capacitor C4 is connected to the drain of the transistor M1. The source of the transistor M2 is grounded. The positive terminal of the inductor L1 is connected to the drain of the transistor M1, the negative terminal is connected to the drain of M2, and the center tap is connected to the power supply VDD. The positive terminal of the inductor L2 is connected to the gate of the transistor M3, the negative terminal is connected to the gate of the transistor M4, and the center tap is connected to the potential VB2. The inductor L1 and the inductor L2 form a transformer. The gate of the transistor M3 is connected to the positive terminal of the capacitor C5 and the positive terminal of the inductor L2. The negative terminal of the capacitor C5 is connected to the drain of the transistor M4. The source of the transistor M3 is grounded. The gate of the transistor M4 is connected to the positive terminal of the capacitor C6 and the negative terminal of the inductor L2. The negative terminal of the capacitor C6 is connected to the drain of the transistor M3. The source of the transistor M4 is grounded. The positive terminal of the inductor L3 is connected to the drain of the transistor M3, the negative terminal is connected to the drain of the transistor M4, and the center tap is connected to the power supply VDD. The positive terminal of the inductor L4 is connected to the positive terminal of the capacitor C7 and is used as the output VOUT H at the same time. The negative terminal of the inductor L4 is grounded. The positive terminal of the capacitor C7 is connected to the positive terminal of the inductor L4, and the negative terminal of the capacitor C7 is grounded. The inductor L3 and the inductor L4 form a transformer.

[0033] In this article, the term "including", "comprising" or any other variant thereof is intended to cover non-exclusive inclusion, so that a series of elements (such as a process, method, article or device) included not only include those elements, but also other elements not explicitly listed. Without more limitations, an element defined by the statement "including one..." does not exclude the existence of other identical elements outside the included elements.

[0034] In the present invention, the embodiments do not describe all the details in detail, nor limit the invention to the specific embodiments described. According to the above description, many changes can be made. These embodiments are selected and specifically described in this specification to better explain the principles and practical applications of the present invention, so that those skilled in the art can make good use of the present invention and its modifications based on the present invention. The present invention is only limited by the claims and their full scope and equivalents.< / m> < / n>

Claims

1. A class F voltage-controlled oscillator with dual-band and low noise. The circuit structure of the frequency source of the present invention includes: Class F voltage-controlled oscillator, high-frequency output buffer, low-frequency output buffer. A continuous tuning signal and a discrete tuning signal are input into the Class F voltage-controlled oscillator. The Class F voltage-controlled oscillator adjusts the frequency and phase of the output signal according to the input signals, outputs a high-frequency signal to the high-frequency output buffer, and outputs a low-frequency signal to the low-frequency output buffer. The high-frequency output buffer outputs a high-frequency clock signal, and the low-frequency output buffer outputs a low-frequency clock signal.

2. The class F voltage controlled oscillator with dual-band low noise according to claim 1, characterized in that The Class F voltage-controlled oscillator can achieve dual-band output, specifically the 24GHz ISM band and the E band.

3. The class F voltage-controlled oscillator with dual-band low noise according to claim 1, characterized in that, The Class F voltage-controlled oscillator contains a pair of cross-coupled transistors as negative resistance transistors, and a center-tapped on-chip transformer is connected between the cross-coupled transistors as a load; the on-chip transformer and the gate capacitor array form a low-frequency resonant cavity, and the on-chip transformer and the drain capacitor array form a high-frequency resonant cavity. The capacitor array includes a tuning unit and a capacitor unit. The tuning unit is composed of capacitor tube pairs, and each capacitor tube pair consists of two common-source common-drain transistors, with the source and drain connected and connected to the output of the frequency controller.

4. The class-F voltage-controlled oscillator with dual-band low noise according to claim 3, wherein The capacitor unit includes an inverter N1, capacitors C1, C2, a transistor M1, and resistors R1, R2. The enable signal EN is connected to the input terminal of the inverter N1, and the output terminal of the inverter N1 is connected to the gate of the transistor M1. The drain of the transistor M1 is connected to the capacitor C1 and the resistor R1, and the other end of the capacitor C1 is used as the output VP. The other end of the resistor R1 is connected to the enable signal EN. The source of the transistor M1 is connected to the capacitor C2 and the resistor R2, and the other end of the capacitor C2 is used as the output VP. The other end of the resistor R2 is connected to the enable signal EN. When the enable signal is at a high level, the NMOS transistor is turned off, and the side of the fixed capacitor connected to the transistor is biased at a high level, which is equivalent to disconnecting from the resonant cavity; when the enable signal is at a low level, the NMOS transistor is turned on, and the side of the fixed capacitor connected to the transistor is biased at a low level, which is equivalent to connecting to the resonant cavity.

5. The class-F voltage-controlled oscillator with dual-band low noise according to claim 1, characterized in that, The high-frequency buffer adopts a fully differential common-source amplifier structure, where the transistor pairs are cross-coupled through neutralization capacitors to improve the stability of the buffer; the buffer stages are coupled in the form of a transformer to improve the bandwidth of the buffer. The high-frequency buffer includes four transistors M1, M2, M3, M4, six capacitors C1, C2, C3, C4, C5, C6, four inductors L1, L2, L3, L4, and two resistors R1, R2. The input signal VHP is connected to the capacitor C1, the other end of the capacitor C1 is connected to the positive terminal of the resistor R1, and the negative terminal of the resistor R1 is connected to the input signal VB1. The input signal VHN is connected to the capacitor C2, the other end of the capacitor C2 is connected to the positive terminal of the resistor R2, and the negative terminal of the resistor R2 is connected to the input signal VB1. The gate of the transistor M1 is connected to the positive terminal of the capacitor C3 and the positive terminal of the resistor R1. The negative terminal of capacitor C3 is connected to the drain of transistor M2. The source of transistor M1 is grounded. The gate of transistor M2 is connected to the positive terminal of capacitor C4 and the positive terminal of resistor R2. The negative terminal of capacitor C4 is connected to the drain of transistor M1. The source of transistor M2 is grounded. The positive terminal of inductor L1 is connected to the drain of transistor M1, the negative terminal is connected to the drain of M2, and the center tap is connected to power supply VDD. The positive terminal of inductor L2 is connected to the gate of transistor M3, the negative terminal is connected to the gate of transistor M4, and the center tap is connected to potential VB2. Inductors L1 and L2 form a transformer. The gate of transistor M3 is connected to the positive terminal of capacitor C5 and the positive terminal of inductor L2. The negative terminal of capacitor C5 is connected to the drain of transistor M4. The source of transistor M3 is grounded. The gate of transistor M4 is connected to the positive terminal of capacitor C6 and the negative terminal of inductor L2. The negative terminal of capacitor C6 is connected to the drain of transistor M3. The source of transistor M4 is grounded. The positive terminal of inductor L3 is connected to the drain of transistor M3, the negative terminal is connected to the drain of transistor M4, and the center tap is connected to power supply VDD. The positive terminal of inductor L4 is connected to the positive section of capacitor C7 and serves as output VOUTH at the same time. The negative terminal of inductor L4 is grounded. The positive terminal of capacitor C7 is connected to the positive terminal of inductor L4, and the negative terminal of capacitor C7 is grounded. Inductors L3 and L4 form a transformer.

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