Single substrate multiplexer

Abstract

At least three acoustic filter circuits FC are arranged on a single chip CH. At least two of them have been electrically connected on the chip for multiplexing. This reduces space consumption and results in a smaller device size.

Description

[0001] This application is a divisional application of the application with application number 202080050974.4 and invention title "Single-substrate multiplexer".

[0002] At least three acoustic filters are arranged on a single chip. At least two of them are electrically connected on the chip for multiplexing. This reduces space consumption and results in a smaller device size. Background Art

[0003] In current mobile communication devices, multiplexers are used to allow filter operation in multiple frequency bands while using the same antenna connected to the multiplexer.

[0004] Discrete electroacoustic components having more than two filter functions or multiplexers are composed of carrier substrates (e.g., laminates and individual filter chips). The corresponding filter functions are embodied on corresponding separate chips. The advantage of this is that separately optimized layer stacks can be used for each filter function, and different filter technologies can be used. Additionally, the chip size for individual filters remains small, thus providing some advantages, for example, in terms of mechanical stability or regarding failures of individual filters during production, or when trimming individual chips to the target frequency.

[0005] However, the carrier substrate must be large enough to keep the distance between the chip edges and the electroacoustic chips to a minimum. Also, heat dissipation is not optimal, cutting small chips from the wafer reduces the acoustically available area, and greater material loss occurs when cutting the wafer.

[0006] Due to the thermal mismatch in the package or between the carrier substrate and the chip, using a larger chip with more than two filter functions on a single chip is more sensitive to cracks and failures during operation. Further, it is difficult to simultaneously meet the optimizations for different filter functions on the same chip. Summary of the Invention

[0007] An object of the present invention is to provide a multiplexer as a one-chip solution that is thermally matched and fully meets the specifications of different filter functions. Another object is to provide a multiplexer with improved heat dissipation characteristics.

[0008] The multiplexer according to independent claim 1 meets at least one of these objects. Advantageous features and embodiments can be obtained according to the dependent claims.

[0009] A multiplexer is formed from a single monolithic stack that includes a carrier substrate comprising Si; a thin-film piezoelectric layer located above the substrate and having a major surface; and at least one dielectric layer disposed between the piezoelectric layer and the substrate. On top of the major surface, the structured metal includes antenna terminals for connection to an antenna, three signal pads, and three SAW filter circuits. The filter circuits are connected in parallel between the antenna terminals and their respective corresponding signal pads. Each of the filter circuits in the filter circuits includes a series signal line and a plurality of SAW resonators connected in series or in parallel with the series signal line. A cavity is provided on top of the stack, within which the SAW resonators are enclosed. The cavity is formed between the major surface of the piezoelectric layer and a lid and / or cover.

[0010] The multiplexer uses a single stack to implement all the filter functions operated by the multiplexer. Through a suitable combination of frequency bands, that is, a suitable combination of the filter functions of these frequency bands, all frequency bands can be operated using the same antenna, where the isolation between the frequency band channels is sufficient and there is no crosstalk.

[0011] The stack uses a thin-film piezoelectric layer that does not generate parasitic modes in any of the filter circuits combined at the antenna terminals. Thus, when the multiplexer operates in one frequency band, the adjacent frequency bands are not disturbed.

[0012] Each filter circuit includes all the resonators required for the filter function. The multiplexer includes separate filter circuits for each frequency band that can be operated by the multiplexer. This provides various technical advantages:

[0013] Wafer material can be saved. Instead of cutting out each small chip separately from the wafer, only a single larger chip needs to be sawn out. This greatly reduces the area loss of the wafer caused by cutting (for example, one-third reduction for three square single chips or half reduction for four square single chips).

[0014] Depending on the process, the acoustic resonators must always maintain a minimum distance from the chip edge. Using a single chip instead of several smaller chips results in a reduction of the entire chip edge area, which cannot be used acoustically and must be kept free of any filter elements. Additionally, the acoustic resonators can be placed more freely because they do not have to be aligned on straight edges in the area between separate filter functions but can be positioned in a variable manner. This provides more degrees of freedom for the design of existing acoustic surfaces, thus making more efficient use of space.

[0015] Additionally, the advantage offered by the single-chip variant is that any thermally dissipated energy generated can be more effectively dissipated. The resulting heat is distributed over a larger chip, radiates better, and can be dissipated through a larger number of bumps. This has a positive impact on the performance compatibility and service life of the component.

[0016] Since typically only one filter circuit of the multiplexer is operating, only the corresponding filter circuit generates heat. The other inactive filter circuits and their corresponding areas occupied provide sufficient space within the stack for adequate heat dissipation to avoid excessive temperature rise.

[0017] Preferably, a substrate material for the stack is used that has a thermal conductivity that is at least ten times higher than the corresponding thermal conductivity of the piezoelectric layer. This relationship can be achieved with a single-crystalline Si carrier substrate and a piezoelectric layer composed of lithium tantalate (LT) or lithium niobate (LN). The thermal conductivity of silicon is approximately 40 times better than that of the common SAW materials LiTaO3 or LiNbO3. The piezoelectric layer with poor thermal conductivity is relatively thin, resulting in a correspondingly low thermal resistance, and heat can be effectively passed through this layer. Therefore, most of the heat dissipation occurs in the well-conducting Si substrate material, thus representing an improvement compared to SAW devices or filter chips implemented on well-known thick piezoelectric substrates.

[0018] According to a preferred embodiment, the piezoelectric layer is a single-crystalline thin film layer of lithium tantalate or lithium niobate and has a thickness in the range of 400 nm to 2000 nm. Such a layer thickness is advantageous for TCFSAW filter circuits operating in the low-frequency band, mid-frequency band, and high-frequency band. To minimize acoustic losses and enable wafer bonding, the piezoelectric layer preferably has smooth upper and lower surfaces. In this context, a smooth surface must be understood as having a roughness value Rq ≤ 0.5 nm, where Rq is the corresponding root mean square value. The root mean square (RMS or rms) is defined as the square root of the mean square (the arithmetic mean of the squares of the set of deviations from the mean line). The exact definition of the roughness parameter can be found at https: / / en.wikipedia.org / wiki / Surface_roughness.

[0019] The dielectric layer below the piezoelectric layer is preferably a silicon oxide layer with a thickness of 300 nm to 2000 nm and a smooth top surface with a roughness value Ra ≤ 0.5 μm, where Ra is the arithmetic mean deviation from the constant mean line of the evaluated profile. Such a dielectric layer can serve to reduce the TCF (thermal coefficient of frequency) of the multiplexer and compensate for or reduce the temperature drift of the filter circuit due to the relatively high TCF of the piezoelectric.

[0020] Fixed positive charges appear between the direct junction of the Si substrate and the silicon oxide layer, and these positive charges attract mobile electrons, thereby causing ohmic losses in the conduction layer. To avoid such losses, it is advantageous to insert a trap-rich layer between the Si and the SiO2 layer. The trap-rich layer can be composed of, for example, polysilicon with a thickness in the range of 100 nm to 2000 nm.

[0021] A multilayer board having contact pads on the bottom surface and the integrated wiring within its multilayer structure can be used for wiring and packaging. The contact pads of the board are connected to corresponding external contacts located on the top surface opposite to the bottom surface to allow connection to an external circuit system of an electronic device such as a mobile phone.

[0022] The multilayer board is mounted and electrically connected to the stack by a connection technique. Thus, the contact pads are connected to corresponding signal pads and antenna terminals on the main surface, for example, by bumps. A sealing device can be provided to seal the cavity formed between the multilayer board and the main surface.

[0023] Alternatively, the SAW resonator can be enclosed in a corresponding cavity integrally formed as a thin-film acoustic package TFAP. Such a TFAP can enclose a single filter function, a part of a filter function, or a single resonator. The TFAP can be produced by applying and structuring a sacrificial material to preform the corresponding cavity. Then, a thin film with mechanical stability is deposited over the entire surface of the chip to cover the sacrificial structure. Then, the cavity is released by removing the sacrificial material.

[0024] Since the single-chip multiplexer eliminates the distance between the individual filter chips required for a multi-chip multiplexer, the surface area of the board can be reduced if a packaging technique with a board (e.g., CSSP) is used. Since the size of a single chip for the single-chip variant is significantly larger than that of a single chip for the multi-chip variant, for the present invention, it is advantageous to use a board material with a thermal expansion coefficient similar to that of the wafer material. This minimizes the mechanical stress during temperature cycling.

[0025] Suitable board materials are, for example, laminates, HTCC, or LTCC. The latter is particularly advantageous in connecting silicon-based TF-SAW wafer materials, thereby allowing for a good adjustment of the thermal expansion coefficients of the stack / wafer and the board. Overall, the competitive advantage stems from the lower cost and smaller size of the multiplexer.

[0026] The complete multiplexer interconnection can be measured at a very early stage of the manufacturing process, and thus the interaction between individual filters can be detected. Therefore, production variations can be compensated for, for example, by trimming at an early stage.

[0027] During the manufacture of a single-chip multiplexer, fluctuations typically have a similar effect on all filters in the stack and can be corrected by a trimming process. This is contrary to the case of a multi-chip component, in which a large statistical deviation of device characteristics and a wide distribution of filter functions may occur. If two filter functions in the filter functions are close to each other in frequency and thus require a high degree of mutual selection of the corresponding counter bands, they can benefit from the single-chip setting of the new multiplexer, since both filter functions will be affected by process variations running in parallel, i.e., the critical passband edges of different filter circuits on the same stack move in the same direction in terms of frequency.

[0028] Therefore, in process engineering, it is easier to ensure the critical duplex spacing. This is not the case for multi-chip components.

[0029] Since all necessary bump connections of all filter circuits of the multiplexer can be processed in one step, other processing times and related costs can be reduced, for example, during sawing or flip-chip bonding.

[0030] The application of the present invention is particularly attractive for multiplexers with a small number of filter circuits / filter functions in which only frequencies must be very precisely met due to high proximity selection requirements, as well as for a large number of filters with less stringent requirements. Then, the critical filters can generally be trimmed, and the filters can be designed to have sufficient margin to meet the less critical specifications.

[0031] According to one embodiment, the multiplexer includes four SAW filter circuits to form a four-way multiplexer. The four filter functions form two duplexers, which are configured to allow the four-way multiplexer to operate under a frequency band combination of frequency bands B1 and B3 or a frequency band combination of frequency bands B25 and B66.

[0032] In this example, the filter functions of the B3 and B25 frequency bands must be very precisely trimmed, while the specifications of the B1 or B66 frequency bands are less important.

[0033] However, more complex selective multiple trimming for individual filter units can also be used.

[0034] Initial trimming can be done during stack production. Thus, the thickness uniformity of the deposited or otherwise generated layers is measured and controlled. If necessary, selective thinning can be performed by removing material with an NF3 beam. The thicknesses of the dielectric layer and the piezoelectric layer are most relevant to the filter specifications. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] The present invention is explained in more detail with reference to the embodiments and the drawings. The drawings are only schematic and may not be drawn to scale.

[0036] Figure 1 Shows a known multiplexer arrangement of four separate chips with the necessary chip-to-chip distance and edge margin on a common multilayer board;

[0037] Figure 2 Shows a single-chip multiplexer according to the present invention and the necessary edge margin;

[0038] Figure 3 Shows a schematic block diagram of four filter circuits arranged on a single chip and connected to a common antenna terminal;

[0039] Figure 4 Shows the schematic filter circuit in more detail;

[0040] Figure 5 Shows a schematic block diagram of a DMS filter that can be used as a resonator in an Rx filter circuit;

[0041] Figure 6 Shows a cross-section of a single-chip stack provided with a structured metallization including pads, electrode structures, and terminals that can be used for a multiplexer;

[0042] Figure 7 Shows a possible schematic package of the multiplexer. Detailed Description

[0043] Figure 1 Shows the arrangement of four separate chips CH on a common multilayer board MLB with the necessary chip-to-chip distance and edge margin. Due to these necessary distances, the acoustically available area AA of the chips CH is smaller than the area of the chips. Further, the chips must be kept at a certain distance from the edge of the multilayer board and between adjacent chips.

[0044] Figure 2 Shows, on the same scale, the necessary area of a multiplexer implemented on a single chip according to the present invention. In this arrangement, no chip-to-chip distance is required, and the chip area required for the margin of a single chip is smaller compared to the Figure 1 arrangement. The same applies to the margin of the multilayer board MLB. Thus, up to 50% and more of the wafer area can be saved, and a multiplexer device can be realized that is correspondingly smaller in size than the known multi-chip components according to Figure 1 the present invention.

[0045] Figure 3An exemplary schematic block diagram shows four filter circuits FC1 to FC4 arranged on a single chip CH and connected to a common antenna terminal AT. Each filter circuit in the filter circuits FC includes a series signal line SSL connecting each corresponding signal pad SP to the antenna terminal AT and a plurality of SAW resonators. Series resonators RS are connected in series, and parallel resonators RP are connected in parallel to the series signal line SSL.

[0046] The filter circuits are arranged in a ladder configuration and may include other elements not shown in the figure for clarity. The number of resonators may be greater to achieve better selectivity. Some of the resonators may be cascaded to increase their power resistance and improve lifespan and reduce non-linear behavior. The filter circuits may consist only of series resonators RS. Passive components may be connected to the resonators or to the series signal line. Capacitors may be connected in parallel circuits to individual resonators to vary their bandwidths. The parallel resonators RP may be connected to ground via inductors. Some of the ground connections may be combined on the chip. The antenna terminal is connected to ground via a coil for phase shift and impedance matching. External matching elements may be connected to the signal pads or the series signal line.

[0047] Two filter circuits may be assigned to the same first cellular band and form the Rx filter and the corresponding Tx filter for that band. The other two filter circuits may be assigned to a second cellular band to allow duplex operation in that second band. Preferably, the filter circuits are assigned to a band combination with not too high a frequency separation. Preferably, the two bands are within the same frequency range selected from the high-frequency band range and / or the mid-frequency band range.

[0048] Figure 4 More detailedly shows a schematic exemplary filter circuit FC similar to the filter circuit depicted in Figure 3 This filter circuit includes five series resonators RS arranged in the series signal line SSL. The corresponding nodes between every two adjacent series resonators are connected to ground via parallel branches, and parallel resonators RP are arranged in each parallel branch. An inductor (not shown) may be connected between the parallel resonator and ground.

[0049] Figure 5A schematic block diagram of an exemplary DMS filter showing a series resonator in an Rx filter circuit that can be used as a multiplexer is shown. The DMS filter includes a first number of interdigital transducer / resonators IDT connected to the input terminal IN of the DMS filter. A second number of interdigital transducers IDT are connected to the output terminal OUT of the DMS filter. All IDTs are arranged in an acoustic track extending between two reflectors REF and are thus acoustically coupled. The first number and the second number can be set higher than the number depicted according to the required selectivity specification. The busbars of the IDTs not connected to the input or output can be grounded or floating. Two DMS filters can be connected in series within the filter circuit. Figure 3 and Figure 4 Other elements of the filter circuit shown constitute the filter circuit.

[0050] Figure 6 A schematic cross-section through a monolithic stack is shown, which has been provided with a structured metallization on top. For example, pads, electrode structures ES such as interdigital transducers, reflectors, conductor lines, terminal AT, and signal pads SP1, SP2 can be formed from the metallization according to the requirements of the multiplexer being formed. Figure 3 The carrier substrate SU is a crystalline silicon material thick enough to provide the required mechanical stability. The stability must be high enough to allow handling of the entire wafer on which the stack ST is formed. The crystalline silicon material of the carrier substrate SU can have a top surface that is a crystalline

[111] surface.

[0051] Optionally, a trap-rich layer TRL is disposed on top of the carrier substrate SU, which includes, for example, a polysilicon layer with a thickness in the range of 100 nm to 2000 nm to eliminate known free charges, for example, at a later Si / SiO2 junction. A dielectric layer DL of SiO2 is formed or deposited to act as a TCF compensation layer. The thickness of the dielectric layer is controlled and set to a value of about 300 nm to 2000 nm, for example, 500 nm. All layer junctions can have smooth top and bottom surfaces, where the layer roughness is small.

[0052] Optionally, a trap-rich layer TRL is disposed on top of the carrier substrate SU, which includes, for example, a polysilicon layer with a thickness in the range of 100 nm to 2000 nm to eliminate known free charges, for example, at a later Si / SiO2 junction. A dielectric layer DL of SiO2 is formed or deposited to act as a TCF compensation layer. The thickness of the dielectric layer is controlled and set to a value of about 300 nm to 2000 nm, for example, 500 nm. All layer junctions can have smooth top and bottom surfaces, where the layer roughness is small.

[0053] After smoothing the surface of the dielectric layer DL, for example, by a CMP method, a piezoelectric wafer is bonded to the dielectric layer DL. After atomic bonding, the thickness of the piezoelectric wafer is reduced to form a thin film piezoelectric layer PL with a thickness of about 400 nm to 2000 nm (for example, 600 nm). This is thin enough to allow rapid heat dissipation from the filter circuit to the underlying substrate and to avoid excitation of parasitic modes in the counterband or other bands that can be operated by the multiplexer. For a thin enough piezoelectric layer, parasitic modes only occur at frequencies above the band used by the multiplexer.

[0054] After reducing the thickness by a suitable process, the thickness of the piezoelectric layer is measured and the entire layer is trimmed to achieve the desired thickness with only a small tolerance across the wafer. This is necessary because the frequency of the filter circuit formed on the piezoelectric layer may depend on its specific thickness and too high a tolerance results in frequency variations and a frequency distribution across the wafer that depends on the remaining thickness variations.

[0055] Lithium tantalate (LT) and lithium niobate (LN) are preferred piezoelectric materials. However, other materials can also be used.

[0056] Importantly, the thermal conductivity of the substrate SU is at least ten times higher than the corresponding thermal conductivity of the piezoelectric layer PL. The conductivity of the silicon substrate SU and the piezoelectric layer PL of LT proposed above differ by about 40 times.

[0057] The top surface of the stack ST is the main surface on which the electrode structure ES, the signal pads SP, and the antenna terminals AT are formed. Figure 6 The metallization is shown in a very schematic depiction. There are other pads on the main surface, such as ground pads for connecting parallel branches to ground, but they are not shown in the schematic.

[0058] Preferably, the electrode structure is formed by a metallization based on Al or an Al alloy. Further, Cu and / or Ti can be other components in the alloy or can be used as discrete sub-layers in a multi-layer metallization. The surface of the metallization can be protected using a passivation layer. The pads are thickened and provided with a solderable surface layer, such as gold or nickel, for example.

[0059] To complete the multiplexer, a package is formed on top of the stack ST. For this reason, a multi-layer board can be bonded to the main surface of the stack.

[0060] Figure 7 A cross-section of such a multiplexer provided with such a cover plate is shown.

[0061] The multi-layer board MLB can be any material, such as an organic laminate (e.g., FR4) or formed from ceramic materials such as LTCC and HTCC. Ceramics are preferred because they have a higher thermal conductivity and because the thermal expansion of the ceramics matches the thermal expansion of the Si carrier. LTCC is preferred for the multi-layer board MLB.

[0062] The wiring is integrated within a multilayer board, and the wiring includes vias that pass through one or more of a ceramic or laminate layer and a wiring plane. The vias connect different wiring planes disposed between two such ceramic or laminate layers, or connect the wiring plane to a contact pad CP on the bottom surface or an external contact EC on the top surface. The wiring is used to interconnect and circuit-connect different signal pads and / or terminals, and provides connections between signal pads, antenna terminals, and external contacts EC disposed on the top of the multilayer board MLB.

[0063] Furthermore, the multilayer board may include integrated passive devices that can be formed by such integrated wiring. These passive devices can support the filter function of a filter circuit. Such integrated passive devices can be used to form a coil connected to an antenna terminal and an inductor in series with a parallel branch. Passive devices that require a higher quality factor (such as those used to match the terminals of a filter circuit) must be implemented as external discrete components that can be connected to external contacts.

[0064] The mounting of the stack ST to the multilayer board MLB can be done at the wafer level. Then, in a final step, the wafer-level package can be separated by cutting (e.g., by sawing) to separate individual devices.

[0065] Alternatively, a large-area multilayer board can be used to mount individual stacks that have been singulated prior to mounting.

[0066] Bumps BU are preferably used to connect the multilayer board to corresponding pads SP and terminals AT on the main surface of the stack ST. To facilitate heat dissipation from the filter circuit and the corresponding active piezoelectric layer to the multilayer board, the maximum number of bumps is preferred.

[0067] In Figure 3 the example, at least 13 pads and terminals need to be contacted separately by separate bumps. A larger number of parallel branches allows the mounting to be performed by a larger number of bumps. Additionally, bumps that do not have any electrical function can be used to provide better heat dissipation.

[0068] In the package, the areas of the stack and the multilayer board can be compatible. However, it may be advantageous if the margins of the stack or the board extend beyond the edge of another package layer. Then, the sealing layer can be applied from the side of the layer or stack with the smaller area. Then, the sealing layer can more easily seal the protruding surfaces in the margin area.

[0069] Sealing can be done using resin, laminate, or foil; and an airtight seal can be achieved by a metal layer as the top sealing layer. The sealing layer needs to be constructed to at least expose the external contacts EC of the package.

[0070] Since the present invention has been described with reference to some embodiments, the present invention should not be limited to any specific embodiment or figure. To the extent that the corresponding features are disclosed in a more general form and are covered by the claims, the features specified in writing or in the drawings in more detail only with reference to the embodiments should not be limited to that detail.

[0071] List of terms and reference numerals used

[0072] Cavity

[0073] Metallization

[0074] Package

[0075] Rx filter

[0076] Tx filter

[0077] AA Acoustic available area

[0078] AT Antenna terminal

[0079] BU Bump

[0080] CH Chip

[0081] CP Contact pad

[0082] DL Dielectric layer

[0083] EC External contact

[0084] ES Electrode structure

[0085] FC SAW filter circuit

[0086] IDT Interdigital transducer

[0087] IN Input terminal of DMS filter

[0088] MLB Multilayer board

[0089] OUT Output terminal of DMS filter

[0090] PL Piezoelectric layer

[0091] REF Reflector

[0092] RS,RP Series and parallel SAW resonators

[0093] SP Signal pad

[0094] SSL Series signal line

[0095] ST Monolithic stack

[0096] SU Carrier substrate

[0097] TRL Trap-rich layer

Claims

1. A device, comprising: A layer stack, comprising: A carrier substrate; A piezoelectric layer disposed above the carrier substrate; At least one dielectric layer disposed between the piezoelectric layer and the carrier substrate; A trap-rich layer disposed between the carrier substrate and the piezoelectric layer, wherein the trap-rich layer comprises polysilicon; and A metallization portion located on or above the piezoelectric layer, comprising: An antenna terminal; and An electrode structure forming four surface acoustic wave (SAW) filter circuits, the four surface acoustic wave (SAW) filter circuits being connected in parallel between the antenna terminal and corresponding signal pads, wherein each of the four SAW filter circuits comprises a corresponding series signal line and a corresponding plurality of SAW resonators, the corresponding plurality of SAW resonators being connected in series or in parallel with the corresponding series signal line; and A package providing a cavity on top of the layer stack, the cavity being formed between at least one of the piezoelectric layer and a lid or cover, wherein the electrode structure forming the four SAW filter circuits is enclosed within the cavity.

2. The device according to claim 1, wherein the carrier substrate comprises silicon (Si).

3. The device according to claim 1, wherein the at least one dielectric layer is a silicon oxide layer.

4. The device according to claim 1, wherein the polysilicon comprises a thickness between 300 nanometers (nm) and 2000 nm.

5. The device according to claim 1, wherein the carrier substrate has a thermal conductivity that is at least ten times greater than that of the piezoelectric layer.

6. The device according to claim 1, further comprising: A multilayer board forming at least part of the package, a bottom surface of the multilayer board comprising contact pads, wherein the multilayer board comprises integrated wiring connecting the contact pads and corresponding external contacts on a top surface opposite the bottom surface, and wherein the multilayer board is mounted to the layer stack using connections to electrically connect the contact pads to corresponding signal pads and the antenna terminal.

7. The device according to claim 6, wherein the multilayer board is selected from the group consisting of a multilayer laminate, HTCC, and LTCC.

8. The device according to claim 1, wherein the cavity is integrally formed.

9. The device according to claim 1, wherein the four SAW filter circuits form a quadplexer including two diplexers.

10. The device according to claim 1, wherein at least one of the four SAW filter circuits is a receive (Rx) filter having a DMS filter in the corresponding series signal line.

11. A device, comprising: A multiplexer comprising three surface acoustic wave (SAW) filter circuits, each of the three SAW filter circuits being coupled to a common antenna terminal and formed together on a single chip, the single chip comprising: A carrier substrate; A piezoelectric layer disposed above the carrier substrate; At least one dielectric layer disposed between the piezoelectric layer and the carrier substrate; A trap-rich layer disposed between the carrier substrate and the piezoelectric layer, wherein the trap-rich layer comprises polysilicon; and A metallization section, provided on or above the piezoelectric layer, includes: the common antenna terminal; and an electrode structure forming the three SAW filter circuits, wherein each of the three SAW filter circuits is formed of a corresponding plurality of SAW resonators.

12. The apparatus according to claim 11, wherein two of the three SAW filter circuits are configured to form a duplexer.

13. The apparatus according to claim 11, wherein two of the three SAW filter circuits are configured to form a duplexer, the duplexer having a first SAW filter circuit of the three SAW filter circuits configured for a receive frequency of a frequency band and a second SAW filter circuit of the three SAW filter circuits configured for a transmit frequency of the frequency band.

14. The apparatus according to claim 11, wherein In addition to the three SAW filter circuits, another SAW filter circuit is provided to form a quadruplexer.

15. The apparatus according to claim 14, wherein the quadruplexer includes a first duplexer associated with a first frequency band and a second duplexer associated with a second frequency band.

16. The apparatus according to claim 11, wherein the three SAW filter circuits are enclosed in a cavity formed integrally as a thin film acoustic package.

17. The apparatus according to claim 11, wherein the multiplexer further includes a package that provides a cavity enclosing the three SAW filter circuits and formed between the piezoelectric layer and a lid or cover.

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