Comparator based on dynamic feedback output common-mode stabilization preamplifier

Abstract

The invention provides a comparator based on a dynamic feedback output common-mode stabilization preamplifier, which relates to the technical field of electronic circuits, and comprises a preamplifier and a rear latch which are cascaded, the preamplifier transmits a differential output signal to the rear latch, and the comparator also comprises a dynamic sampling feedback circuit, the pull-up end of the preamplifier is directly connected with a power supply to generate pull-up current, and the pull-down end of the preamplifier is connected with the power supply through the dynamic sampling feedback circuit; and the dynamic sampling feedback circuit is used for sampling the differential output signal output by the preamplifier to obtain a common-mode voltage, comparing the common-mode voltage with a preset reference voltage, and controlling the charging time of the pull-down end of the preamplifier according to a comparison result to generate a pull-down current, so that the pull-down current is the same as the pull-up current. According to the invention, the pull-down current of the pre-amplifier is adjusted, the stability of the output common-mode voltage is realized, and the defect that the output result of the comparator is wrong due to the instability of the output common-mode voltage is overcome.

Description

Technical Field

[0001] The present invention relates to the technical field of electronic circuits, and in particular to a comparator based on a preamplifier with dynamically feedback output common-mode stability. Background Art

[0002] The noise and mismatch of traditional StrongArm comparators are strongly related to the size and current magnitude of components. It is usually formed by cascading a preamplifier and a post-latch. Under the action of the preamplifier, the noise and mismatch of the post-latch will reduce the equivalent input noise and mismatch, and reduce the operating current and size to meet the requirements of low-power and high-precision analog-to-digital converters.

[0003] The ratio of the transconductance to the current of traditional preamplifiers is limited by the process. Under different input voltages and process nodes, the output common-mode of the preamplifier will also change, and the post-latch cannot work properly, making the latch result controlled by random noise and causing the output result of the comparator to be incorrect. Summary of the Invention

[0004] The present invention provides a comparator based on a preamplifier with dynamically feedback output common-mode stability, which solves the defect that the output common-mode of the preamplifier of the existing comparator is unstable, resulting in incorrect output results of the comparator.

[0005] The present invention provides a comparator based on a preamplifier with dynamically feedback output common-mode stability, including a cascaded preamplifier and a post-latch. The preamplifier transmits a differential output signal to the post-latch, and further includes a dynamic sampling feedback circuit. The pull-up end of the preamplifier is directly connected to the power supply to generate a pull-up current, and the pull-down end of the preamplifier is connected to the power supply through the dynamic sampling feedback circuit; The dynamic sampling feedback circuit is used to sample the differential output signal output by the preamplifier to obtain a common-mode voltage, compare the common-mode voltage with a preset reference voltage, and control the charging time of the pull-down end of the preamplifier according to the comparison result to generate a pull-down current, so that the pull-down current is the same as the pull-up current.

[0006] According to a comparator based on a preamplifier with dynamically feedback output common-mode stability provided by the present invention, the dynamic sampling feedback circuit includes a sampling unit, a sampling comparator and a pulse generation unit, and the sampling unit is connected to the output end of the preamplifier; The preamplifier is used to amplify a differential input signal to obtain the differential output signal; The sampling unit is used to connect the two output voltages of the differential output signal to obtain the common-mode voltage and transmit the common-mode voltage to the sampling comparator; The sampling comparator is used to compare the common-mode voltage and the reference voltage, and output the comparison result to the pulse generation unit; The pulse generation unit includes a fixed pulse branch and an adjustable pulse branch. The adjustable pulse branch is used to respond to the comparison result and cooperate with the fixed pulse branch to adjust the pulse width of the charging pulse signal, and the charging pulse signal is used to control the charging time of the pull-down end of the preamplifier.

[0007] According to a comparator of a common-mode stable preamplifier based on dynamic feedback output provided by the present invention, the fixed pulse branch includes at least one delay element, the delay element is used to generate a fixed delay signal, the adjustable pulse branch includes an adjustable delay element, the bias voltage of the adjustable delay element is determined based on the comparison result and is used to generate an adjustable delay signal, and the delay difference between the fixed delay signal and the adjustable delay signal is used to determine the pulse width of the charging pulse signal.

[0008] According to a comparator of a common-mode stable preamplifier based on dynamic feedback output provided by the present invention, the fixed pulse branch includes at least one delay element, the delay element is used to generate a fixed delay signal, the adjustable pulse branch includes an adjustable delay element, a memory capacitor and a capacitor charging circuit. The capacitor charging circuit is used to charge the memory capacitor in response to the comparison result, and the memory capacitor is used to determine the bias voltage of the adjustable delay element to generate an adjustable delay signal, and the delay difference between the fixed delay signal and the adjustable delay signal is used to determine the pulse width of the charging pulse signal.

[0009] According to a comparator of a common-mode stable preamplifier based on dynamic feedback output provided by the present invention, the capacitor charging circuit is obtained by cascading a PMOS transistor and an NMOS transistor, and the output terminal of the sampling comparator is respectively connected to the gates of the PMOS transistor and the NMOS transistor.

[0010] According to a comparator of a common-mode stable preamplifier based on dynamic feedback output provided by the present invention, the comparison result includes that if the common-mode voltage of the sampling comparator is greater than the reference voltage, a low level is output, and if the common-mode voltage is less than the reference voltage, a high level is output.

[0011] According to a comparator of a common-mode stable preamplifier based on dynamic feedback output provided by the present invention, the sampling comparator is composed of a latch comparator.

[0012] According to a comparator of a common-mode stable preamplifier based on dynamic feedback output provided by the present invention, the reference voltage is determined based on the power supply voltage.

[0013] A comparator based on a dynamically feedback-output common-mode stable preamplifier provided by the present invention, wherein the dynamic sampling feedback circuit is further configured to perform multiple samplings on the differential output signal output by the preamplifier according to the manufacturing process of the preamplifier.

[0014] The present invention further provides an analog-to-digital converter, including the comparator based on the dynamically feedback-output common-mode stable preamplifier according to any one of the above.

[0015] The comparator based on the dynamically feedback-output common-mode stable preamplifier provided by the present invention includes a cascaded preamplifier and a post-latch. The preamplifier transmits the differential output signal to the post-latch, and further includes a dynamic sampling feedback circuit. The pull-up end of the preamplifier is directly connected to the power supply to generate a pull-up current, and the pull-down end of the preamplifier is connected to the power supply through the dynamic sampling feedback circuit. The dynamic sampling feedback circuit is configured to sample the differential output signal output by the preamplifier to obtain a common-mode voltage, compare the common-mode voltage with a preset reference voltage, and control the charging time of the pull-down end of the preamplifier according to the comparison result to generate a pull-down current, so that the pull-down current is the same as the pull-up current. The comparator based on the dynamically feedback-output common-mode stable preamplifier provided by the present invention adds a dynamic sampling feedback circuit to sample and feedback the differential output signal output by the preamplifier to adjust the charging time of the pull-down end of the preamplifier, so that the pull-down current is the same as the pull-up current, and finally realizes the stability of the output common-mode voltage and avoids the error of the comparator output result. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the technical solutions in the present invention or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the drawings in the following description are some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0017] Figure 1 is the circuit schematic diagram of a floating inverting amplifier.

[0018] Figure 2 is one of the circuit schematic diagrams of the comparator based on the dynamically feedback-output common-mode stable preamplifier provided by the present invention.

[0019] Figure 3 is the second circuit schematic diagram of the comparator based on the dynamically feedback-output common-mode stable preamplifier provided by the present invention.

[0020] Figure 4 is the circuit schematic diagram of the pulse generation unit provided by the present invention.

[0021] Figure 5 It is a schematic diagram of the signal waveform of the pulse generation unit provided by the present invention.

[0022] Figure 6a It is a schematic diagram of the area of the comparator of the common-mode stable preamplifier based on dynamic feedback output provided by the present invention. Figure 6b It is a schematic diagram of the area of the existing FIA comparator.

[0023] Figure 7a It is a schematic diagram of the stabilization process of the present invention under different process corners. Figure 7b It is a schematic diagram of the stabilization process of the present invention under different differential input signal conditions.

[0024] Figure 8 It is a schematic diagram of the control flow of the comparator of the common-mode stable preamplifier based on dynamic feedback output provided by the present invention.

[0025] In the figure, 1 - preamplifier, 2 - post-latch, 3 - dynamic sampling feedback circuit. Detailed implementation manners

[0026] To make the objectives, technical solutions and advantages of the present invention clearer, the technical solutions in the present invention will be clearly and completely described below with reference to the accompanying drawings in the present invention. Obviously, the described embodiments are some, but not all, of the embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art without making creative efforts based on the embodiments in the present invention belong to the scope of protection of the present invention.

[0027] Traditional preamplifiers use PMOS input or NMOS input. Its basic working principle is that when CLK = 0, the preamplifier is in the reset state and the post-latch does not work. When the rising edge of CLK arrives, it starts to amplify the input differential signal, and at the same time, the pull-up transistor of the post-latch is turned on. When the voltage of the output node drops to a certain level, the post-latch enters the positive feedback latch state, and the comparator quickly decides zero and one.

[0028] Under different input voltages and process nodes, the output common mode of the preamplifier will also change. At the same time, NMOS or PMOS input cannot achieve current multiplexing and cannot suppress noise by increasing the gain.

[0029] The floating inverter amplifier (FIA) uses a storage capacitor to supply power to the preamplifier to ensure the stability of the output common mode. Its circuit schematic diagram is as Figure 1 shown. In the reset state, first charge the storage capacitor C RES so that its voltage reaches VDD. In the amplification phase, the storage capacitor CRES Connected to the upper and lower ends of the amplifier. Since the charges on the upper and lower plates of the capacitor are equal, there will be no accumulation of common-mode charges at the output end of the amplifier, achieving stable output common-mode. However, the amplification speed will slow down. The storage capacitor C RES needs a relatively large capacitance value to ensure the normal output of the amplifier and suppress noise, and the area of the FIA comparator is also very large.

[0030] It can be seen from this that in the existing comparator under different processes and input common-mode conditions, due to the mismatch between the upper and lower currents of the preamplifier, the output common-mode will be unstable. The FIA comparator can achieve stable output common-mode by utilizing the coupling characteristic of positive and negative charges on the upper and lower plates of the capacitor, but it will reduce the amplification speed of the preamplifier and increase the area of the comparator.

[0031] The present invention provides a comparator based on a dynamic feedback output common-mode stable preamplifier, which can achieve stable output common-mode without increasing the area of the comparator. The following will be described in detail with reference to the accompanying drawings.

[0032] Figure 2 is one of the circuit schematic diagrams of the comparator based on a dynamic feedback output common-mode stable preamplifier provided by the present invention. As Figure 2 shown, the present invention provides a comparator based on a dynamic feedback output common-mode stable preamplifier, including a cascaded preamplifier 1 and a post-latch 2. The preamplifier 1 transmits the differential output signal to the post-latch 2. It also includes a dynamic sampling feedback circuit 3. The pull-up end of the preamplifier 1 is directly connected to the power supply to generate a pull-up current. The pull-down end of the preamplifier 1 is connected to the power supply through the dynamic sampling feedback circuit 3. The existing FIA comparator uses a storage capacitor to supply power to the preamplifier. The volume of the storage capacitor needs to be very large to stably supply power to the preamplifier, thereby increasing the area of the comparator. The present invention directly connects the pull-up end of the preamplifier 1 to the power supply without using a storage capacitor for power supply, thus reducing the area of the comparator.

[0033] The dynamic sampling feedback circuit 3 is used to sample the differential output signal output by the preamplifier 1 to obtain a common-mode voltage, compare the common-mode voltage with a preset reference voltage, and control the charging time of the pull-down end of the preamplifier 1 according to the comparison result to generate a pull-down current, so that the pull-down current is the same as the pull-up current. Due to the influence of the manufacturing process and the input common mode of the preamplifier 1, the output common mode is unstable. Therefore, the present invention proposes a dynamic sampling feedback circuit 3 to collect and judge the output common mode of the preamplifier 1. If the output common mode is unstable, the charging time of the pull-down end of the preamplifier 1 is adjusted so that the pull-down current gradually approaches the pull-up current until they are the same. After the pull-up current and the pull-down current are the same, it is proved that the output common mode of the preamplifier 1 is stable, and finally the output common mode, that is, the common-mode voltage, will be stabilized to the reference voltage. Optionally, the reference voltage is determined based on the power supply voltage. For example, the reference voltage is set to 1 / 2 of the power supply voltage, and it can be set according to the actual application scenario. The present invention does not limit this.

[0034] Combined with Figure 2 To illustrate the principle of the present invention, the pull-up end of the preamplifier 1 is directly connected to the power supply, and the generated pull-up current can be expressed as Ip. The differential input signals VIP and VIN are input to the preamplifier 1. The preamplifier 1 amplifies the differential input signals in response to the clock signal to obtain differential output signals VON and VOP and transmits them to the post-latch 2. The post-latch 2 outputs the comparator output results DON and DOP. Each time after the preamplifier 1 finishes amplifying the input signal, the dynamic sampling feedback circuit 3 connects the differential output signals VON and VOP together to obtain a common-mode voltage VOCM, and then compares the common-mode voltage VOCM with the reference signal VCM. According to the comparison result, the pull-down current In is adjusted to match the pull-up current Ip. After multiple sampling feedback adjustments, the common-mode voltage will be stabilized at the reference voltage VCM, ensuring the normal operation of the post-latch 2.

[0035] It can be understood that the comparator of the preamplifier with stable output common mode based on dynamic feedback provided by the present invention adds a dynamic sampling feedback circuit 3 to sample and feedback the differential output signal output by the preamplifier 1 to adjust the charging time of the pull-down end of the preamplifier 1, so that the pull-down current is the same as the pull-up current, and finally the stability of the output common-mode voltage is achieved, avoiding errors in the comparator output result.

[0036] Figure 3 is the second circuit schematic diagram of the comparator of the preamplifier with stable output common mode based on dynamic feedback provided by the present invention, as Figure 3As shown, on the basis of the above embodiments, as an optional embodiment, the dynamic sampling feedback circuit 3 includes a sampling unit, a sampling comparator, and a pulse generation unit. The sampling unit is connected to the output terminal of the preamplifier 1. The sampling unit is connected to the sampling comparator. The output terminal of the sampling comparator is connected to the input terminal of the pulse generation unit. The output terminal of the pulse generation unit is connected to the pull-down terminal of the preamplifier 1.

[0037] The preamplifier 1 is used to amplify the differential input signal to obtain the differential output signal. Specifically, the preamplifier 1 provided in the present invention includes a two-stage circuit structure. The first stage is a CMOS inverting amplifier structure composed of a pull-up PMOS transistor and a pull-down NMOS transistor, which can achieve current reuse and twice the transconductance, thereby achieving higher energy efficiency. The second stage is an existing StrongArm comparator, which can improve the comparison speed and reduce noise.

[0038] The sampling unit is used to connect the two output voltages of the differential output signal to obtain the common-mode voltage, and transmit the common-mode voltage to the sampling comparator. Optionally, the sampling unit can be composed of two sampling switches. The two sampling switches are respectively connected to the two outputs of the preamplifier and then connected together to the same pin of the sampling comparator.

[0039] The sampling comparator is used to compare the common-mode voltage and the reference voltage, and output the comparison result to the pulse generation unit. Optionally, the sampling comparator is composed of a latch comparator.

[0040] The pulse generation unit includes a fixed pulse branch and an adjustable pulse branch. The adjustable pulse branch is used to respond to the comparison result and cooperate with the fixed pulse branch to adjust the pulse width of the charging pulse signal. The charging pulse signal is used to control the charging time of the pull-down terminal of the preamplifier.

[0041] In an optional embodiment, the fixed pulse branch includes at least one delay element. The delay element is used to generate a fixed delay signal. In the embodiment of the present invention, the number of delay elements is two. The two delay elements are cascaded and used to generate a fixed delay signal after receiving the rising edge of the clock signal. After the fixed delay signal rises, the charging pulse signal rises.

[0042] The adjustable pulse branch includes an adjustable delay element. The adjustable delay element is connected to a power supply, and its bias voltage can be directly connected to the output of the sampling comparator. The bias voltage of the adjustable delay element is determined based on the comparison result and is used to generate an adjustable delay signal. The delay difference between the fixed delay signal and the adjustable delay signal is used to determine the pulse width of the charging pulse signal. Specifically, the comparison result is used to determine the level of the bias voltage. If the bias voltage is high, the power supply is not turned on, the adjustable delay element stops working, outputs a low level, and the charging pulse signal becomes a low level. It can be seen that the pulse width of the charging pulse signal is the difference in delay time between the fixed delay signal and the adjustable delay signal.

[0043] In another optional embodiment, the fixed pulse branch includes at least one delay element. The delay element is used to generate a fixed delay signal. In the embodiment of the present invention, the number of delay elements is two, and the two delay elements are cascaded to generate a fixed delay signal after receiving the rising edge of the clock signal. After the fixed delay signal rises, the charging pulse signal rises.

[0044] The adjustable pulse branch includes an adjustable delay element, a memory capacitor, and a capacitor charging circuit. The capacitor charging circuit is used to charge the memory capacitor in response to the comparison result. The memory capacitor is used to determine the bias voltage of the adjustable delay element to generate an adjustable delay signal. The delay difference between the fixed delay signal and the adjustable delay signal is used to determine the pulse width of the charging pulse signal.

[0045] Optionally, the capacitor charging circuit is obtained by cascading a PMOS transistor and an NMOS transistor. The output terminals of the sampling comparator are respectively connected to the gates of the PMOS transistor and the NMOS transistor.

[0046] Optionally, the comparison result includes that if the common-mode voltage of the sampling comparator is greater than the reference voltage, a low level is output; if the common-mode voltage is less than the reference voltage, a high level is output.

[0047] Figure 4 is a circuit schematic diagram of the pulse generation unit provided by the present invention, Figure 5 is a signal waveform schematic diagram of the pulse generation unit provided by the present invention. The working principle of the dynamic sampling feedback circuit will be described below in conjunction with Figure 4 and Figure 5 When the pulling-up terminal conduction ability of the preamplifier is greater than the pulling-down terminal conduction ability, the common-mode voltage will be greater than the reference voltage VCM. The sampling comparator outputs a low level to the capacitor charging circuit. The capacitor charging circuit conducts to supply power to the memory capacitor. The voltage of the memory capacitor increases, the bias voltage of the adjustable delay element increases, the delay of the adjustable delay element increases, the pulse of the charging pulse signal becomes wider, and the pulling-down terminal conduction ability is enhanced. On the contrary, the voltage of the memory capacitor becomes lower, the pulse of the pulse signal becomes narrower, and the pulling-down terminal conduction ability is reduced.

[0048] When the conduction ability of the PMOS at the pull-up end of the preamplifier 1 is greater than that of the NMOS at the pull-down end, the output common mode is greater than the reference voltage VCM, charging the memory capacitor, increasing the capacitor voltage, widening the pulse of the charging pulse signal VPULSE, thereby increasing the charging time of the NMOS, increasing the bias voltage of the NMOS, and enhancing its conduction ability. The conduction ability of the NMOS is closer to that of the PMOS in the next comparison period. After several rounds of dynamic approximation, the conduction ability of the NMOS will tend to be closer to that of the PMOS, and the output common mode of the preamplifier 1 will tend to the reference voltage VCM, thus ensuring a stable output common mode for the comparator under different PVT processes and input common mode signals, and ensuring the normal operation of the comparator. The present invention utilizes the memory characteristic of the capacitor, determines the bias voltage of the pull-down NMOS based on the quantity on the memory capacitor, dynamically adjusts the charge on the capacitor according to the previous comparison result, and gradually approximates to match the conduction abilities of the NMOS and PMOS, thereby achieving the stability of the output common mode. It should be noted that the memory capacitor does not need to supply power to the preamplifier 1, and there is no limitation on the capacitor model, which can greatly reduce the volume of the comparator.

[0049] Figure 6a It is a schematic diagram of the area of the comparator with a preamplifier for stable output common mode based on dynamic feedback provided by the present invention. Figure 6b It is a schematic diagram of the area of the existing FIA comparator, as Figure 6a and Figure 6b shown. The present invention has been post-simulated under the 22nm CMOS process and can meet the requirements of low power consumption and low noise. The overall area of the comparator with a preamplifier for stable output common mode based on dynamic feedback provided by the present invention can be saved by more than half compared to the FIA.

[0050] Figure 7a It is a schematic diagram of the stable process of the present invention under different process corners. Figure 7b It is a schematic diagram of the stable process of the present invention under different differential input signal conditions, as Figure 7a and Figure 7b shown. Without the dynamic feedback circuit, the output common mode will seriously deviate from VCM, resulting in the comparator being unable to operate normally when the output voltage is lower (higher) than the input comparator threshold voltage of the subsequent NMOS (PMOS). Under the condition of having a dynamic feedback circuit, the output common mode quickly stabilizes to VCM within 200ns, which can not only ensure low noise but also correctly compare to meet the robustness requirements. Therefore, the dynamic sampling feedback circuit 3 is also used to sample the differential output signal output by the preamplifier 1 multiple times according to the manufacturing process of the preamplifier 1.

[0051] Figure 8It is a schematic diagram of the control process of a comparator based on a dynamic feedback output common-mode stable preamplifier provided by the present invention. As Figure 8 shown, the control process of the comparator based on the dynamic feedback output common-mode stable preamplifier provided by the present invention includes three stages.

[0052] In the first stage φ1, the differential input signal is connected to the input terminal of the preamplifier. The bias voltage of the pull-up PMOS is set to 0, and the bias voltage of the pull-down NMOS is controlled by the dynamic sampling feedback circuit. Due to the different inputs of the differential input signal, the currents flowing through the two branches are not equal, causing the differential input signal to be integrally amplified at the output node. When the output voltages of VOP and VON are amplified to a level that can be resolved by the subsequent Latch, the amplification ends. The integral gain of the differential input signal is mainly related to the transconductance, parasitic capacitance, and integration time.

[0053] In the second stage φ2, the preamplifier finishes pre-amplification, and the subsequent latch works to generate the comparator output result. Due to the process influence of the preamplifier, the comparator output result may be incorrect. Next, the third stage is executed.

[0054] In the third stage φ3, the differential output signals of the preamplifier are connected together to generate an output common-mode signal. The dynamic sampling feedback circuit compares the common-mode voltage with the reference voltage VCM to determine whether to increase the pulse width, thereby increasing the charging time of the pull-down NMOS, enhancing its conductivity, and making its conductivity closer to that of the pull-up PMOS in the next comparison cycle. The comparison cycle refers to a high-level cycle of the clock signal. After repeating several comparison cycles, the common-mode voltage stabilizes at the reference voltage, and the comparator output result stabilizes, and will no longer be incorrect due to process and input common-mode influences.

[0055] In summary, the present invention uses a dynamic feedback loop to adjust the conductivity of the NMOS to match that of the PMOS, so as to match the currents of the PMOS and NMOS under different PVT conditions and input common-modes, thereby achieving the stability of the output common-mode. The power consumption of the dynamic feedback loop is very small, which can overcome the power consumption disadvantage of the static feedback circuit. At the same time, avoiding the use of the large capacitor of the Reservoir in the FIA comparator can greatly reduce the area of the entire amplifier, and can also improve the comparison speed. The dynamic feedback structure provided by the present invention can enable the comparator to efficiently and correctly compare the results under various input common-modes, process corners, and harsh temperature conditions, and is applicable to signal environments and temperature environments.

[0056] Next, the analog-to-digital converter provided by the present invention is described. The analog-to-digital converter described below can be mutually corresponding and referenced with the comparator based on the dynamic feedback output common-mode stable preamplifier described above.

[0057] The present invention also provides an analog-to-digital converter, including the comparator based on a dynamically feedback-output common-mode stable preamplifier according to any one of the above.

[0058] As an embodiment, the comparator based on a dynamically feedback-output common-mode stable preamplifier includes a cascaded preamplifier and a post-latch. The preamplifier transmits a differential output signal to the post-latch, and further includes a dynamic sampling feedback circuit. The pull-up end of the preamplifier is directly connected to a power supply to generate a pull-up current, and the pull-down end of the preamplifier is connected to the power supply via the dynamic sampling feedback circuit. The dynamic sampling feedback circuit is configured to sample the differential output signal output by the preamplifier to obtain a common-mode voltage, compare the common-mode voltage with a preset reference voltage, and control the charging time of the pull-down end of the preamplifier according to the comparison result to generate a pull-down current, so that the pull-down current is the same as the pull-up current.

[0059] As an embodiment, the dynamic sampling feedback circuit includes a sampling unit, a sampling comparator, and a pulse generation unit. The sampling unit is connected to the output end of the preamplifier. The preamplifier is configured to amplify a differential input signal to obtain the differential output signal. The sampling unit is configured to connect the two output voltages of the differential output signal to obtain the common-mode voltage and transmit the common-mode voltage to the sampling comparator. The sampling comparator is configured to compare the common-mode voltage with the reference voltage and output the comparison result to the pulse generation unit. The pulse generation unit includes a fixed pulse branch and an adjustable pulse branch. The adjustable pulse branch is configured to, in response to the comparison result, cooperate with the fixed pulse branch to adjust the pulse width of a charging pulse signal, and the charging pulse signal is used to control the charging time of the pull-down end of the preamplifier.

[0060] As an embodiment, the fixed pulse branch includes at least one delay element configured to generate a fixed delay signal, and the adjustable pulse branch includes an adjustable delay element. The bias voltage of the adjustable delay element is determined based on the comparison result and is configured to generate an adjustable delay signal. The delay difference between the fixed delay signal and the adjustable delay signal is used to determine the pulse width of the charging pulse signal.

[0061] As an embodiment, the fixed pulse branch includes at least one delay element, which is configured to generate a fixed delay signal. The adjustable pulse branch includes an adjustable delay element, a memory capacitor, and a capacitor charging circuit. The capacitor charging circuit is configured to charge the memory capacitor in response to the comparison result. The memory capacitor is configured to determine the bias voltage of the adjustable delay element to generate an adjustable delay signal. The delay difference between the fixed delay signal and the adjustable delay signal is used to determine the pulse width of the charging pulse signal.

[0062] As an embodiment, the capacitor charging circuit is formed by cascading a PMOS transistor and an NMOS transistor. The output terminals of the sampling comparator are respectively connected to the gates of the PMOS transistor and the NMOS transistor.

[0063] As an embodiment, the comparison result includes that if the common-mode voltage of the sampling comparator is greater than the reference voltage, a low level is output; if the common-mode voltage is less than the reference voltage, a high level is output.

[0064] As an embodiment, the sampling comparator is composed of a latch comparator.

[0065] As an embodiment, the reference voltage is determined based on the power supply voltage.

[0066] As an embodiment, the dynamic sampling feedback circuit is further configured to perform multiple samplings on the differential output signal output by the preamplifier according to the manufacturing process of the preamplifier.

[0067] It should be noted that the analog-to-digital converter provided by the present invention includes the comparator based on the dynamically feedback output common-mode stable preamplifier described in any of the above embodiments, and has the corresponding technical effects of the comparator based on the dynamically feedback output common-mode stable preamplifier. Details thereof are not described in this embodiment.

[0068] In the description of this specification, the descriptions with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples", etc. mean that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the embodiments of the present invention. In this specification, the schematic descriptions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described can be combined in a suitable manner in any one or more embodiments or examples. In addition, without conflict, those skilled in the art can combine and combine the different embodiments or examples described in this specification and the features of different embodiments or examples.

[0069] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements for some of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A comparator based on a dynamic feedback output common-mode stable preamplifier, comprising a cascaded preamplifier and a post-stage latch, wherein the preamplifier transmits a differential output signal to the post-stage latch, and is characterized in that, It further includes a dynamic sampling feedback circuit. The pull-up end of the preamplifier is directly connected to the power supply to generate a pull-up current, and the pull-down end of the preamplifier is connected to the power supply via the dynamic sampling feedback circuit; The dynamic sampling feedback circuit is used to sample the differential output signal output by the preamplifier to obtain a common-mode voltage, compare the common-mode voltage with a preset reference voltage, and control the charging time of the pull-down end of the preamplifier according to the comparison result to generate a pull-down current, so that the pull-down current is the same as the pull-up current.

2. The comparator of the common-mode stable preamplifier based on dynamic feedback output according to claim 1, characterized in that, The dynamic sampling feedback circuit includes a sampling unit, a sampling comparator and a pulse generation unit. The sampling unit is connected to the output end of the preamplifier; The preamplifier is used to amplify a differential input signal to obtain the differential output signal; The sampling unit is used to connect the two output voltages of the differential output signal to obtain the common-mode voltage and transmit the common-mode voltage to the sampling comparator; The sampling comparator is used to compare the common-mode voltage and the reference voltage and output the comparison result to the pulse generation unit; The pulse generation unit includes a fixed pulse branch and an adjustable pulse branch. The adjustable pulse branch is used to respond to the comparison result and cooperate with the fixed pulse branch to adjust the pulse width of a charging pulse signal, and the charging pulse signal is used to control the charging time of the pull-down end of the preamplifier.

3. The comparator of the common-mode stable preamplifier based on dynamic feedback output according to claim 2, wherein The fixed pulse branch includes at least one delay element, and the delay element is used to generate a fixed delay signal. The adjustable pulse branch includes an adjustable delay element. The bias voltage of the adjustable delay element is determined based on the comparison result and is used to generate an adjustable delay signal. The delay difference between the fixed delay signal and the adjustable delay signal is used to determine the pulse width of the charging pulse signal.

4. The comparator of the common-mode stable preamplifier based on dynamic feedback output according to claim 2, characterized in that, The fixed pulse branch includes at least one delay element, and the delay element is used to generate a fixed delay signal. The adjustable pulse branch includes an adjustable delay element, a memory capacitor and a capacitor charging circuit. The capacitor charging circuit is used to charge the memory capacitor in response to the comparison result. The memory capacitor is used to determine the bias voltage of the adjustable delay element to generate an adjustable delay signal. The delay difference between the fixed delay signal and the adjustable delay signal is used to determine the pulse width of the charging pulse signal.

5. The comparator of the common-mode stable preamplifier based on dynamic feedback output according to claim 4, wherein The capacitor charging circuit is obtained by cascading a PMOS transistor and an NMOS transistor. The output end of the sampling comparator is respectively connected to the gates of the PMOS transistor and the NMOS transistor.

6. The comparator of the common-mode stable preamplifier based on dynamic feedback output according to any one of claims 3-5, characterized in that, The comparison result includes that if the common-mode voltage of the sampling comparator is greater than the reference voltage, a low level is output; if the common-mode voltage is less than the reference voltage, a high level is output.

7. The comparator of the common-mode stable preamplifier based on dynamic feedback output according to claim 6, wherein The sampling comparator is composed of a latch comparator.

8. The comparator of the common-mode stable preamplifier based on dynamic feedback output according to claim 1, characterized in that, The reference voltage is determined based on the power supply voltage.

9. The comparator of the common-mode stable preamplifier based on dynamic feedback output according to claim 1, characterized in that, The dynamic sampling feedback circuit is also used to sample the differential output signal output by the preamplifier multiple times according to the manufacturing process of the preamplifier.

10. An analog-to-digital converter, characterized in that, A comparator for a common-mode stable preamplifier with dynamic feedback output according to any one of claims 1-9.

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