Compact single-ended data receiver based on alternating current coupling

Abstract

The invention provides a compact single-ended data receiver based on AC coupling, the receiver comprising at least one data receiving channel, each data receiving channel comprising: a front-end driver comprising an AC coupling architecture, the front-end driver being used for driving a single path of data sent by a transmitter to a demultiplexer in a process of driving the single path of data sent by the transmitter to the demultiplexer, an alternating-current coupling architecture is adopted to block direct-current components in single-path data, and power supply voltages between the receiver and the transmitter are matched with each other; the clock generator is used for generating a clock signal according to the reference clock corresponding to each data receiving channel and transmitting the clock signal to the demultiplexer; and the demultiplexer is used for deserializing the single-path data transmitted by the front-end driver into multi-path parallel data according to the clock signal transmitted by the clock generator.

Description

Technical Field

[0001] The present invention relates to the field of data reception in high-speed data interfaces, and particularly to a compact single-ended data receiver based on AC coupling. Background Art

[0002] In the rapid development process of modern technology, the integrated circuit field is facing unprecedented changes and challenges. With the booming rise of emerging technologies such as 5G networks, the Internet of Things, and intelligent driving, the creation, capture, replication, and consumption of data have shown an explosive growth trend, which makes the demand for data transmission between chips grow increasingly and become more stringent. In the chip interconnection architecture, the connection between chiplets is crucial. Traditionally, differential signaling schemes have met the data transmission requirements to a certain extent, but with the further development of technology, their limitations have gradually emerged. In the face of high-density IO requirements, differential signaling schemes seem powerless and are difficult to efficiently adapt to the increasing data transmission bandwidth requirements between chips. At the same time, their relatively high power consumption efficiency has also become a non-negligible disadvantage in energy-sensitive modern electronic devices. In contrast, single-ended signaling schemes have gradually come into the field of research and application with their unique advantages. Single-ended signaling schemes have double-pin efficiency and relatively low power consumption efficiency, which provides new ideas and directions for solving the problem of high-speed data transmission between chips. Therefore, in order to meet the urgent needs of future electronic devices for high-speed, small-area, and low-power data transmission between chips, a compact AC-coupled single-ended data receiver is necessary for SerDes chips in many practical application fields. Summary of the Invention

[0003] In view of this, the present invention provides a compact single-ended data receiver based on AC coupling.

[0004] An embodiment of the present invention provides a compact single-ended data receiver based on AC coupling. The receiver includes at least one data reception channel, and each data reception channel includes: a front-end driver including an AC coupling architecture, which is used to block the DC component in the single-channel data during the process of driving the single-channel data sent by the transmitter to the demultiplexer and to make the power supply voltages between the receiver and the transmitter match each other; a clock generator, which is used to generate a clock signal according to the reference clock corresponding to each data reception channel and transmit the clock signal to the demultiplexer; and a demultiplexer, which is used to deserialze the single-channel data transmitted by the front-end driver into multi-channel parallel data according to the clock signal transmitted by the clock generator.

[0005] According to an embodiment of the present invention, the front-end driver includes: a capacitor, the first end of the capacitor is connected to the input end of the front-end driver; a third resistor, both ends of the third resistor are respectively connected to the first end of the capacitor and the ground terminal, and the third resistor and the capacitor form an AC coupling architecture; a first inverter, the input end of the first inverter is connected to the second end of the capacitor; a second inverter, the input end of the second inverter is connected to the output end of the first inverter, and the output end of the second inverter is connected to the output end of the front-end driver; a first resistor, both ends of the first resistor are respectively connected to the input end of the first inverter and the input end of the second inverter; a second resistor, both ends of the second resistor are respectively connected to the input end of the first inverter and the output end of the second inverter.

[0006] According to an embodiment of the present invention, the front-end driver further includes: a continuous-time linear equalizer, the output end of the continuous-time linear equalizer is connected to the input end of the second inverter, and the continuous-time linear equalizer is used to compensate for the attenuation of high-frequency components in the single-channel data.

[0007] According to an embodiment of the present invention, the continuous-time linear equalizer includes: a fourth resistor and a fifth resistor, the first ends of the fourth resistor and the fifth resistor are both connected to the input end of the second inverter; a first transistor to a fourth transistor, the source of the first transistor is connected to the power supply, the drain of the first transistor is connected to the drain of the second transistor, the source of the second transistor is connected to the drain of the third transistor, the source of the third transistor is connected to the drain of the fourth transistor, the source of the fourth transistor is grounded, and the first ends of the fourth resistor and the fifth resistor are also both connected to the source of the second transistor, the second end of the fourth resistor is connected to the gate of the second transistor, and the second end of the fifth resistor is connected to the gate of the third transistor.

[0008] According to an embodiment of the present invention, the clock signal includes a differential clock, a first single-ended clock, and a second single-ended clock, the frequency of the first single-ended clock is a half-frequency of the frequency of the differential clock, and the frequency of the second single-ended clock is a half-frequency of the frequency of the first single-ended clock; the demultiplexer includes: a first-stage demultiplexing structure, which is used to deserialize the single-channel data into two-channel parallel data according to the differential clock; a second-stage demultiplexing structure, which is used to deserialized the two-channel parallel data into four-channel parallel data according to the first single-ended clock; a third-stage demultiplexing structure, which is used to deserialized the four-channel parallel data into eight-channel parallel data according to the second single-ended clock.

[0009] According to an embodiment of the present invention, the first-stage demultiplexing structure includes: a first comparator, including a first non-inverting input terminal, a first inverting input terminal, and a first clock control terminal, the first non-inverting input terminal is used to receive a single-channel data, the first inverting input terminal is used to receive a reference signal, and the first clock control terminal is used to receive a differential clock; a second comparator, including a second non-inverting input terminal, a second inverting input terminal, and a second clock control terminal, the second non-inverting input terminal is used to receive a single-channel data, the second inverting input terminal is used to receive a reference signal, and the second clock control terminal is used to receive a differential clock; a first flip-flop, including a first data input terminal, a first clock input terminal, and a first output terminal, the first data input terminal is connected to the output terminal of the first comparator, and the first clock input terminal inputs the first path of the differential clock; a second flip-flop, including a second data input terminal, a second clock input terminal, and a second output terminal, the second data input terminal is connected to the first output terminal, the second clock input terminal inputs the second path of the differential clock, the first path of the clock is differential from the second path of the clock, and the second output terminal is connected to the second-stage demultiplexing structure; a third flip-flop, including a third data input terminal, a third clock input terminal, and a third output terminal, the third data input terminal is connected to the output terminal of the second comparator, the third clock input terminal inputs the second path of the clock, and the third output terminal is connected to the second-stage demultiplexing structure.

[0010] According to an embodiment of the present invention, both the second-stage demultiplexing structure and the third-stage demultiplexing structure are composed of a plurality of true single-phase clock data flip-flops, and the true single-phase clock data flip-flop samples the input data at the rising edge and the falling edge of the single-ended clock respectively.

[0011] According to an embodiment of the present invention, the clock generator includes: a phase detector, used to compare the phase of the externally input reference clock with the frequency-divided clock signal and output a voltage signal; a filter, used to suppress the high-frequency components of the voltage signal to obtain a filtered signal; a converter, used to convert the filtered signal and the externally input control voltage into a control current; an oscillator, used to generate a clock signal and tune the frequency and phase of the clock signal output according to the control current.

[0012] According to an embodiment of the present invention, the control voltage is also used to adjust the oscillator to the target operating range; the phase detector is implemented based on an exclusive-OR gate architecture, and the gain of the phase detector is 2Icp / π, where Icp represents the charge pump current.

[0013] According to an embodiment of the present invention, each data receiving channel further includes: a buffer, used to buffer and output the multi-channel parallel data.

[0014] It can be seen from the above technical solutions that the compact single-ended data receiver based on AC coupling according to the embodiment of the present invention has at least the following beneficial effects:

[0015] (1) The present invention can deserialze the single-channel serial data transmitted from the transmitter and restore it to multi-channel (e.g., 8-channel) parallel data. By adopting the forward clock technology, it can eliminate the need for a data clock recovery circuit. The reference clock is transmitted through a separate channel, significantly saving circuit area and power consumption.

[0016] (2) The present invention adopts an AC coupling architecture to block the transmission of the DC component of the signal, avoid the problem of power supply voltage mismatch between the receiver and the transmitter, and effectively suppress the influence of ground potential difference on signal quality. Compared with AC coupling at the output end of the transmitter, it does not require additional confirmation of the channel load, reducing the design complexity of impedance matching.

[0017] (3) The receiver of the present invention has a compact structure, with a single-channel data rate up to 32 Gb / s and a margin to meet the 40 Gb / s data rate. It can also be combined into multiple channels according to requirements to achieve multi-channel transmission, having broad application prospects in fields such as large-scale data centers, intelligent driving, and the Internet of Things. Description of the Drawings

[0018] Figure 1 Schematically shows a block diagram of a single-channel compact single-ended data receiver based on AC coupling according to an embodiment of the present invention.

[0019] Figure 2 Schematically shows a circuit block diagram of a front-end driver according to an embodiment of the present invention.

[0020] Figure 3 Schematically shows a circuit block diagram of a 1:8 demultiplexer according to an embodiment of the present invention.

[0021] Figure 4 Schematically shows a circuit block diagram of the first-stage demultiplexing structure of a 1:8 demultiplexer according to an embodiment of the present invention.

[0022] Figure 5 Schematically shows a circuit block diagram of the second and third-stage demultiplexing structures of a 1:8 demultiplexer according to an embodiment of the present invention. Detailed Embodiments

[0023] As used herein, when an element is referred to as "connected" or "coupled", it may mean "electrically connected" or "electrically coupled". "Connected" or "coupled" can also be used to indicate the mutual cooperation or interaction between two or more elements. In addition, although terms such as "first", "second",... are used herein to describe different elements, these terms are only used to distinguish elements or operations described with the same technical terms. Unless the context clearly indicates otherwise, these terms do not particularly refer to or imply an order or sequence, nor are they used to limit the present invention.

[0024] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and this invention, and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0025] The following will disclose multiple embodiments of the present invention in diagrams. For the sake of clarity, many practical details will be described together in the following narrative. However, it should be understood that these practical details are not used to limit the present invention. That is to say, in some embodiments of the present invention, these practical details are unnecessary. In addition, for the purpose of simplifying the diagrams, some well-known conventional structures and elements will be shown in a simple schematic manner in the diagrams.

[0026] In this article, a compact single-ended data receiver based on AC coupling may include one or more data receiving channels. That is to say, the receiver of the present invention can be a single-channel receiver or a multi-channel receiver. The multi-channel receiver can combine multiple single channels for use as needed. Therefore, the structure and details of the single-channel receiver will be mainly introduced below.

[0027] Figure 1 A block diagram of a compact single-ended data receiver based on AC coupling according to an embodiment of the present invention is schematically shown.

[0028] As Figure 1 shown, the single-channel compact single-ended data receiver 100 may include a front-end driver 10, a clock generator 20, and a demultiplexer 30.

[0029] The front-end driver 10 is connected to the demultiplexer 30. When the front-end driver 10 drives the single-channel data DATA_IN sent by a transmitter (not shown in the figure) to the demultiplexer 30, the AC coupling architecture in the front-end driver 10 can block the DC component in the single-channel data DATA_IN, so that the power supply voltages between the receiver 100 and the transmitter match each other. By using the AC coupling architecture to block the transmission of the DC component of the signal, avoiding the problem of power supply voltage mismatch between the receiver and the transmitter, and effectively suppressing the influence of the ground potential difference on the signal quality, compared with AC coupling at the output end of the transmitter, there is no need to additionally confirm the channel load, reducing the design complexity of impedance matching.

[0030] The clock generator 20 is connected to the demultiplexer 30. The clock generator 20 can generate a clock signal according to the reference clock corresponding to each data receiving channel, and transmit the clock signal to the demultiplexer 30. The demultiplexer 30 can deserialze the single-channel data DATA_IN transmitted by the front-end driver 10 into multi-channel parallel data DATA_OUT according to the clock signal transmitted by the clock generator 20. For example, it can deserialize 1-channel data into 8-channel data. In this embodiment, the single-channel compact single-ended data receiver 100 adopts the forward clock technology and does not require an additional clock data recovery circuit. It has the advantages of a compact architecture, small area, and low power consumption, and has broad application prospects in fields such as large-scale data centers, intelligent driving, and the Internet of Things. The rate of the single-channel compact single-ended data receiver 100 can reach 32 Gb / s.

[0031] Please continue to refer to Figure 1 , the clock generator 20 may further include a phase detector 21, a filter 22, a converter 23, and an oscillator 24. The phase detector 21, the filter 22, the converter 23, and the oscillator 24 are connected in sequence to form a phase-locked loop. In this loop, the phase detector 21 can compare the phase of the externally input reference clock CLK_REF with the clock signal after frequency division by the oscillator 24, and output a voltage signal Vp. The output voltage signal Vp can represent the phase difference between the two. The filter 22 can suppress the high-frequency components of the voltage signal Vp to obtain a filtered signal Vpn. The converter 23 can convert the filtered signal Vpn and the externally input control voltage Vx into a control current Ic. The oscillator 24 can generate quadrature clock signals and tune the frequency and phase of the clock signal output according to the control current Ic.

[0032] In some embodiments, the control voltage Vx can be used to coarsely adjust the oscillator 24 to the normal required operating range. Further description will be made in the working steps of the compact single-ended data receiver 100 later.

[0033] In some embodiments, the phase detector 21 can be implemented based on an exclusive-OR gate architecture. When the phase-locked loop is in the locked state, the output voltage of the exclusive-OR gate-based phase detector (XORPD) tends to be stable, and the output average current is equal to the difference between the product of the charging time and the charging current magnitude and the product of the discharging time and the discharging current magnitude divided by the total time. By adjusting the number of bits of the control signal DLY<19:0>, the magnitudes of the charging current and the discharging current can be adjusted. When the magnitudes of the charging current and the discharging current change, the charging time and the discharging time also change accordingly, resulting in a change in the phase of the feedback signal, achieving the effect of adjusting the time delay.

[0034] In some embodiments, the gain of the phase detector 21 can be 2I cp / π, I cpIndicates the charge pump current. The gain of the traditional architecture phase frequency detector is usually 0.5I cp / π. Under the same loop bandwidth, the charge pump current XOR gate required by the present invention is only one-fourth of that of the traditional architecture, greatly reducing the power consumption.

[0035] Please continue to refer to Figure 1 , the single-channel compact single-ended data receiver 100 may further include a buffer 40 for buffering and outputting the multiplexed parallel data. The buffer 40 can buffer the multiplexed parallel data output by the demultiplexer 30 to improve the driving ability of the output data signal and can hand over the output data signal to the subsequent circuit.

[0036] The working process of the single-channel compact single-ended data receiver 100 is described as follows:

[0037] When powering on and starting up, the signal PLL_RST is set to a low level, the loop filter 22 discharges to 0 level, disconnecting the entire phase-locked loop, and the ring current-controlled oscillator 24 starts to oscillate and operates at the initial frequency. After powering on for a period of time, the signal PLL_RST is set to a high level, the loop is closed, and the phase detector 21 based on the XOR gate structure compares the phase difference between the input reference signal CLK_REF and the feedback signal of the ring current-controlled oscillator 24, and outputs a voltage signal Vp proportional to the phase difference, which is sent to the loop filter 22. The control voltage is converted into a control current Ic through the loop filter 22 to adjust the frequency of the quadrature clock of the output signal of the current-controlled oscillator 24. One group of the quadrature clocks is fed back to the phase detector 21 based on the XOR gate structure after passing through the frequency divider. When the phase difference between the input signal and the feedback signal after passing through the frequency divider is zero, the phase-locked loop is locked. In addition, by adjusting the control word DLY<19:0>, the magnitudes of the charging current and the discharging current are adjusted, thereby changing the charging time and the discharging time, achieving the effect of time delay; the other group of output signals provides a clock for the demultiplexer 30, and the demultiplexer 30 decomposes the single-channel data into multiplexed data.

[0038] Figure 2 Schematically shows a circuit block diagram of a front-end driver according to an embodiment of the present invention.

[0039] As Figure 1 and Figure 2As shown, the front-end driver 10 may include a capacitor C1, a resistor R1, a resistor R2, a resistor R3, an inverter INV1, and an inverter INV2. The first terminal of the capacitor C1 (the left side of the capacitor C1 in the figure) is connected to the input terminal of the front-end driver 10, that is, single-channel data is input. Both ends of the resistor R3 are respectively connected to the first terminal of the capacitor C1 and the ground terminal. The resistor R3 and the capacitor C1 form an AC coupling architecture. Specifically, the capacitor C1 can block the DC component of the signal and only allow the AC signal to pass through. The resistor R3 can provide a ground loop for the AC signal, avoid the problem of power supply voltage mismatch between the receiver and the transmitter, and suppress the influence of ground potential difference on the signal quality. The input terminal of the inverter INV1 (the left side of the inverter INV1 in the figure) is connected to the second terminal of the capacitor C1 (the right side of the capacitor C1 in the figure). The input terminal of the inverter INV2 (the left side of the inverter INV2 in the figure) is connected to the output terminal of the inverter INV1 (the right side of the inverter INV1 in the figure), and the output terminal of the inverter INV2 (the right side of the inverter INV2 in the figure) is connected to the output terminal of the front-end driver 10, that is, the output voltage Vout. Both ends of the resistor R1 are respectively connected to the input terminal of the inverter INV1 and the input terminal of the inverter INV2, and both ends of the resistor R2 are respectively connected to the input terminal of the inverter INV1 and the output terminal of the inverter INV2. In this embodiment, the resistor R2 can provide positive feedback, form a voltage divider with the inverter INV1 and the inverter INV2, and feedback the output signal polarity to the receiver input, which helps to stabilize the circuit state and signal processing. The resistor R1 plays a role of negative feedback, driving the input voltage to the high-gain point of the inverter, ensuring that the receiver input is affected by both the receiver output and the feedback network polarity, and enabling the circuit to switch between two stable DC states.

[0040] In some embodiments, the front-end driver 10 further includes a Continuous Time Linear Equalizer (CTLE). The continuous time linear equalizer can be used to compensate for the attenuation of high-frequency components in the single-channel data to cope with different channel conditions, and at the same time, it significantly reduces the circuit area compared with the passive coil inductor.

[0041] As Figure 2 shown, the CTLE adopted by the front-end driver 10 may include resistors R4 to R5, transistors M1 to M4. The first terminals of the resistor R4 and the resistor R5 are both connected to the input terminal of the inverter INV2. The source of the transistor M1 is connected to the power supply, the drain of the transistor M1 is connected to the drain of the transistor M2, the source of the transistor M2 is connected to the drain of the transistor M3, the source of the transistor M3 is connected to the drain of the fourth transistor, the source of the transistor M4 is grounded, the first terminals of the resistor R4 and the resistor R5 are also both connected to the source of the transistor M2, the second terminal of the resistor R4 is connected to the gate of the transistor M2, and the second terminal of the resistor R5 is connected to the gate of the transistor M3.

[0042] As an example, transistors M1 and M4 can be PMOS transistors, and transistors M2 and M3 can be NMOS transistors. By turning on and off to control the current, the active inductor function is achieved. When the input signal changes, for example, from a low level to a high level, the NMOS transistor (such as transistor M3, etc.) turns on, which can accelerate the output discharge process, make the signal edge steeper, and expand the circuit bandwidth. Resistors R4 and R5 cooperate with these MOS transistors to set parameters such as the operating point and impedance of the active inductor circuit, adjust the characteristics of the active inductor, and compensate for the attenuation of high-frequency components caused by channel attenuation to adapt to different channel conditions. At the same time, compared with the passive coil inductor, the active inductor greatly reduces the circuit area.

[0043] Figure 3 A circuit block diagram of a 1:8 demultiplexer according to an embodiment of the present invention is schematically shown.

[0044] Please refer to Figure 1 and Figure 3 , the demultiplexer 30 can have a three-stage structure, and each stage is composed of a demultiplexer DEMUX 1:2 to serially deserialize the data step by step. During the entire serial-to-parallel conversion process, 3 groups of clocks with gradually decreasing speeds (dividing by two step by step) are required, and the clock division is completed by designing a frequency divider. The clock signal can be divided into clock CLKN and clock CLKP, which form a differential clock, single-ended clock CLK2, and single-ended clock CLK4. The frequency of the single-ended clock CLK2 is half of the frequency of the differential clock CLKN and CLKP, and the frequency of the single-ended clock CLK4 is half of the frequency of the single-ended clock CLK2. In addition, since the output data edge of each stage of DEMUX1:2 is aligned with the output clock edge of that stage, in order to ensure that the data can be correctly sampled at the clock signal edge at the receiving end, a clock alignment operation can be performed, that is, the rising edge or falling edge of the clock signal is exactly aligned with the center point of data transmission. This can utilize the delay of the inverter and add multiple groups of inverters between the frequency dividers to achieve the clock delay effect.

[0045] As Figure 3 shown, the demultiplexer 30 can include demultiplexers DEMUX1 to DEMUX7, and the overall structure is three-stage. The first-stage demultiplexing structure includes demultiplexer DEMUX1, which can deserialize the single-channel data D_in into two-channel parallel data according to the differential clocks CLKN and CLKP. The second-stage demultiplexing structure includes demultiplexers DEMUX2 and DEMUX3, which can deserialize the two-channel parallel data into four-channel parallel data according to the first single-ended clock CLK2. The third-stage demultiplexing structure includes demultiplexers DEMUX4 to DEMUX7, which can deserialize the four-channel parallel data into eight-channel parallel data D_0 to D_7 according to the second single-ended clock CLK4.

[0046] Figure 4 Schematically shows a circuit block diagram of the first-stage demultiplexing structure of a 1:8 demultiplexer according to an embodiment of the present invention.

[0047] As Figure 3 and Figure 4 shown, the first-stage demultiplexing structure may include comparator 1, comparator 2, D flip-flop (i.e., data flip-flop) 1, D flip-flop 2, and D flip-flop 3. Both comparator 1 and comparator 2 include a non-inverting input terminal (i.e., the “+” port), an inverting input terminal (i.e., the “-” port), and clock control terminals CK and CKB. All of D flip-flop 1, D flip-flop 2, and D flip-flop 3 include a data input terminal D, a clock input terminal CK, and an output terminal Q. The non-inverting input terminal of comparator 1 receives single-channel data D_in, the inverting input terminal of comparator 1 receives a reference signal REF, and the clock control terminals of comparator 1 respectively receive differential clocks CLKP and CLKN. The non-inverting input terminal of comparator 2 receives single-channel data, the inverting input terminal of comparator 2 receives a reference signal, and the clock control terminals of comparator 2 receive differential clocks CLKP and CLKN. The data input terminal of D flip-flop 1 is connected to the output terminal of comparator 1, and the clock input terminal of D flip-flop 1 inputs clock CLKN. The data input terminal of D flip-flop 2 is connected to the output terminal of D flip-flop 1, the clock input terminal of D flip-flop 2 inputs the clock CLKP of the differential clock, the clock CLKN and the clock CLKP are differential, and the output terminal of D flip-flop 2 is connected to the second-stage demultiplexing structure. The data input terminal of D flip-flop 3 is connected to the output terminal of comparator 2, the clock input terminal of D flip-flop 3 inputs clock CLKP, and the output terminal of D flip-flop 3 is connected to the second-stage demultiplexing structure. In this way, the single-channel data D_in is deserialized into output signal Q0 and output signal Q1. Since the first-stage demultiplexing structure has a high rate, due to the limitations of the True Single Phase Clock (TSPC) data flip-flop, replacing the D flip-flop in the first stage of the first-stage demultiplexing structure with a comparator can increase the rate and meet the margin of 40 Gb / s.

[0048] In some embodiments, the second and third stage demultiplexing structures of the 1:8 demultiplexer may both be composed of multiple True Single Phase Clock data flip-flops (i.e., TSPC-D flip-flops), and the TSPC-D flip-flop samples the input data at the rising edge and falling edge of the single-ended clock respectively. Figure 5 Schematically shows a circuit block diagram of the second and third stage demultiplexing structures of a 1:8 demultiplexer according to an embodiment of the present invention.

[0049] As Figure 3 and Figure 5As shown, the DEMUX 1:2 of the second and third stage demultiplexing structures can be composed of flip-flops 4 to 8. Flip-flop 4 is triggered on the rising edge, flip-flop 5 is triggered on the falling edge, flip-flop 6 is triggered on the rising edge, flip-flop 7 is triggered on the falling edge, and flip-flop 8 is triggered on the rising edge. By using a single-ended clock and sampling the data on both the rising and falling edges of the clock, the requirement for the clock rate can be reduced.

[0050] In summary, the present invention provides an AC-coupled, compact single-ended data receiver with a single-channel rate of up to 32 Gb / s. The data receiver can be composed of a receiver driver, a demultiplexer, an output buffer, an XOR-based phase detector, a loop filter, a voltage-current converter, and a current-controlled oscillator, etc. The present invention can deserialze 1-channel serial data sent from a transmitter and recover it into 8-channel parallel data, and adopts the forward clock technology, without the need for an additional clock data recovery circuit, having the advantages of a compact architecture, small area, and low power consumption, and has broad application prospects in fields such as large-scale data centers, intelligent driving, and the Internet of Things.

[0051] The above specific implementation manners further elaborate on the purpose, technical solutions, and beneficial effects of the present invention. It should be understood that the above are only specific implementation examples of the present invention and are not used to limit the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present invention shall be included within the protection scope of the present invention.

Claims

1. A compact single - ended data receiver based on AC coupling, characterized in that, The receiver includes at least one data receiving channel, and each of the data receiving channels includes: A front-end driver, including an AC coupling architecture, which is used to block the DC component in the single-channel data during the process of driving the single-channel data sent by the transmitter to the demultiplexer, and to match the power supply voltages between the receiver and the transmitter using the AC coupling architecture; A clock generator, which is used to generate a clock signal according to the reference clock corresponding to each data receiving channel, and to transmit the clock signal to the demultiplexer; The demultiplexer, which is used to deserialize the single-channel data transmitted by the front-end driver into multi-channel parallel data according to the clock signal transmitted by the clock generator.

2. The compact single-ended data receiver according to claim 1, wherein The front-end driver includes: A capacitor, the first end of which is connected to the input end of the front-end driver; A third resistor, the two ends of which are respectively connected to the first end of the capacitor and the ground terminal, and the third resistor and the capacitor form the AC coupling architecture; A first inverter, the input end of which is connected to the second end of the capacitor; A second inverter, the input end of which is connected to the output end of the first inverter, and the output end of which is connected to the output end of the front-end driver; A first resistor, the two ends of which are respectively connected to the input end of the first inverter and the input end of the second inverter; A second resistor, the two ends of which are respectively connected to the input end of the first inverter and the output end of the second inverter.

3. The compact single-ended data receiver according to claim 2, wherein The front-end driver further includes: A continuous-time linear equalizer, the output end of which is connected to the input end of the second inverter, and the continuous-time linear equalizer is used to compensate for the attenuation of the high-frequency components in the single-channel data.

4. The compact single-ended data receiver according to claim 3, wherein, The continuous-time linear equalizer includes: A fourth resistor and a fifth resistor, the first ends of which are both connected to the input end of the second inverter; A first transistor to a fourth transistor, the source of the first transistor is connected to the power supply, the drain of the first transistor is connected to the drain of the second transistor, the source of the second transistor is connected to the drain of the third transistor, the source of the third transistor is connected to the drain of the fourth transistor, the source of the fourth transistor is grounded, and the first ends of the fourth resistor and the fifth resistor are also both connected to the source of the second transistor, the second end of the fourth resistor is connected to the gate of the second transistor, and the second end of the fifth resistor is connected to the gate of the third transistor.

5. The compact single-ended data receiver according to claim 1, characterized in that, The clock signal includes a differential clock, a first single-ended clock, and a second single-ended clock. The frequency of the first single-ended clock is half of the frequency of the differential clock, and the frequency of the second single-ended clock is half of the frequency of the first single-ended clock; The demultiplexer includes: A first-stage demultiplexing structure, which is used to deserialize the single-channel data into two-channel parallel data according to the differential clock; A second-stage demultiplexing structure, which is used to deserialize the two-channel parallel data into four-channel parallel data according to the first single-ended clock. The third-level demultiplexing structure is used to deserialize the four-way parallel data into eight-way parallel data according to the second single-ended clock.

6. The compact single-ended data receiver according to claim 5, wherein The first-level demultiplexing structure includes: A first comparator, including a first non-inverting input terminal, a first inverting input terminal, and a first clock control terminal. The first non-inverting input terminal is used to receive the single-channel data, the first inverting input terminal is used to receive a reference signal, and the first clock control terminal is used to receive the differential clock; A second comparator, including a second non-inverting input terminal, a second inverting input terminal, and a second clock control terminal. The second non-inverting input terminal is used to receive the single-channel data, the second inverting input terminal is used to receive the reference signal, and the second clock control terminal is used to receive the differential clock; A first flip-flop, including a first data input terminal, a first clock input terminal, and a first output terminal. The first data input terminal is connected to the output terminal of the first comparator, and the first clock input terminal inputs the first path of the differential clock; A second flip-flop, including a second data input terminal, a second clock input terminal, and a second output terminal. The second data input terminal is connected to the first output terminal, the second clock input terminal inputs the second path of the differential clock, the first path of the clock and the second path of the clock are differential, and the second output terminal is connected to the second-level demultiplexing structure; A third flip-flop, including a third data input terminal, a third clock input terminal, and a third output terminal. The third data input terminal is connected to the output terminal of the second comparator, the third clock input terminal inputs the second path of the clock, and the third output terminal is connected to the second-level demultiplexing structure.

7. The compact single-ended data receiver according to claim 5 or 6, characterized in that, Both the second-level demultiplexing structure and the third-level demultiplexing structure are composed of multiple true single-phase clock data flip-flops, and the true single-phase clock data flip-flop samples the input data at the rising edge and the falling edge of the single-ended clock respectively.

8. The compact single-ended data receiver according to claim 1, wherein, The clock generator includes: A phase detector, used to compare the phase of the externally input reference clock with the frequency-divided clock signal and output a voltage signal; A filter, used to suppress the high-frequency components of the voltage signal to obtain a filtered signal; A converter, used to convert the filtered signal and the externally input control voltage into a control current; An oscillator, used to generate the clock signal and tune the frequency and phase of the clock signal output according to the control current.

9. The compact single-ended data receiver according to claim 8, characterized in that, The control voltage is also used to adjust the oscillator to the target operating range; The phase detector is implemented based on an exclusive-OR gate architecture, and the gain of the phase detector is 2Icp / π, where Icp represents the charge pump current.

10. The compact single-ended data receiver according to claim 1, wherein Each of the data receiving channels further includes: A buffer, used to buffer the multi-way parallel data and then output it.

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