Methods, apparatus, and articles of manufacture for managing termination impedance in redrive

Abstract

The invention relates to a method, an apparatus, and an article of manufacture for managing termination impedance in a redrive. An example apparatus includes a termination network (210A) having a first input terminal coupled to a first input / output terminal (202) and a second input terminal coupled to a second input / output terminal (204). The apparatus includes transmitter circuitry (212A) having a first output terminal coupled to the first input / output terminal (202) and a second output terminal coupled to the second input / output terminal (204). The apparatus includes receiver circuitry (214A) having a first input terminal coupled to a first output terminal of the termination network (210A) and a second input terminal coupled to a second output terminal of the termination network (210A).

Description

[0001] Cross - Reference to Related Applications

[0002] This application claims the benefit and priority of U.S. Provisional Patent Application Serial No. 63 / 626,167, filed on January 29, 2024, the entire disclosure of which is hereby incorporated herein by reference. Technical Field

[0003] This specification generally relates to circuits, and more particularly, to methods, apparatuses, and articles for managing termination impedance in a re-driver. Background Art

[0004] Communication systems experience signal loss caused by one or more transmission paths (e.g., traces, cables, connectors, etc.) of the communication system. Communication systems include retimers and re-drivers to counteract signal loss. For example, a retimer recovers data transmitted in a communication system, extracts an embedded clock signal from the data transmitted in the communication system, and retransmits a copy of the data (e.g., a copy of the retimed data) using the recovered clock signal. A re-driver amplifies the high-frequency portion of a signal in a communication system to counteract frequency-dependent attenuation caused by one or more transmission paths of the communication system. Summary of the Invention

[0005] For a method, apparatus, and article of manufacture for managing termination impedance in a re-driver, an example apparatus includes a first input / output (I / O) terminal and a second I / O terminal. The apparatus includes a first resistor having a first terminal and a second terminal, the first terminal coupled to the first input / output (I / O) terminal and the second terminal coupled to at least one of a power voltage terminal or a ground terminal. The apparatus includes a second resistor having a first terminal coupled to the second terminal of the first resistor and a second terminal coupled to the second I / O terminal. The apparatus includes a third resistor having a first terminal and a second terminal, the first terminal of the third resistor coupled to the first I / O terminal. The apparatus includes a first switch having a control terminal, a first terminal, and a second terminal, the first terminal of the first switch coupled to the second terminal of the first resistor, and the second terminal of the first switch coupled to the second terminal of the third resistor. The apparatus includes a second switch having a control terminal, a first terminal, and a second terminal, the first terminal of the second switch coupled to the first terminal of the first switch and the second terminal of the first resistor. The apparatus includes a fourth resistor having a first terminal coupled to the second terminal of the second switch and a second terminal coupled to the second I / O terminal. The apparatus includes control circuitry having an output terminal coupled to the control terminal of the first switch and the control terminal of the second switch. The apparatus includes transmitter circuitry having a first output terminal coupled to the first I / O terminal and a second output terminal coupled to the second I / O terminal. The apparatus includes receiver circuitry having a first input terminal coupled to the first I / O terminal and a second input terminal coupled to the second I / O terminal. Describe other examples.

[0006] For methods, apparatuses, and articles of manufacture for managing termination impedance in a re-driver, an example apparatus includes a first input / output (I / O) terminal and a second I / O terminal. The apparatus includes a termination network having a first input terminal, a second input terminal, a third input terminal, a first output terminal, and a second output terminal, where the first input terminal of the termination network is coupled to the first I / O terminal and the second input terminal of the termination network is coupled to the second I / O terminal. The apparatus includes a transmitter circuitry having a first output terminal coupled to the first I / O terminal and a second output terminal coupled to the second I / O terminal. The apparatus includes a receiver circuitry having a first input terminal coupled to the first output terminal of the termination network and a second input terminal coupled to the second output terminal of the termination network. The apparatus includes a control circuitry having an output terminal coupled to the third input terminal of the termination network, the control circuitry for: changing the impedance of the termination network to a first value to compensate for at least one transient in a common-mode voltage of the termination network; and based on the common-mode voltage reaching a steady-state value, changing the impedance of the termination network to a second value for steady-state operation. Describe other examples.

[0007] For methods, apparatuses, and articles of manufacture for managing termination impedance in a re-driver, an example includes changing, with a control circuitry, an impedance of a termination network of a re-driver to a first value to compensate for at least one transient in a common-mode voltage of the termination network. The method includes, based on the common-mode voltage reaching a steady-state value, changing, with the control circuitry, the impedance of the termination network to a second value for steady-state operation. Describe other examples. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 is a block diagram of an example communication system that includes one or more re-drivers.

[0009] Figure 2 is for implementing Figure 1 one or more of the re-drivers in a re-driver.

[0010] Figure 3A and 3B (collectively FIG. 3) are block diagrams of example implementations of a shared termination network, transmitter circuitry, and receiver circuitry of Figure 2 .

[0011] Figure 4 is a flow diagram representative of at least one example machine-readable instruction or at least one example operation that can perform at least one of the following: during enabling of Figure 2 the transmitter circuitry ofFigure 2 An example programmable circuit system implementation of a control circuit system executes, instantiates, or implements to control Figure 2 a shared terminal network.

[0012] Figure 5 is a flowchart representing at least one of example machine-readable instructions or example operations, the example operations being capable of performing at least one of the following: during enabling of Figure 2 a receiver circuit system of Figure 2 An example programmable circuit system implementation of a control circuit system executes, instantiates, or implements to control Figure 2 a shared terminal network.

[0013] Figure 6 is a flowchart representing a first example finite state machine, the first example finite state machine being capable of performing at least one of the following: during enabling of Figure 2 a transmitter circuit system of Figure 2 an example programmable circuit system implementation of a re-driver is executed, instantiated, or implemented.

[0014] Figure 7 is a flowchart representing a second example finite state machine, the second example finite state machine being capable of performing at least one of the following: during enabling of Figure 2 a transmitter circuit system of Figure 2 an example programmable circuit system implementation of a re-driver is executed, instantiated, or implemented.

[0015] Figure 8 is a flowchart representing a first example finite state machine, the first example finite state machine being capable of performing at least one of the following: during enabling of Figure 2 a receiver circuit system of Figure 2 an example programmable circuit system implementation of a re-driver is executed, instantiated, or implemented.

[0016] Figure 9 is a flowchart representing a second example finite state machine, the second example finite state machine being capable of performing at least one of the following: during enabling of Figure 2 a receiver circuit system of Figure 2 an example programmable circuit system implementation of a re-driver is executed, instantiated, or implemented.

[0017] Figure 10 illustrates Figure 2 the timing diagram of the example operation of a re-driver.

[0018] Figure 11 depicts when utilizing Figure 2The first graphical illustration of the change in the common-mode voltage at the proximal and distal ends of the transmission path when using the

[0019] Figure 12 is a depiction of when using the Figure 2 The second graphical illustration of the change in the common-mode voltage at the proximal and distal ends of the transmission path when using the

[0020] Figure 13 is a block diagram of an example programmable circuit system platform that includes a programmable circuit system configured to perform at least one of the following: execute, instantiate, or implement instance machine-readable instructions or perform Figure 4 , 5 , 6, 7, 8, and 9 example operations to implement the Figure 2 heavy driver.

[0021] In the drawings, the same reference numerals or other reference indicators are used to indicate features that are the same or similar (at least one of function or structure). Detailed Description

[0022] The drawings are not necessarily to scale. In general, the same reference numerals in the drawings and this specification refer to the same or similar parts. Although the drawings show regions with clear lines and boundaries, at least some of these lines or at least some of these boundaries may be idealized. In reality, at least one of the boundaries or lines may be at least one of the following: observable, blended, or irregular.

[0023] A communication system can be designed to conform to a communication protocol or communication standard. For example, the Universal Serial Bus (USB) standard defines specifications for data exchange and power delivery between electronic devices. The USB standard includes four generations of specifications: USB 1, USB 2, USB 3, and USB 4. The specifications of USB 3 and USB 4 (also referred to as USB 3 and USB 4) allow sharing of the terminals of a heavy driver between the transmitter and receiver of the heavy driver. The terminals or terminal network of a device is a network of electrical components that interfaces between the device and the transmission path. For example, the terminal network of a device interfaces with the transmission path to match the characteristic impedance of the transmission path and reduce signal reflections at the input / output (I / O) terminals of the device.

[0024] As permitted by USB 3 and USB 4, sharing a termination network between the transmitter and receiver of a re-driver reduces the parasitic impedance at the I / O terminals of the re-driver. Also, when the termination network is shared between the transmitter and receiver of the re-driver, the common-mode terminal between the I / O terminals of the re-driver is biased to a voltage. For example, in some protocol states in USB 3 and USB 4, the common-mode terminal between the I / O terminals of the re-driver is biased to 1.8 volts (V). USB 3 and USB 4 include limits on how much the voltage (e.g., common-mode voltage) to which the common-mode terminal between the I / O terminals of the re-driver is biased can change.

[0025] To remain compliant with USB 3 and USB 4, the common-mode voltage of the re-driver cannot vary outside the limits set by USB 3 and USB 4. For example, USB 3 and USB 4 specify that the common-mode voltage of the re-driver cannot be reduced by more than 300 millivolts (mV) (e.g., during transmitter enable) and cannot be increased by more than 1 V (e.g., during receiver enable). Also, to remain compliant with USB 3 and USB 4, the re-driver cannot cause the voltage of a device at the far end of the transmission path to vary outside the limits set by USB 3 and USB 4. In the examples described herein, the near end of the transmission path is a relative term referring to the end of the transmission path to which the first device (e.g., re-driver) is coupled, and the far end of the transmission path is a relative term referring to the end of the transmission path to which the second device is coupled. For example, the first end of the transmission path can be the near end of the transmission path relative to the first device and the far end of the transmission path relative to the second device.

[0026] Because the developer of the re-driver may not know the impedance of the termination network of the device at the far end of the transmission path, biasing the common-mode voltage of the re-driver to a voltage can cause the voltage of the device at the far end of the transmission path to vary outside the limits set by USB 3 and USB 4. For example, USB 3 and USB 4 specify the impedance of the termination network of a compliant device as 42.5 ohms (Ω). However, biasing the common-mode voltage of the re-driver to 1.8 V with a termination network having an impedance of 42.5 Ω can cause the common-mode voltage of the device at the far end of the transmission path to vary outside the limits specified by USB 3 and USB 4.

[0027] For example, biasing the common-mode voltage of a heavy driver to 1.89V (e.g., 1.8V with a 5% variation) using a termination network with an impedance of 42.5Ω can trigger the common-mode voltage of the device at the far end of the transmission path to vary by 25mV outside the limits specified by USB 3 and USB 4 (e.g., the common-mode voltage of the device at the far end of the transmission path can increase by 1.025V or decrease by 325mV). With process, voltage, and temperature (PVT) variations, biasing the common-mode voltage of a heavy driver to 1.89V using a termination network with an impedance of 42.5Ω can trigger the common-mode voltage of the device at the far end of the transmission path to vary by up to 200mV outside the limits specified by USB 3 and USB 4. Due to these complexities, heavy drivers with separate termination networks have been designed for transmitters and receivers.

[0028] The examples described herein include a termination network with a variable impedance shared between the transmitter and receiver of a heavy driver. Moreover, the examples described herein include control circuitry for controlling the impedance of the shared termination network during operation of the heavy driver. In some examples, the described control circuitry biases the driver of the transmitter of the heavy driver with a reduced current to reduce (e.g., minimize) transients in the common-mode voltage of the heavy driver and increases the bias current of the driver to a steady-state value for nominal operation of the heavy driver (e.g., high-speed operation, between 500 megabits per second (MB) (MB / s) and 40 gigabits per second (Gbits) (Gbit / s), up to 4.8 gigabytes per second (GB) (GB / s), between 20 Gbits / s and 120 Gbits / s, up to 14.4 GB / s, etc.). In the examples described herein, the example control circuitry controls the impedance of the shared termination network to prevent (1) the common-mode voltage of the heavy driver and (2) the voltage of the device at the far end of the transmission path from varying outside the limits set by USB 3 and USB 4.

[0029] For example, the described control circuit system performs at least one of the following: reducing the impedance of a shared termination network during operation of a transmitter circuit system of a re-driver, or increasing the impedance of the shared termination network during operation of a receiver circuit system of the re-driver. Moreover, an example control circuit system adjusts the impedance of the shared termination network of the re-driver to reduce (e.g., minimize) an initial transient in the common-mode voltage of the re-driver and returns the impedance of the shared termination network to a steady-state value (e.g., 42.5 Ω) for nominal operation (e.g., high-speed operation, between 500 MB / s and 40 Gbits / s, up to 4.8 GB / s, between 20 Gbits / s and 120 Gbits / s, up to 14.4 GB / s, etc.) of the re-driver. Accordingly, the described examples reduce (e.g., minimize) variations in the common-mode voltage to maintain compliance with the limits specified by USB 3 and USB 4.

[0030] For example, when enabling the receiver circuit system of the re-driver, the example control circuit system increases the impedance of the shared termination network by 20%. By doing so, the example control circuit system reduces the offset of the common-mode voltage of a device at the far end of a transmission path that includes the re-driver to 0.85 V, which is within the variance (e.g., 1 V) allowed by USB 3 and USB 4. After a transient in the common-mode voltage, the example control circuit system returns the impedance of the shared termination network to the value specified by USB 3 and USB 4 (e.g., 42.5 Ω). Moreover, for example, when enabling the transmitter circuit system of the re-driver, the example control circuit system reduces the impedance of the shared termination network by 20%. By doing so, the example control circuit system reduces (e.g., minimizes) the offset of the common-mode voltage of a device at the far end of a transmission path that includes the re-driver to a value within the variance allowed by USB 3 and USB 4. After a transient in the common-mode voltage, the example control circuit system returns the impedance of the shared termination network to the value specified by USB 3 and USB 4 (e.g., 42.5 Ω). Accordingly, the examples described herein maintain compliance with USB 3 and USB 4.

[0031] Figure 1 is a block diagram of an example communication system 100 that includes one or more re-drivers. In Figure 1 this example, communication system 100 includes a first example device 102 A , a second example device 102 B and an example cable 104. The example device 102 A includes a first example processor 106 A , a first example re-driver 108 A , a first example re-timer 110 A and a first example connector 112 AMoreover, the example device 102 B includes a second example processor 106 B , a second example re-driver 108 B , a second example re-timer 110 B and a second example connector 112 B . In Figure 1 the example, the cable 104 includes a third example re-driver 108 C and a fourth example re-driver 108 D .

[0032] In Figure 1 the illustrated example, the processor 106 A includes a first output terminal, a second output terminal and an input terminal. In Figure 1 the example, the re-driver 108 A includes a first input terminal, a second input terminal, a third input terminal, a first output terminal and a second output terminal. Moreover, the re-timer 110 A includes a first input terminal, a second input terminal, a first output terminal, a second output terminal, a third output terminal and a fourth output terminal. In Figure 1 the example, the connector 112 A (e.g., a USB port) includes a first input terminal, a second input terminal, a third input terminal, a first output terminal, a second output terminal and a third output terminal. Moreover, the re-driver 108 C includes a first input terminal, a second input terminal, a third input terminal, a first output terminal and a second output terminal.

[0033] In Figure 1 the illustrated example, the re-driver 108 D includes a first input terminal, a second input terminal, a third input terminal, a first output terminal and a second output terminal. In Figure 1 the example, the connector 112 B (e.g., a USB port) includes a first input terminal, a second input terminal, a third input terminal, a first output terminal, a second output terminal and a third output terminal. Moreover, the re-timer 110 B includes a first input terminal, a second input terminal, a first output terminal, a second output terminal, a third output terminal and a fourth output terminal. In Figure 1 the example, the re-driver 108 B includes a first input terminal, a second input terminal, a third input terminal, a first output terminal and a second output terminal. Moreover, the processor 106 B includes a first output terminal, a second output terminal and an input terminal.

[0034] InFigure 1 In the illustrated example, the processor 106 A has its input terminal coupled to the first output terminal of the re-driver 108 A (e.g., via a printed circuit board (PCB) trace). Also, the first output terminal of the processor 106 A is coupled to the first input terminal of the re-driver 108 A . In Figure 1 the example, the second output terminal of the processor 106 A is coupled to the second input terminal of the re-driver 108 A (e.g., via a PCB trace).

[0035] In Figure 1 the illustrated example, the first input terminal of the re-driver 108 A is coupled to the first output terminal of the processor 106 A and the first output terminal of the re-timer 110 A . Also, the second input terminal of the re-driver 108 A is coupled to the second output terminal of the processor 106 A (e.g., via a PCB trace). In Figure 1 the example, the third input terminal of the re-driver 108 A is coupled to the second output terminal of the re-timer 110 A (e.g., via a PCB trace). Also, the first output terminal of the re-driver 108 A is coupled to the input terminal of the processor 106 A (e.g., via a PCB trace). In Figure 1 the example, the second output terminal of the re-driver 108 A is coupled to the first input terminal of the re-timer 110 A (e.g., via a PCB trace).

[0036] In Figure 1 the illustrated example, the first input terminal of the re-timer 110 A is coupled to the second output terminal of the re-driver 108 A (e.g., via a PCB trace). Also, the second input terminal of the re-timer 110 A is coupled to the first output terminal of the connector 112 A . In Figure 1 the example, the first output terminal of the re-timer 110 A is coupled to the first input terminal of the re-driver 108 A . Also, the second output terminal of the re-timer 110 A is coupled to the second input terminal of the re-driver 108 AThe third input terminal (e.g., via a PCB trace). In Figure 1 In the example of A the third output terminal of A is coupled to the first input terminal of the connector 112 A Moreover, the fourth output terminal of the retimer 110 A is coupled to the second input terminal of the connector 112

[0037] In Figure 1 In the illustrated example of A the first input terminal of the connector 112 A is coupled to the third output terminal of the retimer 110 A Moreover, the second input terminal of the connector 112 A is coupled to the fourth output terminal of the retimer 110 Figure 1 In the example of A the third input terminal of the connector 112 C is coupled to the first output terminal of the heavy driver 108 A Moreover, the first output terminal of the connector 112 A is coupled to the second input terminal of the retimer 110 Figure 1 In the example of A the second output terminal of the connector 112 C is coupled to the second input terminal of the heavy driver 108 A Moreover, the third output terminal of the connector 112 C is coupled to the first input terminal of the heavy driver 108

[0038] In Figure 1 In the illustrated example of C the first input terminal of the heavy driver 108 A is coupled to the third output terminal of the connector 112 C Moreover, the second input terminal of the heavy driver 108 A is coupled to the second output terminal of the connector 112 <oo Figure 1 In the example of C and the heavy driver 108 D are coupled via the example cable transmission path 114. For example, the third input terminal of the heavy driver 108 C is coupled to the first output terminal of the heavy driver 108 D (e.g., via at least one of the cable transmission paths 114). Moreover, the first output terminal of the heavy driver 108 C is coupled to the third input terminal of the connector 112 A In Figure 1In the example of, the heavy driver 108 C The second output terminal of is coupled to the heavy driver 108 D The second input terminal of (e.g., via at least one of the cable transmission paths 114).

[0039] In Figure 1 In the illustrated example of, the heavy driver 108 D The first input terminal of is coupled to the second output terminal of the connector 112 B Moreover, the second input terminal of the heavy driver 108 D is coupled to the second output terminal of the heavy driver 108 C (e.g., via at least one of the cable transmission paths 114). In Figure 1 In the example of, the heavy driver 108 D The third input terminal of is coupled to the third output terminal of the connector 112 B Moreover, the first output terminal of the heavy driver 108 D is coupled to the third input terminal of the heavy driver 108 C (e.g., via at least one of the cable transmission paths 114). In Figure 1 In the example of, the heavy driver 108 D The second output terminal of is coupled to the third input terminal of the connector 112 B

[0040] In Figure 1 In the illustrated example of, the connector 112 B The first input terminal of is coupled to the third output terminal of the heavy timer 110 B Moreover, the second input terminal of the connector 112 B is coupled to the fourth output terminal of the heavy timer 110 B In Figure 1 In the example of, the connector 112 B The third input terminal of is coupled to the second output terminal of the heavy driver 108 D Moreover, the first output terminal of the connector 112 B is coupled to the second input terminal of the heavy timer 110 B In Figure 1 In the example of, the connector 112 B The second output terminal of is coupled to the first input terminal of the heavy driver 108 D Moreover, the third output terminal of the connector 112 B is coupled to the third input terminal of the heavy driver 108 D

[0041] In Figure 1 In the illustrated example of, the heavy timer 110​​B The first input terminal of B is coupled to the re-driver 108 B through the second output terminal (e.g., via a PCB trace). Moreover, the re-timer 110 B has its second input terminal coupled to the first output terminal of the connector 112 Figure 1 In the example of B the re-timer 110, B its first output terminal is coupled to the first input terminal of the re-driver 108 B Moreover, the re-timer 110 B has its second output terminal coupled to the third input terminal of the re-driver 108 (e.g., via a PCB trace). In Figure 1 the example of B the re-timer 110, B its third output terminal is coupled to the first input terminal of the connector 112 B Moreover, the re-timer 110 B has its fourth output terminal coupled to the second input terminal of the connector 112.

[0042] In Figure 1 the illustrated example, B the first input terminal of the re-driver 108 B is coupled to the first output terminal of the processor 106 B and the first output terminal of the re-timer 110. Moreover, the re-driver 108 B has its second input terminal coupled to the second output terminal of the processor 106 (e.g., via a PCB trace). In B the example of Figure 1 the re-driver 108 B has its third input terminal coupled to the second output terminal of the re-timer 110 (e.g., via a PCB trace). Moreover, the re-driver 108 B has its first output terminal coupled to the input terminal of the processor 106 B (e.g., via a PCB trace). In B the example of Figure 1 the re-driver 108 B has its second output terminal coupled to the first input terminal of the re-timer 110 (e.g., via a PCB trace). B

[0043] In Figure 1 the illustrated example, B the input terminal of the processor 106 B is coupled to the first output terminal of the re-driver 108 (e.g., via a PCB trace). Moreover, the processor 106 BThe first output terminal of is coupled to the re-driver 108 B The first input terminal of. In Figure 1 In an example, the processor 106 B The second output terminal of is coupled to the re-driver 108 B The second input terminal of (e.g., via a PCB trace).

[0044] In Figure 1 In the illustrated example, the processor 106 A And the processor 106 B Each of is implemented by an integrated circuit. In Figure 1 In an example, the processor 106 A And the processor 106 B Communicate through the transmission paths of the communication system 100. In Figure 1 In an example, some of the transmission paths of the communication system 100 are lossy. For example, the PCB traces and cable transmission paths 114 of the communication system 100 are lossy.

[0045] In Figure 1 In the illustrated example, the cable 104 includes the re-driver 108 C The re-driver 108 D And the cable transmission path 114. In Figure 1 In an example, the cable transmission path 114 couples the re-driver 108 C To the re-driver 108 D . For example, the cable transmission path 114 has a length between two meters and three meters. Also, for example, under American Wire Gauge (AWG), the cable transmission path 114 has a gauge between 26 and 34. And / or alternatively, the cable transmission path 114 can be of any length or gauge.

[0046] In Figure 1 In the illustrated example, the re-driver 108 A The re-driver 108 B The re-driver 108 C And the re-driver 108 D Each of is implemented by an integrated circuit. In Figure 1 In an example, the re-driver 108 A And the re-driver 108 B Amplify the high-frequency portion of the signals in the communication system 100 to equalize the signal loss caused by the PCB traces of the communication system 100. Also, the re-driver 108 C And the re-driver 108 D Amplify the high-frequency portion of the signals in the communication system 100 to equalize the signal loss caused by the cable transmission path 114 of the communication system 100.

[0047] In Figure 1 the illustrated example, each of retimers 110 A and retimers 110 B is implemented by an integrated circuit. In Figure 1 the example, retimers 110 A and retimers 110 B recover data transmitted in communication system 100. Moreover, retimers 110 A and retimers 110 B extract an embedded clock signal from the data transmitted in communication system 100 and retransmit a copy of the data using the recovered clock signal.

[0048] Figure 2 is a block diagram of example redriver 200 for implementing Figure 1 redrivers 108 A 、108 B 、108 C 、108 D 、one or more of. In Figure 2 the example, redriver 200 includes first example input / output (I / O) terminals 202, second example input / output (I / O) terminals 204, third example input / output (I / O) terminals 206, and fourth example input / output (I / O) terminals 208. Moreover, redriver 200 includes first example shared terminal network 210 A 、first example transmitter circuitry 212 A 、first example receiver circuitry 214 A 、second example shared terminal network 210 B 、second example transmitter circuitry 212 B 、second example receiver circuitry 214 B and control circuitry 216.

[0049] In Figure 2 the illustrated example, shared terminal network 210 A includes a first input terminal, a second input terminal, a third input terminal, a first output terminal, and a second output terminal. Moreover, transmitter circuitry 212 A includes a first input terminal, a second input terminal, a third input terminal, a first output terminal, and a second output terminal. In Figure 2 the example, receiver circuitry 214 A includes a first input terminal, a second input terminal, a first output terminal, and a second output terminal.

[0050] In Figure 2In the illustrated example, the shared terminal network 210 B includes a first input terminal, a second input terminal, a third input terminal, a first output terminal, and a second output terminal. Moreover, the transmitter circuitry 212 B includes a first input terminal, a second input terminal, a third input terminal, a first output terminal, and a second output terminal. In Figure 2 the example, the receiver circuitry 214 B includes a first input terminal, a second input terminal, a third input terminal, a first output terminal, and a second output terminal. Moreover, the control circuitry 216 includes an input terminal, a first output terminal, a second output terminal, a third output terminal, and a fourth output terminal.

[0051] In Figure 2 the illustrated example, the first input terminal of the shared terminal network 210 A is coupled to the first I / O terminal 202. Moreover, the second input terminal of the shared terminal network 210 A is coupled to the second I / O terminal 204. In Figure 2 the example, the third input terminal of the shared terminal network 210 A is coupled to the first output terminal of the control circuitry 216. Moreover, the first output terminal of the shared terminal network 210 A is coupled to the first input terminal of the receiver circuitry 214 A In Figure 2 the example, the second output terminal of the shared terminal network 210 A is coupled to the second input terminal of the receiver circuitry 214 A

[0052] In Figure 2 the illustrated example, the first input terminal of the transmitter circuitry 212 A is coupled to the first output terminal of the receiver circuitry 214 B Moreover, the second input terminal of the transmitter circuitry 212 A is coupled to the second output terminal of the receiver circuitry 214 B In Figure 2 the example, the third input terminal of the transmitter circuitry 212 A is coupled to the second output terminal of the control circuitry 216. Moreover, the first output terminal of the transmitter circuitry 212 A is coupled to the first I / O terminal 202. In Figure 2 the example, the second output terminal of the transmitter circuitry 212 A is coupled to the second I / O terminal 204.

[0053] In​Figure 2 In the illustrated example, the receiver circuit system 214 A has its first input terminal coupled to the first output terminal of the shared terminal network 210 A . Also, the receiver circuit system 214 A has its second input terminal coupled to the second output terminal of the shared terminal network 210 A . In Figure 2 the example, the receiver circuit system 214 A has its first output terminal coupled to the second input terminal of the transmitter circuit system 212 B . Also, the receiver circuit system 214 A has its second output terminal coupled to the first input terminal of the transmitter circuit system 212 B .

[0054] In Figure 2 the illustrated example, the shared terminal network 210 B has its first input terminal coupled to the third I / O terminal 206. Also, the shared terminal network 210 B has its second input terminal coupled to the fourth I / O terminal 208. In Figure 2 the example, the shared terminal network 210 B has its third input terminal coupled to the third output terminal of the control circuit system 216. Also, the shared terminal network 210 B has its first output terminal coupled to the first input terminal of the receiver circuit system 214 B . In Figure 2 the example, the shared terminal network 210 B has its second output terminal coupled to the second input terminal of the receiver circuit system 214 B .

[0055] In Figure 2 the illustrated example, the transmitter circuit system 212 B has its first input terminal coupled to the second output terminal of the receiver circuit system 214 A . Also, the transmitter circuit system 212 B has its second input terminal coupled to the first output terminal of the receiver circuit system 214 A . In Figure 2 the example, the transmitter circuit system 212 B has its third input terminal coupled to the fourth output terminal of the control circuit system 216. Also, the transmitter circuit system 212 B has its first output terminal coupled to the third I / O terminal 206. In Figure 2 the example, the transmitter circuit system 212 BThe second output terminal of is coupled to the fourth I / O terminal 208.

[0056] In Figure 2 the illustrated example of , the first input terminal of the receiver circuit system 214 B is coupled to the first output terminal of the shared terminal network 210 B Moreover, the second input terminal of the receiver circuit system 214 B is coupled to the second output terminal of the shared terminal network 210 B In Figure 2 the illustrated example of , the first output terminal of the receiver circuit system 214 B is coupled to the first input terminal of the transmitter circuit system 212 A Moreover, the second output terminal of the receiver circuit system 214 B is coupled to the second input terminal of the transmitter circuit system 212 A

[0057] In Figure 2 the illustrated example of , the input terminal of the control circuit system 216 is coupled to at least one of a processor (e.g., processor 106 A 、106 B ), a retimer (e.g., retimer 110 A 、110 B ), or a connector (e.g., connector 112 A 、112 B ). Moreover, the first output terminal of the control circuit system 216 is coupled to the third input terminal of the shared terminal network 210 A In Figure 2 the example of , the second output terminal of the control circuit system 216 is coupled to the third input terminal of the transmitter circuit system 212 A Moreover, the third output terminal of the control circuit system 216 is coupled to the third input terminal of the shared terminal network 210 B In Figure 2 the example of , the fourth output terminal of the control circuit system 216 is coupled to the third input terminal of the transmitter circuit system 212 B

[0058] In Figure 2 the illustrated example of , the shared terminal network 210 A is implemented by at least one of one or more switches and passive electrical components or active electrical components. In Figure 2 the example of , the shared terminal network 210 A is referred to as shared because the shared terminal network 210 A serves as the transmitter circuit system 212 Aand the receiver circuitry 214 A for terminal network operation. For example, the shared terminal network 210 A interfaces with the transmission paths at the first I / O terminal 202 and the second I / O terminal 204 to match the characteristic impedance of the transmission paths. By matching the characteristic impedance of the transmission paths, the shared terminal network 210 A reduces reflections of signals transmitted by the transmitter circuitry 212 A at the first I / O terminal 202 and the second I / O terminal 204 or transmitted to the receiver circuitry 214 A .

[0059] In Figure 2 the illustrated example, the transmitter circuitry 212 A is implemented by at least one of one or more switches and passive electrical components or active electrical components. An example transmitter circuitry 212 A equalizes signals received from the receiver circuitry 214 B and retransmits the signals at the first I / O terminal 202 and the second I / O terminal 204. In Figure 2 the example, the receiver circuitry 214 A is implemented by at least one of one or more switches and passive electrical components or active electrical components. An example receiver circuitry 214 A equalizes signals received at the first I / O terminal 202 and the second I / O terminal 204, and transmits the signals to the transmitter circuitry 212 B .

[0060] In Figure 2 the illustrated example, the shared terminal network 210 B is implemented by at least one of one or more switches and passive electrical components or active electrical components. In Figure 2 the example, the shared terminal network 210 B is referred to as shared because the shared terminal network 210 B operates as the terminal network for both the transmitter circuitry 212 B and the receiver circuitry 214 B . For example, the shared terminal network 210 B interfaces with the transmission paths at the third I / O terminal 206 and the fourth I / O terminal 208 to match the characteristic impedance of the transmission paths. By matching the characteristic impedance of the transmission paths, the shared terminal network 210 B reduces reflections of signals transmitted by the transmitter circuitry 212 B at the third I / O terminal 206 and the fourth I / O terminal 208 or transmitted to the receiver circuitry 214 B .

[0061] In Figure 2 the illustrated example, the transmitter circuit system 212 B is implemented by at least one of one or more switches and passive electrical components or active electrical components. The example transmitter circuit system 212 B equalizes the signals received from the receiver circuit system 214 A and retransmits the signals at the third I / O terminal 206 and the fourth I / O terminal 208. In Figure 2 the example, the receiver circuit system 214 B is implemented by at least one of one or more switches and passive electrical components or active electrical components. The example receiver circuit system 214 B equalizes the signals received at the third I / O terminal 206 and the fourth I / O terminal 208, and transmits the signals to the transmitter circuit system 212 A .

[0062] In Figure 2 the illustrated example, the control circuit system 216 is implemented by at least one of a combinational logic circuit system or a sequential logic circuit system. The example control circuit system 216 controls the operation of the re-driver 200. In Figure 2 the example, in response to a re-driver enable signal received at the input terminal of the control circuit system 216, the control circuit system 216 converts the re-driver 200 from a sleep operation mode to an active operation mode. For example, when the re-driver 200 receives a re-driver enable signal and a signal to be transmitted by the re-driver 200, the control circuit system 216 enables the transmitter circuit system 212 A or one of the transmitter circuit systems 212 B and the receiver circuit system 214 A or the corresponding one of the receiver circuit systems 214 B .

[0063] In Figure 2 the illustrated example, when the re-driver 200 receives a re-driver enable signal and a signal at the first I / O terminal 202 and the second I / O terminal 204, the control circuit system 216 enables the receiver circuit system 214 A and the transmitter circuit system 212 B . Moreover, when the re-driver 200 receives a re-driver enable signal and a signal at the third I / O terminal 206 and the fourth I / O terminal 208, the control circuit system 216 enables the receiver circuit system 214 B and the transmitter circuit system 212 A . As described above, the control circuit system 216 enables the transmitter circuit system 212 A, the transmitter circuitry 212 B , the receiver circuitry 214 A or the receiver circuitry 214 B during at least one of which the shared termination network 210 A or the shared termination network 210 B has its impedance adjusted.

[0064] For example, during the enabling of the receiver circuitry 214 A and the transmitter circuitry 212 B the control circuitry 216 increases the impedance of the shared termination network 210 A and decreases the impedance of the shared termination network 210 B . Also, during the enabling of the receiver circuitry 214 B and the transmitter circuitry 212 A the control circuitry 216 increases the impedance of the shared termination network 210 B and decreases the impedance of the shared termination network 210 A . Also, after enabling at least one of the transmitter circuitry 212 A or the receiver circuitry 214 A the control circuitry 216 returns the impedance of the shared termination network 210 A to the steady state value (e.g., 42.5 Ω) for the nominal operation of the re - driver 200 (e.g., high - speed operation, up to 4.8 GB / s during 500 MB / s and 40 Gbits / s, up to 14.4 GB / s between 20 Gbits / s and 120 Gbits / s, etc.). After enabling at least one of the transmitter circuitry 212 B or the receiver circuitry 214 B the control circuitry 216 also returns the impedance of the shared termination network 210 B to the steady state value (e.g., 42.5 Ω) for the nominal operation of the re - driver 200 (e.g., high - speed operation, up to 4.8 GB / s during 500 MB / s and 40 Gbits / s, up to 14.4 GB / s between 20 Gbits / s and 120 Gbits / s, etc.). Thus, the control circuitry 216 reduces the change in the common - mode voltage of at least one of the shared termination network 210 A or the shared termination network 210 B to maintain compliance with the limits specified by USB 3 and USB 4.

[0065] Figure 3 is Figure 2 of the shared termination network 210 A , the transmitter circuitry 212 Aand receiver circuitry 214 A is a block diagram of an example implementation. In the example of FIG. 3, the shared terminal network 210 A includes a first example resistor 302 A a second example resistor 302 B a third example resistor 302 C a fourth example resistor 302 D a fifth example resistor 302 E a sixth example resistor 302 F a seventh example resistor 302 G an eighth example resistor 302 H and a ninth example resistor 302 I . Further, the shared terminal network 210 A includes a first example switch 304 A a second example switch 304 B a third example switch 304 C a fourth example switch 304 D a fifth example switch 304 E a sixth example switch 304 F a seventh example switch 304 G an eighth example switch 304 H a ninth example switch 304 I a tenth example switch 304 J and an eleventh example switch 304 K .

[0066] In the illustrated example of FIG. 3, the shared terminal network 210 A includes an example exclusive - OR (XOR) gate 306, an example NAND gate 308, and an example NOT gate 310. In the example of FIG. 3, the shared terminal network 210 A also includes an example power - voltage terminal 312 and an example ground terminal 314. In the example of FIG. 3, the power - voltage terminal 312 is set to 1.8V (e.g., VCC). Further, the ground terminal 314 is set to 0V (e.g., VSS).

[0067] In the illustrated example of FIG. 3, the transmitter circuitry 212 A includes an example transmitter equalizer circuitry 316, a twelfth example switch 304 L and a first example current source 318 A . In some examples, the transmitter circuitry 212 A includes a thirteenth example switch 304 M and a second example current source 318 B . Further, the transmitter circuitry 212A includes a ground terminal 314. In the example of FIG. 3, the receiver circuitry 214 A includes an example receiver level shifter circuitry 320 and an example receiver equalizer circuitry 322.

[0068] In the illustrated example of FIG. 3, resistor 302 A 、resistor 302 B 、resistor 302 C 、resistor 302 D 、resistor 302 E 、resistor 302 F 、resistor 302 G 、resistor 302 H and resistor 302 I each includes a first terminal and a second terminal. Moreover, switch 304 A 、switch 304 B 、switch 304 C 、switch 304 D 、switch 304 E 、switch 304 F 、switch 304 G 、switch 304 H 、switch 304 I 、switch 304 J 、switch 304 K 、304 L and switch 304 M each includes a control terminal (e.g., a gate terminal), a first terminal (e.g., a source terminal), and a second terminal (e.g., a drain terminal). In the example of FIG. 3, each of XOR gate 306 and NAND gate 308 includes a first input terminal, a second input terminal, and an output terminal. Moreover, NOT gate 310 includes an input terminal and an output terminal.

[0069] In the example of FIG. 3, the transmitter equalizer circuitry 316 includes a first input terminal, a second input terminal, a first driver terminal, a first output terminal, and a second output terminal. In some examples, the transmitter equalizer circuitry 316 includes a second driver terminal. In the example of FIG. 3, current source 318 A and current source 318 B each includes a first terminal and a second terminal.

[0070] In the illustrated example of FIG. 3, the receiver level shifter circuit system 320 includes a first input terminal, a second input terminal, a first output terminal, and a second output terminal. In the example of FIG. 3, the receiver equalizer circuit system 322 includes a first input terminal, a second input terminal, a first output terminal, and a second output terminal. Moreover, the control circuit system 216 includes an input terminal, a first output terminal, a second output terminal, a third output terminal, a fourth output terminal, a fifth output terminal, and a sixth output terminal. In some examples, the control circuit system 216 includes a seventh output terminal.

[0071] In the illustrated example of FIG. 3, the resistor 302 A has a first terminal coupled to the first I / O terminal 202. Moreover, the resistor 302 A has a second terminal coupled to at least one of the power supply voltage terminal 312 or the ground terminal 314. In the example of FIG. 3, the resistor 302 A has a second terminal coupled to the ground terminal 314 via the switch 304 A or at least one of the resistor 302 I and the switch 304. D Moreover, the resistor 302 A has a second terminal coupled to the power supply voltage terminal 312 via the switch 304 B or at least one of the resistor 302 I and the switch 304. C For example, the second terminal of the resistor 302 A is coupled to the second terminal of the switch 304 A , the second terminal of the switch 304 B , and the second terminal of the resistor 302. I

[0072] In the illustrated example of FIG. 3, the first terminal of the resistor 302 B is coupled to the second terminal of the resistor 302 A . Moreover, the second terminal of the resistor 302 B is coupled to the second I / O terminal 204. In the example of FIG. 3, the control terminal of the switch 304 A is coupled to the second terminal of the switch 304 E , the first terminal of the switch 304 A is coupled to the ground terminal 314, and the second terminal of the switch 304 A is coupled to the second terminal of the resistor 302 A . Moreover, the control terminal of the switch 304 B is coupled to the output terminal of the NAND gate 308, the first terminal of the switch 304 B is coupled to the power supply voltage terminal 312, and the switch 304B The second terminal of A is coupled to the second terminal of resistor 302.

[0073] In the illustrated example of FIG. 3, the first terminal of resistor 302 I is coupled to the second terminal of switch 304 C and the second terminal of switch 304. D Moreover, the second terminal of resistor 302 I is coupled to the second terminal of resistor 302 A In the example of FIG. 3, the control terminal of switch 304 C is coupled to the output terminal of NOT gate 310, the first terminal of switch 304 C is coupled to power supply voltage terminal 312, and the second terminal of switch 304 C is coupled to the first terminal of resistor 302 I Moreover, the control terminal of switch 304 D is coupled to the output terminal of NOT gate 310, the first terminal of switch 304 D is coupled to ground terminal 314, and the second terminal of switch 304 D is coupled to the first terminal of resistor 302 I In the illustrated example of FIG. 3, the control terminal of switch 304

[0074] is coupled to the fourth output terminal of control circuitry 216, the first terminal of switch 304 E is coupled to the output terminal of XOR gate 306, and the second terminal of switch 304 E is coupled to the control terminal of switch 304 E In the example of FIG. 3, the first input terminal of XOR gate 306 is coupled to the fourth output terminal of control circuitry 216, and the second input terminal of XOR gate 306 is coupled to the fifth output terminal of control circuitry 216. Moreover, the output terminal of XOR gate 306 is coupled to the first terminal of switch 304 A In the illustrated example of FIG. 3, the first input terminal of NAND gate 308 is coupled to the fourth output terminal of control circuitry 216, and the second input terminal of NAND gate 308 is coupled to the fifth output terminal of control circuitry 216. Moreover, the output terminal of NAND gate 308 is coupled to the control terminal of switch 304 E In the example of FIG. 3, the input terminal of NOT gate 310 is coupled to the fourth output terminal of control circuitry 216, and the output terminal of NOT gate 310 is coupled to the control terminal of switch 304

[0075] and the control terminal of switch 304 B and the second terminal of switch 304 C ​D The control terminal of

[0076] In the illustrated example of FIG. 3, resistor 302 C The first terminal of is coupled to the first I / O terminal 202. Moreover, resistor 302 C The second terminal of is coupled to the second terminal of switch 304 H In the example of FIG. 3, the control terminal of switch 304 H Is coupled to the third output terminal of control circuitry 216, the first terminal of switch 304 H Is coupled to the second terminal of resistor 302 A And the second terminal of switch 304 H Is coupled to the second terminal of resistor 302 C The second terminal of.

[0077] In the illustrated example of FIG. 3, the control terminal of switch 304 K Is coupled to the third output terminal of control circuitry 216, the first terminal of switch 304 K Is coupled to the first terminal of switch 304 H The first terminal of and resistor 302 A The second terminal of, and the second terminal of switch 304 K Is coupled to the first terminal of resistor 302 D In the example of FIG. 3, the first terminal of resistor 302 D Is coupled to the second terminal of switch 304 K Moreover, the second terminal of resistor 302 D Is coupled to the second I / O terminal 204.

[0078] In the illustrated example of FIG. 3, the first terminal of resistor 302 E Is coupled to the first I / O terminal 202. Moreover, the second terminal of resistor 302 E Is coupled to the second terminal of switch 304 G In the example of FIG. 3, the control terminal of switch 304 G Is coupled to the second output terminal of control circuitry 216, the first terminal of switch 304 G Is coupled to the second terminal of resistor 302 A And the second terminal of switch 304 G Is coupled to the second terminal of resistor 302 E The second terminal of.

[0079] In the illustrated example of FIG. 3, the control terminal of switch 304 J Is coupled to the second output terminal of control circuitry 216, the first terminal of switch 304 JThe first terminal of is coupled to switch 304 G The first terminal of and resistor 302 A The second terminal of, and switch 304 J The second terminal of is coupled to resistor 302 F The first terminal of. In the example of FIG. 3, resistor 302 F The first terminal of is coupled to switch 304 J The second terminal of. Moreover, resistor 302 F The second terminal of is coupled to the second I / O terminal 204.

[0080] In the illustrated example of FIG. 3, resistor 302 G The first terminal of is coupled to the first I / O terminal 202. Moreover, resistor 302 G The second terminal of is coupled to switch 304 F The second terminal of. In the example of FIG. 3, switch 304 F The control terminal of is coupled to the first output terminal of control circuitry 216, the first terminal of switch 304 F The first terminal of is coupled to resistor 302 A The second terminal of, and switch 304 F The second terminal of is coupled to resistor 302 G The second terminal of.

[0081] In the illustrated example of FIG. 3, switch 304 I The control terminal of is coupled to the first output terminal of control circuitry 216, the first terminal of switch 304 I The first terminal of is coupled to the first terminal of switch 304 F The first terminal of and resistor 302 A The second terminal of, and switch 304 I The second terminal of is coupled to resistor 302 H The first terminal of. In the example of FIG. 3, resistor 302 H The first terminal of is coupled to switch 304 I The second terminal of. Moreover, resistor 302 H The second terminal of is coupled to the second I / O terminal 204.

[0082] In the illustrated example of FIG. 3, the first input terminal of the transmitter equalizer circuitry 316 is coupled to the first output terminal of the receiver circuitry 214 B The first output terminal of, and the second input terminal of the transmitter equalizer circuitry 316 is coupled to the receiver circuitry 214 BThe second output terminal. Moreover, the first output terminal of the transmitter equalizer circuit system 316 is coupled to the first I / O terminal 202, and the second output terminal of the transmitter equalizer circuit system 316 is coupled to the second I / O terminal 204. In the example of FIG. 3, the first driver terminal of the transmitter equalizer circuit system 316 is coupled to the switch 304 L The second terminal. In some examples, the second driver terminal of the transmitter equalizer circuit system 316 is coupled to the switch 304 M The second terminal.

[0083] In the illustrated example of FIG. 3, the switch 304 L The control terminal is coupled to the sixth output terminal of the control circuit system 216, the first terminal of the switch 304 L Is coupled to the current source 318 A The second terminal, and the second terminal of the switch 304 L Is coupled to the first driver terminal of the transmitter equalizer circuit system 316. Moreover, the first terminal of the current source 318 A Is coupled to the ground terminal 314, and the second terminal of the current source 318 A Is coupled to the first terminal of the switch 304 L In some examples, the control terminal of the switch 304 M Is coupled to the seventh output terminal of the control circuit system 216, the first terminal of the switch 304 M Is coupled to the current source 318 B The second terminal, and the second terminal of the switch 304 M Is coupled to the second driver terminal of the transmitter equalizer circuit system 316. Moreover, in such examples, the first terminal of the current source 318 B Is coupled to the ground terminal 314, and the second terminal of the current source 318 B Is coupled to the first terminal of the switch 304 M The first terminal.

[0084] In the illustrated example of FIG. 3, a first input terminal of the receiver level shifter circuit system 320 is coupled to the first I / O terminal 202, and a second input terminal of the receiver level shifter circuit system 320 is coupled to the second I / O terminal 204. Moreover, a first output terminal of the receiver level shifter circuit system 320 is coupled to a first input terminal of the receiver equalizer circuit system 322, and a second output terminal of the receiver level shifter circuit system 320 is coupled to a second input terminal of the receiver equalizer circuit system 322. In the example of FIG. 3, the first input terminal of the receiver equalizer circuit system 322 is coupled to the first output terminal of the receiver level shifter circuit system 320, and the second input terminal of the receiver equalizer circuit system 322 is coupled to the second output terminal of the receiver level shifter circuit system 320. Moreover, a first output terminal of the receiver equalizer circuit system 322 is coupled to a second input terminal of the transmitter circuit system 212 B and a second output terminal of the receiver equalizer circuit system 322 is coupled to the transmitter circuit system 212 B 's first input terminal.

[0085] In the illustrated example of FIG. 3, an input terminal of the control circuit system 216 is coupled to a processor (e.g., processor 106 A 、106 B ), a retimer (e.g., retimer 110 A 、110 B ), or a connector (e.g., connector 112 A 、112 B ) at least one of them. In the example of FIG. 3, a first output terminal of the control circuit system 216 is coupled to a control terminal of the switch 304 F and a control terminal of the switch 304 I . Moreover, a second output terminal of the control circuit system 216 is coupled to a control terminal of the switch 304 G and a control terminal of the switch 304 J . In the example of FIG. 3, a third output terminal of the control circuit system 216 is coupled to a control terminal of the switch 304 H and a control terminal of the switch 304 K .

[0086] In the illustrated example of FIG. 3, a fourth output terminal of the control circuit system 216 is coupled to the switch 304 EThe control terminal, the first input terminal of the XOR gate 306, the first input terminal of the NAND gate 308, and the input terminal of the NOT gate 310. Moreover, the fifth output terminal of the control circuit system 216 is coupled to the second input terminal of the XOR gate 306 and the second input terminal of the NAND gate 308. In the example of FIG. 3, the sixth output terminal of the control circuit system 216 is coupled to the control terminal of the switch 304 L of the control terminal. In some examples, the seventh output terminal of the control circuit system 216 is coupled to the control terminal of the switch 304 M Although FIG. 3 illustrates an example manner of implementing Figure 2 the shared terminal network 210 A , the transmitter circuit system 212 A and the receiver circuit system 214 A However Figure 2 the shared terminal network 210 B , the transmitter circuit system 212 B and the receiver circuit system 214 B can be respectively similar to the shared terminal network 210 of FIG. 3 A , the transmitter circuit system 212 A and the receiver circuit system 214 A implemented

[0087] In the illustrated example of FIG. 3, the transmitter equalizer circuit system 316 is implemented by one or more switches. For example, the transmitter equalizer circuit system 316 is implemented by one or more negative-positive-negative (NPN) bipolar junction transistors (BJTs). In the example of FIG. 3, the transmitter equalizer circuit system 316 equalizes the signals received from the receiver circuit system 214 at the first input terminal and the second input terminal of the transmitter equalizer circuit system 316 B . Moreover, the transmitter equalizer circuit system 316 retransmits the signals at the first I / O terminal 202 and the second I / O terminal 204

[0088] In the illustrated example of FIG. 3, the current source 318 A is implemented by at least one of one or more switches and passive electrical components or active electrical components. In some examples, the current source 318 B is implemented by at least one of one or more switches and passive electrical components or active electrical components. The current source 318 A and in some examples, the current source 318 B operates as a driver for the transmitter equalizer circuit system 316. The driver of the transmitter equalizer circuit system 316 (e.g., the current source 318 A and in some examples, the current source 318 B)perform at least one of the following: by the control circuitry 216 by closing or opening the switch 304 L and in some instances, the switch 304 M at least one of (e.g., via at least one transmitter driver enable signal) to enable or disable.

[0089] In the illustrated example of FIG. 3, the receiver level shifter circuitry 320 is implemented by at least one of one or more switches and passive electrical components or active electrical components. For example, the receiver level shifter circuitry 320 is implemented by one or more NPN BJTs and one or more current sources. The example receiver level shifter circuitry 320 performs at least one of the following: increasing or decreasing the voltage between the first I / O terminal 202 and the second I / O terminal 204 to a value for operating the receiver equalizer circuitry 322.

[0090] In the illustrated example of FIG. 3, the receiver equalizer circuitry 322 is implemented by at least one of one or more switches and passive electrical components or active electrical components. The example receiver equalizer circuitry 322 equalizes the signals received at the first I / O terminal 202 and the second I / O terminal 204. For example, the receiver equalizer circuitry 322 amplifies the high-frequency portion of the signals received at the first I / O terminal 202 and the second I / O terminal 204 and attenuates the low-frequency portion of the signals to equalize the frequency-dependent attenuation caused by one or more transmission paths. Moreover, the receiver equalizer circuitry 322 transmits the signals to the transmitter circuitry 212 B .

[0091] In the illustrated example of FIG. 3, the control circuitry 216 is implemented by at least one of a combinational logic circuitry or a sequential logic circuitry. For example, the control circuitry 216 is implemented by a digital logic circuitry (e.g., at least one of a combinational digital logic circuitry or a sequential digital logic circuitry). In the example of FIG. 3, the control circuitry 216 controls the impedance of the shared termination network 210 A . For example, when enabling at least one of the transmitter circuitry 212 A or the receiver circuitry 214 A during the nominal operation of the re-driver 200, there are idle cycles during which the control circuitry 216 adjusts the impedance of the shared termination network 210 A to compensate for transients in the common-mode voltage of the shared termination network 210 A . Moreover, after the common-mode voltage of the shared termination network 210 A has reached a steady-state value, the control circuitry 216 sets the shared termination network 210 AThe impedance returns to the steady-state value of the nominal operation of the re-driver 200 (e.g., 42.5 Ω). In this way, the control circuitry 216 maintains compliance of the re-driver 200 with the limits specified by USB 3 and USB 4.

[0092] In the illustrated example of FIG. 3, during the enabling of the transmitter circuitry 212 A the control circuitry 216 reduces the impedance of the shared termination network 210 A to maintain compliance with USB 3 and USB 4. For example, there are at least two cases for enabling the transmitter circuitry 212 A In the first example case, the common-mode voltage terminal of the shared termination network 210 A (e.g., the second terminal of the resistor 302 A is coupled to the power supply voltage terminal 312 via the switch 304 B and via the resistor 302 I and the switch 304 C For example, in the first case, the switch 304 A is open, the switch 304 B is closed, the switch 304 C is closed, and the switch 304 D is open.

[0093] In the first example case, the control circuitry 216 closes the switches 304 A before enabling the transmitter circuitry 212 F 304 G 304 H 304 I 304 J 304 K Thus, the control circuitry 216 reduces the impedance of the shared termination network 210 A before enabling the transmitter circuitry 212 A In the first case, the control circuitry 216 enables the transmitter circuitry 212 L by closing at least one of the switches 304 M (e.g., via at least one transmitter driver enable signal). Thus, the voltage at the common-mode terminal of the shared termination network 210 A (e.g., the second terminal of the resistor 302 A changes from VCC (e.g., 1.8 V) to the effective value of the transmitter circuitry 212 A Advantageously, by reducing the impedance of the shared termination network 210 A before enabling the transmitter circuitry 212 A the voltage at the common-mode terminal of the shared termination network 210A For the impedance, the control circuitry 216 maintains compliance with USB 3 and USB 4, even though during the enabling of the transmitter circuitry 212 A a voltage at the common-mode terminal of the shared termination network 210 A e.g., the second terminal of resistor 302 A may experience at least one transient.

[0094] In an example first case, after the voltage at the common-mode terminal of the shared termination network 210 A e.g., the second terminal of resistor 302 A reaches a steady-state value, the control circuitry 216 returns the impedance of the shared termination network 210 A to the steady-state value of the nominal operation of the re-driver 200 (e.g., 42.5 Ω). For example, after a first threshold amount of time (e.g., 10 - 15 microseconds (μs)) after the control circuitry 216 enables the transmitter circuitry 212 A the control circuitry 216 returns the impedance of the shared termination network 210 A to the value of the steady-state operation (e.g., nominal operation) of the re-driver 200, which has been fine-tuned for process variations of the re-driver 200. In an example first case, after the startup of the transmitter circuitry 212 A has been completed, the re-driver 200 enters nominal operation. For example, after a second threshold amount of time (e.g., 30 μs) after the control circuitry 216 sets the impedance of the shared termination network 210 A to the steady-state value, the re-driver 200 enters nominal operation.

[0095] As described above, there are at least two cases for enabling the transmitter circuitry 212 A In an example second case, the common-mode voltage terminal of the shared termination network 210 A e.g., the second terminal of resistor 302 A is coupled to the power supply voltage terminal 312 via resistor 302 I and switch 304 C For example, in the second case, switch 304 A is open, switch 304 B is open, switch 304 C is closed, and switch 304 D is open.

[0096] In an example second case, the control circuitry 216 closes switch 304 A before enabling the transmitter circuitry 212 F 304G , 304 H , 304 I , 304 J , 304 K . Therefore, the control circuit system 216 reduces the impedance of the shared termination network 210 A before enabling the transmitter circuit system 212 A . In a second scenario, the control circuit system 216 enables the transmitter circuit system 212 L by closing at least one of switch 304 M or switch 304 A (e.g., via at least one transmitter driver enable signal). Moreover, when enabling the transmitter circuit system 212 A , the control circuit system 216 closes switch 304 B . Therefore, the voltage at the common-mode terminal of the shared termination network 210 A (e.g., the second terminal of resistor 302 A ) transitions from VCC (e.g., 1.8V) to the RMS value of the transmitter circuit system 212 A . Advantageously, by reducing the impedance of the shared termination network 210 A before enabling the transmitter circuit system 212 A , the control circuit system 216 maintains compliance with USB 3 and USB 4, even though during the enabling of the transmitter circuit system 212 A , at least one transient may occur at the common-mode terminal of the shared termination network 210 A (e.g., the second terminal of resistor 302 A ).

[0097] In a second instance, after the voltage at the common-mode terminal of the shared termination network 210 A (e.g., the second terminal of resistor 302 A ) reaches a steady-state value, the control circuit system 216 returns the impedance of the shared termination network 210 A to the steady-state value (e.g., 42.5Ω) of the nominal operation of the re-driver 200. For example, after a first threshold amount of time (e.g., 10 - 15 μs) after the control circuit system 216 enables the transmitter circuit system 212 A , the control circuit system 216 returns the impedance of the shared termination network 210 A to the value of the steady-state operation (e.g., nominal operation) of the re-driver 200, which has been fine-tuned for PVT variations of the re-driver 200. In a second instance, after the transmitter circuit system 212 AAfter the startup of A has been completed, the re-driver 200 enters nominal operation. For example, after a second threshold time amount (e.g., 30 μs) after the control circuitry 216 sets the impedance of the shared termination network 210

[0098] to a steady-state value, the re-driver 200 enters nominal operation. A In some instances, the control circuitry 216 interleaves the bias current of the transmitter circuitry 212 A when enabling the transmitter circuitry 212 A . For example, the control circuitry 216 pre-enables the transmitter circuitry 212 A before enabling it. To pre-enable the transmitter circuitry 212 A , the control circuitry 216 enables the transmitter circuitry 212 A with a lower bias current than when the transmitter circuitry 212 A is in nominal operation. For example, the transmitter circuitry 212 A closes switch 304 L and keeps switch 304 M open. After a threshold time amount (e.g., 10 - 15 μs) after pre-enabling the transmitter circuitry 212 A , the control circuitry 216 enables the transmitter circuitry 212 A with the bias current for nominal operation. To enable the transmitter circuitry 212 A with the bias current for nominal operation, the control circuitry 216 closes switch 304 L and closes switch 304 M .

[0099] In the illustrated example of FIG. 3, during the enabling of the receiver circuitry 214 A , the control circuitry 216 increases the impedance of the shared termination network 210 A to maintain compliance with USB 3 and USB 4. For example, there are at least two cases for enabling the receiver circuitry 214 A . In the first case of the example, the common-mode voltage terminal of the shared termination network 210 A (e.g., the second terminal of resistor 302 A ) is coupled to the ground terminal 314 via switch 304 A and via resistor 302 I and switch 304 D . For example, in the first case, switch 304 A is closed and switch 304 BOpen, switch 304 C Open, and switch 304 D Closed.

[0100] In the first case of the example, the control circuitry 216 opens switch 304 A before enabling the receiver circuitry 214 F 、304 G 、304 H 、304 I 、304 J 、304 K 。Thus, the control circuitry 216 increases the impedance of the shared termination network 210 A before enabling the receiver circuitry 214 A In the first case, the control circuitry 216 enables the receiver circuitry 214 by opening switch 304 A and switch 304 D (e.g., via XOR gate 306 and switch 304 E respectively, and via NOT gate 310) and closing switch 304 B and switch 304 C (e.g., via NAND gate 308 and via NOT gate 310 respectively) to enable the receiver circuitry 214 A 。Thus, the voltage at the common-mode terminal of the shared termination network 210 A (e.g., the second terminal of resistor 302 A ) transitions from VSS (e.g., 0V) to VCC (e.g., 1.8V). Advantageously, by increasing the impedance of the shared termination network 210 A before enabling the receiver circuitry 214 A , the control circuitry 216 maintains compliance with USB 3 and USB 4, even though during the enabling of the receiver circuitry 214 A , at least one transient may occur in the voltage at the common-mode terminal of the shared termination network 210 A (e.g., the second terminal of resistor 302 A ). By way of example, by increasing the impedance of the shared termination network 210 A before enabling the receiver circuitry 214 A , the control circuitry 216 prevents the common-mode voltage of the device including the re-driver 200 at the far end of the transmission path from varying outside the limits set by USB 3 and USB 4.

[0101] In the first case of the example, at the common-mode terminal of the shared termination network 210 A (e.g., the second terminal of resistor 302 AAfter the voltage at the second terminal of () reaches a steady-state value, the control circuit system 216 will make the shared termination network 210 A return its impedance to the steady-state value of the nominal operation of the re-driver 200 (e.g., 42.5 Ω). For example, after the first threshold time period (e.g., 10 - 15 μs) after the control circuit system 216 enables the receiver circuit system 214 A , the control circuit system 216 will return the impedance of the shared termination network 210 A to the value of the steady-state operation (e.g., nominal operation) of the re-driver 200, which has been fine-tuned for the process variations of the re-driver 200. In the first example case, after the startup of the receiver circuit system 214 A has been completed, the re-driver 200 enters nominal operation. For example, after the second threshold time period (e.g., 30 μs) after the control circuit system 216 sets the impedance of the shared termination network 210 A to the steady-state value, the re-driver 200 enters nominal operation.

[0102] As described above, there are at least two cases for enabling the receiver circuit system 214 A . In the second example case, the common-mode voltage terminal of the shared termination network 210 A (e.g., the second terminal of the resistor 302 A ) is coupled to the ground terminal 314 via the resistor 302 I and the switch 304 D . For example, in the second case, the switch 304 A is open, the switch 304 B is open, the switch 304 C is open, and the switch 304 D is closed.

[0103] In the second example case, the control circuit system 216 opens the switches 304 A , 304 F , 304 G , 304 H , 304 I , 304 J , 304 K before enabling the receiver circuit system 214 A . Thus, the control circuit system 216 increases the impedance of the shared termination network 210 A before enabling the receiver circuit system 214 D . In the second case, the control circuit system 216 opens the switch 304 B (e.g., via the NOT gate 310) and closes the switch 304 C(e.g., via NAND gate 308 and via inverter 310) to enable receiver circuitry 214 A . Thus, the common-mode terminal of shared termination network 210 A (e.g., the second terminal of resistor 302 A ) has its voltage transition from VSS (e.g., 0V) to VCC (e.g., 1.8V). Advantageously, by increasing the impedance of shared termination network 210 A prior to enabling receiver circuitry 214 A , control circuitry 216 maintains compliance with USB 3 and USB 4, even though during the enabling of receiver circuitry 214 A , at least one transient may occur in the voltage at the common-mode terminal of shared termination network 210 A (e.g., the second terminal of resistor 302 A ). By way of example, by increasing the impedance of shared termination network 210 A prior to enabling receiver circuitry 214 A , control circuitry 216 prevents the common-mode voltage of a device including a re-driver 200 at the far end of the transmission path from varying outside the limits set by USB 3 and USB 4.

[0104] In a second example case, after the voltage at the common-mode terminal of shared termination network 210 A (e.g., the second terminal of resistor 302 A ) reaches a steady-state value, control circuitry 216 returns the impedance of shared termination network 210 A to the steady-state value (e.g., 42.5Ω) for nominal operation of re-driver 200. By way of example, after a first threshold amount of time (e.g., 10 - 15 μs) after control circuitry 216 enables receiver circuitry 214 A , control circuitry 216 returns the impedance of shared termination network 210 A to the value for steady-state operation (e.g., nominal operation) of re-driver 200, which has been fine-tuned for PVT variations of re-driver 200. In the second example case, after the startup of receiver circuitry 214 A has been completed, re-driver 200 enters nominal operation. By way of example, after a second threshold amount of time (e.g., 30 μs) after control circuitry 216 sets the impedance of shared termination network 210 A to the steady-state value, re-driver 200 enters nominal operation.

[0105] In the illustrated example of FIG. 3, switches 304 A , 304 D , 304L and 304 M is an N-channel metal-oxide-semiconductor field-effect transistor (MOSFET). Alternatively, switch 304 A and 304 D and 304 L and 304 M can be at least one of an N-channel field-effect transistor (FET), an N-channel insulated-gate bipolar transistor (IGBT), an N-channel junction field-effect transistor (JFET), an NPN BJT, or a slightly modified P-type equivalent device. In the example of FIG. 3, switch 304 B and 304 C and 304 E [[ID=z17]]and 304 F and 304 G and 304 H and 304 I and 304 J and 304 K is a P-channel MOSFET. Alternatively, switch 304 B and 304 C and 304 E and 304 F and 304 G and 304 H and 304 I and 304 J and 304 K can be at least one of a P-channel FET, a P-channel IGBT, a P-channel JFET, a positive-negative-positive (PNP) BJT, or a slightly modified N-type equivalent device. Switch 304 A and 304 B and 304 C and 304 D and 304 E and 304 F and 304 G and 304 H and 304 I and 304 J and 304 K and 304 L and 304 M can be a depletion device, a drain extension device, an enhancement device, a natural transistor, or other types of device structure transistors. Additionally, switch 304 A and 304 B and 304 C and 304 D and 304 E and 304 F and 304 G and 304 H, 304 I , 304 J , 304 K , 304 L , 304 M can be implemented in or on a silicon substrate (Si), a silicon carbide substrate (SiC), a gallium nitride substrate (GaN), or a gallium arsenide substrate (GaAs).

[0106] Although Figure 2 describes the implementation of Figure 1 the heavy driver 108 A , 108 B , 108 C , 108 D in an example manner of one or more of them, but Figure 2 one or more of the elements, processes, or devices described in Figure 2 can be combined, divided, rearranged, omitted, removed, or implemented in at least one of any other ways. In addition, Figure 2 the example shared terminal network 210 A , the example shared terminal network 210 B , the example transmitter circuit system 212 A , the example transmitter circuit system 212 B , the example receiver circuit system 214 A , the example receiver circuit system 214 B , the example control circuit system 216, or more generally, the example heavy driver 200 can be implemented by hardware alone or by hardware in combination with at least one of software or firmware. Thus, for example, the example shared terminal network 210 A , the example shared terminal network 210 B , the example transmitter circuit system 212 A , the example transmitter circuit system 212 B , the example receiver circuit system 214 A , the example receiver circuit system 214 B , the example control circuit system 216 or more generally, any one of the example heavy drivers 200 can be implemented by a programmable circuit system in combination with machine-readable instructions (e.g., firmware or software), a processor circuit system, an analog circuit, a digital circuit, a logic circuit, a programmable processor, a programmable microcontroller, a graphics processing unit (GPU), a digital signal processor (DSP), an ASIC, a programmable logic device (PLD), or a field-programmable logic device (FPLD) (e.g., FPGA). Additionally, Figure 2 the example heavy driver 200 can include in addition to or instead of Figure 2At least one of one or more elements, one or more processes, or one or more apparatuses as described therein, or may include more than one of any and all of the described elements, processes, and apparatuses.

[0107] Figure 4 is a flowchart representing at least one of example machine-readable instructions or example operation 400, the example operation being capable of performing at least one of the following: while enabling Figure 2 the transmitter circuitry 212 A during use Figure 2 the example programmable circuitry implementation of the control circuitry 216 to execute, instantiate, or effect to control Figure 2 the shared terminal network 210 A . Figure 4 At least one of the example machine-readable instructions or example operation 400 begins at block 402, where the control circuitry 216 monitors the heavy driver enable signal. For example, the control circuitry 216 monitors the input terminals of the control circuitry 216 to obtain the heavy driver enable signal.

[0108] During Figure 4 the illustrated example, at block 404, the control circuitry 216 determines whether the heavy driver enable signal has been received. In response to (e.g., based on) the control circuitry 216 determining that the heavy driver enable signal has been received (block 404: yes), at least one of the example machine-readable instructions or example operation 400 proceeds to block 406. In response to (e.g., based on) the control circuitry 216 determining that the heavy driver enable signal has not been received (block 404: no), at least one of the example machine-readable instructions or example operation 400 returns to block 402.

[0109] During Figure 4 the illustrated example, at block 406, the control circuitry 216 changes the impedance of the shared terminal network 210 of the heavy driver 200 A to a first value to compensate for at least one transient in the common-mode voltage of the shared terminal network 210 A . For example, at block 406, the control circuitry 216 closes the switch 304 F 、304 G 、304 H 、304 I 、304 J 、304 K to reduce the impedance of the shared terminal network 210 A to the first value. To close the switch 304 F 、304 G 、304 H 、304 I, 304 J , 304 K , the control circuit system 216 transmits a logic low value (e.g., 0V) to the switch 304 F , 304 G , 304 H , 304 I , 304 J , 304 K , to the corresponding control terminal of 304. At block 408, the control circuit system 216 changes the common-mode voltage of the shared terminal network 210 A . For example, at block 408, the control circuit system 216 changes the common-mode voltage of the shared terminal network 210 A from VCC (e.g., 1.8V) to the effective value of the transmitter circuit system 212 A .

[0110] In some instances, at block 410, the control circuit system 216 changes the supply current of the transmitter circuit system 212 of the re-driver 200 A (e.g., changes the supply current of the transmitter circuit system of the re-driver 200) to a second value to compensate for at least one transient in the common-mode voltage of the shared terminal network 210 A . For example, at block 410, the control circuit system 216 closes the switch 304 L and keeps the switch 304 M open. In such instances, at block 412, the control circuit system 216 determines whether the common-mode voltage of the shared terminal network 210 A has reached an intermediate value between VCC (e.g., 1.8V) and the effective value of the transmitter circuit system 212 A . For example, at block 412, the control circuit system 216 determines whether a timer maintained by the control circuit system 216 has met a first threshold amount of time (e.g., 10 - 15 μs).

[0111] In response to (e.g., based on) the control circuit system 216 determining that the common-mode voltage of the shared terminal network 210 A has not reached the intermediate value (e.g., block 412: no), at least one of the example machine-readable instructions or example operation 400 returns to block 412. In response to (e.g., based on) the control circuit system 216 determining that the common-mode voltage of the shared terminal network 210 A has reached the intermediate value (e.g., block 412: yes), at least one of the example machine-readable instructions or example operation 400 advances to block 414. At block 414, the control circuit system 216 sets the transmitter circuit system 212 AThe supply current of changes to a steady-state value. For example, at block 414, the control circuitry 216 closes switch 304 M and holds switch 304 L closed to increase the supply current of the transmitter circuitry 212 A to a third value greater than a second value.

[0112] At Figure 4 the illustrated example of, at block 416, the control circuitry 216 determines whether the common-mode voltage of the shared termination network 210 A has reached a steady state (e.g., within a threshold of the effective value of the transmitter circuitry 212 A ). For example, at block 416, the control circuitry 216 determines whether a timer maintained by the control circuitry 216 has met a second threshold amount of time (e.g., 10 - 15 μs). In response to (e.g., based on) the control circuitry 216 determining that the common-mode voltage of the shared termination network 210 A has not reached a steady state (e.g., block 416: no), at least one of the example machine-readable instructions or example operation 400 returns to block 416.

[0113] In response to (e.g., based on) the control circuitry 216 determining that the common-mode voltage of the shared termination network 210 A has reached a steady state (e.g., block 416: yes), at least one of the example machine-readable instructions or example operation 400 proceeds to block 418. At block 418, the control circuitry 216 changes the impedance of the shared termination network 210 A to a steady-state value (e.g., 42.5 Ω). For example, at block 418, the control circuitry 216 returns switch 304 F 、304 G 、304 H 、304 I 、304 J 、304 K to a trim state to increase the impedance of the shared termination network 210 A to a fourth value greater than a first value.

[0114] At Figure 4 the illustrated example of, at block 420, the control circuitry 216 determines whether the enabling of the transmitter circuitry 212 A has been completed. For example, at block 420, the control circuitry 216 determines whether a timer maintained by the control circuitry 216 has met a third threshold amount of time (e.g., 30 μs). In response to (e.g., based on) the control circuitry 216 determining that the enabling of the transmitter circuitry 212 AEnablement (block 420: No), at least one of the example machine-readable instructions or example operations 400 returns to block 420. In response to (e.g., based on) the control circuitry 216 determining that the transmitter circuitry 212 has been enabled A (block 420: Yes), at least one of the example machine-readable instructions or example operations 400 advances to block 422. At block 422, the transmitter circuitry 212 A equalizes one or more signals at the equalization re-driver 200.

[0115] Figure 5 is a flowchart representative of at least one of the example machine-readable instructions or example operations 500, which example operations may perform at least one of the following: during the enablement Figure 2 of the receiver circuitry 214 A using an example programmable circuitry implementation of the control circuitry 216 to execute, instantiate, or effect control of Figure 2 the shared termination network 210 Figure 2 of A . Figure 5 At least one of the example machine-readable instructions or example operations 500 begins at block 502, where the control circuitry 216 monitors a re-driver enable signal. For example, the control circuitry 216 monitors an input terminal of the control circuitry 216 to obtain the re-driver enable signal.

[0116] During Figure 5 the illustrated example, at block 504, the control circuitry 216 determines whether the re-driver enable signal has been received. In response to (e.g., based on) the control circuitry 216 determining that the re-driver enable signal has been received (block 504: Yes), at least one of the example machine-readable instructions or example operations 500 advances to block 506. In response to (e.g., based on) the control circuitry 216 determining that the re-driver enable signal has not been received (block 504: No), at least one of the example machine-readable instructions or example operations 500 returns to block 502.

[0117] During Figure 5 the illustrated example, at block 506, the control circuitry 216 changes the impedance of the shared termination network 210 A of the re-driver 200 to a first value to compensate for at least one transient in the common-mode voltage of the shared termination network 210 A . For example, at block 506, the control circuitry 216 opens the switches 304 F 、 304 G 、 304 H 、 304 I 、 304 J 、 304K to increase the impedance of the shared termination network 210A to a first value. To turn off switch 304 F 、304 G 、304 H 、304 I 、304 J 、304 K ,the control circuitry 216 transmits a logic high value (e.g., 5V) to the control terminals of switch 304 F 、304 G 、304 H 、304 I 、304 J 、304 K to the corresponding control terminals. At block 508, the control circuitry 216 changes the common-mode voltage of the shared termination network 210 A . For example, at block 508, the control circuitry 216 changes the common-mode voltage of the shared termination network 210 A from VSS (e.g., 0V) to VCC (e.g., 1.8V).

[0118] In Figure 5 the illustrated example, at block 510, the control circuitry 216 determines whether the common-mode voltage of the shared termination network 210 A has reached a steady state (e.g., VCC). For example, at block 510, the control circuitry 216 determines whether a timer maintained by the control circuitry 216 has met a first threshold amount of time (e.g., 10 - 15 μs). In response to (e.g., based on) the control circuitry 216 determining that the common-mode voltage of the shared termination network 210 A has not reached a steady state (e.g., block 510: no), at least one of the example machine-readable instructions or example operation 500 returns to block 510.

[0119] In response to (e.g., based on) the control circuitry 216 determining that the common-mode voltage of the shared termination network 210 A has reached a steady state (e.g., block 510: yes), at least one of the example machine-readable instructions or example operation 500 proceeds to block 512. At block 512, the control circuitry 216 changes the impedance of the shared termination network 210 A to a steady state value (e.g., 42.5 Ω). For example, at block 512, the control circuitry 216 returns switch 304 F 、304 G 、304 H 、304 I 、304 J 、304 K to a trim state to increase the impedance of the shared termination network 210A The impedance is reduced to a second value that is less than the first value.

[0120] At Figure 5 In the illustrated example of, at block 514, control circuitry 216 determines whether enabling of receiver circuitry 214 has been completed A For example, at block 514, control circuitry 216 determines whether a timer maintained by control circuitry 216 has met a second threshold amount of time (e.g., 30 μs). In response to (e.g., based on) control circuitry 216 determining that enabling of receiver circuitry 214 has not been completed A (block 514: No), at least one of the example machine-readable instructions or example operation 500 returns to block 514. In response to (e.g., based on) control circuitry 216 determining that enabling of receiver circuitry 214 has been completed A (block 514: Yes), at least one of the example machine-readable instructions or example operation 500 advances to block 516. At block 516, receiver circuitry 214 A equalizes one or more signals at equalization re-driver 200.

[0121] Figure 6 is a flowchart depicting a first example finite state machine (FSM) 600 that can perform at least one of the following: execute, instantiate, or implement using an example programmable circuit system implementation of a re-driver 200 during enabling of Figure 2 a transmitter circuitry 212 of A During Figure 2 In an example of, FSM 600 corresponds to a first scenario for enabling transmitter circuitry 212 as described above Figure 6 In an example of, FSM 600 begins in state 602, in which re-driver 200 is in a sleep operation mode. For example, in state 602, switch 304 A is open, switch 304 Figure 6 is closed, switch 304 A is closed, and switch 304 B is open. Moreover, in state 602, switch 304 C is closed, switch 304 D is open, switch 304 F is closed, switch 304 G is open, switch 304 H is closed, switch 304 I is open, switch 304 J is closed, switch 304 K is in a trim state. In state 602, switch 304 L is open. In an interleaved transmitter circuitry 212 AIn an example of the bias current, switch 304 M is also opened in state 602. Accordingly, the transmitter circuitry 212 A is disabled in state 602.

[0122] In Figure 6 the illustrated example, the FSM 600 transitions from state 602 to state 604 in response to (e.g., based on) the control circuitry 216 receiving a re-driver enable signal. In state 604, switch 304 A is opened, switch 304 B is closed, switch 304 C is closed, and switch 304 D is opened. Moreover, in state 604, switches 304 F , 304 G , 304 H , 304 I , 304 J , 304 K are closed (e.g., to reduce the impedance of the shared termination network 210 A ). In state 604, switch 304 L is opened. In an example of the bias current of the interleaved transmitter circuitry 212 A , switch 304 M is also opened in state 604. Accordingly, the transmitter circuitry 212 A is disabled in state 604.

[0123] In Figure 6 the illustrated example, the FSM 600 transitions out of state 604 in response to (e.g., based on) the control circuitry 216 enabling the driver of the transmitter circuitry 212 A . By way of example, the FSM 600 transitions out of state 604 in response to (e.g., based on) the control circuitry 216 closing at least one of switch 304 L or switch 304 M . In some examples, the FSM 600 transitions from state 604 to state 606. By way of example, when the bias current of the interleaved transmitter circuitry 212 A is present, switch 304 L is closed and switch 304 M is opened, and the FSM 600 transitions from state 604 to state 606.

[0124] In Figure 6 the illustrated example, in state 606, switch 304 A is opened, switch 304 B is closed, switch 304 CClosed, and switch 304 D Open. Also, in state 606, switch 304 F 、304 G 、304 H 、304 I 、304 J 、304 K Closed (e.g., to reduce the impedance of the shared termination network 210 A ). In state 606, switch 304 L is closed and switch 304 M is open. Thus, the transmitter circuitry 212 A is quasi-enabled in state 606.

[0125] In Figure 6 the illustrated example, the FSM 600 transitions from state 606 to state 608 in response to (e.g., based on) the control circuitry 216 determining that a first threshold time amount (e.g., 10 - 15 μs) has elapsed. In Figure 6 the example, the first threshold time amount corresponds to the threshold time amount at which the common-mode voltage of the shared termination network 210 A reaches the intermediate value between VCC and the effective value of the transmitter circuitry 212 A . In state 608, switch 304 A is open, switch 304 B is closed, switch 304 C is closed, and switch 304 D is open. Also, in state 608, switch 304 F 、304 G 、304 H 、304 I 、304 J 、304 K are closed (e.g., to reduce the impedance of the shared termination network 210 A ). In state 608, switch 304 L is closed. In the example of the bias current of the interleaved transmitter circuitry 212 A , switch 304 M is also closed in state 608. Thus, the transmitter circuitry 212 A is enabled in state 608.

[0126] In Figure 6 the illustrated example, the FSM 600 transitions from state 608 to state 610 in response to (e.g., based on) the control circuitry 216 determining that a second threshold time amount (e.g., 10 - 15 μs) has elapsed. In Figure 6In the example, the second threshold time amount corresponds to the common-mode voltage of the shared terminal network 210 A reaching the threshold time amount at which it reaches a steady state. In state 610, switch 304 A is open, switch 304 B is closed, switch 304 C is closed, and switch 304 D is open. Moreover, in state 610, switch 304 F 、304 G 、304 H 、304 I 、304 J 、304 K is in the fine-tuning state. In state 610, switch 304 L is closed. In the example of the bias current of the interleaved transmitter circuit system 212 A , switch 304 M is also closed in state 610. Therefore, the transmitter circuit system 212 A is enabled in state 610.

[0127] In Figure 6 the illustrated example, the FSM 600 transitions from state 610 to state 612 in response to (e.g., based on) the control circuit system 216 determining that a third threshold time amount (e.g., 30 μs) has elapsed. In state 612, switch 304 A is open, switch 304 B is closed, switch 304 C is closed, and switch 304 D is open. Moreover, in state 612, switch 304 F 、304 G 、304 H 、304 I 、304 J 、304 K is in the fine-tuning state. In state 612, switch 304 L is closed. In the example of the bias current of the interleaved transmitter circuit system 212 A , switch 304 M is also closed in state 612. In Figure 6 the example, the third threshold time amount corresponds to the threshold time amount for completing the enabling of the transmitter circuit system 212 A . Therefore, the transmitter circuit system 212 A is in the high-speed operation mode in state 612. In Figure 6 the example, the FSM 600 transitions from state 612 to state 602 in response to (e.g., based on) the control circuit system 216 receiving a re-driver deactivation signal.

[0128] Figure 7 is a flowchart representing a second instance finite state machine (FSM) 700 that can perform at least one of the following: during enabling Figure 2 of the transmitter circuitry 212 A using an instance programmable circuitry implementation of the Figure 2 redriver 200. In an Figure 7 instance, the FSM 700 corresponds to a second case for enabling the transmitter circuitry 212 described above A . Figure 7 The FSM 700 of A starts in state 702, in which the redriver 200 is in a sleep operation mode. For example, in state 702, switch 304 B is open, switch 304 C is closed, and switch 304 D is open. Also, in state 702, switch 304 F , 304 G , 304 H , 304 I , 304 J , 304 K is in a trim state. In state 702, switch 304 L is open. In an instance of the bias current of the interleaved transmitter circuitry 212 A , switch 304 M is also open in state 702. Thus, the transmitter circuitry 212 A is disabled in state 702.

[0129] In the Figure 7 illustrated instance, the FSM 700 transitions from state 702 to state 704 in response to (e.g., based on) the control circuitry 216 receiving a redriver enable signal. In state 704, switch 304 A is open, switch 304 B is open, switch 304 C is closed, and switch 304 D is open. Also, in state 704, switch 304 F , 304 G , 304 H , 304 I , 304 J , 304 K is closed (e.g., to reduce the shared termination network 210 A(the impedance). In state 704, switch 304 L is open. In an example of the bias current of the interleaved transmitter circuit system 212 A , switch 304 M is also open. Thus, the transmitter circuit system 212 A is disabled in state 704.

[0130] In Figure 7 the illustrated example, the FSM 700 transitions out of state 704 in response to (e.g., based on) the control circuit system 216 changing the common-mode voltage of the shared termination network 210 A . For example, the FSM 700 transitions out of state 704 in response to (e.g., based on) the control circuit system 216 closing switch 304 B . Moreover, when the FSM 700 transitions out of state 704, the control circuit system 216 closes switch 304 L or at least one of switch 304 M . In some examples, the FSM 700 transitions from state 704 to state 706. For example, when there is a bias current in the interleaved transmitter circuit system 212 A , switch 304 L closes, switch 304 M opens, and the control circuit system 216 closes switch 304 B , the FSM 700 transitions from state 704 to state 706.

[0131] In Figure 7 the illustrated example, in state 706, switch 304 A is open, switch 304 B is closed, switch 304 C is closed, and switch 304 D is open. Moreover, in state 706, switches 304 F , 304 G , 304 H , 304 I , 304 J , 304 K are closed (e.g., to reduce the impedance of the shared termination network 210 A ). In state 706, switch 304 L is closed and switch 304 M is open. Thus, the transmitter circuit system 212 A is quasi-enabled in state 706.

[0132] In Figure 7In the illustrated example, the FSM 700 transitions from state 706 to state 708 in response to (e.g., based on) the control circuitry 216 determining that a first threshold time amount (e.g., 10 - 15 μs) has elapsed. In Figure 7 the example, the first threshold time amount corresponds to the common - mode voltage of the shared termination network 210 A reaching a threshold time amount that is the intermediate value between VCC and the effective value of the transmitter circuitry 212 A In state 708, switch 304 A is open, switch 304 B is closed, switch 304 C is closed, and switch 304 D is open. Moreover, in state 708, switches 304 F 304 G 304 H 304 I 304 J 304 K are closed (e.g., to reduce the impedance of the shared termination network 210 A ). In state 708, switch 304 L is closed. In an example of the bias current of the interleaved transmitter circuitry 212 A , switch 304 M is also closed in state 708. Thus, the transmitter circuitry 212 A is enabled in state 708.

[0133] In Figure 7 the illustrated example, the FSM 700 transitions from state 708 to state 710 in response to (e.g., based on) the control circuitry 216 determining that a second threshold time amount (e.g., 10 - 15 μs) has elapsed. In Figure 7 the example, the second threshold time amount corresponds to the threshold time amount for the common - mode voltage of the shared termination network 210 A to reach a steady state. In state 710, switch 304 A is open, switch 304 B is closed, switch 304 C is closed, and switch 304 D is open. Moreover, in state 710, switches 304 F 304 G 304 H 304 I 304 J 304 K are in a fine - tuning state. In state 710, switch 304 L is closed. In an interleaved transmitter circuitry 212 AIn an example of the bias current, switch 304 M is also closed in state 710. Accordingly, the transmitter circuitry 212 A is enabled in state 710.

[0134] In Figure 7 the illustrated example, the FSM 700 transitions from state 710 to state 712 in response to (e.g., based on) the control circuitry 216 determining that a third threshold amount of time (e.g., 30 μs) has elapsed. In state 712, switch 304 A is open, switch 304 B is closed, switch 304 C is closed, and switch 304 D is open. Moreover, in state 712, switches 304 F 304 G 304 H 304 I 304 J 304 K are in a trim state. In state 712, switch 304 L is closed. In an example of the bias current of the interleaved transmitter circuitry 212 A , switch 304 M is also closed in state 712. In Figure 7 the example, the third threshold amount of time corresponds to a threshold amount of time for completing the enabling of the transmitter circuitry 212 A . Accordingly, the transmitter circuitry 212 A is in a high-speed operation mode in state 712. In Figure 7 the example, the FSM 700 transitions from state 712 to state 702 in response to (e.g., based on) the control circuitry 216 receiving a re-driver disable signal.

[0135] Figure 8 is a flow diagram depicting a first example finite state machine (FSM) 800 that can perform at least one of the following: execute, instantiate, or implement during the enabling Figure 2 of the receiver circuitry 214 A using an example programmable circuitry implementation of the re-driver 200. In Figure 2 the example, the FSM 800 corresponds to a first scenario for enabling the receiver circuitry 214 Figure 8 described above. A The FSM 800 of Figure 8 begins in state 802, in which the re-driver 200 is in a sleep operation mode. For example, in state 802, switch 304A Closed, switch 304 B Open, switch 304 C Open, and switch 304 D Closed. Moreover, in state 802, switch 304 F 、304 G 、304 H 、304 I 、304 J 、304 K Is in the fine-tuning state. In state 802, the receiver circuit system 214 is deactivated A .

[0136] In Figure 8 The illustrated example of, the FSM 800 transitions from state 802 to state 804 in response to (e.g., based on) the control circuit system 216 receiving a re-driver enable signal. In state 804, switch 304 A Closed, switch 304 B Open, switch 304 C Open, and switch 304 D Closed. Moreover, in state 804, switch 304 F 、304 G 、304 H 、304 I 、304 J 、304 K Open (e.g., to increase the impedance of the shared termination network 210 A ). In state 804, the receiver circuit system 214 is deactivated A .

[0137] In Figure 8 The illustrated example of, the FSM 800 transitions from state 804 to state 806 in response to (e.g., based on) the control circuit system 216 changing the common-mode voltage of the shared termination network 210 A . For example, the FSM 800 transitions from state 804 to state 806 in response to (e.g., based on) the control circuit system 216 closing switch 304 B And switch 304 C And opening switch 304 A And switch 304 D . In state 806, switch 304 A Open, switch 304 B Closed, switch 304 C Closed, and switch 304 D Open. Moreover, in state 806, switch 304 F 、304 G, 304 H , 304 I , 304 J , 304 K Disconnect (e.g., to increase the impedance of the shared termination network 210 A . In state 806, the receiver circuitry 214 is enabled A .

[0138] In Figure 8 the illustrated example, the FSM 800 transitions from state 806 to state 808 in response to (e.g., based on) the control circuitry 216 determining that a first threshold time amount (e.g., 10 - 15 μs) has elapsed. In Figure 8 the example, the first threshold time amount corresponds to the threshold time amount for the common - mode voltage of the shared termination network 210 A to reach a steady state. In state 808, switch 304 A is disconnected, switch 304 B is closed, switch 304 C is closed, and switch 304 D is disconnected. Moreover, in state 808, switches 304 F , 304 G , 304 H , 304 I , 304 J , 304 K are in a trim state. In state 808, the receiver circuitry 214 A is enabled

[0139] In Figure 8 the illustrated example, the FSM 800 transitions from state 808 to state 810 in response to (e.g., based on) the control circuitry 216 determining that a second threshold time amount (e.g., 30 μs) has elapsed. By way of example, the second threshold time amount corresponds to the threshold time amount for completing the enabling of the receiver circuitry 214 A . In state 810, switch 304 A is disconnected, switch 304 B is closed, switch 304 C is closed, and switch 304 D is disconnected. Moreover, in state 810, switches 304 F , 304 G , 304 H , 304 I , 304 J , 304 K are in a trim state. In state 810, the receiver circuitry 214 A is in a high - speed operation mode. In Figure 8In an example, the FSM 800 transitions from state 810 to state 802 in response to (e.g., based on) the control circuitry 216 receiving a redriver disable signal.

[0140] Figure 9 is a flowchart depicting a second instance finite state machine (FSM) 900 that can perform at least one of the following: during enabling Figure 2 of the receiver circuitry 214 A using Figure 2 an instance programmable circuitry implementation of the redriver 200 is executed, instantiated, or implemented. In Figure 9 an example, the FSM 900 corresponds to a second scenario for enabling the receiver circuitry 214 described above A . Figure 9 The FSM 900 of A begins in state 902, in which the redriver 200 is in a sleep operating mode. For example, in state 902, switch 304 B is open, switch 304 C is open, switch 304 D is open, and switch 304 F is closed. Also, in state 902, switches 304 G , 304 H , 304 I , 304 J , 304 K are in a trim state. In state 902, the receiver circuitry 214 is disabled A .

[0141] In Figure 9 the illustrated example, the FSM 900 transitions from state 902 to state 904 in response to (e.g., based on) the control circuitry 216 receiving a redriver enable signal. In state 904, switch 304 A is open, switch 304 B is open, switch 304 C is open, and switch 304 D is closed. Also, in state 904, switches 304 F , 304 G , 304 H , 304 I , 304 J , 304 K are open (e.g., to increase the impedance of the shared termination network 210 A ). In state 904, the receiver circuitry 214 is disabled A .

[0142] In Figure 9 the illustrated example, the FSM 900 transitions from state 904 to state 906 in response to (e.g., based on) the control circuitry 216 changing the common-mode voltage of the shared termination network 210 A . For example, the FSM 900 transitions from state 904 to state 906 in response to (e.g., based on) the control circuitry 216 closing switch 304 B and switch 304 C and opening switch 304 D . In state 906, switch 304 A is open, switch 304 B is closed, switch 304 C is closed, and switch 304 D is open. Moreover, in state 906, switches 304 F , 304 G , 304 H , 304 I , 304 J , 304 K are open (e.g., to increase the impedance of the shared termination network 210 A ). In state 906, the receiver circuitry 214 A is enabled.

[0143] In Figure 9 the illustrated example, the FSM 900 transitions from state 906 to state 908 in response to (e.g., based on) the control circuitry 216 determining that a first threshold time amount (e.g., 10 - 15 μs) has elapsed. In Figure 9 the example, the first threshold time amount corresponds to the threshold time amount for the common-mode voltage of the shared termination network 210 A to reach a steady state. In state 908, switch 304 A is open, switch 304 B is closed, switch 304 C is closed, and switch 304 D is open. Moreover, in state 908, switches 304 F , 304 G , 304 H , 304 I , 304 J , 304 K are in a trim state. In state 908, the receiver circuitry 214 A is enabled.

[0144] In Figure 9In the illustrated example, the FSM 900 transitions from state 908 to state 910 in response to (e.g., based on) the control circuitry 216 determining that a second threshold amount of time (e.g., 30 μs) has elapsed. For example, the second threshold amount of time corresponds to a threshold amount of time for completing the enabling of the receiver circuitry 214 A In state 910, switch 304 A is open, switch 304 B is closed, switch 304 C is closed, and switch 304 D is open. Also, in state 910, switch 304 F 、304 G 、304 H 、304 I 、304 J 、304 K is in a trim state. In state 910, the receiver circuitry 214 A is in a high-speed operation mode. In Figure 9 the example, the FSM 900 transitions from state 910 to state 902 in response to (e.g., based on) the control circuitry 216 receiving a re-driver disable signal.

[0145] Figure 4 、 5 、6, 7, 8, and 9 show a flowchart representing at least one of example machine-readable instructions or example operations that may be executed by a programmable circuitry to perform at least one of implementing or instantiating the re-driver 200 of Figure 2 , and the example operations that may be executed by a programmable circuitry to perform at least one of implementing or instantiating the re-driver 200 of Figure 2 . The machine-readable instructions may be at least one of the following: (a) one or more executable programs or portions of one or more executable programs executed by a programmable circuitry (e.g., the programmable circuitry 1312 shown in the example programmable circuitry platform 1300 described below in connection with Figure 13 ), or (b) one or more functions or portions of functions to be executed by an example programmable circuitry (e.g., an FPGA). In some examples, the machine-readable instructions trigger at least one of the operations, tasks, etc. to be carried out or executed in an automated manner in the real world. As used herein, "automated" means without human intervention.

[0146] The program can be embodied in instructions (e.g., at least one of software or firmware) stored on one or more non-transitory storage media, where the one or more non-transitory storage media are at least one of computer-readable or machine-readable, such as cache memory, magnetic storage devices or disks (e.g., floppy disks, hard disk drives (HDDs), etc.), optical storage devices or discs (e.g., Blu-ray discs, compact discs (CDs), digital versatile discs (DVDs), etc.), redundant arrays of independent disks (RAID), registers, ROM, solid state drives (SSDs), SSD memories, non-volatile memories (e.g., electrically erasable programmable read-only memories (EEPROMs), flash memories, etc.), volatile memories (e.g., any type of random access memory (RAM), etc.) or at least one of any other storage device or storage disc. The instructions in the at least one non-transitory computer-readable or machine-readable medium can perform at least one of the following: be programmed or executed by programmable circuitry in one or more hardware devices, but at least one of the entire program or portions thereof can alternatively perform one or more of the following: (a) be executed or instantiated by one or more hardware devices other than programmable circuitry or (b) be embodied in dedicated hardware. The machine-readable instructions can perform at least one of the following: be distributed across multiple hardware devices or be executed by two or more hardware devices (e.g., server and client hardware devices). For example, the client hardware device can be implemented by an endpoint client hardware device (e.g., a hardware device associated with at least one of a human user or a machine user) or an intermediate client hardware device gateway (e.g., a radio access network (RAN)), which can facilitate communication between the server and the endpoint client hardware device. Similarly, the non-transitory computer-readable storage medium can include one or more media. Additionally, while reference is made to Figure 4 , 5, the flowcharts described in 6, 7, 8, and 9 depict example programs, but many other methods of implementing the instance re-driver 200 may alternatively be used. For example, (a) the order of execution of the blocks of the flowchart may be changed, or (b) at least one of some of the described blocks may be changed, removed, or combined. Additionally or alternatively, any or all of the blocks of the flowchart may be implemented by one or more hardware circuits (e.g., processor circuitry, discrete analog circuitry, integrated analog circuitry, discrete digital circuitry, integrated digital circuitry, FPGA, ASIC, comparator, operational amplifier (op-amp), logic circuits, etc.), the hardware circuits being constructed to perform the corresponding operations without executing software or firmware. The programmable circuitry may be distributed at different network locations or local to at least one of one or more hardware devices (e.g., a single-core processor (e.g., a single-core CPU), a multi-core processor (e.g., a multi-core CPU, XPU, etc.)). For example, the programmable circuitry may be at least one of the following: (a) one or more of a CPU or FPGA located in the same package (e.g., the same integrated circuit (IC) package or in two or more separate enclosures), (b) one or more processors in a single machine, (c) multiple processors distributed across server racks, (d) multiple processors distributed across one or more server racks, (e) etc., or (f) any combination thereof.

[0147] The machine-readable instructions described herein may be stored in one or more of a compressed format, an encrypted format, a segmented format, a compiled format, an executable format, a packaged format, etc. The machine-readable instructions described herein may be stored as data (e.g., computer-readable data, machine-readable data, one or more bits (e.g., one or more computer-readable bits, one or more machine-readable bits, etc.), a bit stream (e.g., a computer-readable bit stream, a machine-readable bit stream, etc.)) or a data structure (e.g., as part of an instruction, code, a representation of code, etc.), and the data structure may be used to perform at least one of the following: create, fabricate, or generate machine-executable instructions. For example, the machine-readable instructions may be segmented and stored on at least one of one or more storage devices, one or more disks, or one or more computing devices (e.g., servers) located at the same or different locations of a network or a collection of networks (e.g., in the cloud, at an edge device, etc.). The machine-readable instructions may need to be installed, modified, adapted, updated, combined, supplemented, configured, decrypted, decompressed, unpackaged, distributed, redistributed, compiled, etc., in order for at least one of them to be directly readable, directly interpretable, or directly executable by at least one of a computing device or other machine. For example, the machine-readable instructions may be stored in multiple parts, and the multiple parts are at least one of separately compressed, separately encrypted, or separately stored on separate computing devices, where when at least one of decryption, decompression, or combination is performed, the parts form a set of at least one of computer-executable or machine-executable instructions, and the computer-executable or machine-executable instructions implement at least one of one or more functions or one or more operations that may together form a program (e.g., the program described herein).

[0148] In another example, the machine-readable instructions may be stored in a state readable by a programmable circuit system, but libraries (e.g., dynamic link libraries (DLLs)), software development kits (SDKs), application programming interfaces (APIs), etc., need to be added in order to execute the machine-readable instructions on a particular computing device or another device. In another example, it may be necessary to adjust the machine-readable instructions (e.g., stored settings, data inputs, recorded network addresses, etc.) before at least one of the machine-readable instructions or the corresponding program can be fully or partially executed. Thus, at least one of the machine-readable, computer-readable, or machine-readable media used herein may contain at least one of the instructions or programs, regardless of the particular format or state of the machine-readable instructions or the program.

[0149] The machine-readable instructions described herein can be represented by any past, present, or future instruction language, scripting language, programming language, etc. For example, the machine-readable instructions can be represented using any one of the following languages: C, C++, Java, C#, Perl, Python, JavaScript, Hypertext Markup Language (HTML), Structured Query Language (SQL), Swift, etc.

[0150] As mentioned above, Figure 4 、 5 Examples of operations for 6, 7, 8, and 9 can be implemented using executable instructions (e.g., at least one of computer-readable or machine-readable instructions) stored on at least one of (a) one or more non-transitory computer-readable media or (b) one or more machine-readable media. As used herein, the term at least one of non-transitory computer-readable media, non-transitory computer-readable storage media, non-transitory machine-readable media, or non-transitory machine-readable storage media is explicitly defined to include at least one of any type of computer-readable storage device or any type of computer-readable storage disk, and to exclude propagated signals and to exclude transmission media. Examples of such at least one of non-transitory computer-readable media, non-transitory computer-readable storage media, non-transitory machine-readable media, or non-transitory machine-readable storage media include optical storage devices, magnetic storage devices, HDDs, flash memories, read-only memories (ROMs), CDs, DVDs, caches, any type of RAM, registers, or any other storage device or storage disk, where information is stored for any duration (e.g., an extended period of time, permanently, for a short instance, for temporary buffering, for caching of information, etc.). As used herein, the terms "non-transitory computer-readable storage device" and "non-transitory machine-readable storage device" are defined to include any physical (at least one of mechanical, magnetic, or electrical) hardware for retaining information for a period of time, and to exclude propagated signals and to exclude transmission media. Examples of at least one of non-transitory computer-readable storage devices or non-transitory machine-readable storage devices include at least one of the following: any type of random access memory, any type of read-only memory, solid-state memory, flash memory, optical disks, magnetic disks, disk drives, or redundant array of independent disks (RAID) systems. As used herein, the term "device" refers to a physical structure, such as one or more of a mechanical device or an electrical device, hardware, or circuitry, which can or cannot be adjusted by computer-readable instructions, machine-readable instructions, etc., and / or is manufactured to execute at least one of computer-readable instructions, machine-readable instructions, etc.

[0151] Figure 10 is illustrative Figure 2Timing diagram 1000 of the operation of an example of the re-driver 200. For example, timing diagram 1000 illustrates the first case for enabling the receiver circuitry 214 described above A In the Figure 10 example, timing diagram 1000 includes a first example curve 1002, a second example curve 1004, a third example curve 1006, and a fourth example curve 1008. For example, curve 1002 represents the signal at the fourth output terminal of the control circuitry 216, and curve 1004 represents the signal at the fifth output terminal of the control circuitry 216. Moreover, curve 1006 represents at least one transmitter driver enable signal for the transmitter circuitry 212 B In the Figure 10 example, curve 1008 represents the signals at the first, second, and third output terminals of the control circuitry 216.

[0152] In the Figure 10 illustrated example, at an example first time 1010, the signal at the fourth output terminal of the control circuitry 216 is at a logic low value (e.g., "0", 0V, etc.), and the signal at the fifth output terminal of the control circuitry 216 is at a logic high value (e.g., "1", 5V, etc.). Thus, at time 1010, switch 304 A is closed, switch 304 B is open, switch 304 C is open, and switch 304 D is closed. Thus, at time 1010, the common-mode voltage terminal of the shared terminal network 210 A (e.g., the second terminal of resistor 302 A ) is coupled to the ground terminal 314 (e.g., the common-mode voltage is set to VSS). Moreover, at time 1010, at least one transmitter driver enable signal for the transmitter circuitry 212 B is at a logic low value (e.g., "0", 0V, etc.). Thus, the transmitter circuitry 212 B is deactivated at time 1010.

[0153] In the Figure 10In the illustrated example, prior to time 1010, the decimal value of the signals at the first output terminal, the second output terminal, and the third output terminal of the control circuitry 216 is six (e.g., the trim state). For example, prior to time 1010, the signal at the first output terminal of the control circuitry 216 is at a logic high value (e.g., "1", 5V, etc.), the signal at the second output terminal of the control circuitry 216 is at a logic high value (e.g., "1", 5V, etc.), and the signal at the third output terminal of the control circuitry 216 is at a logic low value (e.g., "0", 0V, etc.). At time 1010, the decimal value of the signals at the first output terminal, the second output terminal, and the third output terminal of the control circuitry 216 transitions from six (e.g., 110) to seven (e.g., 111). For example, at time 1010, the signal at the first output terminal of the control circuitry 216 remains at a logic high value (e.g., "1", 5V, etc.), the signal at the second output terminal of the control circuitry 216 remains at a logic high value (e.g., "1", 5V, etc.), and the signal at the third output terminal of the control circuitry 216 transitions from a logic low value (e.g., "0", 0V, etc.) to a logic high value (e.g., "5", 5V, etc.).

[0154] In Figure 10 the illustrated example, between time 1010 and an example second time 1012, the signal at the fourth output terminal of the control circuitry 216 transitions from a logic low value (e.g., "0", 0V, etc.) to a logic high value (e.g., "1", 5V, etc.), and the signal at the fifth output terminal of the control circuitry 216 remains at a logic high value (e.g., "1", 5V, etc.). Accordingly, between time 1010 and time 1012, switch 304 A transitions from closed to open, switch 304 B transitions from open to closed, switch 304 C transitions from open to closed, and switch 304 D transitions from closed to open. Accordingly, between time 1010 and time 1012, the common-mode voltage terminal of the shared terminal network 210 A e.g., the second terminal of resistor 302 A transitions from being coupled to the ground terminal 314 (e.g., VSS) to being coupled to the power supply voltage terminal 312 (e.g., VCC).

[0155] Advantageously, by increasing the impedance of the shared terminal network 210 A prior to time 1010, the control circuitry 216 remains compliant with USB 3 and USB 4. For example, although during the change in the common-mode voltage of the shared terminal network 210 A in the shared terminal network 210 Aat the common-mode terminal (e.g., the second terminal of resistor 302 A ), at least one transient may occur in the voltage, but the common-mode voltage of the re-driver 200 will remain within the limits set by USB 3 and USB 4 because the control circuitry 216 increases the impedance of the shared termination network 210 A . Moreover, by increasing the impedance of the shared termination network 210 A before time 1010, the control circuitry 216 prevents the common-mode voltage of the device including the re-driver 200 at the far end of the transmission path from varying outside the limits set by USB 3 and USB 4.

[0156] At Figure 10 the illustrated example of, at time 1012, at least one transmitter driver enable signal for the transmitter circuitry 212 B switches from a logic low value (e.g., "0", 0V, etc.) to a logic high value (e.g., "1", 5V, etc.). Accordingly, the transmitter circuitry 212 B switches from being disabled to being enabled at time 1012. At the instance third time 1014, the decimal value of the signals at the first output terminal, the second output terminal, and the third output terminal of the control circuitry 216 switches from seven to six (e.g., a trim state). For example, at time 1014, the signal at the first output terminal of the control circuitry 216 remains at a logic high value (e.g., "1", 5V, etc.), the signal at the second output terminal of the control circuitry 216 remains at a logic high value (e.g., "1", 5V, etc.), and the signal at the third output terminal of the control circuitry 216 switches from a logic high value (e.g., "5", 5V, etc.) to a logic low value (e.g., "0", 0V, etc.).

[0157] Figure 11 is a first graphical illustration 1100 depicting the variation of the common-mode voltage at the near end and the far end of the transmission path when using the re-driver 200 Figure 2 . For example, the graphical illustration 1100 depicts the variation of the common-mode voltage at the near end and the far end of the transmission path during the enabling of the transmitter circuitry 212 A . In the instance of Figure 11 , the graphical illustration 1100 includes a first example curve 1102 representing the common-mode voltage of the device including the re-driver 200 at the far end of the transmission path and a second example curve 1104 representing the common-mode voltage of the re-driver 200 at the near end of the transmission path.

[0158] At Figure 11In the illustrated example, curve 1102 includes a horizontal axis (e.g., the x-axis) for measuring time in μs. Curve 1102 also includes a vertical axis (e.g., the y-axis) for measuring the common-mode voltage of the device at the far end of the transmission path in mV. At Figure 11 In the example, curve 1104 includes a horizontal axis (e.g., the x-axis) for measuring time in μs. Curve 1104 also includes a vertical axis (e.g., the y-axis) for measuring the common-mode voltage of the heavy driver 200 at the near end of the transmission path in V.

[0159] At Figure 11 In the illustrated example, before the example first time 1106 (e.g., 1 μs), the control circuitry 216 closes switch 304 F 304 G 304 H 304 I 304 J 304 K to reduce the impedance of the shared termination network 210 A . At time 1106, the control circuitry 216 enables the transmitter circuitry 212 by closing switch 304 L or switch 304 M at least one of (e.g., via at least one transmitter driver enable signal). Thus, at time 1106, the common-mode voltage of the heavy driver 200 at the near end of the transmission path begins to transition from VCC (e.g., 1.8 V) to the effective value of the transmitter circuitry 212 A . (e.g., 1.25 V). A

[0160] At Figure 11 In the illustrated example, the common-mode voltage of the device at the far end of the transmission path experiences at least one transient at time 1106. For example, the common-mode voltage of the device at the far end of the transmission path transitions from 0 V to approximately -223 mV in approximately 0.76 μs. Advantageously, by reducing the impedance of the shared termination network 210 A before enabling the transmitter circuitry 212 A , the control circuitry 216 maintains compliance of the heavy driver 200 with USB 3 and USB 4 regardless of at least one transient in the common-mode voltage of the device at the far end of the transmission path. For example, the common-mode voltage of the device at the far end of the transmission path does not decrease by more than 300 mV.

[0161] At Figure 11In the illustrated example, at instance second time 1108 (e.g., 20 μs), the common-mode voltage of the re-driver 200 at the proximal end of the transmission path is within the threshold of the steady-state value (e.g., 1.25 V). Thus, at time 1108, the control circuitry 216 sets the impedance of the shared termination network 210 A back to the steady-state value (e.g., 42.5 Ω) of the nominal operation of the re-driver 200. For example, after a threshold amount of time (e.g., 19 μs) after the control circuitry 216 enables the transmitter circuitry 212 A , the control circuitry 216 sets the impedance of the shared termination network 210 A back to the value of the steady-state operation (e.g., nominal operation) of the re-driver 200, which has been fine-tuned for PVT variations of the re-driver 200.

[0162] Figure 12 is a second graphical illustration 1200 depicting the variation of the common-mode voltage at the proximal and distal ends of the transmission path when using the re-driver 200 Figure 2 . For example, the graphical illustration 1200 depicts the variation of the common-mode voltage at the proximal and distal ends of the transmission path during the enabling of the receiver circuitry 214 A . In the example of Figure 12 , the graphical illustration 1200 includes a first example curve 1202 representing the common-mode voltage of the device including the re-driver 200 at the distal end of the transmission path and a second example curve 1204 representing the common-mode voltage of the re-driver 200 at the proximal end of the transmission path.

[0163] In Figure 12 the illustrated example, curve 1202 includes a horizontal axis (e.g., x-axis) for measuring time in μs. Curve 1202 also includes a vertical axis (e.g., y-axis) for measuring the common-mode voltage of the device at the distal end of the transmission path in mV. In Figure 12 the example, curve 1204 includes a horizontal axis (e.g., x-axis) for measuring time in μs. Curve 1204 also includes a vertical axis (e.g., y-axis) for measuring the common-mode voltage of the re-driver 200 at the proximal end of the transmission path in V.

[0164] In Figure 12 the illustrated example, before instance first time 1206 (e.g., 0.75 μs), the control circuitry 216 opens switches 304 F 、304 G 、304 H 、304 I 、304 J 、304 K , to increase the impedance of the shared termination network 210 AThe impedance. At time 1206, the control circuitry 216 enables the receiver circuitry 214 A . For example, at time 1206, the control circuitry 216 enables the receiver circuitry 214 by (a) opening switch 304 A and switch 304 D and closing switch 304 B and switch 304 C or (b) opening switch 304 D and closing switch 304 B and switch 304 C . Thus, at time 1206, the common-mode voltage of the re-driver 200 at the proximal end of the transmission path begins to transition from VSS (e.g., 0V) to VCC (e.g., 1.8V). A . Thus, at time 1206, the common-mode voltage of the re-driver 200 at the proximal end of the transmission path begins to transition from VSS (e.g., 0V) to VCC (e.g., 1.8V).

[0165] In Figure 12 the illustrated example, the common-mode voltage of the device at the distal end of the transmission path experiences at least one transient at time 1206. For example, the common-mode voltage of the device at the distal end of the transmission path transitions from 0V to approximately 0.81V in approximately 0.73 μs. Advantageously, by increasing the impedance of the shared termination network 210 A before enabling the receiver circuitry 214 A , the control circuitry 216 maintains compliance of the re-driver 200 with USB 3 and USB 4, regardless of at least one transient in the common-mode voltage of the device at the distal end of the transmission path. For example, the common-mode voltage of the device at the distal end of the transmission path does not increase by more than 1V.

[0166] In Figure 12 the illustrated example, at the example second time 1208 (e.g., 11 μs), the common-mode voltage of the re-driver 200 at the proximal end of the transmission path is within the threshold of the steady-state value (e.g., 1.8V). Thus, at time 1208, the control circuitry 216 returns the impedance of the shared termination network 210 A to the steady-state value (e.g., 42.5 Ω) of the nominal operation of the re-driver 200. For example, after a threshold amount of time (e.g., 10.25 μs) after the control circuitry 216 enables the receiver circuitry 214 A , the control circuitry 216 returns the impedance of the shared termination network 210 A to the steady-state value of the nominal operation of the re-driver 200, which has been fine-tuned for PVT variations of the re-driver 200.

[0167] Figure 13is a block diagram of an example programmable circuit system platform 1300 that is configured to perform at least one of the following: execute or instantiate Figure 4 , 5 , at least one of the example machine-readable instructions or example operations of 6, 7, 8, and 9 to implement Figure 2 's re-driver 200. The programmable circuit system platform 1300 can be, for example, at least one of a re-driver, a re-timer, or any other type of computing device or any other type of electronic device.

[0168] The illustrated example of the programmable circuit system platform 1300 includes a programmable circuit system 1312. The illustrated example of the programmable circuit system 1312 is hardware. For example, the programmable circuit system 1312 can be implemented by at least one of one or more integrated circuits, one or more logic circuits, one or more FPGAs, one or more microprocessors, one or more CPUs, one or more GPUs, one or more DSPs, or one or more microcontrollers from any desired family or manufacturer. The programmable circuit system 1312 can be implemented by one or more semiconductor (e.g., silicon-based) devices. In this example, the programmable circuit system 1312 implements an example control circuit system 216.

[0169] The illustrated example of the programmable circuit system 1312 includes local memory 1313 (e.g., cache, registers, etc.). The illustrated example of the programmable circuit system 1312 communicates with main memory 1314, 1316 that includes volatile memory 1314 and non-volatile memory 1316 via a bus 1318. The volatile memory 1314 can be implemented by at least one of synchronous dynamic random access memory (SDRAM), dynamic random access memory (DRAM), dynamic random access memory or any other type of RAM device. The non-volatile memory 1316 can be implemented by flash memory or any other desired type of memory device. Access to the illustrated example of the main memory 1314, 1316 is controlled by a memory controller 1317. In some examples, the memory controller 1317 can be implemented by one or more integrated circuits, logic circuits, microcontrollers, or any other type of circuitry from any desired family or manufacturer to manage the data flow to and from the main memory 1314, 1316.

[0170] The illustrated example of the programmable circuit system platform 1300 also includes interface circuitry 1320. The interface circuitry 1320 can be implemented by hardware according to any type of interface standard, such as an Ethernet interface, a universal serial bus (USB) interface, at least one of an interface, a near field communication (NFC) interface, a peripheral component interconnect (PCI) interface, or a peripheral component interconnect express (PCIe) interface.

[0171] In the illustrated example, one or more input devices 1322 are connected to interface circuitry 1320. The input devices 1322 allow a user (e.g., a human user, a machine user, etc.) to input at least one of data or a command into the programmable circuitry 1312. The input devices 1322 may be implemented by, for example, at least one of an audio sensor, a microphone, a camera (still or video), a keyboard, a button, a mouse, a touch screen, a track pad, a track ball, an isopoint device, or a voice recognition system.

[0172] One or more output devices 1324 are also connected to the interface circuitry 1320 of the illustrated example. The output devices 1324 may be implemented by, for example, at least one of a display device (e.g., a light emitting diode (LED), an organic light emitting diode (OLED), a liquid crystal display (LCD), a cathode ray tube (CRT) display, an in-plane switching (IPS) display, a touch screen, etc.), a haptic output device, a printer, or a speaker. Thus, the interface circuitry 1320 of the illustrated example may include at least one of a graphics driver card, a graphics driver chip, or a graphics processor circuitry such as a GPU.

[0173] The interface circuitry 1320 of the illustrated example also includes a communication device, such as at least one of a transmitter, a receiver, a transceiver, a modem, a residential gateway, a wireless access point, or a network interface, to facilitate data exchange with an external machine (e.g., any type of computing device) via a network 1326. The communication may be performed via, for example, an Ethernet connection, a digital subscriber line (DSL) connection, a telephone line connection, a coaxial cable system, a satellite system, an over-the-horizon wireless system, a line-of-sight wireless system, a cellular phone system, an optical connection, etc. In this example, the interface circuitry 1320 implements an example shared terminal network 210 A 、example shared terminal network 210 B 、example transmitter circuitry 212 A 、example transmitter circuitry 212 B 、example receiver circuitry 214 A and example receiver circuitry 214 B .

[0174] The programmable circuit system platform 1300 of the illustrated example also includes one or more mass storage disks or devices 1328 to store at least one of firmware, software, or data. Examples of such mass storage disks or devices 1328 include at least one of a magnetic storage device (e.g., a floppy disk, a drive, an HDD, etc.), an optical storage device (e.g., a Blu-ray disc, a CD, a DVD, etc.), a RAID system, or a solid-state storage disk or device (e.g., at least one of a flash memory device or an SSD).

[0175] Can be implemented by Figure 4 , 5 , 6, 7, 8, and 9, the machine-readable instructions 1332 can perform at least one of the following: storing in the mass storage device 1328, storing in the volatile memory 1314, storing in the non-volatile memory 1316, or storing on at least one non-transitory computer-readable storage medium that can be removable, such as a CD or a DVD.

[0176] "Comprising" and "including" (and all of their forms and tenses) are used herein as open-ended terms. Thus, whenever a claim uses any form of "comprising" or "including" (e.g., comprises, includes, comprising, including, has, etc.) as a leading term or is employed within any kind of claim recitation, there may be other elements, terms, etc. without exceeding the scope of the corresponding claim or recitation. As used herein, when the phrase "at least" is used as a transitional term in a leading term of a claim, for example, it is open-ended in the same manner as the terms "including" and "comprising".

[0177] As used herein, singular references (e.g., "a", "an", "first", "second", etc.) do not exclude a plurality. As used herein, the term "a" or "an" of an object refers to one or more of the objects. The terms "a" (or "one"), "one or more", and "at least one" can be used interchangeably herein. Moreover, although listed separately, multiple components, elements, or acts can be implemented by, for example, the same entity or object. Also, although individual features may be included in different instances or claims, these features may be combined, and the inclusion in different instances or claims does not imply that the combination of features is infeasible or disadvantageous in at least one of them.

[0178] As used herein, unless otherwise indicated, a connection reference (e.g., attached, coupled, connected, and joined) can include at least one intermediate member in the intermediate member between the elements referenced by the connection reference or the relative movement between those elements. Thus, a connection reference does not necessarily infer that the two elements are directly connected or in a fixed relationship with each other. As used herein, stating that any part "contacts" another part is defined to mean that there is no intermediate part between the two parts.

[0179] Unless otherwise explicitly stated, descriptive terms such as "first", "second", "third", etc. are used herein without inputting or otherwise indicating the meaning of at least one of priority, physical order, arrangement in a list, or sorting in any way, but are only used as at least one of a label or arbitrary name to distinguish elements for ease of understanding the described examples. In some examples, the descriptive term "first" can be used to refer to an element in a specific embodiment, while the same element can be referred to by a different descriptive term such as "second" or "third" in a technical solution. In such cases, such descriptive terms are only used to clearly identify those elements within the context of the discussion (e.g., within the technical solution), where the elements may otherwise share the same name.

[0180] As used herein, the phrase "communicate" includes its variants and encompasses at least one of direct communication or indirect communication through one or more intermediate components, and does not require at least one of direct physical (e.g., wired) communication or continuous communication, but also includes selective communication conducted at one or more of periodic intervals, predetermined intervals, aperiodic intervals, or one-time events.

[0181] As used herein, "programmable circuitry" is defined as including at least one of the following: (i) one or more application-specific circuits (e.g., application-specific integrated circuits (ASICs)) that are constructed to perform specific operations and include one or more semiconductor-based logic devices (e.g., electrical hardware implemented by one or more transistors), or (ii) one or more general-purpose semiconductor-based circuits that can be programmed with instructions to perform at least one of a specific function or a specific operation and include one or more semiconductor-based logic devices (e.g., electrical hardware implemented by one or more transistors). Examples of programmable circuitry include at least one of a programmable microprocessor, such as a central processing unit (CPU) that can execute a first instruction to perform at least one of one or more operations or one or more functions, a field-programmable gate array (FPGA) that can be programmed with a second instruction to trigger at least one of the configuration or structuring of the FPGA to instantiate at least one of one or more operations or one or more functions corresponding to the first instruction, a graphics processing unit (GPU) that can execute a first instruction to perform at least one of one or more operations or one or more functions, a digital signal processor (DSP), an XPU, a network processing unit (NPU), one or more microcontrollers that can execute a first instruction to perform at least one of one or more operations or one or more functions, or an integrated circuit such as an ASIC. For example, an XPU can be implemented by a heterogeneous computing system that includes multiple types of programmable circuitry (e.g., at least one of one or more FPGAs, one or more CPUs, one or more GPUs, one or more NPUs, one or more DSPs, etc., or any combination thereof) and an orchestration technique (e.g., an application programming interface (API)) that can allocate computing tasks to any one of the multiple types of programmable circuitry that is suitable and available to perform the computing task.

[0182] As used herein, an integrated circuit / circuitry is defined as one or more semiconductor packages containing one or more circuit elements such as transistors, capacitors, inductors, resistors, current paths, diodes, etc. For example, an integrated circuit can be implemented as one or more of an ASIC, an FPGA, a chip, a microchip, programmable circuitry, a semiconductor substrate coupling multiple circuit elements, a system-on-chip (SoC), etc.

[0183] As used herein, the phrase "at least one of A or B" (or "at least one of A and B") refers to an embodiment that includes any one of the following: (a) at least one A; (b) at least one B; and (c) at least one A and at least one B.

[0184] In this specification, the term "coupled" may encompass a connection, communication, or signal path that enables a functional relationship consistent with this specification. For example, if device A generates a signal to control device B to perform an action, then: (a) in a first instance, device A is coupled to device B by a direct connection; or (b) in a second instance, device A is coupled to device B through an intermediate component C, provided that the intermediate component C does not change the functional relationship between device A and device B such that device B is controlled by device A through the control signal generated by device A.

[0185] Numeric identifiers such as "first", "second", "third", etc. are only used to distinguish elements of at least one substantially same type in terms of structure or function. These identifiers used in the detailed description do not necessarily coincide with those used in the technical solution.

[0186] A device "configured to" perform a task or function may do at least one of the following: (a) be configured (e.g., at least one of programmed or hardwired) to perform the function when manufactured by the manufacturer; or (b) be configurable (or reconfigurable) by a user after manufacture to perform the function / or at least one of other additional or alternative functions. The configuration may be performed by at least one of firmware or software programming of the device, by at least one of the construction or layout of the hardware components and interconnections of the device, or by a combination thereof.

[0187] As used herein, the terms "terminal", "node", "interconnection", "pin", and "lead" may be used interchangeably. Unless specifically stated to the contrary, these terms are generally used to mean the interconnections or their terminals between device elements, circuit elements, integrated circuits, devices, or other electronic devices or semiconductor components.

[0188] A circuit or device described herein as including certain components may alternatively be adapted to be coupled to those components to form the described circuit system or device. For example, a structure described as including at least one of one or more semiconductor elements (e.g., transistors), one or more passive elements (e.g., at least one of resistors, capacitors, or inductors), or one or more sources (e.g., at least one of a voltage source or a current source) may alternatively include only semiconductor elements within a single physical device (e.g., at least one of a semiconductor die or an integrated circuit (IC) package), and may be adapted to be coupled to one or more of at least some passive elements or at least some sources, for example, by at least one of an end user or a third party, at the time of manufacture or after manufacture to form the described structure.

[0189] The circuits described herein can be reconfigured to include the replacement components to provide functionality that is at least partially similar to the functionality available prior to component replacement. Unless otherwise stated, a component shown as a resistor generally represents any one or more elements coupled in at least one of series or parallel to provide the amount of impedance represented by the shown resistor. For example, a resistor or capacitor shown and described herein as a single component can alternatively be multiple resistors or capacitors coupled in parallel between the same nodes. For example, a resistor or capacitor shown and described herein as a single component can actually be multiple resistors or capacitors coupled in series between the same two nodes as the single resistor or capacitor. Although some of the elements of the described examples are included in an integrated circuit and other elements are external to the integrated circuit, in other example embodiments, additional or fewer features can be incorporated into the integrated circuit. Additionally, at least one of the following: (a) some or all of the features described as being external to the integrated circuit can be included in the integrated circuit, or (b) some of the features described as being internal to the integrated circuit can be incorporated external to the integrated circuit. As used herein, the term "integrated circuit" means one or more circuits that are at least one of the following: (i) incorporated in / above a semiconductor substrate; (ii) incorporated in a single semiconductor package; (iii) incorporated into the same module; or (iv) incorporated in / on the same printed circuit board.

[0190] The use of the phrase "ground" in the foregoing description includes at least one of chassis ground, earth ground, floating ground, virtual ground, digital ground, common ground, or any other form of ground connection applicable to or suitable for the teachings of this specification. As used herein, "about" modifies its subject / value to identify the potential presence of variations that occur in real-world applications. For example, "about" can modify dimensions that may be imprecise due to at least one of manufacturing tolerances or other real-world imperfections. Unless otherwise stated, "about" before a value means + / - 10% of that value, or if the value is zero, a reasonable range of values around zero.

[0191] Within the scope of the technical solution, modifications to the described examples are possible and other embodiments are possible.

[0192] As should be understood from the foregoing, example systems, devices, articles of manufacture, and methods for managing the termination impedance in a re-driver have been described. For example, the described examples include a termination network shared between a receiver circuit system and a transmitter circuit system of the re-driver. Thus, the described examples reduce the parasitic impedance that may exist on the I / O terminals of the re-driver. Also, the described examples utilize a dual-purpose switch to control the common-mode voltage of the shared termination network. For example, the described switch that controls the impedance of the shared termination network during the enabling of at least one of the receiver circuit system or the transmitter circuit system is also used to fine-tune the impedance of the shared termination network for PVT variations. Thus, the described examples reduce the hardware footprint for controlling the impedance of the shared termination network during the enabling of at least one of the receiver circuit system or the transmitter circuit system. Thus, the examples described herein reduce the hardware footprint by using a fine-tuning switch to control the impedance during a common-mode offset.

[0193] Also, the described examples bias the common-mode voltage of the shared termination network of the re-driver to VCC (e.g., 1.8V). Thus, a level-shifter circuit system for the receiver circuit system of the re-driver can be implemented with one or more NPN BJTs. During high-speed operation of the re-driver, an NPN-based level-shifter circuit system operates more efficiently than a PNP-based level-shifter circuit system. The described systems, devices, articles of manufacture, and methods improve the efficiency of using a computing device by reducing the parasitic impedance at the I / O terminals of the re-driver. For example, compared to utilizing a shared termination network between a receiver circuit system and a transmitter circuit system, utilizing two different termination networks for the receiver circuit system and the transmitter circuit system of the re-driver can significantly increase the parasitic impedance at the I / O terminals of the re-driver. Thus, compared to the high-speed performance of a re-driver that utilizes a shared termination network between a receiver circuit system and a transmitter circuit system, the high-speed performance of a re-driver that utilizes two different termination networks for the receiver circuit system and the transmitter circuit system is reduced. Additionally, the examples described herein maintain compliance with USB 3 and USB 4 without degrading the high-speed performance of the re-driver. Thus, the described systems, devices, articles of manufacture, and methods relate to one or more improvements in the operation of a machine (e.g., at least one of a computer or other electronic device or mechanical device).

Claims

1. A device, comprising: a first input / output (I / O) terminal and a second I / O terminal; a first resistor having a first terminal coupled to the first I / O terminal and a second terminal coupled to at least one of a power supply voltage terminal or a ground terminal; a second resistor having a first terminal coupled to the second terminal of the first resistor and a second terminal coupled to the second I / O terminal; a third resistor having a first terminal and a second terminal, the first terminal of the third resistor being coupled to the first I / O terminal; a first switch having a control terminal, a first terminal, and a second terminal, the first terminal of the first switch being coupled to the second terminal of the first resistor, and the second terminal of the first switch being coupled to the second terminal of the third resistor; a second switch having a control terminal, a first terminal, and a second terminal, the first terminal of the second switch being coupled to the first terminal of the first switch and the second terminal of the first resistor; a fourth resistor having a first terminal coupled to the second terminal of the second switch and a second terminal coupled to the second I / O terminal; a control circuit system having an output terminal coupled to the control terminal of the first switch and the control terminal of the second switch; a transmitter circuit system having a first output terminal coupled to the first I / O terminal and a second output terminal coupled to the second I / O terminal; and a receiver circuit system having a first input terminal coupled to the first I / O terminal and a second input terminal coupled to the second I / O terminal.

2. The device according to claim 1, wherein the output terminal of the control circuit system is a first output terminal, the control circuit system has a second output terminal and a third output terminal, and the device further comprises: a third switch having a control terminal, a first terminal, and a second terminal, the control terminal of the third switch being coupled to the second output terminal of the control circuit system; an exclusive-OR gate having a first input terminal coupled to the second output terminal of the control circuit system, a second input terminal coupled to the third output terminal of the control circuit system, and an output terminal coupled to the first terminal of the third switch; a fourth switch having a control terminal coupled to the second terminal of the third switch, a first terminal coupled to the ground terminal, and a second terminal coupled to the second terminal of the first resistor; a fifth switch having a control terminal, a first terminal, and a second terminal, the first terminal of the fifth switch being coupled to the power supply voltage terminal, and the second terminal of the fifth switch being coupled to the second terminal of the first resistor; and a NAND gate having a first input terminal coupled to the second output terminal of the control circuit system, a second input terminal coupled to the third output terminal of the control circuit system, and an output terminal coupled to the control terminal of the fifth switch.

3. The apparatus according to claim 1, wherein the output terminal of the control circuitry is a first output terminal, the control circuitry has a second output terminal, and the apparatus further comprises: a NOT gate having an input terminal and an output terminal, the input terminal of the NOT gate being coupled to the second output terminal of the control circuitry; a third switch having a control terminal, a first terminal, and a second terminal, the control terminal of the third switch being coupled to the output terminal of the NOT gate, the first terminal of the third switch being coupled to the power supply voltage terminal; a fourth switch having a control terminal, a first terminal, and a second terminal, the control terminal of the fourth switch being coupled to the output terminal of the NOT gate, the first terminal of the fourth switch being coupled to the ground terminal; and a fifth resistor having a first terminal coupled to the second terminals of the third switch and the fourth switch and a second terminal coupled to the second terminal of the first resistor.

4. The apparatus according to claim 1, wherein the output terminal of the control circuitry is a first output terminal, the control circuitry has a second output terminal and a third output terminal, and the transmitter circuitry comprises: a first current source having a first terminal and a second terminal, the first terminal of the first current source being coupled to the ground terminal; a second current source having a first terminal and a second terminal, the first terminal of the second current source being coupled to the ground terminal; a third switch having a control terminal, a first terminal, and a second terminal, the control terminal of the third switch being coupled to the second output terminal of the control circuitry, the first terminal of the third switch being coupled to the second terminal of the first current source; a fourth switch having a control terminal, a first terminal, and a second terminal, the control terminal of the fourth switch being coupled to the third output terminal of the control circuitry, the first terminal of the fourth switch being coupled to the second terminal of the second current source; and a transmitter equalizer circuitry having a first driver terminal coupled to the second terminal of the third switch, a second driver terminal coupled to the second terminal of the fourth switch, a first output terminal coupled to the first I / O terminal, and a second output terminal coupled to the second I / O terminal.

5. An apparatus comprising: a first input / output I / O terminal and a second I / O terminal; a termination network having a first input terminal, a second input terminal, a third input terminal, a first output terminal, and a second output terminal, the first input terminal of the termination network being coupled to the first I / O terminal, the second input terminal of the termination network being coupled to the second I / O terminal; a transmitter circuitry having a first output terminal coupled to the first I / O terminal and a second output terminal coupled to the second I / O terminal; A receiver circuit system having a first input terminal coupled to the first output terminal of the terminal network and a second input terminal coupled to the second output terminal of the terminal network; And A control circuit system having an output terminal coupled to the third input terminal of the terminal network, the control circuit system being configured to: Change the impedance of the terminal network to a first value to compensate for at least one transient in the common-mode voltage of the terminal network; and Based on the common-mode voltage reaching a steady-state value, change the impedance of the terminal network to a second value for steady-state operation.

6. The apparatus according to claim 5, wherein the control circuit system is configured to change the common-mode voltage of the terminal network.

7. The apparatus according to claim 5, wherein the control circuit system is configured to determine whether the common-mode voltage has reached the steady-state value based on a timer satisfying a threshold amount of time.

8. The apparatus according to claim 5, wherein the first value is less than the second value, and the control circuit system is configured to: Close at least one switch of the terminal network to reduce the impedance of the terminal network to the first value to compensate for at least one transient in the common-mode voltage of the terminal network during enabling of the transmitter circuit system; and Based on the common-mode voltage reaching the steady-state value, increase the impedance of the terminal network to the second value.

9. The apparatus according to claim 5, wherein the first value is greater than the second value, and the control circuit system is configured to: Open at least one switch of the terminal network to increase the impedance of the terminal network to the first value to compensate for at least one transient in the common-mode voltage of the terminal network during enabling of the receiver circuit system; and Based on the common-mode voltage reaching the steady-state value, reduce the impedance of the terminal network to the second value.

10. The apparatus according to claim 5, wherein the transmitter circuit system includes an input terminal, the output terminal of the control circuit system is a first output terminal, the control circuit system includes a second output terminal coupled to the input terminal of the transmitter circuit system, and the control circuit system is configured to: Change the supply current of the transmitter circuit system to a third value to compensate for at least one transient in the common-mode voltage of the terminal network; and Based on the common-mode voltage reaching an intermediate value different from the steady-state value, change the supply current of the transmitter circuit system to a fourth value for steady-state operation.

11. The apparatus according to claim 10, wherein the third value is less than the fourth value, and the control circuit system is configured to reduce the supply current of the transmitter circuit system to the third value to compensate for at least one transient in the common-mode voltage of the terminal network during enabling of the transmitter circuit system.

12. The apparatus according to claim 10, wherein the third value is less than the fourth value, and the control circuitry is configured to increase the supply current of the transmitter circuitry to the fourth value based on the common-mode voltage reaching the steady-state value.

13. A method, comprising: changing, with a control circuitry, an impedance of a termination network of a heavy driver to a first value to compensate for at least one transient in a common-mode voltage of the termination network; and changing, based on the common-mode voltage reaching a steady-state value, the impedance of the termination network to a second value for steady-state operation with the control circuitry.

14. The method according to claim 13, further comprising changing the common-mode voltage of the termination network.

15. The method according to claim 13, further comprising determining whether the common-mode voltage has reached the steady-state value based on a timer satisfying a threshold amount of time.

16. The method according to claim 13, wherein the first value is less than the second value, and the method further comprises: closing at least one switch of the termination network to reduce the impedance of the termination network to the first value to compensate for the at least one transient in the common-mode voltage of the termination network during enabling of a transmitter circuitry of the heavy driver; and increasing the impedance of the termination network to the second value based on the common-mode voltage reaching the steady-state value.

17. The method according to claim 13, wherein the first value is greater than the second value, and the method further comprises: opening at least one switch of the termination network to increase the impedance of the termination network to the first value to compensate for the at least one transient in the common-mode voltage of the termination network during enabling of a receiver circuitry of the heavy driver; and decreasing the impedance of the termination network to the second value based on the common-mode voltage reaching the steady-state value.

18. The method according to claim 13, further comprising: changing a supply current of a transmitter circuitry of the heavy driver to a third value to compensate for the at least one transient in the common-mode voltage of the termination network; and changing, based on the common-mode voltage reaching an intermediate value different from the steady-state value, the supply current of the transmitter circuitry to a fourth value for steady-state operation.

19. The method according to claim 18, wherein the third value is less than the fourth value, and the method further comprises decreasing the supply current of the transmitter circuitry to the third value to compensate for the at least one transient in the common-mode voltage of the termination network during enabling of the transmitter circuitry of the heavy driver.

20. The method according to claim 18, wherein the third value is less than the fourth value, and the method further comprises increasing the supply current of the transmitter circuitry to the fourth value based on the common-mode voltage reaching the steady-state value.

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