Semiconductor structure and forming method thereof

Abstract

The embodiment of the invention provides a semiconductor structure and a forming method thereof. The semiconductor structure comprises a substrate and bit lines located on the substrate, and the bit lines extend in the second direction; the active layer is located on one side of the bit line in the first direction, and the active layer comprises a source electrode region, a channel region and a drain electrode region which are arranged in the first direction; the word line extends along the third direction and is opposite to the partial side wall, extending along the third direction, of the active layer; the capacitor structure is electrically connected with the drain electrode region of the active layer; wherein the channel region comprises a first end and a second end which are opposite to each other along the first direction, and along the second direction, the width of the first end is D1, and the width of the second end is D2, and D2gt; d1. According to the embodiment of the invention, the gate induced drain leakage current (GIDL) can be reduced, the electric leakage of the capacitor end can be reduced, and the electrical performance of the semiconductor structure can be improved.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to the field of semiconductor technologies, and particularly to a semiconductor structure and a method for forming the same. Background Art

[0002] With the development of the integration density of dynamic memories towards higher levels, higher requirements are imposed on the arrangement of transistors and the size of transistors in a dynamic memory array structure. However, due to limitations of manufacturing factors such as lithography machines and various electrical parasitic effects, there is a limit to the reduction of their critical dimensions. Therefore, how to fabricate chips with higher storage density on a single wafer is the research direction of many scientific researchers and semiconductor practitioners.

[0003] The emergence of three-dimensional dynamic random access memories (3D DRAMs), especially 3D DRAMs including multilayer horizontal cells (MHCs), which usually include a plurality of transistors stacked on a substrate, meets the above requirements. However, since the transistors stacked up and down are usually isolated by an insulating layer, the channel layers of the transistors in the stacked structure are suspended on the substrate. During the actual operation of the transistors, charge accumulation usually occurs, and it is easy to accumulate charges in the channel regions of the transistors. Due to the barrier of the insulating layer, these accumulated charges cannot be effectively released, resulting in the generation of the floating body effect, which easily causes the threshold voltage of the transistors to drift, and seriously, the transistors cannot operate normally. In addition, due to the reduction in size, the leakage current of the transistors increases, and the gate-induced drain leakage current (GIDL) increases, affecting the further improvement of the performance of semiconductor devices. Summary of the Invention

[0004] Embodiments of the present disclosure provide a semiconductor structure and a method for forming the same, which are at least beneficial to reducing the gate-induced drain leakage current (GIDL), contributing to reducing the leakage at the capacitor end, improving the floating body effect of the semiconductor structure, and enhancing the performance of the semiconductor structure.

[0005] On the one hand, embodiments of the present disclosure provide a semiconductor structure, including:

[0006] A substrate;

[0007] A bit line located on the substrate, the bit line extending along a second direction;

[0008] An active layer located on one side of the bit line along a first direction, the active layer including a source region, a channel region, and a drain region arranged along the first direction;

[0009] The word line extends along a third direction and faces a part of the side wall of the active layer extending along the third direction. The first direction, the second direction, and the third direction intersect pairwise.

[0010] The capacitor structure is located on a side of the active layer away from the bit line along the first direction, and the capacitor structure is electrically connected to the drain region of the active layer.

[0011] Wherein, the channel region includes a first end and a second end opposite to each other along the first direction. Along the second direction, the width of the first end is D1, the width of the second end is D2, and D2 > D1.

[0012] In some embodiments, the active layer includes a first active layer, a second active layer, and a third active layer. The first active layer and the second active layer extend along the first direction, the third active layer extends along the second direction. One side of the third active layer along the first direction is electrically connected to the bit line. The first active layer and the second active layer respectively include a source region, a channel region, and a drain region arranged along the first direction.

[0013] In some embodiments, it further includes: a conductive layer. The conductive layer is located on a side of the first active layer and the second active layer away from the word line along the second direction. The conductive layer is electrically connected to the channel region. The conductive layer extends along the third direction and is electrically connected to the substrate.

[0014] In some embodiments, the substrate includes an N-type doped single-crystalline silicon substrate or a P-type doped single-crystalline silicon substrate.

[0015] In some embodiments, it further includes: a first isolation layer located on a side of the word line away from the bit line along the first direction. The first isolation layer extends along the third direction. The first isolation layer includes a first isolation main body portion and a first isolation protruding portion. The first isolation protruding portion protrudes from the first isolation main body portion along the first direction and the second direction respectively.

[0016] In some embodiments, it further includes: a second isolation layer. A part of the second isolation layer is located between the conductive layer and a part of the channel region.

[0017] In some embodiments, the word line includes a first main body portion and a first extension portion. The first extension portion protrudes from the first main body portion along the first direction and the second direction respectively.

[0018] In some embodiments, along the third direction, the width of the first extension portion between adjacent channel regions along the second direction is D3, wherein D2 > D3 > D1.

[0019] In some embodiments, an insulating layer is provided between the word line and the substrate.

[0020] In some embodiments, along the first direction, the width of the conductive layer is smaller than the width of the word line.

[0021] On the other hand, an embodiment of the present disclosure further provides a semiconductor memory, which includes the semiconductor structure as described in any one of the above, and a plurality of the semiconductor structures are arranged in an array and stacked along the second direction and the third direction. Along the second direction, the bit lines of adjacent semiconductor structures in the same layer are electrically connected to each other. Along the third direction, the word lines of a plurality of semiconductor structures stacked in the same column are electrically connected to each other.

[0022] On the other hand, an embodiment of the present disclosure further provides a method for forming a semiconductor structure, including: providing a substrate;

[0023] Forming a bit line on the substrate, and the bit line extends along the second direction;

[0024] Forming an active layer on the substrate, and the active layer includes a source region, a channel region, and a drain region arranged along the first direction;

[0025] Forming a word line on the substrate, and the word line extends along the third direction and is directly opposite to a part of the side wall of the active layer extending along the third direction. The first direction, the second direction, and the third direction intersect pairwise;

[0026] Forming a capacitor structure on the substrate, and the capacitor structure is located on a side of the active layer away from the bit line along the first direction, and the capacitor structure is electrically connected to the drain region of the active layer.

[0027] Wherein, the channel region includes a first end and a second end opposite to each other along the first direction. Along the second direction, the width of the first end is D1, the width of the second end is D2, and D2 > D1.

[0028] In some embodiments, it further includes: forming a conductive layer on the substrate, the conductive layer is electrically connected to the channel region, the conductive layer extends along the third direction, and is electrically connected to the substrate.

[0029] The technical solutions provided by the embodiments of the present disclosure have at least the following advantages: The semiconductor structure includes: a substrate, a bit line located on the substrate, the bit line extending along a second direction; an active layer located on one side of the bit line along a first direction, the active layer including a first active layer, a second active layer, and a third active layer, one side of the third active layer along the first direction being electrically connected to the bit line, and the first active layer and the second active layer each including a source region, a channel region, and a drain region arranged along the first direction; a word line extending along a third direction and facing a part of the side wall of the active layer extending along the third direction; a capacitor structure electrically connected to the drain region of the active layer; wherein, the channel region includes a first end and a second end opposite to each other along the first direction, along the second direction, the width of the first end is D1, the width of the second end is D2, and D2 > D1. The embodiments of the present disclosure can reduce the gate-induced drain leakage current (GIDL), help reduce the leakage of the capacitor terminal, and improve the electrical performance of the semiconductor structure. Description of the Drawings

[0030] One or more embodiments are exemplarily illustrated by the pictures in the corresponding drawings. These exemplary illustrations do not limit the embodiments. Unless otherwise stated, the figures in the drawings do not constitute a proportional limitation; in order to more clearly illustrate the technical solutions in the embodiments of the present disclosure or the prior art, the following will briefly introduce the drawings required to be used in the embodiments. Obviously, the following-described drawings are only some embodiments of the present disclosure. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0031] Figure 1 It is a schematic plan view of a semiconductor structure provided by an embodiment of the present disclosure;

[0032] Figure 2 It is a schematic perspective view of a semiconductor structure provided by an embodiment of the present disclosure;

[0033] Figure 3 It is a schematic plan view of an active layer of a semiconductor structure provided by an embodiment of the present disclosure;

[0034] Figure 4 It is a schematic perspective view of a first isolation structure in a semiconductor structure provided by an embodiment of the present disclosure;

[0035] Figure 5 It is a schematic perspective view of a word line in a semiconductor structure provided by an embodiment of the present disclosure;

[0036] Figure 6 It is a schematic perspective view of a semiconductor memory provided by an embodiment of the present disclosure;

[0037] Figures 7 - 26Partial schematic diagrams corresponding to the steps of a method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure.

[0038] Description of reference numerals:

[0039] 110: Bit line; 120: Word line; 121: First main body portion; 122: First extension portion; 130: Capacitor structure; 140: Conductive layer; 150: First isolation layer; 1501: First isolation main body portion; 1502: First isolation protrusion portion; 160: Second isolation layer; 170: Gate oxide layer; 180: Active layer; 181: First active layer; 182: Second active layer; 183: Third active layer; 181-1 / 182-1: Channel region; 181-2 / 182-2: Source region; 181-3 / 182-3: Drain region; 201: Semiconductor substrate; 202: First semiconductor layer; 203: Second semiconductor layer; 200: Stacked structure; 204: First trench isolation structure; 205: Second trench isolation structure; 2041: Dielectric layer; 206: First groove; 207: Lateral groove; 208: Support layer; 2081: Main body portion; 2082: Protrusion portion; 209: Second groove; 210: Third groove; 211: Fourth groove; 212: Opening; 213: Fifth groove; 300: Initial stacked structure; 301: First part; 302: Second part; 400: Second stacked structure; 401: First stacked portion; 402: Second stacked portion. Detailed implementation manners

[0040] The technical solutions of the present disclosure will be further elaborated in detail below in conjunction with the drawings and embodiments. Although the exemplary implementation methods of the present disclosure are shown in the drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the implementation manners described herein. On the contrary, these implementation manners are provided to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0041] In the following paragraphs, the present disclosure will be described more specifically by way of example with reference to the drawings. The advantages and features of the present disclosure will be clearer according to the following description and claims. It should be noted that the drawings are all in a very simplified form and use non-precise scales, only for the purpose of conveniently and clearly assisting in explaining the purpose of the embodiments of the present disclosure.

[0042] It can be understood that the meanings of "on...", "above...", and "over..." in the present disclosure should be interpreted in the broadest manner, so that "on..." not only means "on" something without any intermediate features or layers (i.e., directly on something), but also includes the meaning of having intermediate features or layers "on" something.

[0043] In the embodiments of the present disclosure, terms such as "first", "second", "third", etc. are used to distinguish similar objects and do not necessarily describe a specific order or sequence.

[0044] In the embodiments of the present disclosure, the term "layer" refers to a portion of a material that includes a region having a thickness. The layer may extend over the entirety of a structure below or above, or may have a scope that is less than the scope of the structure below or above. Additionally, the layer may be a region of a homogeneous or heterogeneous continuous structure having a thickness less than the thickness of the continuous structure. For example, the layer may be located between the top and bottom surfaces of the continuous structure, or the layer may be between any horizontal planes at the top and bottom surfaces of the continuous structure. The layer may extend horizontally, vertically, and / or along an inclined surface. The layer may include a plurality of sub-layers.

[0045] It should be noted that the technical solutions described in the embodiments of the present disclosure can be arbitrarily combined without conflict.

[0046] As can be seen from the background art, in the current stacked structure, due to the isolation effect of the insulating layer, accumulated charges are likely to exist in the stacked semiconductor channels. Therefore, the electrical performance of three-dimensional semiconductor devices needs to be improved.

[0047] The embodiments of the present disclosure provide a semiconductor structure and a method for forming the same. In the semiconductor structure, the active layer, the bit line, and the word line extend in different directions, and the bit line and the capacitor structure are respectively located at both ends of the active layer along the first direction, which is beneficial to forming a 3D stacked semiconductor structure. Additionally, the active layer includes a source-drain region and a channel region, and a conductive layer is formed on one side of the channel region and is electrically connected to the channel region. The conductive layer extends in a direction perpendicular to the surface of the substrate and is electrically connected to the substrate, and the substrate is a doped semiconductor substrate and is grounded. Since the channel region in the active layer can be electrically connected to the substrate through the conductive layer, the accumulated charges in the channel region can be released into the substrate through the conductive layer, thereby solving the floating body effect problem existing in the three-dimensional semiconductor structure and improving the performance of the semiconductor structure. Furthermore, the channel region includes a first end and a second end located at opposite ends in the first direction, the first end is connected to the drain, the second end is connected to the source, the source and the drain are respectively connected to the bit line and the capacitor structure, and along the second direction, the width of the first end is less than the width of the second end, so that it is easy for the channel region to achieve full inversion at the first end. On the one hand, the accumulation of charges can be reduced. On the other hand, through the fully inverted channel, the gate-induced drain leakage current (GIDL) can be reduced. Additionally, by reducing the thickness and width of the drain, the overlapping area between the drain and the lower electrode of the capacitor can be reduced, which helps to eliminate or improve the tunneling effect (T-BTBT), helps to reduce the leakage of the capacitor terminal, and improves the electrical performance of the semiconductor structure.

[0048] The following will elaborate on the embodiments of the present disclosure in conjunction with the accompanying drawings. However, those of ordinary skill in the art can understand that in the embodiments of the present disclosure, many technical details are presented to help readers better understand the embodiments. However, even without these technical details and various changes and modifications based on the following embodiments, the technical solutions required to be protected by the embodiments of the present disclosure can still be achieved.

[0049] An embodiment of the present disclosure provides a semiconductor structure. The following will elaborate on the semiconductor structure provided by an embodiment of the present disclosure in conjunction with the accompanying drawings. Figure 1 is a top view of the semiconductor structure provided by an embodiment of the present disclosure, Figure 2 is a three-dimensional structure diagram of the semiconductor structure provided by an embodiment of the present disclosure, Figure 3 is a top view of the active layer of the semiconductor structure provided by an embodiment of the present disclosure, Figure 4 is a three-dimensional structure diagram of the first isolation layer in the semiconductor structure provided by an embodiment of the present disclosure, Figure 5 is a three-dimensional structure diagram of the word line and a top view of the first extension in the semiconductor structure provided by an embodiment of the present disclosure.

[0050] Referring to Figures 1 - 3 , the semiconductor structure includes: a first region I and a second region II. The first region I is a transistor region, and the second region II is a capacitor region. In the transistor region, it includes a bit line 110 extending along the second direction Y, an active layer 180 extending along the first direction X and the second direction Y respectively, a word line 120 extending along the third direction, and a conductive layer 140. The conductive layer 140 extends along the third direction Z and is electrically connected to a substrate (not shown). The first direction X, the second direction Y, and the third direction Z intersect pairwise, where the plane determined by the first direction X and the second direction Y is parallel to the surface of the substrate. In some embodiments, the first direction X, the second direction Y, and the third direction Z may be perpendicular to each other pairwise. In practical applications, it is sufficient that the angle between any two of the first direction X, the second direction Y, and the third direction Z is not 0° or 180°. For ease of description, the following will elaborate with the example that the first direction X, the second direction Y, and the third direction Z are perpendicular to each other pairwise. As Figure 1As shown, the semiconductor structure further includes: a gate oxide layer 170 located between the word line 120 and the active layer 180 and between the word line 120 and the substrate. A first isolation layer 150 is located at one end of the word line 120 away from the bit line 110 along the first direction X, and the first isolation layer 150 extends along the third direction Z and is connected to the substrate. Along the first direction X, the first isolation layer 150 straddles the first region I and the second region II. A second isolation layer 160 straddles the first region I and the second region II along the first direction X, and a part of the second isolation layer is located between the conductive layer 140 and the active layer 180. In some embodiments, the thickness of the second isolation layer 160 along the third direction is the same as the thickness of the active layer along the third direction. The second region II includes a capacitor region, and the capacitor region includes a capacitor structure 130, which includes a capacitor lower electrode, a capacitor dielectric layer, and a capacitor upper electrode. The capacitor lower electrode is in contact with the first isolation layer 150 and the second isolation layer 160 respectively, and is electrically connected to one end of the active layer 180 away from the bit line 110 along the first direction X.

[0051] It can be understood that one side of the active layer 180 is in contact and connection with the conductive layer 140. The conductive layer 140 extends along the third direction Z and is electrically connected to the substrate. The substrate is a doped semiconductor structure and is grounded, so that the active layer 180 can be grounded through the conductive layer 140. In this way, it is beneficial to release the accumulated charges in the active layer to the ground terminal through the conductive layer 140, thereby improving the floating body effect and enhancing the electrical performance of the semiconductor structure.

[0052] In some embodiments, the width of the conductive layer 140 along the first direction X is smaller than the width of the word line 120 along the first direction. By setting the width of the conductive layer 140 to be smaller than the width of the word line 120, the facing area between the conductive layer 140 and the word line 120 can be reduced, and the parasitic capacitance between the two can be decreased.

[0053] In some embodiments, refer to Figure 1 and Figure 3, the active layer 180 includes a first active layer 181 and a second active layer 182 extending along a first direction X, and a third active layer 183 extending along a second direction Y. Opposite ends of the third active layer 183 along the second direction Y are respectively in contact with and electrically connected to one end of the first active layer 181 and the second active layer 182 along the first direction X. In some embodiments, the first active layer 181, the second active layer 181, and the third active layer 183 are an integral structure. One end of the third active layer 183 away from the first active layer 181 and the second active layer 182 along the first direction X is electrically connected to the bit line 110. In some embodiments, the active layer 183 is in direct contact with and electrically connected to the bit line 110. In some embodiments, a metal silicide filling layer is further provided between the active layer 183 and the bit line 110, and the contact resistance between the active layer 183 and the bit line 110 is reduced by the metal silicide, improving the electrical performance of the semiconductor structure. In addition, in the embodiments of the present disclosure, the active layer 183 extends along the second direction Y and forms an integral structure with the source electrode of the transistor, increasing the contact area between the source electrode and the bit line, reducing the contact resistance between the source electrode and the bit line, and further improving the electrical performance of the semiconductor structure.

[0054] Reference Figure 1 and Figure 3 , the first active layer 181 and the second active layer 182 extend along the first direction X. The first active layer 181 and the second active layer 182 respectively include a channel region 181-1 / 182-2, a source region 181-2 / 182-2, and a drain region 181-3 / 182-3. The source region and the drain region are located on both sides of the channel region along the first direction X. In some embodiments, the source region and the drain region are active layers of a first doping type, and the channel region is an active layer of a second doping type. In some embodiments, the doping types of the source region, the drain region, and the channel region are the same, thereby forming a junctionless transistor structure. As Figure 3 shown, the channel regions 181-1 / 182-2 respectively include a second end close to the source region 181-2 / 182-2 and a first end close to the drain region 181-3 / 182-3 along the first direction X. Among them, along the second direction, the width of the first end is D1, and the width of the second end is D2, where D2 > D1. In some embodiments, 2D1 <= D2, that is, the width of D1 is less than or equal to half of the width of D2. In the embodiments of the present disclosure, the thickness of the channel region near the drain end is set to be thinner, so that when an activation voltage is applied to the word line 120, the channel region on the side close to the drain region can achieve a fully depleted structure, reducing the accumulation of parasitic charges. At the same time, since a fully depleted structure can be achieved, the leakage current of the capacitor structure connected to the drain region can be effectively reduced, and the time for the capacitor structure to store charges can be increased, thereby improving the overall performance of the semiconductor structure.

[0055] Reference Figure 1 andFigure 4 , the first isolation layer 150 includes silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. In the embodiments of the present disclosure, the first isolation layer 150 is made of silicon nitride material. Along the first direction X, one end of the first isolation layer 150 is in contact connection with the word line 120, and the other end is in contact connection with the capacitor structure 130. Among them, the first isolation layer 150 spans the first region I and the second region II in the first direction X. In some embodiments, the first isolation layer 150 is only located in the first region I along the first direction X. As Figure 4 shown in the three-dimensional structure schematic diagram of the first isolation layer 150, the first isolation layer 150 extends along the third direction Z. The first isolation layer 150 includes a first isolation main body portion 1501 and a first isolation protruding portion 1502. The first isolation protruding portion 1502 protrudes from the first isolation main body portion 1501 along one side of the first direction X and opposite sides of the second direction Y respectively. Along the other side of the first direction X, the first isolation main body portion 1501 and the first isolation protruding portion 1502 are aligned along the third direction Z. Along the third direction Z, an active layer 180 and / or a capacitor structure 130 are embedded between adjacent first isolation protruding portions 1502, thereby forming an effective supporting effect on the active layer and / or the capacitor structure and improving the stability during the manufacturing process.

[0056] Reference Figure 1 and Figure 2 , the second isolation layer 160 includes silicon oxide, silicon nitride, a low-k dielectric material, or a combination thereof. In the embodiments of the present disclosure, the second isolation layer 160 is made of silicon oxide material. The second isolation layer 160 spans the first region I and the second region II in the first direction X. In some embodiments, the second isolation layer 160 is only located in the first region I along the first direction X. Part of the second isolation layer 160 is located between the conductive layer 140 and the active layer 180, and the projection of the contact surface between the second isolation layer 160 and the active layer 180 on the plane determined by the first direction X and the second direction Y is in an arc shape. And the width of the channel region 181-1 / 182-2 in the active layer 180 along the second direction Y gradually decreases in the first direction X and reaches the minimum value D1 at the second end. That is to say, the width of the second isolation layer 160 in the first region I along the second direction Y gradually increases in the extending direction of the first direction X. By providing the second isolation layer 160, an isolation structure is formed between the conductive layer 140 and the word line 120, and between the conductive layer 140 and the capacitor structure 130. On the one hand, insulation between the conductive layer and the capacitor structure can be achieved, and on the other hand, the parasitic capacitance can be effectively reduced, improving the overall performance of the semiconductor structure.

[0057] Reference Figure 1 , Figure 2 and Figure 5, the word line 120 may include a conductive material, for example, doped Si, doped Ge, TiN, TaN, W, Ti, Ta, Cu, Al, Ag, Au, WSi, CoSi, TiSi, or a combination thereof. As Figure 5 (a) shows a schematic three-dimensional structure diagram of the word line 120. The word line 120 extends along the third direction Z, and an insulating layer is disposed between the word line 120 and the substrate, so that the word line 120 is electrically insulated from the substrate. The word line 120 includes: a first main body portion 121 and a first extension portion 122. The first extension portion 122 protrudes from the first main body portion 121 along one side of the first direction X and opposite sides of the second direction Y. On the other side along the first direction, the first main body portion 121 and the first extension portion 122 are aligned along the third direction Z. In some embodiments, the portions of the first main body portion 121 and the first extension portion 122 that are aligned along the third direction Z are in contact with the portions of the first isolation main body portion 1501 and the first isolation protrusion portion 1502 that are aligned along the third direction Z. Along the third direction Z, the channel region of the active layer 180 is embedded between adjacent first extension portions 122, so that the first main body portion 121 and the first extension portion 122 are respectively adjacent to the channel region, thereby forming a triple-gate transistor structure, further increasing the width of the channel region of the transistor and improving the control ability of the gate over the channel region. In addition, the active layer 180 is embedded between the first extension portions 122, which also serves to stabilize the overall structure and improve the stability of the manufacturing process. In some embodiments, as Figure 5 (b) shows, along the third direction Z, the width D3 of the first extension portion 122 located between adjacent channel regions along the second direction Y is less than the maximum width D2 of the channel region along the second direction Y and greater than the minimum width D1. In the embodiments of the present disclosure, the width D3 of the first extension portion 122 along the second direction Y is greater than the minimum width D1 of the channel region along the second direction Y, so that the three sides of the channel region near the drain region are completely surrounded by the word line structure, strengthening the channel control of the word line structure over this region, more easily forming a depletion layer structure, reducing the GIDL effect of the transistor, reducing the leakage current of the capacitor, and improving the electrical performance of the semiconductor structure.

[0058] In some embodiments, the material of the substrate may be single-crystalline silicon, polycrystalline silicon, amorphous silicon, germanium, silicon carbide, silicon germanide, Germanium on Insulator (abbreviated as GOI), or Silicon on Insulator (abbreviated as SOI), etc. In the embodiments of the present disclosure, the material of the substrate includes an N-type or P-type doped single-crystalline silicon material.

[0059] In some embodiments, the material of the bit line 110 may include a conductive material, such as doped Si, doped Ge, titanium nitride (TiN), tantalum nitride (TaN), tungsten (W), titanium (Ti), tantalum (Ta), copper (Cu), aluminum (Al), silver (Ag), gold (Au), tungsten silicide (WSi), cobalt silicide (CoSi), titanium silicide (TiSi), or a combination thereof.

[0060] In some embodiments, the material of the gate oxide layer 170 may include a high-k dielectric material, silicon dioxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), or a combination thereof.

[0061] In some embodiments, the material of the conductive layer 140 may include any one of tungsten, tantalum, molybdenum, titanium nitride, or tantalum nitride. In some other embodiments, the material of the conductive layer 140 is doped polysilicon.

[0062] In summary, in the semiconductor structure, the extending directions of the active layer, the bit line, and the word line are different, and the bit line and the capacitor structure are respectively located at two ends of the semiconductor channel, which is conducive to forming a 3D stacked semiconductor structure. In addition, the active layer includes a source-drain region and a channel region, and a conductive layer is formed on one side of the channel region and is electrically connected to the channel region. The conductive layer extends in a direction perpendicular to the surface of the substrate and is electrically connected to the substrate, which is a doped semiconductor substrate and is grounded. Since the channel region in the active layer can be electrically connected to the substrate through the conductive layer, the accumulated charges in the channel region can be released to the substrate through the conductive layer, thereby reducing the floating body effect problem existing in the three-dimensional semiconductor structure and improving the performance of the semiconductor structure. In addition, the channel region includes a first end and a second end located at opposite ends in a first direction, the first end is connected to the drain, the second end is connected to the source, the source and the drain are respectively connected to the bit line and the capacitor structure, and along a second direction, the width of the first end is smaller than the width of the second end, so that it is easy to achieve full inversion at the first end of the channel region. On the one hand, the accumulation of charges can be reduced. On the other hand, through the fully inverted channel, the gate-induced drain leakage current (GIDL) can be reduced. In addition, by reducing the thickness and width of the drain, the overlapping area between the drain and the lower electrode of the capacitor can be reduced, which helps to eliminate or improve the tunneling effect (T-BTBT), helps to reduce the leakage of the capacitor end, and improves the electrical performance of the semiconductor structure.

[0063] In some other embodiments of the present disclosure, a semiconductor memory is further disclosed, which includes a plurality of semiconductor structures as shown above, and the plurality of semiconductor structures are arranged in an array and stacked along the second direction Y and the third direction Z. Along the second direction Y, the bit lines of adjacent semiconductor structures in the same layer are electrically connected to each other. Along the third direction Z, the conductive layers of the stacked plurality of semiconductor structures in the same column are electrically connected to each other, and the word lines of the plurality of semiconductor structures are electrically connected to each other. The first isolation layer 150 extends through the plurality of semiconductor structures along the third direction and is formed as an integral structure.

[0064] Another embodiment of the present disclosure further provides a manufacturing method of a semiconductor structure for preparing the semiconductor structure provided in the foregoing embodiment. The following will be combined with Figures 7 - 26 to detail the manufacturing method of the semiconductor structure provided in another embodiment of the present disclosure. Figures 7 - 26 FIGS. are partial schematic diagrams corresponding to the steps of the manufacturing method of the semiconductor structure provided in another embodiment of the present disclosure.

[0065] It should be noted that the same or corresponding parts as those in the foregoing embodiment will not be described herein again. Referring to Figures 7 - 26 , the manufacturing method of the semiconductor structure includes: providing a substrate;

[0066] forming bit lines on the substrate, and the bit lines extend along the second direction;

[0067] forming an active layer on the substrate, and the active layer includes a source region, a channel region, and a drain region arranged along the first direction;

[0068] forming word lines on the substrate, the word lines extend along the third direction and are directly opposite to a part of the side walls of the active layer extending along the third direction,

[0069] the first direction, the second direction, and the third direction intersect pairwise;

[0070] forming a capacitor structure on the substrate, the capacitor structure is located on one side of the active layer away from the bit lines along the first direction, and the capacitor structure is electrically connected to the drain region of the active layer

[0071] wherein, the channel region includes a first end and a second end opposite to each other along the first direction. Along the second direction, the width of the first end is D1, and the width of the second end is D2, and D2 > D1.

[0072] In some embodiments, forming the semiconductor structure includes the following steps:

[0073] providing a substrate, and the step of forming the substrate includes the following steps, such as Figure 7As shown, a substrate is provided, and the substrate is doped and annealed to form a substrate 201. Among them, the substrate material includes single-crystalline silicon, polycrystalline silicon, amorphous silicon, germanium, silicon carbide, silicon germanide, Germanium on Insulator (GOI for short), or Silicon on Insulator (SOI for short), etc. In the embodiments of the present disclosure, the substrate material is selected as single-crystalline silicon material. By performing N-type or P-type doping treatment on the single-crystalline silicon material and annealing treatment, an N-type or P-type substrate 201 is formed. The N-type element can be a Group V element such as phosphorus (P), bismuth (Bi), antimony (Sb), or arsenic (As). The P-type element can be a Group III element such as boron (B), aluminum (Al), gallium (Ga), or indium (In). In some embodiments, only the upper surface of the substrate can be doped to form an N-type doping layer or a P-type doping layer on the substrate surface, or the entire substrate can be doped to form an N-type substrate 201 or a P-type substrate 201. In the embodiments of the present disclosure, the formation of an N-type substrate is taken as an example for illustration.

[0074] Forming an active layer on the substrate, the active layer includes a first active layer, a second active layer, and a third active layer. The first active layer and the second active layer extend in a first direction, and the third active layer extends in the second direction. The steps of the first active layer and the second active layer respectively including a source region, a channel region, and a drain region arranged in the first direction include the following steps, as Figure 8As shown, a multi-layer stacked structure 200 stacked along the third direction Z is formed on a substrate 201. Along the third direction, the stacked structure 200 includes a first semiconductor layer 202 and a second semiconductor layer 203 stacked in sequence. The first semiconductor layer 202 may be formed of or include at least one of, for example, silicon germanium, silicon oxide, silicon nitride, and silicon oxynitride. In some embodiments, the first semiconductor layer 202 may be formed by an epitaxial growth method and may be, for example, a silicon germanium layer. The second semiconductor layer 203 may be formed of or include at least one of, for example, silicon, germanium, silicon germanium, and indium gallium zinc oxide (IGZO). In some embodiments, the second semiconductor layer 203 may be formed of or include the same semiconductor material as the substrate 201. For example, the second semiconductor layer 203 may be formed by an epitaxial growth method and may be a single crystal silicon layer. In the embodiments of the present disclosure, taking the epitaxially grown germanium silicon layer and silicon layer as examples for illustration, the formed stacked structure has a crystal structure similar to a superlattice. Since the lattice structures of the germanium silicon layer and the silicon layer are the same, a stacked structure can be formed by epitaxial growth, reducing the generation of defects in the stacked structure and being beneficial to improving the electrical performance of the formed semiconductor structure. The embodiments of the present disclosure illustrate by taking the formation of a five-layer stacked structure as an example. In actual processes, this is not limited thereto, and the specific number of stacked layers can be selected according to actual stacking requirements.

[0075] As Figure 9 shown, a mask layer (not shown) is formed above the stacked structure 200, and the stacked structure 200 is patterned through the mask layer to form a groove structure in the stacked structure 200. The groove structure exposes a partial surface of the substrate 201. The patterning process includes dry etching, wet etching, or a combination of both. An insulating dielectric layer is filled in the groove structure to form a first trench isolation structure 204 and a second trench isolation structure 205, and the remaining stacked structure 200 forms an initial stacked structure 300. Among them, the material of the filled insulating dielectric layer includes silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), or a combination thereof. In the embodiments of the present disclosure, the material of the insulating dielectric layer is selected as silicon oxide material. The formed initial stacked structure 300 is the remaining stacked structure after etching the stacked structure 200, and it includes a plurality of first portions 301 extending along the first direction X and spaced apart along the second direction Y, and a second portion 302 extending along the second direction Y. Along the second direction Y, a plurality of first trench isolation structures 204 are provided between adjacent first portions 301. The first trench isolation structure 204 extends along the first direction X, and the second trench isolation structure 205 is provided on a side of the second portion 302 away from the first portion 301 along the first direction X. The second trench isolation structure 205 extends along the second direction Y.

[0076] As Figure 10As shown, an etching process is performed on the first part 301 of the initial stacked structure 300 through a mask structure (not shown), and a first groove 206 is formed at one end close to the second part 302. The etching process includes a dry etching or wet etching process. The first groove 206 extends along the third direction Z, penetrates the initial stacked structure 300, and exposes a partial surface of the partial substrate 201. In some embodiments, an over-etching process may be performed on the substrate 201 to form a recessed structure corresponding to the first groove 206 in the substrate 201. In the embodiments of the present disclosure, the example where the first groove 206 exposes the upper surface of the substrate 201 and the projection on the surface of the substrate 201 is rectangular is used for illustration. In some embodiments, the projection may be circular, polygonal or other irregular shapes, and no specific limitation is made thereto. The first semiconductor layer 202 in the initial stacked structure 300 is laterally etched through the first groove 206 to form a lateral groove 207 surrounding the first groove 206. Figure 11 is Figure 10 a cross-sectional view of the structure shown along the part A-A', as Figure 11 As shown, the first semiconductor layer 202 is laterally etched through the first groove 206 exposing the surface of the substrate 201. In the embodiments of the present disclosure, an isotropic wet etching process may be used to wet-etch the first semiconductor layer 202. Along the second direction Y, with the first trench isolation structure 204 as an etching stop layer, a lateral groove 207 is etched and formed. In the embodiments of the present disclosure, the first semiconductor layer 202 and the second semiconductor layer 203 are respectively formed of different materials. Therefore, a wet etching solution having a high etching selectivity (such as greater than 10:1) for the first semiconductor layer and the second semiconductor layer is selected for etching. While partially removing the first semiconductor layer, the second semiconductor layer is not removed or a small amount of the second semiconductor layer is removed.

[0077] The step of forming a word line on the substrate, where the word line extends along the third direction and is opposite to a partial sidewall of the active layer extending along the third direction, includes the following steps, as Figures 12 - 14 As shown, a support layer 208 is filled in the formed first groove 206 and the lateral groove 207. The support layer 208 is deposited through processes such as Chemical Vapor Deposition (abbreviated as CVD), Physical Vapor Deposition (abbreviated as PVD), or Atomic Layer Deposition (abbreviated as ALD). The material of the deposited support layer 208 includes silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), or a combination thereof. In the embodiments of the present disclosure, the material of the support layer 208 is selected as a silicon nitride material. As Figure 13As shown, the deposited support layer 208 fills the first groove 206 and the lateral groove 207. Along the first direction X, the two ends of the support layer 208 are respectively in contact with the first semiconductor layer 202 and the second semiconductor layer 203. Along the second direction Y, the two ends of the support layer 208 are respectively in contact with the first trench isolation structure 204 and the second semiconductor layer 203. Figure 14 It is a three-dimensional structure diagram of the support layer 208. As Figure 14 shown, the support layer 208 includes a main body portion 2081 located in the first groove 206 and a protruding portion 2082 located in the lateral groove 207.

[0078] As Figure 15 shown, using the first trench isolation structure 204, the second trench isolation structure 205 and the support layer 208 as the support structure, the first semiconductor layer 202 in the initial stacked structure 300 is laterally etched, and the first semiconductor layer 202 is completely removed. A dielectric layer 2041 is filled in the gap after removing the first semiconductor layer 202 to form a second stacked structure 400. The second stacked structure 400 includes a plurality of first stacked portions 401 extending along the first direction X and spaced apart along the second direction Y and a second stacked portion 402 extending along the second direction Y. The first stacked portion 401 and the second stacked portion 402 include alternately stacked dielectric layers 2041 and second semiconductor layers 203. The material of the dielectric layer 2041 includes silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), low-k dielectric material or a combination thereof. In the embodiments of the present disclosure, the material of the dielectric layer 2041 is selected as silicon oxide material. In the embodiments of the present disclosure, the support layer 208 includes a protruding portion 2082 that protrudes from the main body portion 2081 both along the first direction X and the second direction Y. The protruding portion 2082 protrudes between the second semiconductor layers 203 adjacent along the third direction, and has an effective supporting effect on the suspended second semiconductor layer 203 during the process of etching and removing the first semiconductor layer 202, thereby improving the stability during the manufacturing process.

[0079] As Figure 16 and Figure 17 shown, a dry or wet etching process is used to etch part of the support layer 208, remove part of the support layer 208 to form a second groove 209, and the remaining support layer forms a first isolation layer 150. Figure 17 It is Figure 16 a cross-sectional view of the structure along A-A', as Figure 17As shown, through an etching process, a part of the main body 2081 and a part of the protruding part 2082 near the second trench isolation structure 205 are removed, and the remaining part of the main body 2081 forms the first isolation main body 1501 of the first isolation layer 150, and the remaining part of the protruding part 2082 forms the first isolation protruding part 1502 of the first isolation layer 150. In some embodiments, one side of the remaining part of the main body 2081 and the remaining part of the protruding part 2082 along the first direction X is aligned in the third direction Z. As Figure 17 shown, the formed second groove 209 is formed in the first stack portion 401 and exposes a part of the surface of the substrate 201.

[0080] As Figure 18 and Figure 19 shown, a dielectric layer and a conductive layer are sequentially deposited in the second groove 209 through processes such as chemical vapor deposition, physical vapor deposition, or atomic layer deposition to form the gate oxide layer 170 and the word line 120 respectively. The material of the gate oxide layer 170 includes high-k dielectric materials, silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), or a combination thereof. In the embodiments of the present disclosure, the material of the gate oxide layer 170 is selected as silicon oxide material. In some embodiments, an atomic layer deposition process can be used to form a gate oxide layer with a uniform thickness. In some embodiments, an in-situ oxidation process can also be used to in-situ oxidize only the exposed surfaces of the second semiconductor layer and the substrate to form an oxide layer. The deposited material of the word line 120 includes conductive materials such as doped Si, doped Ge, TiN, TaN, W, Ti, Ta, Cu, Al, Ag, Au, WSi, CoSi, TiSi, or a combination thereof. Figure 19 is Figure 18 a cross-sectional view of the structure along A-A', as Figure 19 shown, the deposited gate oxide layer 170 covers the second semiconductor layer 203, the dielectric layer 2041, the substrate 201, and the exposed surface of the first isolation layer 150 located in the groove 209. A conductive layer is filled in the groove after depositing the gate oxide layer 170 to form the word line 120. Chemical mechanical polishing (CMP) treatment is performed on the deposited dielectric layer and conductive layer so that the upper surfaces of the formed gate oxide layer 170 and the word line 120 are flush with the upper surface of the topmost second semiconductor layer 203.

[0081] The step of forming a conductive layer on the substrate includes, as Figure 20 and Figure 21As shown, part of the first trench isolation structure 204 is etched to form a third groove 210 that extends along the second direction Y and exposes a partial surface of the substrate 201. Along the second direction Y, the third groove 210 also exposes the sidewalls of the second semiconductor layers 203 that are arranged at intervals along the second direction Y. Conductive material is filled in the third groove 210, and the filled conductive material is etched to form a plurality of conductive layers 140 that are arranged at intervals along the second direction Y. One sidewall of the conductive layer 140 is in contact with and electrically connected to the second semiconductor layer 2032. Along the third direction Z, the bottom of the conductive layer 140 is in contact with and electrically connected to the substrate 201. In some embodiments, after filling the conductive material in the third groove 210, there is no need to perform an etching process on the conductive material, such that adjacent second semiconductor layers along the second direction Y share the same conductive layer 140, and the conductive layer 140 extends along the third direction Z and is electrically connected to the upper surface of the substrate 201. In some embodiments, the filled conductive material includes a polysilicon material, and the doping type is the same as the doping type of the substrate.

[0082] As Figure 22 shown, a second etching is performed on part of the first trench isolation structure 204 to form a fourth groove 211 that extends along the second direction Y and exposes a partial surface of the substrate 201. The fourth groove 211 is located on a side of the conductive layer 140 away from the second trench isolation structure 205 along the first direction X. The fourth groove 211 also exposes a partial sidewall of the conductive layer 140, a partial sidewall of the second semiconductor layer 203, and a partial sidewall of the dielectric layer 2041. In some embodiments, the fourth groove 211 may not expose the substrate 201, and a part of the first isolation trench structure is reserved at the bottom of the fourth groove 211, and no specific limitation is made thereto. Lateral etching is performed on the second semiconductor layer 203 along the fourth groove 211 to form a groove structure (not shown) in the second semiconductor layer 203. The lateral etching process selects an isotropic wet etching process, and an insulating dielectric layer is filled in the formed concave structure to form a second isolation layer 160. The material of the second isolation layer 160 includes silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), a low-k dielectric material, or a combination thereof. In the embodiments of the present disclosure, the material of the second isolation layer 160 is selected as a silicon oxide material. While filling the concave structure to form the second isolation layer 160, the fourth groove 211 is filled to form a structure as Figure 23 shown, Figure 24 is Figure 23 a top view of the shown structure. In some embodiments, the concave structure and the fourth groove structure may be filled separately, and the material for filling the concave structure and the material for filling the fourth groove may be the same or different.

[0083] The steps of forming the bit line include the following steps, as Figure 25, the second trench isolation structure 205 is etched away to form an opening 212, and the opening 212 exposes the sidewall of the second stacked portion 402. The second semiconductor layer 203 in the second stacked portion 402 is etched laterally along the opening 212 to form a fifth groove 213. As Figure 26 shown, a conductive material layer is filled in the fifth groove 213 to form a bit line 110, and an insulating dielectric layer is filled in the opening 212 to form a second trench isolation structure 205. The conductive material layer filled in the fifth groove 213 includes a conductive material, such as doped Si, doped Ge, titanium nitride (TiN), tantalum nitride (TaN), tungsten (W), titanium (Ti), tantalum (Ta), copper (Cu), aluminum (Al), silver (Ag), gold (Au), tungsten silicide (WSi), cobalt silicide (CoSi), titanium silicide (TiSi), or a combination thereof. The material of the insulating dielectric layer includes silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), a low-k dielectric material, or a combination thereof. In the embodiments of the present disclosure, the material of the insulating dielectric layer is a silicon oxide material.

[0084] As Figure 26 shown, in the capacitor region II, the second conductive layer 203 in the first stacked portion 401 is removed to form a void structure. In the formed void structure, a capacitor lower electrode, a capacitor dielectric layer, and a capacitor upper electrode are deposited to form a capacitor structure 130. The capacitor lower electrode corresponds to and is electrically connected to the drain region of the active layer.

[0085] In summary, in the semiconductor structure formed by the manufacturing method provided in another embodiment of the present disclosure, the extending directions of the active layer, the bit line, and the word line are different, and the bit line and the capacitor structure are respectively located at both ends of the semiconductor channel, which is conducive to forming a 3D stacked semiconductor structure. In addition, the active layer includes a source-drain region and a channel region, and a conductive layer is formed on one side of the channel region and is electrically connected to the channel region. The conductive layer extends in a direction perpendicular to the surface of the substrate, and is electrically connected to the substrate, the substrate is a doped semiconductor substrate, and the semiconductor substrate is grounded. Since the channel region in the active layer can be electrically connected to the substrate through the conductive layer, the accumulated charges in the channel region can be released into the substrate through the conductive layer, thereby solving the problem of the floating body effect in the three-dimensional semiconductor structure and improving the performance of the semiconductor structure. In addition, the channel region includes a first end and a second end located at opposite ends in a first direction, the first end is connected to the drain, the second end is connected to the source, the source and the drain are respectively connected to the bit line and the capacitor structure, and along a second direction, the width of the first end is smaller than the width of the second end, so that it is easy to achieve full inversion at the first end of the channel region. On the one hand, the accumulation of charges can be reduced. On the other hand, through the fully inverted channel, the gate-induced drain leakage current (GIDL) can be reduced. In addition, by reducing the thickness and width of the drain, the overlapping area between the drain and the lower electrode of the capacitor can be reduced, which helps to eliminate or improve the tunneling effect (T-BTBT), helps to reduce the leakage at the capacitor end, and improves the electrical performance of the semiconductor structure.

[0086] The various semiconductor structures shown in this specific embodiment can be used in electronic devices with a storage function. The electronic device can be a terminal device, such as a mobile phone, a tablet computer, a smart bracelet, or it can also be a personal computer (PC), a server, a workstation, etc. The storage function in the electronic device can be realized by the following memories: dynamic random access memory (DRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), magnetic random access memory (MRAM), or resistive random access memory (RRAM).

[0087] The above is only a specific embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present disclosure can easily think of changes or substitutions, which should be covered by the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be subject to the protection scope of the claims.

Claims

1. A semiconductor structure, characterized in that, Comprising: A substrate; Bit lines, located on the substrate, and the bit lines extend along a second direction; An active layer, located on one side of the bit lines along a first direction, and the active layer includes a source region, a channel region, and a drain region arranged along the first direction; Word lines, extending along a third direction and facing the side walls of the part of the active layer extending along the third direction, and the first direction, the second direction, and the third direction intersect pairwise; A capacitive structure, located on the side of the active layer away from the bit lines along the first direction, and the capacitive structure is electrically connected to the drain region of the active layer; Wherein, the channel region includes a first end and a second end opposite to each other along the first direction. Along the second direction, the width of the first end is D1, the width of the second end is D2, and D2 > D1.

2. The semiconductor structure according to claim 1, wherein The active layer includes a first active layer, a second active layer, and a third active layer. The first active layer and the second active layer extend along the first direction, the third active layer extends along the second direction, one side of the third active layer along the first direction is electrically connected to the bit lines, and the first active layer and the second active layer respectively include a source region, a channel region, and a drain region arranged along the first direction.

3. The semiconductor structure according to claim 2, wherein, Further comprising: A conductive layer, located on the side of the first active layer and the second active layer away from the word lines along the second direction, the conductive layer is electrically connected to the channel region, the conductive layer extends along the third direction, and is electrically connected to the substrate.

4. The semiconductor structure according to any one of claims 1-3, characterized in that, The substrate includes an N-type doped single-crystalline silicon substrate or a P-type doped single-crystalline silicon substrate.

5. The semiconductor structure according to claim 1, wherein, Further comprising: A first isolation layer, located on the side of the word lines away from the bit lines along the first direction; The first isolation layer extends along the third direction, and the first isolation layer includes a first isolation main body portion and a first isolation protruding portion, and the first isolation protruding portion protrudes from the first isolation main body portion along the first direction and the second direction respectively.

6. The semiconductor structure according to claim 3, wherein, Further comprising: A second isolation layer, and part of the second isolation layer is located between the conductive layer and part of the channel region.

7. The semiconductor structure according to claim 1, wherein The word line includes a first main body portion and a first extension portion, and the first extension portion protrudes from the first main body portion along the first direction and the second direction respectively.

8. The semiconductor structure according to claim 7, wherein Along the third direction, the width of the first extension portion located between adjacent channel regions along the second direction is D3, wherein D2 > D3 > D1.

9. The semiconductor structure according to claim 1, wherein An insulating layer is provided between the word line and the substrate.

10. The semiconductor structure according to claim 3, characterized in that, Along the first direction, the width of the conductive layer is smaller than the width of the word line.

11. A three-dimensional semiconductor memory, characterized in that: Including a plurality of semiconductor structures according to any one of claims 1-10, and the plurality of semiconductor structures are arranged in an array and stacked along the second direction and the third direction. Along the second direction, the bit lines of adjacent semiconductor structures in the same layer are electrically connected to each other. Along the third direction, the word lines of a plurality of semiconductor structures stacked in the same column are electrically connected to each other.

12. A method for forming a semiconductor structure, characterized in that, Comprising: Providing a substrate; Forming bit lines on the substrate, and the bit lines extend along a second direction; An active layer is formed on the substrate, and the active layer includes a source region, a channel region, and a drain region arranged in a first direction; a word line is formed on the substrate, the word line extends in a third direction and is opposite to a part of the side wall of the active layer extending in the third direction, and the first direction, the second direction, and the third direction intersect pairwise. A capacitor structure is formed on the substrate, the capacitor structure is located on a side of the active layer away from the bit line along the first direction, and the capacitor structure is electrically connected to the drain region of the active layer. Wherein, the channel region includes a first end and a second end opposite to each other along the first direction. Along the second direction, the width of the first end is D1, the width of the second end is D2, and D2 > D1.

13. The method for forming a semiconductor structure according to claim 12, wherein, Further included: A conductive layer is formed on the substrate, the conductive layer is electrically connected to the channel region, and the conductive layer extends in the third direction and is electrically connected to the substrate.

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