Semiconductor device and preparation method thereof, and storage system

Abstract

The invention discloses a semiconductor device, a preparation method thereof and a storage system. The semiconductor device comprises a stacking structure which comprises interlayer dielectric layers and gate layers which are alternately stacked along a first direction; the grid line isolation structure extends along a second direction and penetrates through the stacking structure along the first direction; wherein the stacked structure comprises a core region and a connecting region located on at least one side of the core region in the second direction, and in the third direction, the size of the portion, located in the core region, of the gate layer is larger than the size of the portion, located in the connecting region, of the gate layer; in the first direction, the thickness of the portion, close to the grid line isolation structure, of the interlayer dielectric layer is smaller than the thickness of the portion, away from the grid line isolation structure, of the interlayer dielectric layer, and the first direction, the second direction and the third direction intersect in pairs.

Description

Technical Field

[0001] Embodiments of the present application relate to the field of semiconductor technology, and particularly to semiconductor devices, methods for manufacturing the same, and storage systems. Background Art

[0002] As the feature size of semiconductor manufacturing processes becomes smaller and smaller, the storage density of semiconductor devices becomes higher and higher. Taking three-dimensional memories as an example, three-dimensional memories generally include a stacked structure and a channel structure penetrating the stacked structure. The stacked structure includes alternately stacked interlayer dielectric layers and gate layers. The stacked structure has a core region and a connection region, and the widths of the gate layers in the core region and the connection region are different.

[0003] Currently, how to further improve the performance of semiconductor devices is one of the technical problems that those skilled in the art urgently need to solve. Summary of the Invention

[0004] The semiconductor devices, methods for manufacturing the same, and storage systems provided by the embodiments of the present application can solve or partially solve the above-mentioned deficiencies in the prior art or other deficiencies in the prior art.

[0005] According to a semiconductor device provided in the first aspect of the present application, it includes:

[0006] A stacked structure including alternately stacked interlayer dielectric layers and gate layers along a first direction; and

[0007] A gate line isolation structure extending along a second direction and penetrating the stacked structure along the first direction;

[0008] Wherein, the stacked structure includes a core region and a connection region located on at least one side of the core region along the second direction. In a third direction, the size of the gate layer in the core region is larger than that in the connection region. In the first direction, the thickness of the interlayer dielectric layer close to the gate line isolation structure is smaller than that far from the gate line isolation structure. The first direction, the second direction, and the third direction intersect pairwise.

[0009] According to a method for manufacturing a semiconductor device provided in the second aspect of the present application, it includes:

[0010] Forming a gate line gap extending along the second direction and penetrating a stacked structure along the first direction, where the stacked structure includes alternately stacked interlayer dielectric layers and interlayer sacrificial layers along the first direction;

[0011] Removing part of the interlayer sacrificial layer through the gate line gap to form a groove recessed along the third direction between two adjacent interlayer dielectric layers;

[0012] Processing the portion of the interlayer dielectric layer protruding from the interlayer sacrificial layer such that the thickness of the interlayer dielectric layer closer to the gate line gap in the first direction is less than its thickness farther from the gate line gap; and

[0013] Filling a first sacrificial material into the groove;

[0014] Wherein, the first direction, the second direction, and the third direction intersect pairwise.

[0015] According to the storage system provided in the third aspect of the present application, the storage system includes a controller and the semiconductor device described above, the controller is coupled to the semiconductor device and is configured to control the semiconductor device to store data.

[0016] The semiconductor device, its manufacturing method, and the storage system provided by the embodiments of the present application can, after implementing the small-head process, avoid the second sacrificial material from filling into the groove when forming the gap sacrificial layer subsequently, such that the gap sacrificial layer is only located within the gate line gap. Furthermore, the difficulty of removing the gap sacrificial layer subsequently can be reduced, and the requirement that the gate layer has different dimensions in the core area and the connection area can be avoided when removing the gap sacrificial layer subsequently. Compared with the related art where the small-head process is implemented for the portions of the stacked structure in the core area and the connection area in different process steps, the embodiments of the present application have lower costs and a simpler process.

[0017] It should be understood that the content described in this part is not intended to identify the key or important features of the embodiments of the present application, nor is it used to limit the scope of the present application. Other features of the present application will become easily understandable through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] By reading the detailed description of the non-limiting embodiments with reference to the following drawings, other features, objectives, and advantages of the present application will become more apparent. The drawings are used to better understand the solution and do not constitute a limitation to the present application. In the drawings:

[0019] Figures 1 to 11 is a process schematic diagram of a manufacturing method of a semiconductor device according to one embodiment of the present application;

[0020] Figures 12 to 29 is a process schematic diagram of a manufacturing method of a semiconductor device according to another embodiment of the present application;

[0021] Figure 30 is a flow schematic diagram of a manufacturing method of a semiconductor device according to one embodiment of the present application;

[0022] Figure 31is a schematic flow chart of a method for manufacturing a semiconductor device according to another embodiment of the present application;

[0023] Figure 32 is a block diagram of a system having a semiconductor device according to an embodiment of the present application;

[0024] Figure 33 is a schematic diagram of a memory card having a semiconductor device according to an embodiment of the present application; and

[0025] Figure 34 is a schematic diagram of a solid - state drive having a semiconductor device according to an embodiment of the present application.

[0026] Reference numerals:

[0027] 100, stacked structure; 101, core region; 102, connection region; 103, first gap;

[0028] 104, second gap; 105, third gap; 106, fourth gap;

[0029] 110, interlayer dielectric layer; 111, first part; 112, second part;

[0030] 120, gate layer; 130, interlayer sacrificial layer; 131, groove;

[0031] 140, first blocking sacrificial layer; 150, second blocking sacrificial layer; 160, stacked structure;

[0032] 200, gate line isolation structure; 201, gate line gap; 210, conductive structure;

[0033] 220, isolation layer; 230, gap sacrificial layer; 300, channel structure; 310, functional layer;

[0034] 311, blocking layer; 312, charge trapping layer; 313, tunneling layer; 320, channel layer;

[0035] 330, filling core layer; 340, channel plug; 400, top selection stacked structure;

[0036] 410, top selection dielectric layer; 420, top selection gate layer;

[0037] 500, top selection channel structure; 510, top isolation layer; 520, top connection structure;

[0038] 521, top channel layer; 522, top plug; 523, top filling layer;

[0039] 600, Source electrode layer; 700, Substrate; 800, System; 801, Memory system;

[0040] 802, Semiconductor device; 803, Memory controller; 804, Host;

[0041] 810, Memory card; 811, Memory card connector; 820, SSD;

[0042] 821, SSD connector. Detailed implementation mode

[0043] To better understand the present application, more detailed descriptions of various aspects of the present application will be made with reference to the accompanying drawings. It should be understood that these detailed descriptions are only descriptions of exemplary embodiments of the present application, and do not limit the scope of the present application in any way. Throughout the specification, the same reference numerals refer to the same elements. The expression "and / or" includes any and all combinations of one or more of the associated listed items.

[0044] It should be noted that in this specification, the expressions such as first, second, third, etc. are only used to separate one feature from another feature area, and do not represent any limitation on the features, especially do not represent any order.

[0045] In the drawings, for the sake of illustration, the thickness, dimensions and shapes of the components have been slightly adjusted. The drawings are only examples and are not drawn strictly to scale. As used herein, terms such as "substantially", "about" and similar terms are used as terms indicating approximation, rather than terms indicating degree, and are intended to illustrate the inherent deviations in measured or calculated values that would be recognized by those of ordinary skill in the art.

[0046] It should also be understood that expressions such as "including", "including having", "having", "containing" and / or "containing having" in this specification are open-ended rather than closed-ended expressions, which mean that there are the stated features, elements and / or components, but do not exclude the existence of one or more other features, elements, components and / or their combinations. In addition, when an expression such as "at least one of..." appears after the list of listed features, it modifies the entire list of features, rather than just the individual elements in the list. In addition, when describing the embodiments of the present application, the use of "may" means "one or more embodiments of the present application". And the term "exemplary" is intended to refer to an example or illustration.

[0047] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. It should also be understood that, unless otherwise specified in this application, words defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and should not be interpreted in an idealized or overly formal sense.

[0048] It should be noted that, without conflict, the embodiments in this application and the features in the embodiments can be combined with each other. Additionally, unless explicitly defined or conflicting with the context, the specific steps included in the methods described in this application do not have to be limited to the recorded order and can be executed in any order or in parallel. The following will describe this application in detail with reference to the accompanying drawings and in conjunction with the embodiments.

[0049] Furthermore, in this application, the term "layer" refers to a portion of material including a region having a thickness. The layer can extend over the entirety of a structure below or above, or can have a scope smaller than the scope of the structure below or above. Additionally, the layer can be a region of a homogeneous or heterogeneous continuous structure with a thickness less than the thickness of the continuous structure. The layer can extend horizontally, vertically, and / or along an inclined surface. The layer can include a plurality of sub-layers. Also, in this application, when using "connected" or "coupled", it can indicate direct contact or indirect contact between the corresponding components, unless otherwise explicitly defined or derivable from the context.

[0050] Figure 30 The flowchart of a method for manufacturing a semiconductor device according to one embodiment of this application is shown. The embodiment of this application provides a method for manufacturing a semiconductor device, and this manufacturing method 1000 includes:

[0051] S100. Form a stacked structure 160 on one side of a substrate 700 and a channel structure 300 that penetrates the stacked structure 160 in a first direction and extends into the substrate 700. The stacked structure 160 includes an interlayer dielectric layer 110 and an interlayer sacrificial layer 130 that are alternately stacked in a first direction (z direction). The stacked structure 160 has a core region 101 and a connection region 102 located on at least one side of the core region 101 in a second direction (see Figure 1 ).

[0052] S110. Form a gate line gap 201 that extends in a second direction (y direction) and penetrates the stacked structure 160 in the first direction.

[0053] S120. Fill the gate line gap 201 with a second sacrificial material to form a gap sacrificial layer 230 (see Figure 2 ).

[0054] S130. Remove the part of the gap sacrificial layer 230 located in the connection area 102 to expose the part of the gate line gap 201 located in the connection area 102 (see Figure 3 );

[0055] S140. Remove a part of the interlayer sacrificial layer 130 located in the connection area 102 through the part of the gate line gap 201 located in the connection area 102 to form a fourth gap 106 (see Figure 4 );

[0056] S150. Deposit a barrier sacrificial material on the part of the gate line gap 201 located in the connection area 102 to form a second barrier sacrificial layer 150 in the fourth gap 106 (see Figure 5 );

[0057] S160. Remove the part of the gap sacrificial layer 230 located in the core area 101 and the second barrier sacrificial layer 150 to expose the gate line gap 201 and form a third gap 105 located in the connection area 102 between two adjacent interlayer dielectric layers 110 (see Figure 6 );

[0058] S170. Form a first barrier sacrificial layer 140 in the third gap 105. Specifically, as Figure 7 shown, a barrier sacrificial material can be deposited in the gate line gap 201. A part of the barrier sacrificial material fills the third gap 105, and the other part covers the inner wall of the gate line gap 201; as Figure 8 shown, remove the barrier sacrificial material covering the inner wall of the gate line gap 201, and the remaining barrier sacrificial material in the third gap 105 constitutes the first barrier sacrificial layer 140;

[0059] S180. Remove the part of the interlayer sacrificial layer 130 located in the core area 101 to form a first gap 103 between two adjacent interlayer dielectric layers 110 (see Figure 9 ). For example, since the materials of the interlayer sacrificial layer 130 and the first barrier sacrificial layer 140 are different, an etching solution with a higher etching selectivity for the interlayer sacrificial layer 130 relative to the first barrier sacrificial layer 140 can be selected to remove the part of the interlayer sacrificial layer 130 located in the core area 101.

[0060] S190. Remove the first barrier sacrificial layer 140 to form a second gap 104 communicating with the first gap 103 between two adjacent interlayer dielectric layers 110 (see Figure 10 );

[0061] S200. Fill the gate material in the first gap 103 and the second gap 104 through the gate line gap 201 to form a gate layer 120 (see Figure 11 ).

[0062] AsFigure 4 As shown, since only a part of the interlayer sacrificial layer 130 located in the connection area 102 is removed through the gate line gap 201 in step S140, some of the interlayer sacrificial layer 130 still remains in the connection area 102, so that the size of the fourth gap 106 formed in the third direction (x direction) is smaller than the size of the interlayer sacrificial layer 130 in the connection area 102 in the third direction (x direction). Therefore, the size of the gate layer 120 formed subsequently in the core area 101 in the third direction (x direction) is larger than its size in the connection area 102 in the third direction (x direction). The first direction, the second direction, and the third direction intersect pairwise.

[0063] In addition, when removing the interlayer sacrificial layer 130 by a wet process in the related art, the phenomenon of "big head" or "flat head" may occur at the end of the interlayer dielectric layer 110 close to the gate line gap 201. Among them, the "big head" phenomenon generally means that the end of the interlayer dielectric layer 110 close to the gate line gap 201 is spherical, and its thickness in the first direction (z direction) at this position is greater than the thickness of the interlayer dielectric layer 110 away from the gate line gap 201; the "flat head" phenomenon generally means that the thickness of the interlayer dielectric layer 110 is the same everywhere. Since the subsequent gate material is filled into the gap between two adjacent interlayer dielectric layers 110 through the gate line gap 201, and in the above cases, the opening of the gap between two adjacent interlayer dielectric layers 110 is smaller close to the gate line gap 201, both of these phenomena are likely to cause the gate material to fail to fill the gap between two adjacent interlayer dielectric layers 110, resulting in gaps, which will further affect the performance of the semiconductor device.

[0064] To avoid the above problems, a small-head process can be adopted after forming the gate line gap 201, so that the thickness of the interlayer dielectric layer 110 close to the gate line gap 201 is smaller than its thickness away from the gate line gap 201. Specifically, as Figure 12 shown, after forming the gate line gap 201 on the stacked structure 160, a part of the interlayer sacrificial layer 130 can be removed through the gate line gap 201, so that the part of the interlayer dielectric layer 110 close to the gate line gap 201 protrudes in the third direction (x direction) from the remaining interlayer sacrificial layer 130; as Figure 15 and Figure 16 shown, the part of the interlayer dielectric layer 110 that protrudes from the interlayer sacrificial layer 130 is etched, so that the thickness of the part of the interlayer dielectric layer 110 close to the gate line gap 201 is smaller than the part away from the gate line gap 201. Thus, in the first direction, the height of the gap between two adjacent interlayer dielectric layers 110 in the area close to the gate line gap 201 is greater than the height of the area away from the gate line gap 201. In other words, the opening of the gap between two adjacent interlayer dielectric layers 110 is larger close to the gate line gap 201. Therefore, when filling the gate material into the gap through the gate line gap 201 subsequently, the gate material can fill the gap and it is not easy to generate gaps.

[0065] In order to improve the performance of semiconductor devices, a small-head process needs to be applied to the manufacturing method of the semiconductor device provided by the embodiment of the present application. The small-head process is usually implemented after the formation of the gate line gap 201 and before the filling of the gate line gap 201, that is, after the execution of step S110 and before the execution of step S120. However, since a part of the interlayer sacrificial layer 130 needs to be removed during the implementation of the small-head process, the part of the interlayer dielectric layer 110 close to the gate line gap 201 protrudes from the remaining interlayer sacrificial layer 130. Therefore, a groove 131 recessed along the third direction (x direction) is formed between two adjacent interlayer dielectric layers 110. After the implementation of the small-head process, a gap sacrificial layer 230 needs to be formed by filling a second sacrificial material in the gate line gap 201. Thus, a part of the gap sacrificial layer 230 is located between two adjacent interlayer dielectric layers 110, and another part is located in the gate line gap 201. In other words, the side wall of the gap sacrificial layer 230 extending along the first direction (z direction) is overall serrated. This will increase the difficulty of removing the gap sacrificial layer 230 subsequently. When performing step S160 subsequently, that is, removing the part of the gap sacrificial layer 230 located in the core area 101, in order to remove the second sacrificial material filled in the groove 131, not only the second blocking sacrificial layer 150 is removed, but also the remaining part of the interlayer sacrificial layer 130 located in the connection area 102 is removed. At this time, the part of the interlayer sacrificial layer 130 located in the connection area 102 has been completely removed, which results in the size of the gate layer 120 in the core area 101 along the third direction (x direction) being the same as its size in the connection area 102 along the third direction (x direction), failing to meet the requirement that the sizes of the gate layer 120 in the core area 101 and the connection area 102 are different. It can be seen that the small-head process is difficult to be compatible with the manufacturing method of the semiconductor device in the above embodiment of the present application. If two small-head processes are adopted and the small-head process is respectively implemented on the parts of the stacked structure 160 located in the core area 101 and the connection area 102 in different process steps, not only will the cost be significantly increased, but also the feature size of the gate line gap 201 will be increased, affecting the process window of the entire process flow.

[0066] To solve the above problems, as Figure 31 shown, the embodiment of the present application also provides another manufacturing method of a semiconductor device. The manufacturing method 2000 includes:

[0067] S200. Form a gate line gap 201 extending along the second direction and penetrating the stacked structure 160 along the first direction, where the stacked structure 160 includes interlayer dielectric layers 110 and interlayer sacrificial layers 130 stacked alternately along the first direction (see Figure 1 ).

[0068] S210. Remove part of the interlayer sacrificial layer 130 through the gate line slit 201 to form a groove 131 that is recessed in the third direction (x direction) between two adjacent interlayer dielectric layers 110 (see Figure 12 ); wherein, the first direction, the second direction, and the third direction intersect pairwise;

[0069] S220. Process the part of the interlayer dielectric layer 110 that protrudes from the interlayer sacrificial layer 130 so that the thickness of the interlayer dielectric layer 110 near the gate line slit 201 is less than its thickness far from the gate line slit 201 (see Figure 15 );

[0070] S230. Fill the first sacrificial material in the groove 131 (see Figure 17 );

[0071] In the embodiment of the present application, after implementing the small-head process, by filling the first sacrificial material in the groove 131, it is possible to avoid the second sacrificial material from filling into the groove 131 when forming the gap sacrificial layer 230 subsequently, so that the gap sacrificial layer 230 is only located in the gate line slit 201. Furthermore, the difficulty of removing the gap sacrificial layer 230 subsequently can be reduced, and it can be avoided that the requirements for different sizes of the gate layer 120 in the core area 101 and the connection area 102 cannot be achieved when removing the gap sacrificial layer 230 subsequently, thereby realizing the compatibility of the small-head process and the requirements for different sizes of the gate layer 120 in the core area 101 and the connection area 102. In addition, compared with the related art in which the small-head process is respectively implemented on the parts of the stacked structure 160 located in the core area 101 and the connection area 102 in different process steps, the embodiment of the present application has lower cost and simpler process.

[0072] Next, each step in the semiconductor device manufacturing method in the embodiment of the present application will be specifically introduced.

[0073] Step S200

[0074] In step S200, a gate line slit 201 (Gate Line Slit, GLS) is formed that extends in the second direction (y direction) and penetrates the stacked structure 160 in the first direction (z direction). Figure 1 Fig. shows a cross-sectional schematic diagram of a semiconductor device formed with a gate line slit 201 in the embodiment of the present application. Among them, the gate line slit 201 can be formed in the stacked structure 160 through processes such as dry or wet etching. As an example, the stacked structure 160 includes a core area 101 and a connection area 102 located on at least one side of the core area 101 in the second direction (y direction), and a part of the gate line slit 201 is located in the core area 101, and another part is located in the connection area 102.

[0075] Before performing step S200, the manufacturing method further includes: forming a stacked structure 160 on one side of a substrate 700, the stacked structure 160 including interlayer dielectric layers 110 and interlayer sacrificial layers 130 alternately stacked along a first direction (z direction); forming a channel structure 300 that penetrates the stacked structure 160 along the first direction (z direction) and extends into the substrate 700.

[0076] Wherein, the substrate 700 can be a single-layer structure or a multi-layer structure. For example, the material of the substrate 700 can include, but is not limited to, single-crystalline silicon (Si), single-crystalline germanium (Ge), silicon germanium (GeSi), silicon carbide (SiC), silicon-on-insulator (SOI), germanium-on-insulator (GOI), or group III-V compounds such as gallium arsenide. In some embodiments, a well region formed by doping with an N-type or P-type dopant may be formed in a partial region of the substrate 700. Wherein, the dopant may include at least one of phosphorus (P), arsenic (As), and antimony (Sb). Additionally, the stacked structure 160 can be formed on one side of the substrate 700 through a thin film deposition process, and the thin film deposition process can be, but is not limited to, a physical vapor deposition (PVD) process, a chemical vapor deposition (CVD) process, an atomic layer deposition (ALD) process, or a combination of any several of the above processes. The stacked structure 160 can include, but is not limited to, 64 pairs, 128 pairs, or more than 128 pairs of interlayer dielectric layers 110 and interlayer sacrificial layers 130. The more the number of layers of the interlayer dielectric layers 110 and the interlayer sacrificial layers 130, the higher the integration degree, and the more the number of storage units of the final semiconductor device. The number of layers of the interlayer dielectric layers 110 and the interlayer sacrificial layers 130 can be designed according to actual requirements, and the present application does not limit this. Wherein, the material of the interlayer dielectric layer 110 can include, but is not limited to, silicon oxide, silicon oxynitride, silicon nitride, or high-K materials such as hafnium oxide, zirconium oxide, aluminum oxide, tantalum oxide, etc., and the material of the interlayer sacrificial layer 130 can include, but is not limited to, silicon oxynitride, silicon nitride, polysilicon, or polycrystalline germanium.

[0077] As described above, the stacked structure 160 may include a core region 101 and a connection region 102 located on at least one side of the core region 101 along the second direction (y direction). It should be noted that the connection region 102 may be a stepped structure or a non-stepped structure. For example, in the SCT (Staircase Contact) architecture, the connection region 102 does not need to be stepped. If the connection region 102 of the stacked structure 160 is a stepped structure, then after alternately stacking the interlayer dielectric layer 110 and the interlayer sacrificial layer 130 on one side of the substrate 700, a stepped structure can be formed by performing multiple trim-etch cycle processes on the portions of the interlayer dielectric layer 110 and the interlayer sacrificial layer 130 located in the connection region 102.

[0078] In some embodiments, the channel structure 300 may be formed by the following steps: forming a channel hole (not shown) that penetrates the stacked structure 160 along the first direction and extends into the substrate 700 from a side of the stacked structure 160 away from the substrate 700; wherein, in view of the problem of lateral etching in wet etching, the channel hole can be formed by a dry etching process, a combination of dry and wet etching processes, or a patterning process, and the patterning process includes photolithography, cleaning, and chemical mechanical polishing processes. Among them, the cross-sectional shape of the channel hole, that is, the cross-sectional shape of the channel hole perpendicular to its extending direction, can be but is not limited to being circular, elliptical, or polygonal. As Figure 14As shown, a functional layer 310 is formed on the inner wall of the channel hole. The functional layer 310 includes a blocking layer 311, a charge trapping layer 312, and a tunneling layer 313. Specifically, the blocking layer 311 can be formed on the inner wall of the channel hole to block the outflow of charges stored in the subsequently formed charge trapping layer 312. Among them, the material of the blocking layer 311 can include, but is not limited to, silicon oxide, silicon nitride, high-K dielectric materials, or any combination of the above. The charge trapping layer 312 is formed on the side of the blocking layer 311 away from the inner wall of the channel hole to store charges. Among them, the material of the charge trapping layer 312 can include, but is not limited to, silicon nitride, silicon oxynitride, silicon, or any combination of the above. The tunneling layer 313 is formed on the side of the charge trapping layer 312 away from the blocking layer 311. Among them, the material of the tunneling layer 313 can include, but is not limited to, silicon oxide or silicon nitride. A channel layer 320 is formed on the side of the tunneling layer 313 away from the charge trapping layer 312. The channel layer 320 is used to transport the required charges, namely electrons or holes. Among them, the material of the channel layer 320 can include, but is not limited to, amorphous silicon, polycrystalline silicon, or single-crystalline silicon. A filling core layer 330 is formed in the pores surrounded by the channel layer 320. Among them, the material of the filling core layer 330 can include, but is not limited to, silicon oxide, silicon nitride, silicon oxynitride, spin-on glass, carbon-doped oxide, etc. A channel plug 340 in contact with the channel layer 320 is formed on the side of the filling core layer 330 away from the substrate 700. The material of the channel plug 340 can be the same as that of the channel layer 320. Among them, the blocking layer 311, the charge trapping layer 312, the tunneling layer 313, and the functional layer 310 can all be formed by a thin film deposition process. In addition, in order to relieve the structural stress, at least one air gap can be formed in the filling core layer 330 by controlling the corresponding parameters in the channel filling process during the formation of the filling core layer 330.

[0079] Figure 13 shows Figure 12 an enlarged schematic view at A, Figure 14 shows Figure 12 an enlarged schematic view at B.

[0080] In some embodiments, after the channel structure 300 is formed, the manufacturing method further includes: forming a top select stack structure 400 on the side of the stack structure 160 away from the substrate 700 (see Figure 12 and Figure 13);Select the side of the top selection stack structure 400 away from the stack structure 160, and form a top selection channel structure 500 that penetrates the top selection stack structure 400 along the first direction (z direction). The top selection channel structure 500 is electrically connected to the channel structure 300. As an example, the top selection stack structure 400 can be formed in the following manner: Alternately stack a top selection dielectric layer 410 and a top selection gate layer 420 along the first direction on the side of the stack structure 160 away from the substrate 700. For example, a layer of top selection dielectric layer 410 is formed on the side of the stack structure 160 away from the substrate 700, a top selection gate layer 420 is formed on the side of the top selection dielectric layer 410 away from the stack structure 160, and another layer of top selection dielectric layer 410 is formed on the side of the top selection gate layer 420 away from the stack structure 160. The materials of the two layers of top selection dielectric layer 410 can be the same or different.

[0081] In some embodiments, the top selection channel structure 500 includes a top isolation layer 510 and a top connection structure 520. The top selection channel structure 500 can be formed in the following manner: Select the side of the top selection stack structure 400 away from the stack structure 160, and form a top isolation hole (not shown) that penetrates the top selection stack structure 400 along the first direction; Form a top isolation layer 510 on the sidewall of the top isolation hole extending along the first direction (z direction); Form a top connection structure 520 in the pore surrounded by the top isolation layer 510. Among them, the top isolation hole can be formed by a dry etching process, a combination of dry and wet etching processes, or a patterning process. The top isolation layer 510 can be formed on the inner wall of the top isolation hole by a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof.

[0082] In some embodiments, the top connection structure 520 includes a top filling layer 523, a top channel layer 521, and a top plug 522. The top connection structure 520 can be formed in the following manner: Form a top channel layer 521 connected to the channel plug 340 of the channel structure 300 on the sidewall of the pore surrounded by the top isolation layer 510; Form a top filling layer 523 in the pore surrounded by the top channel layer 521; Select the side of the top filling layer 523 away from the stack structure 160, and remove a part of the top filling layer 523 to form a pit; Form a top plug 522 in the pit.

[0083] In some embodiments, the manufacturing method further includes: Forming a top selection tangent structure that penetrates at least all of the top selection gate layers 420 along the first direction (z direction), and the top selection tangent structure extends along the second direction (y direction).

[0084] Step S210

[0085] In step S210, a part of the interlayer sacrificial layer 130 is removed through the gate line gap 201 to form a groove 131 that is recessed in the third direction (x direction) between two adjacent interlayer dielectric layers 110. Figure 15 The cross-sectional schematic diagram of the semiconductor device in which a part of the interlayer sacrificial layer 130 is removed according to the embodiment of the present application is shown. Figure 16 Shown is Figure 15 the enlarged schematic diagram at C; as Figure 15 and Figure 16 shown, after removing a part of the interlayer sacrificial layer 130, the sidewall of the interlayer dielectric layer 110 exposed in the gate line gap 201 is not flush with the sidewall of the remaining interlayer sacrificial layer 130 exposed in the gate line gap 201 in the first direction (z direction), and a part of the interlayer dielectric layer 110 protrudes in the third direction (x direction) from the adjacent interlayer sacrificial layer 130.

[0086] As an example, if the interlayer dielectric layer 110 is a silicon oxide layer and the interlayer sacrificial layer 130 is a silicon nitride layer, an etchant such as phosphoric acid solution, which has a relatively high etching selectivity for the interlayer sacrificial layer 130 compared to the interlayer dielectric layer 110, can be selected to remove a part of the interlayer sacrificial layer 130 to form the groove 131. Among them, the recessed dimension of the groove 131 in the third direction (x direction) can be controlled by adjusting the concentration of the etchant, the type of the etchant, and the etching duration. Among them, as Figure 16 shown, the recessed dimension of the groove 131 in the third direction can be less than 20 nm. In other words, the dimension L of the part of the interlayer dielectric layer 110 protruding from the adjacent interlayer sacrificial layer 130 in the third direction (x direction) is less than 20 nm.

[0087] Step S220

[0088] In step S220, the part of the interlayer dielectric layer 110 protruding from the interlayer sacrificial layer 130 can be processed so that the thickness of the interlayer dielectric layer 110 close to the gate line gap 201 is less than its thickness far from the gate line gap 201. Thus, in the first direction, the gap between two adjacent interlayer dielectric layers 110 has a greater height in the area close to the gate line gap 201 than in the area far from the gate line gap 201. In other words, the opening of the gap between two adjacent interlayer dielectric layers 110 is larger at the position close to the gate line gap 201. Therefore, when filling the gate material in this gap through the gate line gap 201 subsequently, the gate material can fill the gap completely and it is not easy to generate gaps.

[0089] As an example, if the interlayer dielectric layer 110 is a silicon oxide layer and the interlayer sacrificial layer 130 is a silicon nitride layer, an etching solution such as hydrofluoric acid solution, which has a high etching selectivity for the interlayer dielectric layer 110 relative to the interlayer sacrificial layer 130, can be selected to etch the portion of the interlayer dielectric layer 110 that protrudes beyond the interlayer sacrificial layer 130. It should be noted that when etching the interlayer dielectric layer 110 with hydrofluoric acid solution, the concentration of the hydrofluoric acid solution should be relatively low, otherwise over-etching is likely to occur, resulting in the complete etching of the portion of the interlayer dielectric layer 110 that protrudes beyond the interlayer sacrificial layer 130. For example, the molar ratio of water to hydrogen fluoride in the hydrofluoric acid solution is greater than 200 and less than 500.

[0090] It should be noted that after processing the portion of the interlayer dielectric layer 110 that protrudes beyond the interlayer sacrificial layer 130 by etching or other means, the portion of the interlayer dielectric layer 110 that protrudes beyond the interlayer sacrificial layer 130 may have different thicknesses along the third direction (x direction). For example, as Figure 16 shown, along the third direction (x direction), the thickness of the portion of the interlayer dielectric layer 110 that protrudes beyond the interlayer sacrificial layer 130 gradually increases in the direction away from the gate line gap 201. In other words, at this time, the height of the groove 131 in the first direction (z direction) gradually decreases in the direction away from the gate line gap 201. Another example is that the portion of the interlayer dielectric layer 110 that protrudes beyond the interlayer sacrificial layer 130 includes a first sub-portion and a second sub-portion (not shown). The first sub-portion is closer to the gate line gap 201 than the second sub-portion along the third direction (x direction). The first sub-portion has the same thickness along the third direction (x direction), and the second sub-portion also has the same thickness along the third direction (x direction), and the thickness of the first sub-portion is less than the thickness of the second sub-portion. Still another example is that the thickness of the first sub-portion of the interlayer dielectric layer 110 gradually increases in the direction away from the gate line gap 201, the second sub-portion has the same thickness along the third direction (x direction), and the maximum thickness of the first sub-portion is the same as the thickness of the second sub-portion. As an example, as Figure 16 shown, the difference between the maximum thickness D1 and the minimum thickness D2 of the portion of the interlayer dielectric layer 110 that protrudes beyond the interlayer sacrificial layer 130 is 6 nm to 8 nm.

[0091] Step S230

[0092] In step S230, a first sacrificial material is filled in the groove 131. The first sacrificial material may include, but is not limited to, silicon nitride. The first sacrificial material may be deposited in the groove 131 through a thin film deposition process, and the thin film deposition process may be, but is not limited to, a Physical Vapor Deposition (PVD) process, a Chemical Vapor Deposition (CVD) process, an Atomic Layer Deposition (ALD) process, or a combination of any of the above processes. Figure 17 The cross-sectional schematic diagram of the semiconductor device after filling the first sacrificial material in the embodiment of the present application is shown. As Figure 17 shown, the first sacrificial material has the same material as the interlayer sacrificial layer 130. After the first sacrificial material is filled in the groove 131, there is no obvious interface between the interlayer sacrificial layer 130 and the first sacrificial material filled in the groove 131. The first sacrificial material filled in the groove 131 may be flush with the side wall of the interlayer dielectric layer 110 close to the gate line gap 201, or may protrude from the side wall of the interlayer dielectric layer 110 close to the gate line gap 201. As an example, the deposition size of the first sacrificial material filled in the groove 131 in the third direction may be 20 nm to 30 nm.

[0093] After filling the first sacrificial material in the groove 131, the manufacturing method further includes: replacing a part of the interlayer sacrificial layer 130 with the gate layer 120 through the gate line gap 201. Among them, in the third direction (x direction), the size of the gate layer 120 located in the core area 101 is larger than the size of the gate layer 120 located in the connection area 102. The material of the gate layer 120 may include, but is not limited to, polysilicon, tungsten, aluminum, titanium, copper, cobalt, tungsten nitride, or a combination of any of the above.

[0094] As an example, in order to make the gate layer 120 have different sizes in the core area 101 and the connection area 102, the gate layer 120 may be formed in the following manner: As Figure 24 shown, a part of the interlayer sacrificial layer 130 located in the connection area 102 is replaced with the first barrier sacrificial layer 140 through the gate line gap 201; since only a part of the interlayer sacrificial layer 130 located in the connection area 102 is replaced with the first barrier sacrificial layer 140, there is still a part of the interlayer sacrificial layer 130 on the side of the first barrier sacrificial layer 140 away from the gate line gap 201 in the third direction (x direction). Therefore, the size of the first barrier sacrificial layer 140 in the third direction (x direction) is smaller than the size of the stack structure 160 in the connection area 102 in the third direction (x direction). The material of the first barrier sacrificial layer 140 may include, but is not limited to, amorphous silicon, polysilicon, or single crystal silicon. As Figure 25As shown, the portion of the interlayer sacrificial layer 130 located in the core region 101 is removed to form a first gap 103 between two adjacent interlayer dielectric layers 110. For example, the portion of the interlayer sacrificial layer 130 located in the core region 101 can be removed by an etching solution that has a higher etching selectivity for the interlayer sacrificial layer 130 compared to the first blocking sacrificial layer 140; as Figure 26 shown, the first blocking sacrificial layer 140 is removed to form a second gap 104 that communicates with the first gap 103 between two adjacent interlayer dielectric layers 110; since the second gap 104 is formed by removing the first blocking sacrificial layer 140, and the first blocking sacrificial layer 140 is formed by replacing a portion of the interlayer sacrificial layer 130 located in the connection region 102, while the first gap 103 is formed by removing all of the interlayer sacrificial layer 130 located in the core region 101, the dimension of the first gap 103 in the third direction (x direction) is greater than the dimension of the second gap 104 in the third direction (x direction). Among them, the second gap 104 communicates with the first gap 103 in the second direction (y direction). As Figure 27 shown, during the process of depositing the gate material through the gate line gap 201, the gate material fills the first gap 103 and the second gap 104 to form the gate layer 120. Thus, the dimension of the portion of the gate layer 120 located in the core region 101 in the third direction (x direction) is greater than the dimension of the portion of the gate layer 120 located in the connection region 102 in the third direction (x direction).

[0095] In some embodiments, a portion of the interlayer sacrificial layer 130 can be replaced with the first blocking sacrificial layer 140 in the following manner: as Figure 18 shown, a second sacrificial material is filled in the gate line gap 201 to form a gap sacrificial layer 230; wherein, the second sacrificial material can include, but is not limited to, amorphous silicon, polycrystalline silicon, or single crystal silicon. As Figure 19 shown, the portion of the gap sacrificial layer 230 located in the connection region 102 is removed. For example, a patterned mask layer can be formed on a layer of the stack structure 160 away from the substrate 700, the mask layer has an opening corresponding to the portion of the gate line gap 201 located in the connection region 102, and the portion of the gap sacrificial layer 230 located in the connection region 102 is removed through the patterned mask layer. As Figure 21 shown, a portion of the interlayer sacrificial layer 130 located in the connection region 102 is replaced with a second blocking sacrificial layer 150; as Figure 22 shown, the portion of the gap sacrificial layer 230 located in the core region 101 and the second blocking sacrificial layer 150 are removed to expose the gate line gap 201 and form a third gap 105 located in the connection region 102 between two adjacent interlayer dielectric layers 110; as Figure 24 shown, a first blocking sacrificial layer 140 is formed in the third gap 105.

[0096] As an example, the second barrier layer 311 can be formed in the following manner: As Figure 20 shown, a portion of the interlayer sacrificial layer 130 located in the connection region 102 is removed through the portion of the gate line gap 201 located in the connection region 102 to form a fourth gap 106; since only a portion of the interlayer sacrificial layer 130 located in the connection region 102 is removed, the dimension of the fourth gap 106 in the third direction (x direction) is smaller than the dimension of the stacked structure 160 in the connection region 102 in the third direction (x direction). As Figure 21 shown, a barrier sacrificial material is deposited on the side of the stacked structure 160 away from the substrate 700. Since only the portion of the gap sacrificial layer 230 located in the connection region 102 is removed, in other words, only the portion of the gate line gap 201 located in the connection region 102 is exposed, the deposited barrier sacrificial material will be deposited in the fourth gap 106 through the portion of the gate line gap 201 located in the connection region 102 to form a second barrier sacrificial layer 150. Of course, during this process, the barrier material will also be deposited on the inner wall of the gate line gap 201 and on the side of the stacked structure 160 away from the substrate 700.

[0097] As an example, after removing the portion of the gap sacrificial layer 230 located in the core region 101 and the second barrier sacrificial layer 150, the first barrier layer 311 can be formed in the third gap 105 in the following manner: As Figure 23 shown, a barrier sacrificial material is deposited on the side of the stacked structure 160 away from the substrate 700. Since at this time, the portions of the gap sacrificial layer 230 located in the core region 101 and the connection region 102 have both been removed, in other words, the portions of the gate line gap 201 located in the core region 101 and the connection region 102 have both been exposed, the barrier sacrificial material will be deposited into the third gap 105 through the portion of the gate line gap 201 located in the connection region 102 to form a first barrier sacrificial layer 140. The barrier sacrificial material will also be deposited on the side of the stacked structure 160 away from the substrate 700 and on the inner walls of the gate line gap 201 located in the core region 101 and the connection region 102. As Figure 24 shown, the barrier sacrificial material deposited on the inner wall of the gate line gap 201 is removed. During the process of removing the barrier sacrificial material deposited on the inner wall of the gate line gap 201, in order to completely remove the barrier sacrificial material deposited in the core region 101, a portion of the first barrier sacrificial layer 140 may also be removed. In other words, in the connection region 102, the portion of the interlayer dielectric layer 110 close to the gate line gap 201 protrudes beyond the first barrier sacrificial layer 140. It should be noted that during the process of removing the barrier sacrificial material deposited on the inner wall of the gate line gap 201, the first barrier sacrificial layer 140 may not be removed, and the side walls of the first barrier sacrificial layer 140 and the interlayer dielectric layer 110 close to the gate line gap 201 in the connection region 102 are flush in the first direction (z direction).

[0098] In some embodiments, as Figure 28As shown, after forming the gate layer 120, the manufacturing method may further include: forming an isolation layer 220 on the sidewalls of the gate line gap 201 extending in the first direction (z direction); and forming a conductive structure 210 in the gap surrounded by the isolation layer 220.

[0099] In some embodiments, the manufacturing method may further include: removing the substrate 700 to expose a partial functional layer 310 of the channel structure 300; removing the exposed portion of the functional layer 310 of the channel structure 300 to expose a partial channel layer 320 of the channel structure 300; and forming a source layer 600 on one side of the stacked structure 100, where the source layer 600 is in contact with the exposed portion of the channel layer 320 of the channel structure 300 and the conductive structure 210.

[0100] In addition, as Figure 28 shown, an embodiment of the present application further provides a semiconductor device, which includes a stacked structure 100 and a gate line isolation structure 200. The stacked structure 100 includes an interlayer dielectric layer 110 and a gate layer 120 alternately stacked in the first direction (z direction), and the gate line isolation structure 200 extends in the second direction (y direction) and penetrates the stacked structure 100 in the first direction (z direction).

[0101] Among them, the stacked structure 100 includes a core area 101 and a connection area 102 located on at least one side of the core area 101 in the second direction (y direction). In the third direction (x direction), the size of the gate layer 120 located in the core area 101 is larger than its size located in the connection area 102. In the first direction (z direction), the thickness of the interlayer dielectric layer 110 close to the gate line isolation structure 200 is smaller than its thickness away from the gate line isolation structure 200. The first direction, the second direction, and the third direction intersect pairwise.

[0102] It can be seen that the semiconductor device of the embodiment of the present application realizes the compatibility of the processes with different sizes of the gate layer in the core area 101 and the connection area 102 and the small-head process. In the first direction, the thickness of the interlayer dielectric layer 110 close to the gate line isolation structure 200 is smaller than its thickness away from the gate line isolation structure 200. In the third direction (x direction), the size of the gate layer 120 located in the core area 101 is larger than its size located in the connection area 102.

[0103] Figure 28 Shows a cross-sectional schematic diagram of the semiconductor device in the embodiment of the present application in blue Figure 29 Shows Figure 28 an enlarged schematic diagram at D in

[0104] In some embodiments, as Figure 29As shown, the interlayer dielectric layer 110 includes a first portion 111 and a second portion 112. The first portion 111 is close to the gate line isolation structure 200, and the second portion 112 is located on the side of the first portion 111 away from the gate line isolation structure 200. Among them, the thickness of the first portion 111 in the first direction (z direction) is less than the thickness of the second portion 112 in the first direction (z direction). As an example, the first portion 111 has a plurality of thicknesses along the third direction (x direction). For example, along the third direction (x direction), the thickness of the first portion 111 gradually increases in the direction away from the gate line isolation structure 200. Among them, the size of the first portion 111 along the third direction can be less than 20 nm. The difference between the maximum thickness and the minimum thickness of the first portion 111 can be 6 nm to 8 nm.

[0105] In some embodiments, the semiconductor device further includes a plurality of channel structures 300 distributed in the core region 101 and the connection region 102. The channel structures 300 penetrate the stacked structure 100 along the first direction (z direction). Among them, the channel structures 300 located in the connection region 102 are generally virtual channel structures. Among them, as Figure 14 shown, the channel structure 300 includes a channel layer 320 and a functional layer 310. The functional layer 310 covers the sidewalls of the channel layer 320 extending along the first direction (z direction). The functional layer 310 includes a tunneling layer 313, a charge trapping layer 312, and a blocking layer 311. The tunneling layer 313 is located on the sidewalls of the channel layer 320. The charge trapping layer 312 is located on the side of the tunneling layer 313 away from the channel layer 320. The blocking layer 311 is located on the side of the charge trapping layer 312 away from the tunneling layer 313. Among them, the functional layer 310 and the channel layer 320 of the channel structure 300, the corresponding part of the gate layer 120 of the stacked structure 100, and a part of the gate layer 120 together form a memory cell. A plurality of memory cells are connected in series along the stacking direction of the stacked structure 100, that is, the first direction (z direction), to form a memory string. The memory cells located in the same row, that is, distributed along the third direction (x direction), can be connected to the same word line. The remaining part of the gate layer 120 can be used as the word line of a plurality of memory cells in the corresponding memory string. Each memory string, that is, the memory cells in the same column, can be connected to the same bit line. Under the voltage control of the corresponding word line, the carriers in the channel layer 320 of the memory cell enter the charge trapping layer 312 of the functional layer 310, or the carriers in the charge trapping layer 312 of the functional layer 310 return to the channel layer 320, thereby realizing the programming or erasing of the memory cell.

[0106] In some embodiments, as Figure 13As shown, the semiconductor device further includes a top selection stack structure 400 and a top selection channel structure 500. The gate line isolation structure 200 penetrates the top selection channel structure 500 and the stack structure 100 along the first direction (z direction). Among them, the top selection stack structure 400 is located on one side of the stack structure 100 along the first direction (z direction). The top selection channel structure 500 is correspondingly arranged with the channel structure 300 located in the core area 101. The top selection channel structure 500 penetrates the top selection stack structure 400 along the first direction (z direction) and is connected to the corresponding channel structure 300.

[0107] As an example, the top selection stack structure 400 includes top selection dielectric layers 410 and top selection gate layers 420 that are alternately stacked along the first direction (z direction). For example, the top selection stack structure 400 includes two top selection dielectric layers 410 and a top selection gate layer 420 located between the two top selection dielectric layers 410. As an example, the top selection channel structure 500 includes a top connection structure 520 and a top isolation layer 510. The top isolation layer 510 coats the sidewalls of the top connection structure 520 extending along the first direction (z direction). The top connection structure 520 includes a top filling layer 523, a top channel layer 521, and a top plug 522. The top channel layer 521 coats the sidewalls of the top filling layer 523 extending along the first direction (z direction) and is connected to the channel structure 300. The top plug 522 is located on the side of the top filling layer 523 away from the channel structure 300 and is in contact with the top channel layer 521.

[0108] In some embodiments, the gate line isolation structure 200 includes a conductive structure 210 and an isolation layer 220. The conductive structure 210 penetrates the stack structure 100 along the first direction (z direction). The isolation layer 220 coats the sidewalls of the conductive structure 210 extending along the first direction (z direction).

[0109] In addition, the embodiment of the present application further provides a storage system. The storage system includes a controller and the above-mentioned semiconductor device. The controller is coupled to the semiconductor device and is used to control the semiconductor device to store data.

[0110] Figure 32 The block diagram of a system with a semiconductor device according to an embodiment of the present application is shown. The system 800 can be a mobile phone, a desktop computer, a laptop computer, a tablet computer, an in-vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a storage device therein. As Figure 32As shown, system 800 may include host 804 and memory system 801, and memory system 801 has one or more semiconductor devices 802 and memory controller 803. Host 804 may be a processor of an electronic device, e.g., a central processing unit (CPU), or may be a system on a chip (SoC), e.g., an application processor (AP). Host 804 may be configured to send or receive data from semiconductor device 802.

[0111] Semiconductor device 802 may be any semiconductor device disclosed in this application, e.g., Figure 28 the semiconductor device shown. According to some embodiments, memory controller 803 is coupled to semiconductor device 802 and host 804, and is configured to control semiconductor device 802. Memory controller 803 may manage data stored in semiconductor device 802 and communicate with host 804.

[0112] In some embodiments, memory controller 803 is designed to operate in a low duty cycle environment, such as a Secure Digital (SD) card, a Compact Flash (CF) card, a Universal Serial Bus (USB) flash drive, or other media used in electronic devices such as personal calculators, digital cameras, mobile phones, etc. In some embodiments, memory controller 803 is designed to operate in a high duty cycle environment, such as a solid state drive (SSD) or an embedded multimedia card (eMMC), which is used as a data storage device for mobile devices such as smart phones, tablets, laptops, etc. and enterprise storage arrays. Memory controller 803 may be configured to control operations of semiconductor device 802, such as read, erase, and program operations. Memory controller 803 may also be configured to manage various functions related to data stored in or to be stored in semiconductor device 802, including but not limited to bad block management, garbage collection, logical to physical address translation, wear leveling, etc. In some embodiments, memory controller 803 is further configured to process error correction code (ECC) related to data read from or written to semiconductor device 802. Any other suitable functions may also be performed by memory controller 803, e.g., formatting semiconductor device 802. Memory controller 803 may communicate with an external device (e.g., host 804) according to a specific communication protocol. For example, memory controller 803 may communicate with an external device through at least one of various interface protocols, such as USB protocol, MMC protocol, Peripheral Component Interconnect (PCI) protocol, high-speed PCI (PCI-E) protocol, Advanced Technology Attachment (ATA) protocol, Serial ATA protocol, Parallel ATA protocol, Small Computer System Interface (SCSI) protocol, Enhanced Small Disk Interface (ESDI) protocol, Integrated Drive Electronics (IDE) protocol, FireWire protocol, etc.

[0113] The memory controller 803 and one or more semiconductor devices 802 can be integrated into various types of storage devices. For example, they can be included within the same package (such as a Universal Flash Storage (UFS) package or an eMMC package). That is, the memory system 801 can be implemented and packaged into different types of end electronic products. In one example as shown in Figure 33 the memory controller 803 and a single semiconductor device 802 can be integrated into a memory card 810. The memory card 810 can include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a Memory Stick, a Multimedia Card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), a UFS, etc. The memory card 810 can further include a memory card connector 811 that couples the memory card 810 to a host (such as, Figure 32 the host 804 in Figure 34 ). In another example as shown in Figure 32 the memory controller 803 and multiple semiconductor devices 802 can be integrated into a Solid State Drive (SSD) 820. The SSD 820 can further include an SSD connector 821 that couples the SSD 820 to a host (such as,

[0114] It should be understood that the various forms of the processes shown above can be used, with steps reordered, added, or deleted. As an example, the steps recited in the present disclosure of the invention can be executed in parallel, sequentially, or in a different order, as long as the desired results of the technical solutions disclosed in this application can be achieved, and no limitation is imposed herein.

[0115] The above specific embodiments do not constitute a limitation to the protection scope of this application. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this application shall be included within the protection scope of this application.

Claims

1. A semiconductor device, characterized in that, Comprising: A stacked structure including interlayer dielectric layers and gate layers alternately stacked along a first direction; And A gate line isolation structure extending along a second direction and penetrating the stacked structure along the first direction; Wherein, the stacked structure includes a core region and connection regions located on at least one side of the core region along the second direction. In a third direction, the size of the gate layer in the core region is larger than its size in the connection regions. In the first direction, the thickness of the interlayer dielectric layer close to the gate line isolation structure is smaller than its thickness away from the gate line isolation structure. The first direction, the second direction, and the third direction intersect pairwise.

2. The semiconductor device according to claim 1, wherein, The interlayer dielectric layer includes: A first part close to the gate line isolation structure; and A second part located on a side of the first part away from the gate line isolation structure; Wherein, the thickness of the first part is smaller than the thickness of the second part, and the first part has different thicknesses along the third direction.

3. The semiconductor device according to claim 2, wherein Along the third direction, the thickness of the first part gradually increases in a direction away from the gate line isolation structure.

4. The semiconductor device according to claim 2, wherein, The size of the first part along the third direction is less than 20 nm.

5. The semiconductor device according to claim 2, wherein, The difference between the maximum thickness and the minimum thickness of the first part is 6 nm to 8 nm.

6. The semiconductor device according to any one of claims 1 to 5, wherein, The semiconductor device further includes: A plurality of channel structures distributed in the core region and the connection regions, and the channel structures penetrate the stacked structure along the first direction.

7. The semiconductor device according to claim 6, wherein, The semiconductor device further includes: A top selection stacked structure located on one side of the stacked structure along the first direction; and A top selection channel structure correspondingly arranged with the channel structure in the core region, and the top selection channel structure penetrates the top selection stacked structure along the first direction and is connected to the corresponding channel structure; Wherein, the gate line isolation structure penetrates the top selection stacked structure along the first direction.

8. The semiconductor device according to any one of claims 1 to 5, wherein, The gate line isolation structure includes: A conductive structure penetrating the stacked structure along the first direction; and An isolation layer covering sidewalls of the conductive structure extending along the first direction.

9. A method for manufacturing a semiconductor device, characterized in that, Comprising: Forming a gate line gap extending along the second direction and penetrating a stacked structure along the first direction, wherein the stacked structure includes interlayer dielectric layers and interlayer sacrificial layers alternately stacked along the first direction; Removing part of the interlayer sacrificial layer through the gate line gap to form a groove recessed along the third direction between two adjacent interlayer dielectric layers; Processing a part of the interlayer dielectric layer protruding from the interlayer sacrificial layer to make the thickness of the interlayer dielectric layer close to the gate line gap in the first direction smaller than its thickness away from the gate line gap; and Filling a first sacrificial material in the groove; Wherein, the first direction, the second direction, and the third direction intersect pairwise.

10. The manufacturing method of the semiconductor device according to claim 9, wherein, The stacked structure includes a core region and connection regions located on at least one side of the core region along the second direction; Wherein, after filling the first sacrificial material in the groove, the manufacturing method further includes: Part of the interlayer sacrificial layer is replaced with the gate layer through the gate line gap, wherein, in the third direction, the size of the gate layer located in the core region is larger than the size of the gate layer located in the connection region.

11. The method for manufacturing a semiconductor device according to claim 10, wherein, Replacing part of the interlayer sacrificial layer with the gate layer through the gate line gap includes: Replacing a part of the interlayer sacrificial layer located in the connection region with a first barrier sacrificial layer through the gate line gap; Removing the part of the interlayer sacrificial layer located in the core region to form a first gap between two adjacent interlayer dielectric layers; Removing the first barrier sacrificial layer to form a second gap communicating with the first gap between two adjacent interlayer dielectric layers; Filling the first gap and the second gap with gate material to form the gate layer.

12. The manufacturing method of the semiconductor device according to claim 11, wherein, Replacing a part of the interlayer sacrificial layer located in the connection region with a first barrier sacrificial layer through the gate line gap includes: Forming a gap sacrificial layer in the gate line gap; Removing the part of the gap sacrificial layer located in the connection region; Replacing a part of the interlayer sacrificial layer located in the connection region with a second barrier sacrificial layer; Removing the part of the gap sacrificial layer located in the core region and the second barrier sacrificial layer to expose the gate line gap and form a third gap located in the connection region between two adjacent interlayer dielectric layers; and Forming the first barrier sacrificial layer in the third gap.

13. The method for manufacturing a semiconductor device according to claim 12, wherein, Replacing a part of the interlayer sacrificial layer located in the connection region with a second barrier sacrificial layer includes: Removing a part of the interlayer sacrificial layer located in the connection region through a part of the gate line gap located in the connection region to form a fourth gap; and Depositing a barrier sacrificial material in the part of the gate line gap located in the connection region to form the second barrier sacrificial layer in the fourth gap.

14. The method for manufacturing a semiconductor device according to claim 12, wherein, Forming the first barrier sacrificial layer in the third gap includes: Depositing a barrier sacrificial material through the gate line gap to form the first barrier sacrificial layer in the third gap; and Removing the barrier sacrificial material deposited on the inner wall of the gate line gap.

15. The method for preparing a semiconductor device according to any one of claims 9 to 14, wherein, Processing the part of the interlayer dielectric layer protruding from the interlayer sacrificial layer includes: Etching the part of the interlayer dielectric layer protruding from the interlayer sacrificial layer so that the part of the interlayer dielectric layer protruding from the interlayer sacrificial layer has different thicknesses in the third direction.

16. The method for manufacturing a semiconductor device according to claim 15, wherein, In the third direction, the thickness of the part of the interlayer dielectric layer protruding from the interlayer sacrificial layer gradually increases in the direction away from the gate line gap.

17. The method for manufacturing a semiconductor device according to claim 16, wherein, The size of the part of the interlayer dielectric layer protruding from the interlayer sacrificial layer in the third direction is less than 20 nm.

18. The method for manufacturing a semiconductor device according to claim 16, wherein, The difference between the maximum thickness and the minimum thickness of the part of the interlayer dielectric layer protruding from the interlayer sacrificial layer is 6 nm to 8 nm.

19. A storage system, characterized in that, The storage system includes a controller and the semiconductor device according to any one of claims 1 to 8, the controller being coupled to the semiconductor device and configured to control the semiconductor device to store data.

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