Heterojunction bipolar transistor, radio frequency module and communication equipment

Abstract

The heterojunction bipolar transistor provided by the embodiment of the invention comprises a device main body and a first dielectric structure, and the device main body comprises a semiconductor lamination layer, emitter metal, base metal, a first passivation layer and first metal; the base metal comprises a finger part which is adjacent to the emitter step along the first direction and is arranged at an interval; a first passivation layer covering the emitter metal, the base metal, and the semiconductor stack; the first passivation layer is provided with a first opening; the second metal is connected with the emitter metal through the first opening; the second metal comprises a connecting part connected with the emitting electrode metal and an extending part located on the connecting part, and in the first direction, the extending part extends to the position above the finger part, and an interval space is formed between the extending part and the part, covering the finger part, of the first passivation layer; wherein the first dielectric structure covers the device main body and fills the interval space. The heterojunction bipolar transistor, the radio frequency component and the communication equipment provided by the embodiment of the invention have the characteristic of smaller parasitic capacitance.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular, to a heterojunction bipolar transistor, a radio frequency module, and a communication device. Background Art

[0002] As the operating frequency of radio frequency amplifiers gets higher and higher, the influence of parasitic capacitance in HBT (Heterojunction Bipolar Transistor) products on performance becomes greater and greater. In the existing HBT process, the metal trace led out from the emitter crosses the base metal when connecting to the emitter metal, so a large parasitic capacitance will be generated between the emitter trace metal and the base metal. Summary of the Invention

[0003] Therefore, to overcome the problem of large parasitic capacitance in heterojunction bipolar transistors in the prior art, embodiments of the present invention provide a heterojunction bipolar transistor, a radio frequency module, and a communication device, which can reduce the parasitic capacitance through a first dielectric structure and improve the device performance.

[0004] An embodiment of the present invention provides a heterojunction bipolar transistor, including: a device body and a first dielectric structure. The device body includes: a semiconductor stack having a first surface, and an emitter step protruding from the first surface; an emitter metal disposed on the emitter step; a first metal including a base metal, at least a part of the base metal being disposed above the first surface and connected to the semiconductor stack; the base metal includes fingers, the fingers being adjacent to and spaced apart from the emitter step along a first direction; a first passivation layer covering the emitter metal, the base metal, and the semiconductor stack; the first passivation layer having a first opening; a second metal connected to the emitter metal through the first opening; the second metal includes a connection part connected to the emitter metal and an extension part located above the connection part, along the first direction, the extension part extends above the fingers and a gap space is formed between the extension part and a part of the first passivation layer covering the fingers; wherein, the first dielectric structure covers the device body and fills the gap space.

[0005] An embodiment of the present invention further provides a radio frequency module including the foregoing heterojunction bipolar transistor. [[ID=2?]]

[0006] An embodiment of the present invention further provides a communication device including the foregoing radio frequency module.

[0007] The above embodiments of the present invention have at least one or more of the following beneficial effects: By setting the second metal into two parts, namely a connecting part and an extending part, and forming a spaced space between the part of the extending part located above the base metal and the first passivation layer covering the finger part, the distance between the second metal and the base metal below it can be increased; and by arranging the first dielectric structure to fill the spaced space, the parasitic capacitance between the second metal and the base metal below it can be reduced, and the extending part can be supported by the first dielectric structure, thereby improving the device performance and structural stability of the heterojunction bipolar transistor. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The following will describe in detail the specific embodiments of the present invention with reference to the drawings.

[0009] Figure 1a It is a top view structural schematic diagram of a device body in a heterojunction bipolar transistor provided by an embodiment of the present invention.

[0010] Figure 1b It is a top view structural schematic diagram of a device body in another heterojunction bipolar transistor provided by an embodiment of the present invention.

[0011] Figure 1c It is Figure 1b a top view structural schematic diagram of the second metal 51 in

[0012] Figure 2a It is a cross-sectional structural schematic diagram corresponding to the A-A cross-section of a heterojunction bipolar transistor provided by an embodiment of the present invention and Figure 1a in

[0013] Figure 2b It is a cross-sectional structural schematic diagram corresponding to the A-A cross-section of another embodiment of a heterojunction bipolar transistor and Figure 1a in

[0014] Figure 2c It is a cross-sectional structural schematic diagram corresponding to the A-A cross-section of yet another embodiment of a heterojunction bipolar transistor and Figure 1a in

[0015] Figure 3 It is Figure 2a a schematic diagram of a modified embodiment of

[0016] Figure 4a It is a cross-sectional schematic diagram corresponding to the B-B cross-section of a heterojunction bipolar transistor provided by an embodiment of the present invention and Figure 1a in

[0017] Figure 4b It is a cross-sectional schematic diagram corresponding to the B-B cross-section of another embodiment of a heterojunction bipolar transistor and Figure 1a in

[0018] Figure 4c AND of heterojunction bipolar transistor Figure 1a Schematic cross-sectional view of another embodiment corresponding to the B-B cross-section.

[0019] Figure 5 is Figure 3 Partial enlarged schematic view of region C.

[0020] Figure 6 Schematic structural view corresponding to the B-B cross-section under a step of the method for manufacturing a heterojunction bipolar transistor provided by an embodiment of the present invention.

[0021] Figure 7 is Figure 6 Schematic structural view corresponding to the B-B cross-section under a step after the step shown.

[0022] Figure 8 is Figure 7 Schematic structural view corresponding to the A-A cross-section under the step shown.

[0023] Figure 9 is Figure 7 Schematic structural view corresponding to the B-B cross-section under a step after the step shown.

[0024] Figure 10 is Figure 9 Schematic structural view corresponding to the A-A cross-section under the step shown.

[0025] Figure 11 is Figure 9 Schematic structural view corresponding to the B-B cross-section under a step after the step shown.

[0026] Figure 12 is Figure 11 Schematic structural view corresponding to the A-A cross-section under the step shown.

[0027] Figure 13 is Figure 11 Schematic structural view corresponding to the B-B cross-section under a step after the step shown.

[0028] Figure 14 is Figure 13 Schematic structural view corresponding to the A-A cross-section under the step shown.

[0029]

Description of the reference numerals

[0030] 100, device main body; 10, semiconductor stack; 11, base region step; 111, collector layer; 112, base layer; 113, emitter layer; 114, step side; 1141, first side; 1142, second side; 1143, third side; 1144, fourth side; 115, recess; 12, first surface; 13, second surface; 14, substrate; 15, sub-collector layer; 16, emitter step; 20, emitter metal; 31, first passivation layer; 311, first opening; 312, second opening; 32, second passivation layer; 33, third passivation layer; 331, third opening; 332, fourth opening; 34, fourth passivation layer; 40, first metal; 41, base metal; 411, end; 4111, first extension; 4112, second extension; 4113, third extension; 412, finger; 4121, first finger; 4122, second finger; 4123, intermediate finger; 413, first end face; 42, connecting metal; 51, second metal; 511, connecting part; 512, extension; 513, drainage part; 60, spacer; 70, collector metal; 80, second dielectric structure; 81, outer surface; 200, first dielectric structure; 301, dielectric material layer; 302, first photoresist; 303, second photoresist; 304, third photoresist. Detailed implementation manners

[0031] To make the above objects, features, and advantages of the present invention more apparent and understandable, the following provides a detailed description of the specific implementation manners of the present invention with reference to the accompanying drawings.

[0032] To enable those of ordinary skill in the art to better understand the technical solutions of the present invention, the following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0033] It should be noted that the terms "first", "second", etc. in the description and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that the terms used in this way are interchangeable where appropriate so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0034] It should also be noted that the division of multiple embodiments in the present invention is only for the convenience of description and should not constitute a special limitation. The features in various embodiments can be combined and referenced to each other without contradiction.

[0035] An embodiment of the present invention provides a heterojunction bipolar transistor, comprising: a device body 100 and a first dielectric structure 200. In order to more clearly illustrate the main structure of the heterojunction bipolar transistor provided in this embodiment, Figure 1a Only part of the structure of the device body 100 is shown, and the first passivation layer 31 is made transparent. In order to facilitate the distinction of the boundaries of each structure, the pattern of the base metal 41 is filled. In addition, although the second metal 51 and the connecting metal 42 are located above the base metal, they are represented by dotted lines, and the structure covered by the second metal 51 and the connecting metal 42 is still represented by solid lines. Figures 2a to 4a , a cross-sectional view of a heterojunction bipolar transistor including a device body 100 and a first dielectric structure 200 is shown. Figure 2a , Figure 2b and Figure 2c and Figure 1a The position of the AA section is the same. Figure 3 for Figure 2a A variation of Figure 4a , Figure 4b and Figure 4c and Figure 1a The positions of the BB sections are the same, wherein the Y direction is the first direction and the X direction is the second direction.

[0036] Reference Figure 1a and Figure 2a, the device body 100 includes: a semiconductor stack 10, an emitter metal 20, a first metal 40, a first passivation layer 31, and a second metal 51. The semiconductor stack 10 has a first surface 12. The semiconductor stack 10 includes an emitter step 16 protruding from the first surface 12. The emitter metal 20 is disposed on the emitter step 16. The first metal 40 includes a base metal 41, and at least a part of the base metal 41 is disposed above the first surface 12 and connected to the semiconductor stack 10. The base metal 41 includes finger portions 412, and the finger portions 412 are adjacent to and spaced from the emitter step 16 along a first direction. The first passivation layer 31 covers the emitter metal 20, the base metal 41, and the semiconductor stack 10. The first passivation layer 31 has a first opening 311. The second metal 51 is connected to the emitter metal 20 through the first opening 311. The second metal 51 includes a connection portion 511 connected to the emitter metal 20 and an extension portion 512 located above the connection portion 511. Along the first direction, the extension portion 512 extends above the finger portions 412 and forms a spaced-apart space 60 between the portion of the first passivation layer 31 covering the finger portions 412. A first dielectric structure 200 covers the device body 100 and fills the spaced-apart space 60.

[0037] Specifically, referring to Figure 2a , in a specific embodiment, the semiconductor stack 10 specifically includes a substrate 14, a sub-collector layer 15, a collector layer 111, a base layer 112, and an emitter layer 113 stacked in sequence, wherein the collector layer 111, the base layer 112, and the emitter layer 113 together form a base region step 11. The first surface 12 is also the surface on the side of the base region step 11 away from the substrate 14 (which can be simply referred to as the upper surface of the base region step 11), that is, the surface on the side of the emitter layer 113 away from the base layer 112 (which can be simply referred to as the upper surface of the emitter layer 113). The semiconductor stack 10 (base region step 11) also has a step side surface 114 adjacent to the first surface 12, and the number of step side surfaces 114 is multiple. For example, Figure 1a shows a third side surface 1143 and a fourth side surface 1144 opposite to each other along the first direction (Y direction), and a first side surface 1141 and a second side surface 1142 opposite to each other along the second direction (X direction). The multiple step side surfaces 114 are, for example, inclined with respect to the first surface 12. Depressions 115 located on the collector layer 111 are respectively formed on the multiple step side surfaces 114. The semiconductor stack 10 also has a second surface 13 exposed to the base region step 11. As Figure 2a shown, the second surface 13 is the surface of the sub-collector layer 15 away from the substrate 14. In some embodiments, an etch stop layer is further disposed between the sub-collector layer 15 and the base region step 11, and the second surface 13 is the surface of the etch stop layer away from the sub-collector layer 15. Collector metals 70 are further disposed on opposite sides of the base region step 11 along the first direction and are connected to the sub-collector layer 15.

[0038] The material of the substrate 14 can be, for example, a group III-V semiconductor, such as any one or a combination of GaN, AlGaN, AlN, GaAs, AlGaAs, InP, InGaAs, InAlAs.

[0039] The sub-collector layer 15 can be, for example, a group III-V semiconductor, which may include group III-V semiconductors, such as any one or a combination of GaN, AlGaN, AlN, GaAs, AlGaAs, InP, InGaAs, InAlAs.

[0040] The etch stop layer can be, for example, a group III-V semiconductor, such as any one or a combination of InGaP, InGaAs, GaAsP, AlGaAs, InAlAs, GaSb.

[0041] The collector layer 111 can be, for example, a group III-V semiconductor, such as any one or a combination of GaN, AlGaN, AlN, GaAs, AlGaAs, InP, InGaAs, InAlAs.

[0042] The base layer 112 can be, for example, a group III-V semiconductor, such as any one or a combination of GaN, AlGaN, AlN, GaAs, AlGaAs, InP, InGaAs, InAlAs.

[0043] The emitter layer 113 can be, for example, a group III-V semiconductor, such as any one or a combination of GaN, AlGaN, AlN, GaAs, AlGaAs, InP, InGaAs, InAlAs, InGaP. The emitter layer 113 can be a multi-layer structure.

[0044] Among them, the doping types of the sub-collector layer 15, the collector layer 111, and the emitter layer 113 are the first doping type, and the doping type of the base layer 112 is the second doping type. When the first doping type is n-type, the second doping type is p-type. When the first doping type is p-type, the second doping type is n-type.

[0045] The emitter step 16 can be multi-layer, for example, including a layer of InGaAs layer and a layer of GaAs layer. Among them, the InGaAs layer is the cap layer for making the emitter metal ohmic contact; the GaAs layer is used to solve the lattice matching problem between InGaAs in the cap layer and InGaP in the emitter layer. The emitter metal 20 can be a conductive metal such as Ti, Pt, Au, Al, Cu, W, Ni, Ge, such as Figure 1a and Figure 2aThe width of the emitter metal 20 shown may not be equal to the width of the emitter step 16. Of course, in some embodiments, the width of the emitter metal 20 may be equal to the width of the emitter step 16.

[0046] The base metal 41 may be a multi-layer metal of a Pt / Ti / Pt / Au / Ti stack. In some embodiments, the thickness of the base metal 41 (i.e., the distance between the top surface of the base metal 41 and the first surface 12) is greater than the sum of the thicknesses of the emitter step 16 and the emitter metal 20 (i.e., the distance between the top surface of the emitter metal 20 and the first surface 12). Specifically, the thickness of the finger portion 412 is greater than the sum of the thicknesses of the emitter step 16 and the emitter metal 20. Of course, in some embodiments, the thickness of the base metal 41 may also be less than the sum of the thicknesses of the emitter step 16 and the emitter metal 20. In some embodiments, a fourth passivation layer 34 is further provided between the base metal 41 and the first surface 12. Specifically, the fourth passivation layer 34 has a portion covering the top of the emitter metal 20, a portion covering the sides of the emitter step 16 and the emitter metal 20, and a portion covering the portion of the first surface 12 exposed outside the emitter step 16 and the base metal 41. The base metal 41 can be connected to the base layer 112 by alloying with the emitter layer 113 through the fourth passivation layer 34. Or the base metal 41 can be connected to the base layer 112 through an opening in the fourth passivation layer 34 and the emitter layer 113. The base metal 41 includes, for example, a plurality of finger portions 412 and an end portion 411 connecting the plurality of finger portions 412. As Figure 1a shown, the base metal 41 includes three finger portions 412 and an end portion 411 connected to the ends of the three finger portions 412. Among them, the plurality of finger portions 412 are adjacent to and spaced from the emitter step 16 in the first direction, and the plurality of finger portions 412 and the emitter step 16 both extend in the second direction. Refer to Figure 3 , in some embodiments, a heterojunction bipolar transistor may also include only one emitter step 16, and the base metal 41 includes two finger portions 412 disposed on opposite sides of the emitter step 16 in the first direction. The fourth passivation layer 34 further covers, for example, the top surface of the emitter metal 20 and the sides of the emitter metal 20 and the emitter step. The fourth passivation layer 34 can be any one or a combination of insulating materials such as SiN, Si3N4, Si2N3, SiO2, SiON, Al2O3, AlN, BCB (benzocyclobutene). The thickness of the fourth passivation layer 34 is 100 to 1000 angstroms.

[0047] The first passivation layer 31 can be any one or a combination of insulating materials such as SiN, Si3N4, Si2N3, SiO2, SiON, Al2O3, AlN, BCB (benzocyclobutene), etc. The thickness of the first passivation layer 31 is 100 to 3000 angstroms. The first passivation layer 31 has a portion located on top of the base metal 41 and the emitter metal 20, a portion located on one side of the base metal 41, the emitter step 16, the emitter metal 20, and the step side 114, a portion covering the collector metal 70, and portions located above the first surface 12 and above the second surface 13. As Figure 2a or Figure 3 shown in the orientation, the extension portion 512 extends at both ends in the first direction to above the two outermost opposite finger portions 412 in the first direction. And a gap space 60 is formed by suspending the extension portion 512 from any one of the finger portions 412 located below it. The width of the extension portion 512 in the first direction can be greater than the maximum distance between the two outermost opposite finger portions 412 in the first direction, that is, the extension portion 512 can extend in the first direction and extend beyond the finger portion 412 at the outermost edge.

[0048] By forming the gap space 60, the gap distance between the second metal 51 and the base metal 41 can be increased, and the parasitic capacitance between the second metal 51 and the base metal 41 can be reduced. The second metal 51 can be a multi-layer metal of a Ti / Pt / Au stack. In some embodiments, the extension portion 512 can also extend in the second direction to above the end portion 411, and a gap space 60 is formed between the extension portion 512 and the portion of the first passivation layer 31 covering the end portion 411.

[0049] The first dielectric structure 200 can be, for example, a low dielectric constant polymer organic material such as PI (polyimide) or PBO (polybenzoxazole). The dielectric constant of the first dielectric structure 200 is 0 to 10 F / m (Faraday / meter). For example, the dielectric constant of the first dielectric structure 200 can be 2.5 to 4.0 F / m, more specifically, for example, 2.5 to 2.7 F / m or 3.0 to 4.0 F / m. As Figure 2aAs shown, the first dielectric structure 200 extends from the portion of the first passivation layer 31 covering the second surface 13 in a direction gradually away from the substrate 14 to above the top of the second metal 51 to cover the entire portion of the device body 100 above the second surface 13. That is, the first dielectric structure 200 not only covers the top of the second metal 51, but also covers the side surfaces of the second metal 51 and fills the spacer 60. By filling the spacer 60 with the first dielectric structure 200, the parasitic capacitance between the second metal 51 and the base metal 41 can be reduced, improving the performance of the heterojunction bipolar transistor. Moreover, the first dielectric structure 200 can support the suspended portion of the extension 512, ensuring the structural stability. At the same time, the first dielectric structure 200 covering the entire device body 100 can also planarize the surface of the device body 100.

[0050] In some embodiments, the thickness of the first dielectric structure 200 above the second metal 51 layer is 0.1 to 1 micron. This can achieve the planarization of the surface of the heterojunction bipolar transistor and facilitate subsequent processes to open an opening in the first dielectric structure 200 to connect the second metal 51 to an external structure.

[0051] In some embodiments, a second passivation layer 32 is further provided between the first dielectric structure 200 and the device body 100. That is, the second passivation layer 32 covers the surface of the second metal 51 and also covers the portion of the device body 100 exposed outside the connection between the second metal 51 and the emitter metal 20. The material of the second passivation layer 32 can be set with reference to the material of the first passivation layer 31, and the second passivation layer 32 can include a single-layer or multi-layer material layer. The thickness range of the second passivation layer 32 is 0.01 to 0.3 micron.

[0052] In some embodiments, the height range of the spacer 60 is 0.2 to 1 micron. As Figure 2a and Figure 3 shown, the height of the spacer 60 is the maximum distance between the side of the extension 512 facing the base metal 41 and the portion of the first passivation layer 31 covering the finger 412, which can also be referred to as the suspended height. Selecting an appropriate height for the spacer 60 can ensure a good effect of reducing the parasitic capacitance while ensuring the structural stability of the second metal 51.

[0053] In some embodiments, the thickness of the extension 512 is less than the thickness of the connection portion 511. As Figure 2a and Figure 3 shown, the thickness of the connection portion 511 is D1, and the thickness of the extension 512 is D2, where D2 is less than D1, which can ensure the stability of the second metal 51 and is not easily damaged during the manufacturing process. Referring to Figure 2a , by setting the thicknesses of the extension 512 and the connection portion 511 within a suitable range, it is possible to prevent, as Figure 2aThe arched part of the middle extension 512 located above the middle finger part 4123 is broken.

[0054] In some embodiments, along the first direction, the distance between the edge of the extension 512 and the edge of the connecting part 511 on the same side is 0.1 - 5 microns. Refer to Figure 2a and Figure 3 , taking the edge of the extension 512 close to the fourth side 1144 and the edge of the connecting part 511 close to the fourth side 1144 as an example, the distance between the two along the first direction is marked as D3, that is, the range of D3 is 0.1 - 5 microns.

[0055] In some embodiments, along the first direction, the distance between the edge of the extension 512 and the edge of the connecting part 511 on the same side is less than or equal to 5 times the thickness of the extension 512, that is, D3 is less than 5 times D2. In some embodiments, D3 is less than 2 times D2. This can prevent the overlong suspended part of the extension 512 suspended above the finger part 412 from breaking.

[0056] In some embodiments, the width of the connecting part 511 along the first direction gradually increases in the direction away from the emitter metal 20. That is, the side surface of the connecting part 511 is inclined. In some embodiments, an arc surface transition can be adopted between the bottom surface of the connecting part 511 and the extension 512. In some embodiments, the inclination angle range of the side surface of the connecting part 511 is 0 - 45°, refer to Figure 14 , the inclination angle of the side surface of the connecting part 511 is the included angle between the connecting part 511 and the vertical direction, that is, Figure 14 the angle α in. The inclined side surface of the connecting part 511 can increase the connection area between the connecting part 511 and the extension, enhance the overall structural stability of the second metal 51, and ensure a small contact area between the connecting part 511 and the emitter metal 20.

[0057] In some embodiments, refer to Figure 4a , the first metal 40 further includes a connecting metal 42. The semiconductor stack 10 has a first side surface 1141 and a second side surface 1142 adjacent to the first surface 12 and opposite to each other along the second direction. The first passivation layer 31 has a second opening 312 located above the base metal 41. The connecting metal 42 is connected to the base metal 41 through the second opening 312. Specifically, the connecting metal 42 is connected to the end 411 of the base metal 41. The first dielectric structure 200 and the second passivation layer 32 also cover the connecting metal 42.

[0058] In some embodiments, the device body 100 further includes a third passivation layer 33, and the third passivation layer 33 covers the emitter step 16 and the semiconductor stack 10.

[0059] In some embodiments, such as Figure 4aAs shown, the base metal 41 is entirely located above the first surface 12. At this time, the connecting metal 42 also extends beyond the portion of the first passivation layer 31 covering the first side surface 1141.

[0060] In some embodiments, as Figure 4b shown, the end portion 411 of the base metal 41 includes a first extension portion 4111, a second extension portion 4112, and a third extension portion 4113 connected in sequence. The first extension portion 4111 is located above the base region step 11. The second extension portion 4112 is located outside the first side surface 1141. The third extension portion 4113 is located above the portion of the third passivation layer 33 covering the second surface 13. At this time, the second opening 312 is located above the third extension portion 4113.

[0061] In some embodiments, the device body 100 further includes a second dielectric structure 80, and the second dielectric structure 80 is at least located between the first passivation layer 31 and the first side surface 1141. For example, the second dielectric structure 80 can be located Figure 4a between the portion of the first passivation layer 31 covered by the connecting metal 42 and the first side surface 1141, or can be located Figure 4b between the second extension portion 4112 and the first side surface 1141. In some embodiments, referring to Figure 4c , the second dielectric structure 80 can also be located between the first passivation layer 31 and the second side surface 1142. In some embodiments, referring to Figure 2b or Figure 2c , the second dielectric structure 80 can also be located between the first passivation layer 31 and the third side surface 1143 and / or between the first passivation layer 31 and the fourth side surface 1144; that is, in some embodiments, the second dielectric structure 80 can be disposed around one or more of the plurality of step side surfaces 114 of the base region step 11. The material of the second dielectric structure 80 can be set with reference to the material of the first dielectric structure 200. In some embodiments, the second dielectric structure 80 can be air, that is, the second dielectric structure 80 is a hollow structure, and the portion of the first passivation layer 31 located outside the step side surface 114 and the third passivation layer 33 are at least partially spaced apart. The second dielectric structure 80 is located between the connecting metal 42 and the base region step 11, which can reduce the parasitic capacitance between the connecting metal 42 and the high-concentration epitaxial layer material of the base region step 11, and further improve the performance of the heterojunction bipolar transistor. In some embodiments, the second dielectric structure 80 has an outer surface 81 facing away from the first side surface 1141, and the maximum distance D4 between the outer surface 81 and the first side surface 1141 is less than 30 microns. Specifically, the range of D4 is 1 to 30 microns. When the second dielectric structure 80 is located outside the second side surface 1142, in some embodiments, the second metal 51 can be led out along the second side surface 1142, and the parasitic capacitance between the second metal 51 and the base region step 11 can also be reduced at this time.

[0062] In some embodiments, the second dielectric structure 80 at least partially extends over the semiconductor stack 10, which can also reduce the parasitic capacitance between the connecting metal 42 and the first surface 12. In some embodiments, referring to Figure 5 The thickness D5 of the portion of the second dielectric structure 80 located above the semiconductor stack 10 ranges from 0.01 to 2 micrometers. The selection of the thickness D5 can ensure the reduction of the parasitic capacitance between the connecting metal 42 and the first surface 12 while avoiding an excessive thickness that would cause an overly large slope for the connecting metal 42 to extend over the second dielectric structure 80, and can ensure the strength of the connecting metal 42. In other embodiments, referring to Figure 2b and Figure 4c , in some embodiments, the height of the second dielectric structure 80 can be lower than the height of the base region step 11, that is, the top surface of the second dielectric structure 80 is below the first surface 12.

[0063] In some embodiments, the base metal 41 at least partially extends over the second dielectric structure 80. Specifically, as Figure 2b shown, the finger portion 412 includes a first finger portion 4121 and a second finger portion 4122 located at opposite ends of the end portion 411 along the first direction, and an intermediate finger portion 4123 located between the first finger portion 4121 and the second finger portion 4122. In some embodiments, a part of the first finger portion 4121 extends over the second dielectric structure 80 located outside the third side surface 1143. In some embodiments, a part of the second finger portion 4122 extends over the second dielectric structure 80 located outside the fourth side surface 1144. Referring to Figure 4b , the first extension portion 4111 of the end portion 411 extends over the second dielectric structure 80 located outside the first side surface 1141. Since the second dielectric structure 80 has a portion located outside the base region step 11, when the base metal 41 extends over the second dielectric structure 80, it can extend beyond the edge of the base region step 11. For the base metal 41 of the same area, as Figures 4a to 4c shown in the embodiment, the width of the base region step 11 along the second direction can be set smaller than the conventional base region step width. For the base metal 41 of the same area, as Figure 2b and Figure 2c shown in the embodiment, the width of the base region step 11 along the first direction can be set smaller than the conventional base region step width. Therefore, the BC junction capacitance can be reduced, and the performance of the heterojunction bipolar transistor can be further improved. And as Figure 2b shown in the embodiment, when the width remains unchanged, the widths of the first finger portion 4121 and the second finger portion 4122 located above the base region step 11 are smaller, which can also reduce the area of the base region step 11 and reduce the BC junction capacitance.

[0064] The portion of the base metal 41 extending over the second dielectric structure 80 has a first end face 413 located between the first side face 1141 and the second dielectric structure 80 in the second direction. That is, in some embodiments, the base metal 41 extends beyond the edge of the base region step 11 and does not extend beyond the edge of the second dielectric structure 80. Refer to Figure 6 , the maximum distance D6 between the first end face 413 and the first side face 1141 in the second direction does not exceed 30 micrometers.

[0065] In some embodiments, the second opening 312 in the first passivation layer 31 is located in the portion where the base metal 41 extends over the second dielectric structure 80. That is, the connection portion of the connecting metal 42 and the base metal 41 is located over the second dielectric structure 80, which can reduce the parasitic capacitance.

[0066] In some embodiments, the third passivation layer 33 has a third opening 331 located on the first surface 12 and a fourth opening 332 communicating with the first opening 311. The second metal 51 passes through the first opening 311 and the fourth opening 332 to connect with the emitter metal 20. The base metal 41 passes through the third opening 331 to connect with the semiconductor stack 10; the second dielectric structure 80 is located between the third passivation layer 33 and the first passivation layer 31. Specifically, the third passivation layer 33 covers the fourth passivation layer 34 and extends to cover the side face of the step 114 and the second surface 13. The collector metal 70 is connected to the sub-collector layer 15 through the opening in the third passivation layer 33 and the opening in the etch stop layer. The material of the third passivation layer 33 can be set with reference to the material of the first passivation layer 31. The thickness of the third passivation layer 33 is 100 - 1000 angstroms.

[0067] The following refers to Figures 6 to 14 to illustrate by way of example the manufacturing method of a heterojunction bipolar transistor provided by a specific embodiment of the present invention. Among them Figure 6 、 Figure 7 、 Figure 9 、 Figure 11 、Figure 1 and Figure 4a are of the same perspective, Figure 8 、 Figure 10 、 Figure 12 、 Figure 14 and Figure 3 are of the same perspective.

[0068] As Figure 6 shown, first, a dielectric material layer 301 is formed on the base structure, and the dielectric material layer 301 is etched using the first photoresist 302. The base structure includes a semiconductor stack 10, an emitter step 16 protruding on the first surface 12 of the semiconductor stack 10, and an emitter metal 20 ( Figure 6The middle emitter step 16 and the emitter metal 20 are blocked by the dielectric material layer 301), as well as the fourth passivation layer 34 and the third passivation layer 33. The dielectric material layer 301 extends from the portion of the third passivation layer 33 covering the second surface 13 in a direction gradually away from the substrate 14 to above the top of the base structure. The first photoresist 302 has two opposite edges in the second direction located on opposite sides of the first side surface 1141 in the second direction respectively, so that after etching is completed, the Figure 7 and Figure 8 shown structure is obtained. The dielectric material layer 301 is etched to form the second dielectric structure 80. By setting the shape and position of the first photoresist 302 during etching, the second dielectric structure 80 is located outside the first side surface 1141 and partially extends above the semiconductor stack 10. The dielectric material layer 301 is a low dielectric constant dielectric material such as PI or PBO. It is difficult to make small-size openings for this type of material. In this embodiment, the dielectric material layer 301 is etched by the first photoresist 302 so that the dielectric material layer 301 can be opened in a large area, which can avoid the process difficulties of small-size openings and is convenient for implementation.

[0069] Referring to Figure 9 and Figure 10 , then openings are made in corresponding positions of the third passivation layer 33 and the fourth passivation layer 34, and a metal material is deposited to form the base metal 41 and the collector metal 70, so that the base metal 41 is connected to the semiconductor stack 10 and partially extends above the second dielectric structure 80, and the collector metal 70 is connected to the sub-collector layer 15. Then the first passivation layer 31 is covered again, so that the first passivation layer 31 covers the third passivation layer 33, covers the base metal 41, and covers the collector metal 70.

[0070] Referring to Figure 11 and Figure 12 , the first passivation layer 31 is opened through the second photoresist 303 to form the first opening 311 and the second opening 312. At the same time, the fourth opening 332 and the fifth opening communicating with the first opening 311 are opened in the third passivation layer 33 and the fourth passivation layer 34.

[0071] Then at Figure 13 and Figure 14In the steps shown, without removing the second photoresist 303, a third photoresist 304 is formed on the second photoresist 303, and a second metal 51 is formed through steps such as photolithography, development, and evaporation. The portion of the second metal 51 within the opening of the second photoresist 303 forms a connection portion 511, and the portion of the second metal 51 above the second photoresist 303 and within the opening of the third photoresist 304 forms an extension portion 512. The extension portion 512 extends along a first direction above the finger portion 412. In this embodiment, without removing the second photoresist 303 before forming the second metal 51, the second photoresist 303 can be used as a support for the extension portion 512, fewer photoresists can be used, and the process flow can be simplified.

[0072] Then, the second photoresist 303 and the third photoresist 304 are removed, and a spacer space 60 is formed between the extension portion 512 and the first passivation layer 31 covering the top of the finger portion 412. Then, a connection metal 42 is evaporated such that the connection metal 42 is connected to the base metal 41 through the second opening 312 and extends to the side of the second dielectric structure 80 away from the first side 1141. The device body 100 is obtained. Finally, a second passivation layer 32 and a first dielectric structure 200 are fabricated on the device body 100 such that the second passivation layer 32 covers the surfaces of the first passivation layer 31, the second metal 51, and the connection metal 42. The first dielectric structure 200 covers the second passivation layer 32 and extends from the portion of the second passivation layer 32 covering the second surface 13 in a direction gradually away from the substrate 14 to above the top of the second metal 51 covered by the second passivation layer 32. The first dielectric structure 200 can fill the spacer space 60, which can reduce the parasitic capacitance between the second metal 51 and the base metal 41 located below the second metal 51. At the same time, the first dielectric structure 200 can also provide support for the extension portion 512 to ensure the structural stability. In subsequent processes, openings can also be made in the portions of the first dielectric structure 200 and the second passivation layer 32 covering the second metal 51 to achieve the connection of the second metal 51 to an external structure.

[0073] In some embodiments, referring to Figure 1b and Figure 1c , a drainage portion urchased 513 communicating with the spacer space 60 is provided in the second metal 51. In the shape of the orthographic projection of the second metal 51 on the first surface 12 (i.e., in the top view of the second metal 51), the drainage portion 513 extends along the first direction. The drainage portion 513 can be a through hole penetrating from bottom to top (along the stacking direction of the emitter step 16 and the emitter metal 20). In some embodiments, the drainage portion 513 can be in the shape of a notch with an opening at one end along the first direction. By providing the drainage portion 513, in the process of subsequently forming the first dielectric structure 200, the material of the first dielectric structure 200 can be better filled into the spacer space 60 through the drainage portion 513.

[0074] The number of the drainage parts 513 can be one or more. When the number of the drainage parts 513 is multiple, the multiple drainage parts 513 are arranged at intervals along the second direction. In some embodiments, when the drainage part 513 is in the shape of a notch as shown in Figure 1b , the opening directions of the adjacent drainage parts 513 along the second direction are opposite, which can ensure the stability of the overall structure of the second metal 51.

[0075] In some embodiments, the total area of the region where the orthographic projection pattern of the drainage part 513 on the top surface of the emitter metal 20 intersects with the top surface of the emitter metal 20 (corresponding to Figure 1b the total area of the 4 right-slanted line filled regions in the figure) is S1, and the contact area between the connecting part 511 and the emitter metal 20 is S2. The ratio of S1 to S2 is less than or equal to 50%, which can ensure the drainage effect of the drainage part 513 and the stability of the second metal 51.

[0076] In some embodiments, the orthographic projection of the drainage part 513 on the first surface 12 is located between the two opposite edges of the orthographic projection of the emitter metal 20 on the first surface 12 along the second direction. In some embodiments, referring to Figure 1b , the minimum distance D7 between the drainage part 513 and the edge of the emitter metal 20 along the second direction is greater than or equal to 1 micron.

[0077] Some embodiments of the present invention further provide a radio frequency module, including the heterojunction bipolar transistor provided in any of the foregoing embodiments or the heterojunction bipolar transistor prepared by the preparation method of the heterojunction bipolar transistor provided in any of the above embodiments. The radio frequency module is, for example, an integrated radio frequency switch, a filter, etc. The radio frequency module provided in this embodiment has at least the same effect as the heterojunction bipolar transistor, which will not be elaborated here.

[0078] Some embodiments of the present invention further provide a communication device, including the foregoing radio frequency module. The communication device can be, for example, a mobile phone, a WiFi wireless router device, etc. It has at least the same effect as the foregoing heterojunction bipolar transistor, which will not be elaborated here.

[0079] The above is only a preferred embodiment of the present invention and does not impose any form of limitation on the present invention. Although the present invention has been disclosed above with the preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can make some changes or modifications to the equivalent embodiments by using the disclosed technical content within the scope of the technical solution of the present invention. However, as long as it does not depart from the content of the technical solution of the present invention, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention still fall within the scope of the technical solution of the present invention.

Claims

1. A heterojunction bipolar transistor, characterized in that, Comprising: A device body and a first dielectric structure, wherein the device body comprises: A semiconductor stack having a first surface and an emitter step protruding from the first surface; Emitter metal disposed on the emitter step; The first metal includes base metal, and at least part of the base metal is disposed above the first surface and connected to the semiconductor stack; the base metal includes fingers, and the fingers are adjacent to and spaced from the emitter step in a first direction; A first passivation layer covering the emitter metal, the base metal, and the semiconductor stack; the first passivation layer has a first opening; Second metal connected to the emitter metal through the first opening; the second metal includes a connection portion connected to the emitter metal and an extension portion located above the connection portion, and in the first direction, the extension portion extends above the finger and forms a spaced space between the portion of the first passivation layer covering the finger; Wherein, the first dielectric structure covers the device body and fills the spaced space.

2. The heterojunction bipolar transistor according to claim 1, characterized in that, A second passivation layer is further provided between the first dielectric structure and the device body.

3. The heterojunction bipolar transistor according to claim 1, characterized in that, The height of the spaced space is 0.2 to 1 micron.

4. The heterojunction bipolar transistor according to claim 1, wherein The thickness of the extension portion is less than the thickness of the connection portion.

5. The heterojunction bipolar transistor according to claim 1, characterized in that, In the first direction, the distance between the edge of the extension portion and the edge of the connection portion on the same side is 0.1 to 5 microns; and / or, in the first direction, the distance between the edge of the extension portion and the edge of the connection portion on the same side is less than or equal to 5 times the thickness of the extension portion.

6. The heterojunction bipolar transistor according to claim 1, wherein, The width of the connection portion in the first direction gradually increases in a direction away from the emitter metal.

7. The heterojunction bipolar transistor according to claim 1, characterized in that, The thickness of the first dielectric structure above the top of the second metal is 0.1 to 5 microns.

8. The heterojunction bipolar transistor according to claim 2, characterized in that, The thickness of the second passivation layer is 0.1 to 1 micron.

9. The heterojunction bipolar transistor according to claim 1, wherein The first metal further includes connection metal, and the semiconductor stack has a first side surface and a second side surface adjacent to and opposite to the first surface in a second direction; the first passivation layer has a second opening located above the base metal, and the connection metal is connected to the base metal through the second opening.

10. The heterojunction bipolar transistor according to claim 9, wherein The device body further includes a second dielectric structure, and the second dielectric structure is at least located between the first passivation layer and the first side surface.

11. The heterojunction bipolar transistor according to claim 10, wherein The second dielectric structure at least partially extends above the semiconductor stack.

12. The heterojunction bipolar transistor according to claim 10, wherein At least part of the base metal extends above the second dielectric structure.

13. The heterojunction bipolar transistor according to claim 10, wherein, The device body further includes a third passivation layer, the third passivation layer covers the semiconductor stack, the third passivation layer has a third opening located above the first surface and a fourth opening communicating with the first opening, and the second metal passes through the first opening and the fourth opening to be connected to the emitter metal; The base metal passes through the third opening to be connected to the semiconductor stack; the second dielectric structure is located between the third passivation layer and the first passivation layer.

14. The heterojunction bipolar transistor according to claim 10, characterized in that, The second dielectric structure has an outer surface facing away from the first side surface, and the maximum distance between the outer surface and the first side surface is less than 30 microns.

15. The heterojunction bipolar transistor according to claim 11, wherein The thickness range of the portion of the second dielectric structure located above the semiconductor stack is from 0.01 to 2 micrometers.

16. The heterojunction bipolar transistor according to claim 12, characterized in that, The portion of the base metal extending above the second dielectric structure has a first end face located between the first side face and the second dielectric structure along the second direction.

17. A radio frequency module, characterized in that, It includes a heterojunction bipolar transistor according to any one of claims 1 to 16.

18. A communication device, characterized in that, It includes a radio frequency module according to claim 17.

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