Semiconductor device and forming method thereof

Abstract

The invention provides a semiconductor device and a forming method thereof. Some implementations provide semiconductor fabrication techniques and related semiconductor structures for forming p-type metal oxide semiconductor (PMOS) nanostructure transistors and n-type metal oxide semiconductor (NMOS) nanostructure transistors in semiconductor devices. The techniques include forming respective (different) types of gate metals of PMOS nanostructure transistors and maintaining intrinsic NMOS nanostructure transistors of the semiconductor device. A p-type gate metal may be formed around the nanostructured channel of the PMOS nanostructured transistor. A self-assembled monolayer may then be formed on a surface of the p-type gate metal layer. During formation of an n-type gate metal around a nanostructured channel of an NMOS nanostructured transistor, a self-assembled monolayer on a p-type gate metal prevents formation of the n-type gate metal on the p-type gate metal. This results in little no deposition of the n-type gate metal on the p-type gate metal, which minimizes the impact of the p-type threshold voltage on the PMOS nanostructured transistor.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more particularly to semiconductor devices and methods of forming the same. Background Art

[0002] With the progress of semiconductor device manufacturing and the reduction of the size of technology processing nodes, transistors may be affected by short-channel effects (SCEs) such as hot-carrier degradation, barrier lowering, and quantum confinement. Additionally, as the gate length of transistors decreases for smaller technology nodes, source / drain (S / D) electron tunneling increases, which increases the off-current of the transistor (the current flowing through the channel of the transistor when the transistor is in the off configuration). Silicon (Si) / silicon germanium (SiGe) nanostructure transistors (such as nanowires, nanosheets, and gate-all-around (GAA) devices) are potential candidates for overcoming short-channel effects at smaller technology nodes. Relative to other types of transistors, nanostructure transistors are effective structures that may experience reduced SCEs and enhanced carrier mobility. Summary of the Invention

[0003] In one aspect, embodiments of the present application provide a method, including: forming a first plurality of nanostructure channel layers arranged along a direction substantially perpendicular to a semiconductor substrate of a semiconductor device; forming a second plurality of nanostructure channel layers arranged along a direction substantially perpendicular to the semiconductor substrate; forming a first type of metal layer surrounding each of the first plurality of nanostructure channel layers; forming a self-assembled monolayer on the first type of metal layer; and forming a second type of metal layer on the second plurality of nanostructure channel layers, wherein the self-assembled monolayer inhibits the formation of the second type of metal layer on the first type of metal layer.

[0004] In one aspect, embodiments of the present application provide a method, including: forming a first plurality of nanostructure channel layers arranged along a direction substantially perpendicular to a semiconductor substrate of a semiconductor device; forming a second plurality of nanostructure channel layers arranged along a direction substantially perpendicular to the semiconductor substrate; forming a gate dielectric layer surrounding the first plurality of nanostructure channel layers and surrounding the second plurality of nanostructure channel layers; forming a self-assembled monolayer on the gate dielectric layer surrounding the second plurality of nanostructure channel layers; forming a p-type metal layer of a first gate structure on the first plurality of nanostructure channel layers, wherein the material of the self-assembled monolayer inhibits the p-type metal layer from adsorbing on the gate dielectric layer surrounding the second plurality of nanostructure channel layers; and after forming the p-type metal layer, forming an n-type metal layer of a second gate structure on the second plurality of nanostructure channel layers.

[0005] In one aspect, embodiments of the present application provide a semiconductor device, comprising: a first plurality of nanostructured channel layers arranged in a direction substantially perpendicular to a semiconductor substrate of the semiconductor device; a second plurality of nanostructured channel layers adjacent to the first plurality of nanostructured channel layers and arranged in a direction substantially perpendicular to the semiconductor substrate; a first gate structure surrounding the first plurality of nanostructured channel layers, the first gate structure comprising: a p-type metal layer; and a residue located on the p-type metal layer, the residue comprising a ligand of at least one of the following: sulfur (S), silicon (SI), or phosphorus (P); and a second gate structure surrounding each of the second plurality of nanostructured channel layers, the second gate structure comprising an n-type metal layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, for clarity of discussion, the dimensions of various features may be arbitrarily increased or decreased.

[0007] Figures 1A to 1C is a diagram of an example implementation of a fin definition process described herein.

[0008] Figure 2 is a diagram of an example dummy gate structure formation process described herein.

[0009] Figure 3 is a diagram of an example implementation of a source / drain recess formation process described herein.

[0010] Figure 4A and Figure 4B is a diagram of an example implementation of an internal spacer formation process described herein.

[0011] Figure 5 is a diagram of an example implementation of a source / drain region formation process described herein.

[0012] Figure 6 is a diagram of an example implementation of an interlayer dielectric formation process described herein.

[0013] Figures 7A to 7H is a diagram of an example implementation of an alternative gate process described herein.

[0014] Figure 8 is a diagram of an example of element concentrations in a gate structure of a nanostructured transistor described herein.

[0015] Figure 9 is a diagram of an example of element concentrations in a gate structure of a nanostructured transistor described herein.

[0016] Figures 10A to 10D It is a diagram of an exemplary implementation of a gate structure in the nanostructure transistor described herein.

[0017] Figure 11A and Figure 11B It is a diagram of an exemplary implementation of a work function metal layer for forming a gate structure of a nanostructure transistor described herein.

[0018] Figure 12 and Figure 13 It is a flowchart of an exemplary process associated with forming a semiconductor device described herein.

[0019] Figures 14A to 14I It is a diagram of an exemplary implementation of a work function metal layer for forming a gate structure of a nanostructure transistor described herein.

[0020] Figure 15 It is a flowchart of an exemplary process associated with forming a semiconductor device described herein. Detailed Description

[0021] The following disclosure provides many different embodiments or examples for implementing different features of the provided subject matter. To simplify the present disclosure, specific examples of components and arrangements are described below. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature above or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features such that the first and second features may not be in direct contact. Additionally, the present disclosure may repeat reference numerals and / or characters in various examples. Such repetition is for the purpose of brevity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0022] Furthermore, spatially relative terms (such as, "beneath", "below", "lower", "above", "upper", etc.) may be used herein to facilitate describing one element or feature's relationship to another (one or more) element or (one or more) feature as illustrated in the figures. In addition to the orientation depicted in the figures, spatially relative terms are also intended to encompass different orientations of the device in use or operation. The device may be oriented in other directions (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein may be interpreted accordingly.

[0023] A nanostructure transistor may include a gate structure surrounding a plurality of nanostructure channels. The gate structure surrounding the nanostructure channels enhances the control of the gate structure over the conductive channels in the nanostructure channels, increases the drive current of the nanostructure transistor, and / or may reduce the short-channel effect (SCE) of the nanostructure transistor, etc. In some cases, a semiconductor device may include p-type metal-oxide-semiconductor (PMOS) nanostructure transistors and n-type metal-oxide-semiconductor (NMOS) nanostructure transistors. Integrating PMOS nanostructure transistors and NMOS nanostructure transistors into the same semiconductor device enables the implementation of complementary metal-oxide-semiconductor (CMOS) integrated circuits in the semiconductor device. CMOS integrated circuits have many use cases in the semiconductor industry, including microprocessors (e.g., central processing units (CPUs)), graphics processing units (GPUs), memory devices, digital logic circuits, image sensors (e.g., CMOS image sensors), and / or radio frequency (RF) circuits, etc.

[0024] The threshold voltage (V t ) of a nanostructure transistor is the gate voltage required to selectively turn the nanostructure transistor on or off. If the threshold voltage of the nanostructure transistor is too low (meaning the gate voltage used to activate the nanostructure transistor is too low), then when the nanostructure transistor is off, the nanostructure transistor may experience a large amount of current leakage. Conversely, if the threshold voltage of the nanostructure transistor is too high, the power efficiency of the nanostructure transistor may be reduced because a higher gate voltage is required to operate the nanostructure transistor. For PMOS nanostructure transistors and NMOS nanostructure transistors, the type of metal used for the gate structure can directly affect the threshold voltages of the PMOS nanostructure transistors and NMOS nanostructure transistors. Tuning the work function (φ m ) of the gate structure for the optimal performance of PMOS nanostructure transistors may result in a large bandgap between the work function of the gate structure of NMOS nanostructure transistors and the conduction band (E C ), thereby resulting in a high threshold voltage (and low power efficiency) of NMOS nanostructure transistors. Tuning the work function of the gate structure for the optimal performance of NMOS nanostructure transistors may result in a large bandgap between the work function of the gate structure of PMOS nanostructure transistors and the valence band (E V ), thereby resulting in a high threshold voltage (and low power efficiency) of PMOS nanostructure transistors.

[0025] Some implementations described herein provide semiconductor manufacturing techniques and related semiconductor structures for forming PMOS nanostructure transistors and NMOS nanostructure transistors in a semiconductor device. The techniques described herein include forming various (different) types of gate metals for PMOS nanostructure transistors and preserving the intrinsic NMOS nanostructure transistors of the semiconductor device. A p-type gate metal can be formed around the nanostructure channel of the PMOS nanostructure transistor. A self-assembled monolayer can then be formed on the surface of the p-type gate metal layer. During the formation of the n-type gate metal around the nanostructure channel of the NMOS nanostructure transistor, the self-assembled monolayer on the p-type gate metal prevents the formation of the n-type gate metal on the p-type gate metal. This results in little deposition of the n-type gate metal on the p-type gate metal, which minimizes the effect of the p-type threshold voltage (PV t ) on the PMOS nanostructure transistor. In this way, the techniques described herein enable the work functions of both the NMOS nanostructure transistor and the PMOS nanostructure transistor to be tuned to achieve the desired threshold voltages for the NMOS nanostructure transistor and the PMOS nanostructure transistor. This enables low current leakage to be achieved for the NMOS nanostructure transistor and the PMOS nanostructure transistor and enables high operating efficiency to be achieved for the NMOS nanostructure transistor and the PMOS nanostructure transistor.

[0026] Figures 1A to 1C is a diagram of an example implementation 100 of the fin definition process described herein. Example implementation 100 includes an example of forming the fin structure of semiconductor device 105 described herein and related shallow trench isolation (STI) regions. Semiconductor device 105 can be fabricated to include one or more transistors. The one or more transistors can include (one or more) nanostructure transistors, such as nanowire transistors, nanosheet transistors, gate-all-around (GAA) transistors, multi-bridge channel transistors, nanoribbon transistors, and / or other types of nanostructure transistors. Example implementation 100 includes an example of forming the fin structure of the transistors of semiconductor device 105 and related STI regions.

[0027] Figures 1A to 1C show a perspective view and a cross-sectional view along line A-A in the perspective view of semiconductor device 105, respectively. As Figure 1A shown, the processing of semiconductor device 105 is performed in conjunction with semiconductor substrate 110. Semiconductor substrate 110 includes a silicon (Si) substrate, a substrate formed of a material including silicon, a III-V compound semiconductor material (such as gallium arsenide (GaAs)) substrate, a silicon-on-insulator (SOI) substrate, a germanium (Ge) substrate, a silicon-germanium (SiGe) substrate, a silicon carbide (SiC) substrate, or another type of semiconductor substrate.

[0028] A layer stack 115 is formed on a semiconductor substrate 110. The layer stack 115 may be referred to as a superlattice. The layer stack 115 includes a plurality of alternating layers arranged in a direction generally perpendicular to the semiconductor substrate 110 (e.g., the z-direction). For example, the layer stack 115 includes alternating layers of a sacrificial nanostructure layer 120 and a nanostructure channel layer 125 above the semiconductor substrate 110 in the vertical direction. Figure 1A The number of the shown sacrificial nanostructure layers 120 and the number of the nanostructure channel layers 125 are examples, and other numbers of the sacrificial nanostructure layers 120 and the nanostructure channel layers 125 are within the scope of the present disclosure.

[0029] The sacrificial nanostructure layer 120 enables defining a vertical distance between adjacent nanostructure channels formed from the nanostructure channel layer 125 and serves as a placeholder layer for subsequently formed gate structures of transistors of the semiconductor device 105, and these gate structures are formed around the nanostructure channels. The sacrificial nanostructure layer 120 includes a first material composition, while the nanostructure channel layer 125 includes a second material composition. In some implementations, the first material composition and the second material composition are the same material composition. In some implementations, the first material composition and the second material composition are different material compositions. For example, the sacrificial nanostructure layer 120 may include silicon germanium (SiG), while the nanostructure channel layer 125 may include silicon (Si). This enables the sacrificial nanostructure layer 120 and / or the nanostructure channel layer 125 to be selectively etched according to the type of etchant used (e.g., enabling the sacrificial nanostructure layer 120 to be etched while the nanostructure channel layer 125 is not etched, enabling the nanostructure channel layer 125 to be etched while the sacrificial nanostructure layer 120 is not etched).

[0030] One or more types of deposition tools may be used to deposit and / or grow the alternating layers of the layer stack 115 to include nanostructures (e.g., nanosheets) on the semiconductor substrate 110. For example, the deposition tool may be used to grow the sacrificial nanostructure layer 120 and / or the nanostructure channel layer 125 by epitaxial growth, and the epitaxial growth may include epitaxial techniques such as molecular beam epitaxy (MBE), metalorganic chemical vapor deposition (MOCVD) process, and / or another suitable epitaxial technique. Additionally and / or alternatively, the sacrificial nanostructure layer 120 and / or the nanostructure channel layer 125 may be deposited by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), and / or another suitable deposition technique.

[0031] One or more mask layers can be formed on the layer stack 115 (e.g., using one or more deposition tools). The (one or more) mask layers can include a hard mask (HM) layer 130, a capping layer 135, an oxide layer 140, and / or a nitride layer 145. The (one or more) mask layers can be used to perform fin patterning operations to form fin structures in the semiconductor substrate 110.

[0032] As Figure 1B shown, the layer stack 115 and the semiconductor substrate 110 are etched to remove some portions of the layer stack 115 and some portions of the semiconductor substrate 110. This results in the formation of fin structures 150 extending above the semiconductor substrate 110. The fin structures 150 can extend in the y-direction in the semiconductor device 105 and can be arranged in the x-direction in the semiconductor device 105. The fin structures 150 include portions 155 of the layer stack 115 that are above and / or on the fin portions 160 of the layer stack 115 that are above the semiconductor substrate 110. The fin structures 150 can be formed by patterning one or more mask layers and etching the semiconductor substrate 110 based on the pattern formed in the one or more mask layers. Lithography techniques (including double patterning or multi-patterning techniques) can be used to pattern the one or more mask layers. Etching tools can be used to etch the semiconductor substrate 110 based on the pattern using dry etching techniques (e.g., reactive ion etching), wet etching techniques, and / or a combination thereof.

[0033] As Figure 1B further shown, some of the fin structures 150 can be formed to have different widths for different types of nanostructure transistors. As an example, a first subgroup of fin structures 150a can be formed for p-type nanostructure transistors (e.g., p-type metal oxide semiconductor (PMOS) nanostructure transistors), while a second subgroup of fin structures 150b can be formed for n-type nanostructure transistors (e.g., n-type metal oxide semiconductor (NMOS) nanostructure transistors). As another example, a first subgroup of fin structures 150a can be formed for nanostructure transistors configured to operate at a lower voltage, while a second subgroup of fin structures 150b can be formed for nanostructure transistors configured to operate at a higher voltage.

[0034] As Figure 1C shown, a liner 165 and a STI region 170 are formed between adjacent fin portions 160 of the fin structures 150. The liner 165 and the STI region 170 can each include a dielectric material, such as silicon oxide (SiO x ), silicon nitride (Si x N y ), silicon oxynitride (SiON), fluorinated silicate glass (FSG), a low-k dielectric material, and / or another suitable insulating material.

[0035] Deposition tools can be used to conformally deposit liners (e.g., using ALD or other conformal deposition techniques), and can deposit a dielectric layer on liner 165 (e.g., using CVD, PVD, ALD, and / or other suitable deposition techniques) such that the dielectric layer completely fills the space between fin structures 150 and extends above the tops of fin structures 150. A planarization tool can then be used to perform a planarization or polishing operation (e.g., a chemical mechanical planarization (CMP) operation) to planarize the dielectric layer such that the top surface of the dielectric layer is substantially coplanar with the top of nitride layer 145. Nitride layer 145 serves as a CMP stop layer during the planarization operation. An etch tool can then be used to etch the dielectric layer to form STI regions 170 such that the top surface of STI regions 170 is substantially coplanar with or below the bottommost sacrificial nanostructure layer 120.

[0036] As noted above, Figures 1A to 1C is provided as an example. Other examples may be different from those described with respect to Figures 1A to 1C the description.

[0037] Figure 2 is an illustration of an example implementation 200 of the dummy gate formation process described herein. Example implementation 200 includes an example of forming a dummy gate structure 205 of a nanostructure transistor of semiconductor device 105. In some implementations, the operations described with respect to example implementation 200 are performed after the processes described in conjunction with Figures 1A to 1C the description.

[0038] Figure 2 shows a perspective view of semiconductor device 105 with a dummy gate structure 205 formed thereon. Dummy gate structure 205 (also referred to as a dummy gate stack or a temporary gate structure) is formed over some portions of fin structures 150 and some portions of STI regions 170. Dummy gate structure 205 extends in the x direction and is arranged in the y direction such that dummy gate structure 205 is substantially perpendicular to fin structures 150. Dummy gate structure 205 is a sacrificial structure that will be replaced by a replacement gate structure or a replacement gate stack in subsequent process stages of semiconductor device 105. Dummy gate structure 205 can also be used to define source / drain (S / D) recesses in fin structures 150, in which source / drain regions of the nanostructure transistor are formed.

[0039] The dummy gate structure 205 may include a gate electrode layer 210, a hard mask layer 215 on and / or over the gate electrode layer 210, a spacer layer 220 on opposite sides of the gate electrode layer 210, and a gate dielectric layer 225 under the gate electrode layer 210. The gate electrode layer 210 includes polysilicon (polysilicon or PO) or other materials. The hard mask layer 215 includes one or more layers, such as an oxide layer (e.g., a liner oxide layer, which may include silicon dioxide (SiO2) or another material) and a nitride layer formed over the oxide layer (e.g., a liner nitride layer, which may include silicon nitride (e.g., Si3N4) or another material). The spacer layer 220 includes silicon oxycarbide (SiOC), nitrogen-free SiOC, or other suitable materials. The gate dielectric layer 225 may include silicon oxide (e.g., SiO x )), silicon nitride (e.g., Si x N y ), a high-k (high dielectric constant) dielectric material (e.g., a dielectric material having a dielectric constant greater than about 3.9), and / or another suitable material.

[0040] Various semiconductor processing techniques for defining the dummy gate structure 205 (e.g., techniques for depositing the layers of the dummy gate structure 205, patterning the layers of the dummy gate structure 205) and / or other semiconductor processing techniques may be used to form the layers of the dummy gate structure 205.

[0041] Figure 2 Also shown are reference cross-sections used in the subsequent figures described herein. Cross-section A-A is in the x-z plane (referred to as a y-cut) of the fin structure 150 in the source / drain region of the semiconductor device 105. Cross-section B-B is in the y-z plane perpendicular to cross-section A-A (referred to as an x-cut) and extends across the dummy gate structure 205 and along the underlying fin structure 150. Cross-section C-C is in the x-z plane parallel to cross-section A-A and perpendicular to cross-section B-B and extends along the dummy gate structure 205. For clarity, the subsequent figures refer to these reference cross-sections. In some figures, some reference numerals of the components or features shown therein may be omitted to avoid obscuring other components or features for ease of depicting the figures.

[0042] As noted above, Figure 2 is provided as an example. Other examples may be different from those described with respect to Figure 2 .

[0043] Figure 3FIG. 0 is a diagram of an example implementation 300 of a source / drain recess formation process described herein. Example implementation 300 includes an example of forming source / drain recesses 305 in source / drain regions of a nanostructure transistor of a semiconductor device 105. Figure 3 shows Figure 2 multiple perspective views shown, including Figure 2 a perspective view of cross-sectional plane A-A in Figure 2 a perspective view of cross-sectional plane B-B in Figure 2 and a perspective view of cross-sectional plane C-C in. In some implementations, the operations described in connection with example implementation 300 are performed after the process described in connection with Figures 1A to 2 .

[0044] As Figure 3 shown in cross-sectional plane A-A and cross-sectional plane B-B in, in an etching operation, source / drain recesses 305 are formed to pass through some portions 155 of fin structure 150. Source / drain recesses 305 are formed on opposite sides of dummy gate structure 205. The etching operation can be performed using an etching tool and can be referred to as a strained source / drain (SSD) etching operation. In some implementations, the etching operation includes using plasma etching techniques, wet chemical etching techniques, and / or another type of etching technique.

[0045] Source / drain recesses 305 also extend into a portion of fin portions 160 of fin structure 150. This results in the formation of mesa regions 310 in fin structure 150. Sidewalls of those portions of each source / drain recess 305 that are below layer stack 115 correspond to sidewalls of mesa region 310. Mesa region 310 (also referred to as a pedestal) refers to a region of fin portions 160 of fin structure 150 on which a nanostructure channel is defined from nanostructure channel layer 125. Nanostructure channel 315 extends between adjacent source / drain recesses 305.

[0046] Nanostructure channel 315 includes silicon-based nanostructures (e.g., nanosheets or nanowires, etc.) that serve as a semiconductor channel of a nanostructure transistor of semiconductor device 105. In some implementations, nanostructure channel 315 may include silicon germanium (SiGe) or another silicon-based material. Nanostructure channel 315 is arranged in a direction generally perpendicular to semiconductor substrate 110 (e.g., the z direction). In other words, nanostructure channel 315 is arranged or stacked in a vertical direction above semiconductor substrate 110.

[0047] As noted above, Figure 3 is provided as an example. Other examples may be different from those described in connection with Figure 3 .

[0048] Figure 4A and Figure 4B is an illustration of an example implementation 400 of the internal spacer formation process described herein. The example implementation 400 includes an example of forming an internal spacer between the ends of the nanostructure channel 315 that are exposed in the source / drain recess 305. Figure 4A and Figure 4B each show Figure 2 multiple perspective views shown, including Figure 2 a perspective view of cross-sectional plane A-A in Figure 2 a perspective view of cross-sectional plane B-B in Figure 2 and a perspective view of cross-sectional plane C-C in. In some implementations, the operations described in connection with the example implementation 400 are performed after the process described in connection with Figures 1A to 3 .

[0049] As Figure 4A shown in cross-sectional plane B-B in, the ends of the sacrificial nanostructure layer 120 that are exposed in the source / drain recess 305 are etched laterally (e.g., in the x direction generally parallel to the length of the sacrificial nanostructure layer 120) in an etching operation, thereby forming a cavity 405 between the ends of the nanostructure channel 315 that are exposed in the source / drain recess 305. In particular, an etching tool can be used to laterally etch the ends of the sacrificial nanostructure layer 120 under the dummy gate structure 205 through the source / drain recess 305 to form a cavity 405 between the ends of the nanostructure channel 315. The cavity 405 can be formed in an approximately curved shape, an approximately concave shape, an approximately triangular shape, an approximately square shape, or other shapes.

[0050] As Figure 4B shown in cross-sectional plane A-A and cross-sectional plane B-B in, an internal spacer (InSP) 410 is formed in the cavity 405 between the ends of the nanostructure channels 315 that are adjacent in the vertical direction and are in the source / drain recess 305. The internal spacer 410 is included to reduce parasitic capacitance in the nanostructure transistor and to protect the source / drain regions (which are subsequently formed in the source / drain recess 305) from being etched during the nanosheet release operation for removing the sacrificial nanostructure layer 120 between the nanostructure channels 315. The internal spacer 410 includes silicon nitride (Si x N y ), silicon oxide (SiO x ), silicon oxynitride (SiON), silicon carbonitride (SiOC), silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN), and / or another dielectric material.

[0051] To form the internal spacer 410, a deposition tool can be used to deposit a dielectric material layer along the sidewalls and bottom surface of the source / drain recess in the cavity 405. CVD techniques, PVD techniques, and ALD techniques and / or another deposition technique can be used to deposit the dielectric material layer. An etch tool is used to subsequently remove the excess material of the dielectric material layer from the source / drain recess such that the remaining portion corresponds to the internal spacer 410 in the cavity 405. In some implementations, the etch operation may cause the surface of the internal spacer 410 facing the source / drain recess 305 to be curved or indented. In some implementations, the surface of the internal spacer 410 facing the source / drain recess 305 is approximately flat such that the surface of the internal spacer 410 and the surface of the end of the nanostructure channel 315 are approximately flat and flush.

[0052] As noted above, Figure 4A and Figure 4B are provided as examples. Other examples may be different from those described with respect to Figure 4A and Figure 4B described.

[0053] Figure 5 is an illustration of an example implementation 500 of the source / drain region formation process described herein. Example implementation 500 includes an example of forming the source / drain regions of the nanostructure transistors of the semiconductor device 105. Figure 5 shows Figure 2 multiple perspective views shown, including Figure 2 a perspective view of the cross-sectional plane A-A in Figure 2 a perspective view of the cross-sectional plane B-B in Figure 2 and a perspective view of the cross-sectional plane C-C in Figures 1A to 4B In some implementations, the operations described in connection with example implementation 500 are performed after the process described in connection with

[0054] As Figure 5 shown in the cross-sectional plane A-A and the cross-sectional plane B-B in

[0055] The buffer region 505 may include silicon (Si), silicon doped with boron or another dopant (SiB), and / or another material. The buffer region 505 may be included between the source / drain region 510 and the mesa region 310 adjacent to the buffer region 505 to reduce, minimize, and / or prevent dopant migration from the source / drain region 510 into the adjacent mesa region 310 and / or current leakage from the source / drain region 510 to the adjacent mesa region 310, which may otherwise cause a short-channel effect in the semiconductor device 105. Accordingly, the buffer region 505 may improve the performance of the semiconductor device 105 and / or increase the yield of the semiconductor device 105.

[0056] The source / drain region 510 may refer to the source or the drain individually or collectively, depending on the context. The source / drain region 510 may be included on opposite sides of the dummy gate structure 205 such that the nanostructure channel 315 under the dummy gate structure 205 extends between the source / drain regions 510 and is electrically coupled to the source / drain regions 510. Each of the source / drain regions 510 includes silicon (Si) having one or more dopants, such as a p-type material (e.g., boron (B) or germanium (Ge), etc.), an n-type material (e.g., phosphorus (P) or arsenic (As), etc.), and / or another type of dopant. Accordingly, the semiconductor device 105 may include a p-type metal-oxide semiconductor (PMOS) nanostructure transistor (which includes a p-type source / drain region 510), an n-type metal-oxide semiconductor (NMOS) nanostructure transistor (which includes an n-type source / drain region 510), and / or other types of nanostructure transistors.

[0057] One or more layers of the source / drain region 510 may be epitaxially grown, deposited (e.g., using CVD, PVD, ALD), and / or may be formed using one or more other deposition techniques. For example, a deposition tool may epitaxially grow a first layer of the source / drain region 510 (referred to as L1) over the relevant buffer region 505 (which may be referred to as L0), and may epitaxially grow a second layer of the source / drain region 510 (referred to as L2, L2-1, and / or L2-2) over the first layer. The first layer may include lightly doped silicon (e.g., doped with boron (B), phosphorus (P), and / or another dopant), and may be included as a shielding layer to reduce the short-channel effect in the semiconductor device 105 and reduce dopant extrusion or migration into the nanostructure channel 315. The second layer may include highly doped silicon or highly doped silicon germanium. The second layer may be included to provide compressive stress in the source / drain region 510 to reduce boron loss.

[0058] The capping layer 515 may include silicon, silicon germanium, doped silicon, doped silicon germanium, and / or other materials. The capping layer 515 may be included to reduce dopant diffusion and protect the underlying source / drain regions 510 during semiconductor processing operations of the semiconductor device 105 prior to contact formation. Additionally, the capping layer 515 may contribute to the formation of a metal-semiconductor (e.g., silicide) alloy.

[0059] As noted above, Figure 5 is provided as an example. Other examples may be different from those described with respect to Figure 5 described.

[0060] Figure 6 is an illustration of an example implementation 600 of an interlayer dielectric (ILD) formation process described herein. Figure 6 Shows Figure 2 A plurality of perspective views are shown, including Figure 2 A perspective view of the cross-sectional plane A-A in Figure 2 A perspective view of the cross-sectional plane B-B in Figure 2 And a perspective view of the cross-sectional plane C-C in. In some implementations, the operations described in connection with example implementation 600 are performed after the process described in connection with Figures 1A to 5 described.

[0061] As Figure 6 Shown in the cross-sectional plane A-A and the cross-sectional plane B-B in, a dielectric layer 605 is formed over the source / drain regions 510. The dielectric layer 605 (which may be referred to as an ILD layer) fills the regions between the dummy gate structures 205. The dielectric layer 605 is formed to reduce the likelihood of damaging the source / drain regions 510 and / or prevent damage to the source / drain regions 510 during an alternative gate process for replacing the dummy gate structures 205. The dielectric layer 605 may be referred to as an ILD zero (ILD0) layer or another ILD layer.

[0062] In some implementations, prior to forming the dielectric layer 605, a contact etch stop layer (CESL) is conformally deposited over the source / drain regions 510 (e.g., by a deposition tool). Alternatively, the capping layer 515 may be the CESL. Then the dielectric layer 605 is formed over the CESL. The CESL may provide a mechanism for stopping an etch process when forming contacts or vias to the source / drain regions 510. The CESL may be formed of a dielectric material having an etch selectivity different from that of adjacent layers or components. The CESL may include or may be a nitrogen-containing material, a silicon-containing material, and / or a carbon-containing material. Additionally, the CESL may include or may be silicon nitride (Si x N y) Silicon carbonitride (SiCN), carbon nitride (CN), silicon oxynitride (SiON), silicon oxycarbide (SiCO), or a combination thereof, etc. A deposition process (such as ALD, CVD, or other deposition techniques) can be used to deposit the CESL.

[0063] As pointed out above, Figure 6 is provided as an example. Other examples can be different from those Figure 6 described.

[0064] Figures 7A to 7H is a diagram of an example implementation 700 of the replacement gate (RPG) process described herein. The example implementation 700 includes an example of a replacement gate process for replacing a dummy gate structure 205 with a high-k / metal gate structure (e.g., a replacement gate structure) of a nanostructure transistor of a semiconductor device 105. Figures 7A to 7H Each shows Figure 2 one or more perspective views shown, such as Figure 2 a perspective view of cross-sectional plane B-B in Figure 2 and / or a perspective view of cross-sectional plane C-C in Figures 1A to 6 In some implementations, the operations described in connection with example implementation 700 are performed after the operations described in connection with

[0065] As Figure 7A shown by cross-sectional plane B-B and cross-sectional plane C-C in

[0066] the replacement gate process includes a dummy gate removal operation. The dummy gate removal operation includes removing the dummy gate structure 205 from the semiconductor device 105. The removal of the dummy gate structure 205 leaves an opening (or recess) between the dielectric layers 605 and provides access to the underlying sacrificial nanostructure layer 120. The dummy gate structure 205 can be removed in one or more etching operations. Such etching operations can include plasma etching techniques, wet chemical etching techniques, and / or another type of etching technique.

[0067] The mesa region 310a and the nanostructure channel 315a can be exposed to prepare for forming an n-type gate structure of the NMOS nanostructure transistor of the semiconductor device 105 around the nanostructure channel 315a. The mesa region 310b and the nanostructure channel 315b can be exposed to prepare for forming a p-type gate structure of the PMOS nanostructure transistor of the semiconductor device 105 around the nanostructure channel 315b.

[0068] In some implementations, the z-direction thickness of the nanostructure channel 315a is in the range of about 3 nanometers to about 10 nanometers. However, other values and ranges of the z-direction thickness of the nanostructure channel 315a are within the scope of the present disclosure. In some implementations, the z-direction thickness of the nanostructure channel 315b is in the range of about 3 nanometers to about 10 nanometers. However, other values and ranges of the z-direction thickness of the nanostructure channel 315b are within the scope of the present disclosure.

[0069] In some implementations, the z-direction distance (e.g., channel-to-channel pitch) between adjacent nanostructure channels 315a in the vertical direction is in the range of about 3 nanometers to about 10 nanometers. However, other values and ranges of the z-direction pitch between the nanostructure channels 315a are within the scope of the present disclosure. In some implementations, the z-direction distance (e.g., channel-to-channel pitch) between adjacent nanostructure channels 315b in the vertical direction is in the range of about 3 nanometers to about 10 nanometers. However, other values and ranges of the z-direction pitch between the nanostructure channels 315b are within the scope of the present disclosure.

[0070] As Figure 7A Further shown, the alternative gate process includes a nanostructure release operation (e.g., a silicon-germanium release operation). The nanostructure release operation is performed to remove the sacrificial nanostructure layer 120 (e.g., a silicon-germanium layer). This results in generating openings 705 (e.g., regions around the nanostructure channels 315a) between the nanostructure channels 315a and openings 705 (e.g., regions around the nanostructure channels 315b) between the nanostructure channels 315b. The sacrificial nanostructure layer 120 can be removed through the space previously occupied by the dummy gate structure 205. The nanostructure release operation can include performing an etching operation using an etching tool to remove the sacrificial nanostructure layer 120 based on the difference in etching selectivity between the material of the sacrificial nanostructure layer 120 and the materials of the nanostructure channels 315a and the nanostructure channels 315b, and between the material of the sacrificial nanostructure layer 120 and the material of the inner spacer 410. The inner spacer 410 can be used as an etch stop layer in the etching operation to protect the source / drain regions 510 from being etched.

[0071] As Figure 7BAs shown, an interface layer 715 can be formed around the nanostructure channel 315a and the nanostructure channel 315b. The interface layer 715 can be conformally deposited (e.g., using ALD techniques, CVD techniques, and / or another suitable conformal deposition technique) such that the interface layer 715 is deposited as a conformal thin film. The interface layer 715 can include silicon dioxide (SiO2) and / or another suitable dielectric material that can be used to tune the interface between the gate dielectric layer 720 and the nanostructure channel 315a and the nanostructure channel 315b. In some implementations, the interface layer 715 can have a thickness that includes a range from about 5 angstroms to about 25 angstroms. However, other values and ranges for the thickness of the interface layer 715 are within the scope of the present disclosure.

[0072] As Figure 7B Further shown, a gate dielectric layer 720 is formed around the nanostructure channel 315a and the nanostructure channel 315b. The gate dielectric layer 720 can be conformally deposited (e.g., using ALD techniques, CVD techniques, and / or another suitable conformal deposition technique) such that the gate dielectric layer 720 is deposited as a conformal thin film.

[0073] The gate dielectric layer 720 can include one or more high-k materials (e.g., dielectric materials having a dielectric constant greater than that of silicon dioxide (SiO2, dielectric constant of about 3.9)). Examples of such high-k materials include lanthanum oxide (La x O y , such as La2O3), hafnium oxide (HfO x , such as HfO2), zirconium oxide (ZrO x , such as ZrO2), and / or aluminum oxide (Al x O y , such as Al2O3) and other examples of high-k dielectric materials. Additionally and / or alternatively, instead of a high-k dielectric material, silicon dioxide (SiO2) and / or another dielectric material can be used.

[0074] In some implementations, the gate dielectric layer 720 is formed to include a multilayer thin film of two or more high-k dielectric materials. For example, the gate dielectric layer 720 can include a first layer and a second layer on the first layer, the first layer including hafnium oxide (HfO x , such as HfO2), and the second layer including zirconium oxide (ZrO x , such as ZrO2). Other combinations of high-k dielectric layers of the gate dielectric layer 720 are within the scope of the present disclosure.

[0075] In some implementations, the gate dielectric layer 720 can have a thickness that includes a range from about 5 angstroms to about 30 angstroms. However, other values and ranges for the thickness of the gate dielectric layer 720 are within the scope of the present disclosure.

[0076] As Figure 7B Further shown, a p-type metal layer 725 is formed on the gate dielectric layer 720. In some implementations, an adhesion liner is first formed on the gate dielectric layer 720, and the p-type metal layer 725 is formed on the adhesion liner. The p-type metal layer 725 is formed on the exposed portions of the mesa regions 310a and 310b and on the nanostructure channels 315a and 315b such that the p-type metal layer 725 wraps around the nanostructure channels 315a and 315b.

[0077] In some embodiments, the p-type metal layer 725 wraps around the nanostructure channels 315a and 315b such that between vertically adjacent pairs of nanostructure channels 315a, the p-type metal layer 725 is merged, while between vertically adjacent pairs of nanostructure channels 315b, the p-type metal layer 725 is not merged. In some embodiments, the p-type metal layer 725 wraps around the nanostructure channels 315a and 315b, and between vertically adjacent pairs of nanostructure channels 315a, the p-type metal layer 725 is not merged, and / or between vertically adjacent pairs of nanostructure channels 315b, the p-type metal layer 725 is not merged. In these implementations, seams may occur in portions of the p-type metal layer 725 between vertically adjacent pairs of nanostructure channels 315a and / or in portions of the p-type metal layer 725 between vertically adjacent pairs of nanostructure channels 315b.

[0078] Since the p-type gate structure 710b includes a metal gate structure, the work function tuning of the p-type gate structure 710b can be performed by including one or more work function tuning metals in the p-type gate structure 710b, which is different from a polysilicon gate structure whose work function is tuned by doping the polysilicon material with a p-type dopant and / or an n-type dopant. The p-type metal layer 725 can be included as the p-type work function metal in the p-type gate structure 710b to tune the work function of the p-type gate structure 710b. The p-type metal layer 725 can include one or more p-type metals such as tungsten (W), cobalt (Co), titanium nitride (TiN), tungsten nitride (WN), and / or another metal having a work function greater than about 4.7 electron volts (eV), etc. The p-type metal layer 725 can be included to tune the work function of the PMOS nanostructure transistor such that the work function is adjusted to be close to the valence band of the material of the nanostructure channel 315b. This enables a relatively low threshold voltage to be achieved for the PMOS nanostructure transistor while enabling relatively low current leakage for the PMOS nanostructure transistor.

[0079] A deposition tool can be used to deposit the p-type metal layer 725 using PVD technology, ALD technology, CVD technology, oxidation technology, and / or another suitable deposition technology. The p-type metal layer 725 can be deposited in one or more deposition operations. In some implementations, the p-type metal layer 725 is formed to have a thickness in the range of about 0.1 angstroms to about 50 angstroms. However, other values and ranges for the thickness of the p-type metal layer 725 are within the scope of the present disclosure.

[0080] As noted above, the p-type metal layer 725 is formed to surround the nanostructured channel 315a and the nanostructured channel 315b. This is because the p-type metal layer 725 is formed without using a mask layer around the nanostructured channel 315a. If the p-type metal layer 725 surrounds the nanostructured channel 315a, the p-type metal layer 725 may cause the work function of the n-type gate structure 710a to be too far from the conduction band of the material of the nanostructured channel 315a. Thus, as Figure 7C and Figure 7D shown, after the p-type metal layer 725 is formed, the p-type metal layer 725 is removed from the nanostructured channel 315a.

[0081] As Figure 7C shown, a photoresist layer 730 can be formed over the semiconductor device 105. The photoresist layer 730 can be formed over the p-type metal layer 725 on the mesa region 310a, the mesa region 310b, the nanostructured channel 315a, and the nanostructured channel 315b. A deposition tool can be used to deposit the photoresist layer 730 using spin coating technology and / or another deposition technology.

[0082] As Figure 7C further shown, a pattern is formed in the photoresist layer 730. The n-type gate structure 710a is exposed through the pattern in the photoresist layer 730. This enables the photoresist layer 730 to be used to remove the p-type metal layer 725 from the mesa region 310a and the nanostructured channel 315a, without removing the p-type metal layer 725 from the mesa region 310b and the nanostructured channel 315b. An exposure tool can be used to expose the photoresist layer 730 to a radiation source to pattern the photoresist layer 730. A development tool can be used to develop and remove the portion of the photoresist layer 730 on the mesa region 310a and the nanostructured channel 315a.

[0083] As Figure 7DAs shown, the portions of the p-type metal layer 725 that are exposed through the pattern in the photoresist layer 730 are removed from the mesa region 310a and from the nanostructured channel 315a. The photoresist layer 730 over the p-type gate structure 710b protects those portions of the p-type metal layer 725 that are not removed from the mesa region 310b and the nanostructured channel 315b. An etching tool can be used to etch the p-type metal layer 725 based on the pattern in the photoresist layer 730 to remove those portions of the p-type metal layer 725 from the mesa region 310a and from the nanostructured channel 315a. In some implementations, the etching operation includes a plasma etching operation, a wet chemical etching operation, and / or another type of etching operation.

[0084] Subsequently, a photoresist removal tool can be used to remove the remaining portion of the photoresist layer 730. A chemical stripper, plasma ashing, and / or another technique can be used to remove the remaining portion of the photoresist layer 730. Removing the remaining portion of the photoresist layer 730 exposes the p-type metal layer 725 on the mesa region 310b and the nanostructured channel 315b.

[0085] As Figure 7E shown, a self-assembled monolayer 735 is formed on the p-type metal layer 725 of the p-type gate structure 710b. In other words, the self-assembled monolayer 735 is formed on the p-type metal layer 725 that surrounds the nanostructured channel 315b and includes the mesa region 310b.

[0086] The self-assembled monolayer 735 includes a "monolayer" film because the self-assembled monolayer 735 can have a single-molecule thickness (e.g., the thickness of a single-molecule thick layer of the material corresponding to the self-assembled monolayer 735). The self-assembled monolayer 735 is formed on the p-type metal layer 725 to block or inhibit the formation of the n-type metal layer on the p-type metal layer 725. Subsequently, an n-type metal layer will be formed on the nanostructured channel 315a of the n-type gate structure 710a for tuning the work function of the n-type gate structure 710a. The self-assembled monolayer 735 minimizes or reduces the effect of the n-type metal layer on the work function of the p-type gate structure 710b.

[0087] The self-assembled monolayer 735 includes one or more materials that enable the self-assembled monolayer 735 to be selectively deposited on the p-type metal layer 725, with little or no deposition of the self-assembled monolayer 735 on the gate dielectric layer 720 of the n-type gate structure 710a. For example, the self-assembled monolayer 735 can be formed from a material that includes an anchoring group 740, which promotes the adsorption of the material of the self-assembled monolayer 735 onto the p-type metal layer 725 and prevents adsorption onto the high-k dielectric material of the gate dielectric layer 720. In some implementations, the adsorption selectivity of the anchoring group 740 of the self-assembled monolayer 735 can be in the range of 20:1 (e.g., 20:1 adsorption on the p-type metal layer 725 relative to adsorption on the high-k dielectric material of the gate dielectric layer 720) to about 70:1 to achieve sufficient deposition selectivity of the self-assembled monolayer 735. Examples of such materials include materials having an anchoring group 740 that includes an amino group (-NH2 group), a thiol group (-SH group), a carboxyl group (-COOH group), a carbonyl group (-COH group), a trichlorosilane group (-SiCl3 group), and / or a phosphonate group (-P group), etc. In some implementations, the anchoring group 740 includes a nitrogen ligand (N-ligand), a sulfur ligand (S-ligand), a silicon ligand (Si-ligand), a phosphorus ligand (P-ligand), and / or another type of ligand.

[0088] The self-assembled monolayer 735 includes one or more materials that enable the self-assembled monolayer 735 to block or inhibit the precursor of the n-type metal layer of the n-type gate structure 710a from being adsorbed onto the p-type metal layer 725 of the p-type gate structure 710b. For example, the self-assembled monolayer 735 can be formed from a material that includes a side-chain group 745 that includes a hydrocarbon group such as an aryl hydrocarbon chain.

[0089] In some implementations, the self-assembled monolayer 735 is formed by depositing a solution containing the material of the self-assembled monolayer 735 onto the surface of the p-type metal layer 725 using a spin-coating technique. In some implementations, a pre-cleaning operation uses isopropyl alcohol (IPA) or another cleaner to pre-clean the p-type metal layer 725 before depositing the solution.

[0090] The solution can include the material of the self-assembled monolayer 735 dissolved in a solvent, which enables the material of the self-assembled monolayer 735 to be distributed on the p-type metal layer 725. The solvent can include a γ-butyrolactone (GBL) solvent, a diethylformamide (DEF) solvent, a propylene glycol monomethyl ether acetate (PGMEA) solvent, a propylene glycol monomethyl ether (PGME) solvent, and / or another suitable solvent.

[0091] Once the p-type metal layer 725 is coated with a solvent, a spin drying operation can be performed to cure the solution by evaporating the solvent such that the material of the self-assembled monolayer 735 remains on the p-type metal layer 725. The molecules of the material spontaneously self-assemble into a monolayer, thereby forming the self-assembled monolayer 735. In some implementations, another cleaning operation is performed prior to the spin drying operation (e.g., using IPA or another cleaner). In some implementations, the spin drying operation is performed in a range from about 200 revolutions per minute (rpm) to about 1000 rpm. However, other values and ranges for the spin drying operation are within the scope of the present disclosure.

[0092] In some implementations, the self-assembled monolayer 735 is formed to have a thickness in a range from about 0.1 angstroms to about 10 angstroms. If the thickness of the self-assembled monolayer 735 is less than about 0.1 angstroms, the self-assembled monolayer 735 may be insufficient to block or inhibit the formation of the n-type metal layer on the p-type metal layer 725, resulting in degradation of the work function of the p-type gate structure 710b. If the thickness of the self-assembled monolayer 735 is greater than about 10 angstroms, the self-assembled monolayer 735 may be too thick to be sufficiently removed from the p-type gate structure 710b. If the thickness of the self-assembled monolayer 735 is in a range from about 0.1 angstroms to about 10 angstroms, the self-assembled monolayer 735 can sufficiently block or inhibit the formation of the n-type metal layer on the p-type metal layer 725 and can be sufficiently removed from the p-type gate structure 710b. However, other values for the thickness of the self-assembled monolayer 735 and ranges other than from about 0.1 angstroms to about 10 angstroms are also within the scope of the present disclosure.

[0093] As Figure 7F shown, after the self-assembled monolayer 735 is formed on the p-type metal layer 725 of the p-type gate structure 710b, an n-type metal layer 750 is formed on the n-type gate structure 710a. The n-type metal layer 750 is formed such that the n-type metal layer 750 surrounds each nanostructured channel 220a. The n-type metal layer 750 is also formed on the exposed portion of the mesa region 310a below the nanostructured channel 315a. A deposition tool can be used to deposit the n-type metal layer 750 using CVD techniques, PVD techniques, ALD techniques, and / or another suitable deposition technique. The n-type metal layer 750 can be deposited in one or more deposition operations.

[0094] In some embodiments, the n-type metal layer 750 wraps around the nanostructure channel 315a, and the n-type metal layer 750 is merged between vertically adjacent pairs of the nanostructure channels 315a. In some embodiments, the n-type metal layer 750 wraps around the nanostructure channel 315a, and the n-type metal layer 750 is not merged between vertically adjacent pairs of the nanostructure channels 315a in the vertical direction. In these implementations, seams may occur in portions of the n-type metal layer 750 between vertically adjacent pairs of the nanostructure channels 315a.

[0095] The n-type metal layer 750 includes one or more metal materials that tune or adjust the work function of the n-type gate structure 710a near the conduction band of the material of the nanostructure channel 220a. In some implementations, the n-type metal layer 750 includes titanium aluminum (TiAl). In some implementations, the n-type metal layer 750 includes titanium aluminum carbon (TiAlC). In some implementations, the n-type metal layer 750 includes another aluminum-containing metal. In some implementations, another n-type metal material is included in the n-type metal layer 750.

[0096] The n-type metal layer 750 is formed without using an additional mask layer for the p-type metal layer 725 that covers the p-type gate structure 710b. Instead, the self-assembled monolayer 735 on the p-type metal layer 725 blocks or inhibits the formation of the n-type metal layer 750 on the p-type metal layer 725. Thus, the self-assembled monolayer 735 enables the n-type metal layer 750 to be selectively deposited on the gate dielectric layer 720 over the nanostructure channel 315a. In particular, the side chain groups 745 of the material of the self-assembled monolayer 735 inhibit the precursor of the n-type metal layer 750 from adsorbing on the p-type metal layer 725.

[0097] As Figure 7G shown, after the n-type metal layer 750 is formed, the self-assembled monolayer 735 can subsequently be removed. Various techniques can be used to remove the self-assembled monolayer 735 from the p-type metal layer 725 of the p-type gate structure 710b. Alternatively, the removal of the self-assembled monolayer 735 can be omitted, such that the self-assembled monolayer 735 remains on the p-type metal layer 725.

[0098] In some implementations, a thermal decomposition operation can be performed to remove the self-assembled monolayer 735 from the p-type metal layer 725 of the p-type gate structure 710b. The thermal decomposition operation can include heating the self-assembled monolayer 735 to a temperature included in the range of about 300 degrees Celsius to about 500 degrees Celsius to decompose the hydrocarbon chains in the self-assembled monolayer 735. Decomposing the side chain groups 745 (e.g., hydrocarbon chains) in the self-assembled monolayer 735 causes the self-assembled monolayer 735 to desorb from the p-type metal layer 725.

[0099] In some implementations, a plasma treatment operation can be performed on the self-assembled monolayer 735 to remove the self-assembled monolayer 735 from the p-type metal layer 725. The plasma treatment operation can include using a plasma (e.g., an oxygen-based plasma, a nitrogen-based plasma) to clean the surface of the p-type metal layer 725. This causes the self-assembled monolayer 735 to peel off from the surface of the p-type metal layer 725.

[0100] In some implementations, the self-assembled monolayer 735 is completely removed from the p-type metal layer 725. In some implementations, as Figure 7G shown, the removal of the self-assembled monolayer 735 can leave a self-assembled monolayer residue 755 on the p-type metal layer 725. The self-assembled monolayer residue 755 can include residual anchoring groups 740 of the self-assembled monolayer 735 that are adsorbed on the surface of the p-type metal layer 725. The residual anchoring groups 740 can include ligands of one or more elements of the residual anchoring groups 740, such as sulfur (S) ligands (e.g., in implementations where the anchoring groups 740 of the self-assembled monolayer 735 include thiol groups), silicon (Si) ligands (e.g., in implementations where the anchoring groups 740 of the self-assembled monolayer 735 include trichlorosilane (SiCl3)), and / or phosphorus (P) ligands (e.g., in implementations where the anchoring groups 740 of the self-assembled monolayer 735 include phosphonates), etc.

[0101] In some implementations, the deposition of the material of the n-type metal layer 750 on the p-type metal layer 725 is completely blocked by the self-assembled monolayer 735. In some implementations, (e.g., in implementations where at least a portion of the self-assembled monolayer 735 on the p-type metal layer 725 is discontinuous and / or porous) the self-assembled monolayer residue 755 also includes an n-type metal layer residue. The n-type metal layer residue can include aluminum (Al) residues remaining on the p-type metal layer 725 of the p-type gate structure 710b after the formation of the n-type metal layer 750 on the n-type gate structure 710a. However, the thickness of the self-assembled monolayer residue 755 (including aluminum residues) on the p-type gate structure 710b (represented as dimension D1 in Figure 7G is less than the thickness of the n-type metal layer 750 on the n-type gate structure 710a (in Figure 7Gis represented as dimension D2), because the self-assembled monolayer 735 is used to block or inhibit the deposition of the material of the n-type metal layer 750 on the p-type gate structure 710b. For example, the thickness (dimension D2) of the n-type metal layer 750 on the n-type gate structure 710a can be in the range of about 5 angstroms to about 50 angstroms, while the thickness (dimension D1) of the self-assembled monolayer residue 755 (including aluminum residue) on the p-type gate structure 710b can be less than about 5 angstroms and as thin as about 0.1 angstroms. Due to the minimum thickness of the self-assembled monolayer residue 755, the self-assembled monolayer residue 755 can be a discontinuous film (e.g., a porous film) remaining on the p-type metal layer 725. However, other values and ranges for the thickness of the self-assembled monolayer residue 755 and the thickness of the n-type metal layer 750 are within the scope of the present disclosure.

[0102] The smaller thickness (dimension D1) of the self-assembled monolayer residue 755 (including aluminum residue) on the p-type gate structure 710b results in a reduced or minimized effect of the n-type metal layer 750 on the work function of the p-type gate structure 710b. In particular, compared to the case where the self-assembled monolayer 735 is used to block the formation of the n-type metal layer 750 on the p-type gate structure 710b, the smaller thickness (dimension D1) of the self-assembled monolayer residue 755 (including aluminum residue) on the p-type gate structure 710b causes the work function of the p-type gate structure 710b to be closer to the valence band of the material of the nanostructure channel 315b. Therefore, using the self-assembled monolayer 735 to block the formation of the n-type metal layer 750 on the p-type gate structure 710b enables the work function of the p-type gate structure 710b to be tuned to achieve the p-type threshold voltage (PV t ) of the PMOS nanostructure transistor, and this p-type threshold voltage (PV t ) enables the PMOS nanostructure transistor to operate effectively and have low current leakage.

[0103] As Figure 7HAs shown, a gate electrode layer 760 of an n-type gate structure 710a is formed over the n-type metal layer 750, and a gate electrode layer 760 of a p-type gate structure 710b is formed over the p-type metal layer 725. In some implementations, in the case where the self-assembled monolayer residue 755 remains on the p-type metal layer 725, the gate electrode layer 760 is formed over the self-assembled monolayer residue 755. In some implementations, separate gate electrode layers 760 are formed for the n-type gate structure 710a and the p-type gate structure 170b, respectively. In some implementations, a common gate electrode layer 760 is formed for the n-type gate structure 710a and the p-type gate structure 710b. In some implementations, an adhesion layer is first formed over the n-type metal layer 750 and / or the p-type metal layer 725, and the gate electrode layer 760 is formed over the adhesion layer. The adhesion layer may include titanium nitride (TiN) and / or another material that promotes adhesion of the gate electrode layer 760 to the n-type metal layer 750 and / or the p-type metal layer 725.

[0104] The gate electrode layer 760 includes one or more metal materials such as ruthenium (Ru), tungsten (W), cobalt (Co), copper (Cu), and / or molybdenum (Mo), etc. A deposition tool may be used to deposit the gate electrode layer 760 using CVD techniques, PVD techniques, ALD techniques, electroplating techniques, and / or other suitable deposition techniques. The gate electrode layer 760 may be deposited in one or more deposition operations. In some implementations, a seed layer is first deposited, and the gate electrode layer 760 is deposited over the seed layer. In some implementations, a planarization tool may be used to perform a CMP operation or another type of planarization operation to planarize the gate electrode layer 760 after depositing the gate electrode layer 760.

[0105] In this manner, the semiconductor device 105 may include a plurality of nanostructured channels 315a arranged along a z-direction that is substantially perpendicular to the semiconductor substrate 110 of the semiconductor device 105 and a plurality of nanostructured channels 315b arranged along a z-direction that is substantially perpendicular to the semiconductor substrate 110 of the semiconductor device 105. The nanostructured channels 315a and the nanostructured channels 315b may be adjacent to each other in the semiconductor device 105. The semiconductor device 105 may include an n-type gate structure 710a that surrounds the nanostructured channel 315a and a p-type gate structure 710b that surrounds the nanostructured channel 315b. The p-type gate structure 710b may include a p-type metal layer 725 and a self-assembled monolayer residue 755 on the p-type metal layer 725. The n-type gate structure 710a may include an n-type metal layer 750. The self-assembled monolayer residue 755 may include one or more ligands of the anchoring groups of the self-assembled monolayer 735 that is used to block or inhibit deposition of the n-type metal layer 750 on the p-type metal layer 725, and / or the self-assembled monolayer residue 755 may include residual material of the n-type metal layer 750.

[0106] As pointed out above, Figures 7A to 7H is provided as an example. Other examples may be different from those Figures 7A to 7H described.

[0107] Figure 8 is a diagram of Example 800 of the elemental concentrations in the gate structure of the nanostructure transistor described herein. In particular, Example 800 includes the aluminum concentration 805 in the n-type gate structure 710a and the aluminum concentration 810 in the p-type gate structure 710b of the nanostructure transistor, which is formed by using a self-assembled monolayer 735 to block or inhibit the deposition of the n-type metal layer 750 on the p-type gate structure 710b, as described in connection with Figures 7A to 7H the description.

[0108] As Figure 8 shown, the aluminum concentration 805 and the aluminum concentration 810 are shown as functions of the intensity 815 and depth 820 in the n-type gate structure 710a and the p-type gate structure 710b. The intensity 815 of the aluminum concentration 805 is highest in the n-type metal layer 750 of the n-type gate structure 710a, since the n-type metal layer 750 is composed of an n-type work function metal containing aluminum (such as titanium aluminum (TiAl) or tantalum aluminum carbide (TaAlC), etc.). The intensity 815 of the aluminum concentration 810 in the p-type gate structure 710b is highest in the self-assembled monolayer residue 755, since the self-assembled monolayer residue 755 may include a small amount of aluminum residue on the p-type metal layer 725. However, the intensity 815 of the aluminum in the self-assembled monolayer residue 755 is less than the intensity 815 of the aluminum in the n-type metal layer 750, since the self-assembled monolayer 735 is used to block or inhibit the deposition of the n-type metal layer 750 on the p-type gate structure 710b.

[0109] As pointed out above, Figure 8 is provided as an example. Other examples may be different from those Figure 8 described.

[0110] Figure 9 is a diagram of Example 900 of the elemental composition of the gate structure of the nanostructure transistor described herein. In particular, Example 900 includes the elemental composition 905 of the p-type gate structure 710b of the nanostructure transistor, which is formed by using a self-assembled monolayer 735 to block or inhibit the deposition of the n-type metal layer 750 on the p-type gate structure 710b, as described in connection with Figures 7A to 7H the description.

[0111] As Figure 9As shown, elemental component 905 is shown as a function of concentration 910 and depth 915 in p-type gate structure 710b. Elemental component 905 includes self-assembled monolayer residue component 920 and n-type metal layer residue component 925. Self-assembled monolayer residue component 920 corresponds to self-assembled monolayer residue 755 that may remain on p-type metal layer 725 of p-type gate structure 710b after removal of self-assembled monolayer 735.

[0112] Self-assembled monolayer residue component 920 may include ligands of one or more elements of anchoring group 740 of self-assembled monolayer 735 adsorbed on the surface of p-type metal layer 725 after removal of self-assembled monolayer 735. Ligands may include, for example, sulfur (S) ligands (e.g., in implementations where anchoring group 740 of self-assembled monolayer 735 includes a thiol group), silicon (Si) ligands (e.g., in implementations where anchoring group 740 of self-assembled monolayer 735 includes trichlorosilane (SiCl3)), and / or phosphorus (P) ligands (e.g., in implementations where anchoring group 740 of self-assembled monolayer 735 includes a phosphonate), etc.

[0113] N-type metal layer residue component 925 may include aluminum (Al) residue remaining on p-type metal layer 725 of p-type gate structure 710b after formation of n-type metal layer 750 on n-type gate structure 710a. As Figure 8 pointed out, the concentration of aluminum residue on p-type gate structure 710b is less than the concentration of aluminum on n-type gate structure 710a because self-assembled monolayer 735 is used to block or inhibit deposition of the material of n-type metal layer 750 on p-type gate structure 710b.

[0114] As pointed out above, Figure 9 is provided as an example. Other examples may be different from those described with respect to Figure 9 described.

[0115] Figures 10A to 10D is an illustration of an example implementation of a gate structure in the nanostructure transistor described herein. In particular, Figures 10A to 10D illustrates various example implementations of p-type metal layer 725 (e.g., p-type work function metal layer) of p-type gate structure 710b of the nanostructure transistor included in semiconductor device 105 and / or various example implementations of n-type metal layer 750 (e.g., n-type work function metal layer) of n-type gate structure 710a.

[0116] Figure 10AAn example implementation 1000 is shown, where a seam 1005 occurs in the p-type metal layer 725 of the p-type gate structure 710b. The seam 1005 may occur between portions of the p-type metal layer 725 that are located between vertically adjacent nanostructure channels 315b. In some implementations, a small amount of the self-assembled monolayer film 735 described herein may be deposited in the seam 1005.

[0117] Figure 10B An example implementation 1010 is shown, where between vertically adjacent nanostructure channels 315b, the p-type metal layer 725 of the p-type gate structure 710b is not merged. In some implementations, the space between portions of the p-type metal layer 725 that are located over vertically adjacent nanostructure channels 315b is filled with another p-type metal layer. In some implementations, the space between portions of the p-type metal layer 725 that are located over vertically adjacent nanostructure channels 315b is filled with the gate electrode layer 760. In some implementations, a small amount of the self-assembled monolayer film 735 described herein may be deposited in the space between portions of the p-type metal layer 725 that are located over vertically adjacent nanostructure channels 315b.

[0118] Figure 10C An example implementation 1015 is shown, where in the space between vertically adjacent nanostructure channels 315b, the p-type metal layer 725 of the p-type gate structure 710b is fully merged.

[0119] Figure 10D An example implementation 1020 is shown, where an adhesion layer 1025 may be included over the n-type metal layer 750 of the n-type gate structure 710a and over the p-type metal layer 725 of the p-type gate structure 710b (including over the self-assembled monolayer residue 755). The adhesion layer 1025 may include titanium nitride (TiN) and / or another suitable material to facilitate adhesion between the n-type metal layer 750 and the gate electrode layer 760, and / or to facilitate adhesion between the p-type metal layer 725 and the gate electrode layer 760.

[0120] As Figure 10D further shown in example implementation 1020 as, between vertically adjacent nanostructure channels 315a, the n-type metal layer 750 of the n-type gate structure 710a is not merged. In some implementations, the adhesion layer 1025 fills the gap between portions of the n-type metal layer 750 that are located between vertically adjacent nanostructure channels 315b.

[0121] As noted above, Figures 10A to 10D is provided as an example. Other examples may be different from those Figures 10A to 10D described.

[0122] Figure 11A and Figure 11B are illustrations of example implementation 1100 of a work function metal layer that forms a gate structure of a nanostructure transistor as described herein. As Figure 11A shown, example implementation 1100 includes forming a self-assembled monolayer 1105, similar to that described in connection with Figure 7E However, in example implementation 1100, the self-assembled monolayer 1105 is formed on the gate dielectric layer 720 of the n-type gate structure 710a, as Figure 11A shown, rather than on the p-type metal layer 725 of the p-type gate structure 710b, as Figure 7E shown. Thus, in example implementation 1100, the self-assembled monolayer 1105 includes one or more materials that promote the selective deposition of the self-assembled monolayer 1105 on the gate dielectric layer 720 and prevent or inhibit the deposition of the self-assembled monolayer 1105 on the p-type metal layer 725 of the p-type gate structure 710b. In some implementations, the self-assembled monolayer 1105 is formed to have a thickness in the range greater than 0 angstroms and less than or approximately equal to 2 angstroms. However, other values and ranges for the thickness of the self-assembled monolayer 1105 are within the scope of the present disclosure.

[0123] As Figure 11B shown, forming the self-assembled monolayer 1105 on the gate dielectric layer 720 of the n-type gate structure 710a enables the deposition of an additional layer on the p-type gate structure 710b, while the self-assembled monolayer 1105 blocks or inhibits the deposition of the additional layer on the n-type gate structure 710a. In this manner, the self-assembled monolayer 1105 promotes the selective formation of an additional layer on the p-type gate structure 710b. In some implementations, the additional layer includes an additional p-type work function layer. For example, the self-assembled monolayer 1105 blocks or inhibits the deposition of another p-type metal layer 1110 on the n-type gate structure 710a, which enables the p-type metal layer 1110 to be selectively formed on the p-type metal layer 725 of the p-type gate structure 710b.

[0124] In some implementations, the self-assembled monolayer 1105 is subsequently removed, and the operations described in connection with Figures 7E to 7H are performed to selectively form an n-type metal layer 750 on the n-type gate structure 710a using another self-assembled monolayer 735, while the self-assembled monolayer 735 blocks or inhibits the deposition of the n-type metal layer 750 on the p-type metal layer 1110 of the p-type gate structure 710b.

[0125] As noted above, Figure 11A and Figure 11B are provided as examples. Other examples may be associated with those regarding Figure 11A andFigure 11B is different from that described.

[0126] Figure 12 is a flowchart of an example process 1200 associated with forming a semiconductor device described herein. In some implementations, one or more semiconductor processing tools (e.g., deposition tools, exposure tools, development tools, etching tools, planarization tools, ion implantation tools, annealing tools, wafer / die transfer tools, and / or another type of semiconductor processing tool) are used to perform Figure 12 one or more process blocks of.

[0127] As Figure 12 shown, process 1200 may include: forming a first plurality of nanostructured channel layers arranged along a direction substantially perpendicular to the semiconductor substrate of the semiconductor device (block 1210). For example, as described herein, one or more semiconductor processing tools may be used to form a first plurality of nanostructured channel layers (e.g., nanostructured channels 315b) arranged along a direction (e.g., the z-direction) substantially perpendicular to the semiconductor substrate (e.g., semiconductor substrate 110) of the semiconductor device (e.g., semiconductor device 105).

[0128] As Figure 12 further shown, process 1200 may include: forming a second plurality of nanostructured channel layers arranged along the direction substantially perpendicular to the semiconductor substrate (block 1220). For example, as described herein, one or more semiconductor processing tools may be used to form a second plurality of nanostructured channel layers (e.g., nanostructured channels 315a) arranged along the direction substantially perpendicular to the semiconductor substrate.

[0129] As Figure 12 further shown, process 1200 may include: forming a first type of metal layer surrounding each of the first plurality of nanostructured channel layers (block 1230). For example, as described herein, one or more semiconductor processing tools may be used to form a first type of metal layer (e.g., p-type metal layer 725) surrounding each of the first plurality of nanostructured channel layers.

[0130] As Figure 12 further shown, process 1200 may include: forming a self-assembled monolayer on the first type of metal layer (block 1240). For example, as described herein, one or more semiconductor processing tools may be used to form a self-assembled monolayer (e.g., self-assembled monolayer 735) on the first type of metal layer.

[0131] As Figure 12As further shown, process 1200 may include: forming a second type of metal layer (block 1250) on the second plurality of nanostructured channel layers. For example, as described herein, one or more semiconductor processing tools may be used to form a second type of metal layer (e.g., n-type metal layer 750) on the second plurality of nanostructured channel layers. In some implementations, the self-assembled monolayer inhibits the formation of the second type of metal layer on the first type of metal layer.

[0132] Process 1200 may include additional implementations, such as any single implementation described below and / or incorporated in one or more other processes described elsewhere herein, or any combination of these implementations.

[0133] In a first implementation, forming the self-assembled monolayer includes: depositing a solution containing the material of the self-assembled monolayer by spin coating, and performing a spin drying operation to cure the solution to form the self-assembled monolayer.

[0134] In a second implementation, either alone or in combination with the first implementation, process 1200 includes: removing the self-assembled monolayer after forming the second type of metal layer.

[0135] In a third implementation, either alone or in combination with one or more of the first and second implementations, after removing the self-assembled monolayer, residues of the self-assembled monolayer (e.g., self-assembled monolayer residues 755) remain on the first type of metal layer.

[0136] In a fourth implementation, either alone or in combination with one or more of the first to third implementations, removing the self-assembled monolayer includes: performing a thermal decomposition operation on the self-assembled monolayer to decompose the hydrocarbon chains of the self-assembled monolayer.

[0137] In a fifth implementation, either alone or in combination with one or more of the first to fourth implementations, performing the thermal decomposition operation includes: heating the self-assembled monolayer to a temperature included in the range of about 300 degrees Celsius to about 500 degrees Celsius.

[0138] In a sixth implementation, either alone or in combination with one or more of the first to fifth implementations, removing the self-assembled monolayer includes: performing a plasma treatment operation on the self-assembled monolayer to remove the self-assembled monolayer.

[0139] In a seventh implementation, either alone or in combination with one or more of the first to sixth implementations, forming the self-assembled monolayer includes: forming the self-assembled monolayer into a discontinuous thin film.

[0140] Although Figure 12illustrates an example block of process 1200, but in some implementations, process 1200 includes additional blocks, fewer blocks, different blocks, or differently arranged blocks compared to those depicted in Figure 12 Two or more blocks of process 1200 may be performed in parallel, additionally or alternatively.

[0141] Figure 13 is a flowchart of an example process 1300 associated with forming a semiconductor device described herein. In some implementations, one or more semiconductor processing tools (e.g., deposition tools, exposure tools, development tools, etching tools, planarization tools, ion implantation tools, annealing tools, wafer / die transfer tools, and / or another type of semiconductor processing tool) are used to perform Figure 13 one or more process blocks of.

[0142] As Figure 13 shown, process 1300 may include: forming a first plurality of nanostructured channel layers arranged along a direction substantially perpendicular to the semiconductor substrate of the semiconductor device (block 1310). For example, as described herein, one or more semiconductor processing tools may be used to form a first plurality of nanostructured channel layers (e.g., nanostructured channels 315b) arranged along a direction (z-direction) substantially perpendicular to the semiconductor substrate (e.g., semiconductor substrate 110) of the semiconductor device (e.g., semiconductor device 105).

[0143] As Figure 13 further shown, process 1300 may include: forming a second plurality of nanostructured channel layers arranged along the direction substantially perpendicular to the semiconductor substrate (block 1320). For example, as described herein, one or more semiconductor processing tools may be used to form a second plurality of nanostructured channel layers (e.g., nanostructured channels 315a) arranged along the direction substantially perpendicular to the semiconductor substrate.

[0144] As Figure 13 further shown, process 1300 may include: forming a p-type metal layer of a first gate structure on the first plurality of nanostructured channel layers (block 1330). For example, as described herein, one or more semiconductor processing tools may be used to form a p-type metal layer (e.g., p-type metal layer 725) of a first gate structure (e.g., p-type gate structure 710b) on the first plurality of nanostructured channel layers.

[0145] As Figure 13 further shown, process 1300 may include: depositing a solution onto the p-type metal layer (block 1340). For example, as described herein, one or more semiconductor processing tools may be used to deposit a solution onto the p-type metal layer. In some implementations, the solution includes a material dissolved in a solvent.

[0146] As Figure 13 As further shown, process 1300 may include: curing the solution to form a self-assembled monolayer film containing the material on the p-type metal layer (block 1350). For example, as described herein, one or more semiconductor processing tools may be used to cure the solution to form a self-assembled monolayer film containing the material on the p-type metal layer (e.g., self-assembled monolayer film 735).

[0147] As Figure 13 As further shown, process 1300 may include: forming an n-type metal layer of a second gate structure on a second plurality of nanostructured channel layers (block 1360). For example, as described herein, one or more semiconductor processing tools may be used to form an n-type metal layer (e.g., n-type metal layer 750) of a second gate structure (e.g., n-type gate structure 710a) on a second plurality of nanostructured channel layers. In some implementations, the material of the self-assembled monolayer film includes a side chain group (e.g., side chain group 745) that inhibits the adsorption of the n-type metal layer on the p-type metal layer.

[0148] Process 1300 may include additional implementations, such as any single implementation described below and / or incorporated in one or more other processes described elsewhere herein or any combination of these implementations.

[0149] In a first implementation, the material of the self-assembled monolayer film includes an anchoring group (e.g., anchoring group 740) that promotes the adsorption of the material of the self-assembled monolayer film on the p-type metal layer.

[0150] In a second implementation, either alone or in combination with the first implementation, the anchoring group includes at least one of an amino group, a thiol group, a carboxyl group, a carbonyl group, trichlorosilane (SiCl3), or a phosphonate ester.

[0151] In a third implementation, either alone or in combination with one or more of the first and second implementations, the side chain group includes an aryl hydrocarbon chain.

[0152] In a fourth implementation, either alone or in combination with one or more of the first to third implementations, process 1300 includes: removing the self-assembled monolayer film after forming the n-type metal layer, wherein after removing the self-assembled monolayer film, a self-assembled monolayer film residue (e.g., self-assembled monolayer film residue 755) remains on the p-type metal layer.

[0153] In a fifth implementation, either alone or in combination with one or more of the first to fourth implementations, the self-assembled monolayer film residue includes at least one of a sulfur (S) ligand, a silicon (Si) ligand, or a phosphorus (P) ligand.

[0154] In a sixth implementation, either alone or in combination with one or more of the first through fifth implementations, the thickness of the self-assembled monolayer residue (e.g., dimension D1) is less than the thickness of the n-type metal layer on the second plurality of nanostructured channel layers (e.g., dimension D2).

[0155] In a seventh implementation, either alone or in combination with one or more of the first through sixth implementations, the solvent includes at least one of a γ-butyrolactone (GBL) solvent, a diethylformamide (DEF) solvent, a propylene glycol monomethyl ether acetate (PGMEA) solvent, or a propylene glycol monomethyl ether (PGME) solvent.

[0156] Although Figure 13 example blocks of process 1300 are shown, in some implementations, process 1300 includes additional blocks, fewer blocks, different blocks, or differently arranged blocks compared to those depicted in Figure 13 . Additionally or alternatively, two or more blocks of process 1300 may be executed in parallel.

[0157] Figures 14A to 14I is a diagram of an example implementation 1400 of a work function metal layer that forms a gate structure of a nanostructured transistor described herein. Example implementation 1400 includes an example of using different self-assembled monolayers for an n-type gate structure 710a and a p-type gate structure 710b to inhibit the growth of opposite metal layer types. For example, as described in connection with Figures 14A to 14I , a first self-assembled monolayer may be formed on the n-type gate structure 710a to inhibit the growth of the p-type metal layer 725 on the n-type gate structure 710a, and a second (different) self-assembled monolayer may be formed on the p-type gate structure 710b to inhibit the growth of the n-type metal layer 750 on the p-type gate structure 710b.

[0158] As Figure 14A shown, example implementation 1400 includes forming a self-assembled monolayer 1405 on the gate dielectric layer 720 of the n-type gate structure 710a and on the gate dielectric layer 720 of the p-type gate structure 710b, as Figure 14A shown. Thus, in example implementation 1400, the self-assembled monolayer 1405 includes one or more materials that promote selective deposition of the self-assembled monolayer 1405 on the gate dielectric layer 720. For example, the self-assembled monolayer 1405 may include an anchoring group that promotes adsorption of the material to the gate dielectric layer 720.

[0159] In some implementations, the material of the self-assembled monolayer 1405 is resistant to the adsorption of the precursor of the p-type metal layer 725 formed for the p-type gate structure 710b. For example, the material of the self-assembled monolayer 1405 may include side chain groups that are resistant to the adsorption of titanium nitride (TiN) precursors (such as titanium tetrachloride (TiCl4) and / or ammonia (NH3), etc.). In this way, the self-assembled monolayer 1405 can be used to inhibit the growth of the p-type metal layer 725 on the n-type metal gate structure 710a.

[0160] As Figure 14B shown, a mask layer 1410 is formed on the n-type gate structure 710a. The mask layer 140 may include a photoresist layer formed using a deposition tool (e.g., using a spin coating technique). Alternatively, the mask layer 1410 may include another type of mask layer and may be formed using another deposition technique.

[0161] As Figure 14C shown, the self-assembled monolayer 1405 is removed from the p-type gate structure 710b, while the mask layer 1410 protects the self-assembled monolayer 1405 on the n-type gate structure 710a. In other words, the self-assembled monolayer 1405 is selectively removed from the p-type gate structure 710b such that the self-assembled monolayer 1405 remains on the n-type gate structure 710a. One or more of the techniques described in conjunction with Figure 7G can be used to remove the self-assembled monolayer 1405. In some implementations, another technique may be used to remove the self-assembled monolayer 1405.

[0162] As Figure 14D further shown, the p-type metal layer 725 is selectively formed on the gate dielectric layer 720 of the nanostructure channel 315b and not on the nanostructure channel 315 because the self-assembled monolayer 1405 blocks or inhibits the growth of the p-type metal layer 725 on the nanostructure channel 315a (e.g., on the n-type metal layer 750 formed thereon).

[0163] Forming the p-type metal layer 725 on the nanostructure channel 315b but not on the nanostructure channel 315a using the self-assembled monolayer 1405 enables the p-type metal layer 725 to be selectively formed on the nanostructure channel 315b without using subsequent patterning and etching steps of forming a mask layer on the p-type metal layer 725 on the nanostructure channel 315b and etching the p-type metal layer 725 on the nanostructure channel 315a to remove the p-type metal layer 725 from the nanostructure channel 315a. This prevents residual material of the p-type metal layer 725 from remaining on the nanostructure channel 315a. Otherwise, residual material of the p-type metal layer 725 may remain on the nanostructure channel 315a because the p-type metal layer 725 is not completely removed from the nanostructure channel 315b.

[0164] The self-assembled monolayer 1405 enables the p-type metal layer 725 to be selectively formed on the nanostructured channel 315b because the material and monolayer structure of the self-assembled monolayer 1405 inhibit the precursors of the material of the p-type metal layer 725 from being adsorbed onto the surface of the gate dielectric layer 720 on the nanostructured channel 315a. For example, the material of the self-assembled monolayer 1405 inhibits the adsorption of precursors such as titanium tetrachloride (TiCl4) and / or ammonia (NH3), which can be adsorbed onto the surface of the gate dielectric layer 720 on the nanostructured channel 315b and react to form titanium nitride (TiN) of the p-type metal layer 725. In particular, the chemical incompatibility between the side chain groups of the material of the self-assembled monolayer 1405 and the precursors of the material of the p-type metal layer 725, either alone or in combination with the surface barrier provided by the dense molecular monolayer structure of the self-assembled monolayer 1405, can inhibit the adsorption of the precursors of the material of the p-type metal layer 725.

[0165] As Figure 14E shown, after the p-type metal layer 725 is formed on the gate dielectric layer 720 of the p-type gate structure 710b, the self-assembled monolayer 1405 is removed from the n-type gate structure 710a. One or more of the techniques described in connection with Figure 7G can be used to remove the self-assembled monolayer 1405. In some implementations, another technique can be used to remove the self-assembled monolayer 1405.

[0166] As Figure 14F shown, a self-assembled monolayer 735 is formed on the p-type metal layer 725 of the p-type gate structure 710b. The self-assembled monolayer 735 can include a material different from the material of the self-assembled monolayer 1405. This enables the self-assembled monolayer 735 to be selectively deposited on the p-type metal layer 725 with little or no deposition of the self-assembled monolayer 735 on the gate dielectric layer 720 of the n-type gate structure 710a. In addition, the material of the self-assembled monolayer 735 can be resistant to the adsorption of precursors for the n-type metal layer 750 to be formed for the n-type gate structure 710a. For example, the material of the self-assembled monolayer 735 can be resistant to the adsorption of titanium aluminum carbon (TiAlC) precursors such as titanium tetrachloride (TiCl4) and / or triethylaluminum (Al2(C2H5)6 or TEA), etc. In this way, the self-assembled monolayer 735 can be used to inhibit the growth of the n-type metal layer 750 on the p-type metal gate structure 710b. For example, the self-assembled monolayer 735 can include one or more of the materials described in connection with Figure 7E

[0167] As Figure 14G ​As shown, after forming a self-assembled monolayer 735 on the p-type metal layer 725 of the p-type gate structure 710b, an n-type metal layer 750 is formed on the n-type gate structure 710a. The self-assembled monolayer 735 on the p-type metal layer 725 blocks or inhibits the formation of the n-type metal layer 750 on the p-type metal layer 725. Thus, the self-assembled monolayer 735 enables the n-type metal layer 750 to be selectively deposited on the gate dielectric layer 720 over the nanostructure channel 315a. The n-type metal layer 750 can be formed as described in connection with Figure 7F The description.

[0168] As Figure 14H Shown, after forming the n-type metal layer 750, the self-assembled monolayer 735 can subsequently be removed. For example, one or more techniques described in connection with Figure 7G The description can be used to completely or partially remove the self-assembled monolayer 735.

[0169] As Figure 14I Shown, a gate electrode layer 760 of the n-type gate structure 710a is formed over the n-type metal layer 750, and a gate electrode layer 760 of the p-type gate structure 710b is formed over the p-type metal layer 725. The gate electrode layer 760 can be formed in a similar manner as described above in connection with Figure 7H The description.

[0170] As noted above, Figures 14A to 14I Is provided as an example. Other examples can be different from those described with respect to Figures 14A to 14I The description.

[0171] Figure 15 Is a flowchart of an example process 1500 associated with forming a semiconductor device described herein. In some implementations, one or more semiconductor processing tools (e.g., deposition tools, exposure tools, development tools, etching tools, planarization tools, ion implantation tools, annealing tools, wafer / die transfer tools, and / or another type of semiconductor processing tool) are used to perform Figure 15 One or more process blocks of.

[0172] As Figure 15 Shown, process 1500 can include: forming a first plurality of nanostructure channel layers disposed along a direction substantially perpendicular to the semiconductor substrate of the semiconductor device (block 1510). For example, as described herein, one or more semiconductor processing tools can be used to form a first plurality of nanostructure channel layers (e.g., nanostructure channels 315b) disposed along a direction (z-direction) substantially perpendicular to the semiconductor substrate (e.g., semiconductor substrate 110) of the semiconductor device (e.g., semiconductor device 105).

[0173] As Figure 15Further shown, process 1500 may include: forming a second plurality of nanostructured channel layers arranged along a direction substantially perpendicular to the semiconductor substrate (block 1520). For example, as described herein, one or more semiconductor processing tools may be used to form a second plurality of nanostructured channel layers (e.g., nanostructured channels 315a) arranged along a direction substantially perpendicular to the semiconductor substrate.

[0174] As Figure 15 Further shown, process 1500 may include: forming a gate dielectric layer around the first and second pluralities of nanostructured channel layers (block 1530). For example, as described herein, one or more semiconductor processing tools may be used to form a gate dielectric layer (e.g., gate dielectric layer 720) around the first and second pluralities of nanostructured channel layers.

[0175] As Figure 15 Further shown, process 1500 may include: forming a self-assembled monolayer on the gate dielectric layer around the second plurality of nanostructured channel layers (block 1540). For example, as described herein, one or more semiconductor processing tools may be used to form a self-assembled monolayer (e.g., self-assembled monolayer 1405) on the gate dielectric layer around the second plurality of nanostructured channel layers.

[0176] As Figure 15 Further shown, process 1500 may include: forming a p-type metal layer of a first gate structure on the first plurality of nanostructured channel layers (block 1550). For example, as described herein, one or more semiconductor processing tools may be used to form a p-type metal layer (e.g., p-type metal layer 725) of a first gate structure (e.g., p-type gate structure 710b) on the first plurality of nanostructured channel layers. In some implementations, the material of the self-assembled monolayer inhibits the adsorption of the p-type metal layer on the gate dielectric layer around the second plurality of nanostructured channel layers.

[0177] As Figure 15 Further shown, process 1500 may include: after forming the p-type metal layer, forming an n-type metal layer of a second gate structure on the second plurality of nanostructured channel layers (block 1560). For example, as described herein, one or more semiconductor processing tools may be used to form an n-type metal layer (e.g., n-type metal layer 750) of a second gate structure (e.g., n-type gate structure 710a) on the second plurality of nanostructured channel layers after forming the p-type metal layer.

[0178] Process 1500 may include additional implementations, such as any single implementation described below and / or incorporated in one or more other processes described elsewhere herein, or any combination of these implementations.

[0179] In a first implementation, the self-assembled monolayer is a first self-assembled monolayer, and process 1500 includes: depositing a solution onto a p-type metal layer on a first plurality of nanostructured channels before forming an n-type metal layer, where the solution includes a material dissolved in a solvent, curing the solution to form a second self-assembled monolayer (e.g., self-assembled monolayer 735) containing the material on the p-type metal layer, where the material of the second self-assembled monolayer includes a side chain group (e.g., side chain group 745) that inhibits the adsorption of the n-type metal layer onto the p-type metal layer.

[0180] In a second implementation, either alone or in combination with the first implementation, the material of the self-assembled monolayer includes an anchoring group (e.g., anchoring group 740) that promotes the adsorption of the material of the self-assembled monolayer onto the p-type metal layer, where the anchoring group includes at least one of an amino group, a thiol group, a carboxyl group, a carbonyl group, trichlorosilane (SiCl3), or a phosphonate.

[0181] In a third implementation, either alone or in combination with one or more of the first and second implementations, process 1500 includes: removing the second self-assembled monolayer after forming the n-type metal layer, where after removing the second self-assembled monolayer, a self-assembled monolayer residue (e.g., self-assembled monolayer residue 755) remains on the p-type metal layer, where the second self-assembled monolayer residue includes at least one of a sulfur (S) ligand, a silicon (Si) ligand, or a phosphorus (P) ligand.

[0182] In a fourth implementation, either alone or in combination with one or more of the first to third implementations, the solvent includes at least one of a γ-butyrolactone (GBL) solvent, a diethylformamide (DEF) solvent, a propylene glycol monomethyl ether acetate (PGMEA) solvent, or a propylene glycol monomethyl ether (PGME) solvent.

[0183] In a fifth implementation, either alone or in combination with one or more of the first to fourth implementations, process 1500 includes: removing the self-assembled monolayer from a gate dielectric layer surrounding a second plurality of nanostructured channel layers before forming an n-type gate structure on the second plurality of nanostructured channel layers.

[0184] In a sixth implementation, either alone or in combination with one or more of the first to fifth implementations, the self-assembled monolayer includes a material that promotes the adsorption of the self-assembled monolayer onto the gate dielectric layer and inhibits the adsorption of a precursor of the p-type metal layer onto the gate dielectric layer.

[0185] In a seventh implementation, either alone or in combination with one or more of the first through sixth implementations, forming a self-assembled monolayer on a gate dielectric layer surrounding a second plurality of nanostructured channel layers includes: forming a self-assembled monolayer on a gate dielectric layer surrounding the second plurality of nanostructured channel layers and surrounding a first plurality of nanostructured channel layers; forming a mask layer (e.g., masking layer 1410) over the second plurality of nanostructured channel layers; and removing the self-assembled monolayer from the first plurality of nanostructured channel layers while the mask layer prevents the self-assembled monolayer from being removed from the second plurality of nanostructured channel layers.

[0186] Although Figure 15 example blocks of process 1500 are shown, in some implementations, process 1500 includes additional blocks, fewer blocks, different blocks, or differently arranged blocks compared to those depicted Figure 15 herein. Additionally or alternatively, two or more blocks of process 1500 may be executed in parallel.

[0187] In this manner, the techniques described herein include forming each (different) type of gate metal for PMOS nanostructured transistors and maintaining the intrinsic NMOS nanostructured transistors of a semiconductor device. A p-type gate metal may be formed around the nanostructured channel of a PMOS nanostructured transistor. A self-assembled monolayer may then be formed on the surface of the p-type gate metal layer. During formation of an n-type gate metal around the nanostructured channel of an NMOS nanostructured transistor, the self-assembled monolayer on the p-type gate metal prevents the formation of the n-type gate metal on the p-type gate metal. This results in little deposition of the n-type gate metal on the p-type gate metal, which minimizes the effect of the p-type threshold voltage (PV t ) on the PMOS nanostructured transistor. In this manner, the techniques described herein enable the work functions of both the NMOS nanostructured transistors and the PMOS nanostructured transistors to be tuned to achieve the desired threshold voltages for the NMOS nanostructured transistors and the PMOS nanostructured transistors. This enables low current leakage to be achieved for both the NMOS nanostructured transistors and the PMOS nanostructured transistors and enables high operating efficiency to be achieved for both the NMOS nanostructured transistors and the PMOS nanostructured transistors.

[0188] As described in more detail above, some implementations described herein provide a method. The method includes: forming a first plurality of nanostructured channel layers disposed along a direction substantially perpendicular to a semiconductor substrate of a semiconductor device. The method includes: forming a second plurality of nanostructured channel layers disposed along the direction substantially perpendicular to the semiconductor substrate. The method includes: forming a first type of metal layer surrounding each of the first plurality of nanostructured channel layers; The method includes: forming a self-assembled monolayer on the first type of metal layer. The method includes: forming a second type of metal layer on the second plurality of nanostructured channel layers, wherein the self-assembled monolayer inhibits the formation of the second type of metal layer on the first type of metal layer.

[0189] As described in more detail above, some implementations described herein provide a method. The method includes: forming a first plurality of nanostructured channel layers disposed along a direction substantially perpendicular to a semiconductor substrate of a semiconductor device. The method includes: forming a second plurality of nanostructured channel layers disposed along the direction substantially perpendicular to the semiconductor substrate. The method includes: forming a p-type metal layer of a first gate structure on the first plurality of nanostructured channel layers. The method includes: depositing a solution onto the p-type metal layer, wherein the solution includes a material dissolved in a solvent. The method includes: curing the solution to form a self-assembled monolayer containing the material on the p-type metal layer. The method includes: forming an n-type metal layer of a second gate structure on the second plurality of nanostructured channel layers, wherein the material of the self-assembled monolayer includes side chain groups that inhibit the n-type metal layer from adsorbing on the p-type metal layer.

[0190] As described in more detail above, some implementations described herein provide a method. The method includes: forming a first plurality of nanostructured channel layers disposed along a direction substantially perpendicular to a semiconductor substrate of a semiconductor device. The method includes: forming a second plurality of nanostructured channel layers disposed along the direction substantially perpendicular to the semiconductor substrate. The method includes: forming a gate dielectric layer surrounding the first plurality of nanostructured channel layers and the second plurality of nanostructured channel layers. The method includes: forming a self-assembled monolayer on the gate dielectric layer surrounding the second plurality of nanostructured channel layers. The method includes: forming a p-type metal layer of a first gate structure on the first plurality of nanostructured channel layers, wherein the material of the self-assembled monolayer inhibits the p-type metal layer from adsorbing on the gate dielectric layer surrounding the second plurality of nanostructured channel layers. The method includes: forming an n-type metal layer of a second gate structure on the second plurality of nanostructured channel layers after forming the p-type metal layer.

[0191] As described in more detail above, some implementations described herein provide a semiconductor device. The semiconductor device includes a first plurality of nanostructured channel layers disposed along a direction substantially perpendicular to a semiconductor substrate of the semiconductor device. The semiconductor device includes a second plurality of nanostructured channel layers adjacent to the first plurality of nanostructured channel layers and disposed along the direction substantially perpendicular to the semiconductor substrate. The semiconductor device includes a first gate structure that wraps around the first plurality of nanostructured channel layers and includes: a p-type metal layer; and a residue located on the p-type metal layer, the residue including at least one ligand of sulfur (S), silicon (Si), or phosphorus (P). The semiconductor device includes a second gate structure that wraps around each of the second plurality of nanostructured channel layers and includes an n-type metal layer.

[0192] Some specific examples are provided below.

[0193] Example 1. A method includes: forming a first plurality of nanostructured channel layers disposed along a direction substantially perpendicular to a semiconductor substrate of a semiconductor device; forming a second plurality of nanostructured channel layers disposed along the direction substantially perpendicular to the semiconductor substrate; forming a first-type metal layer that wraps around each of the first plurality of nanostructured channel layers; forming a self-assembled monolayer on the first-type metal layer; and forming a second-type metal layer on the second plurality of nanostructured channel layers, wherein the self-assembled monolayer inhibits the formation of the second-type metal layer on the first-type metal layer.

[0194] Example 2. The method according to Example 1, wherein forming the self-assembled monolayer includes: depositing a solution containing a material of the self-assembled monolayer by spin coating; and performing a spin drying operation to cure the solution to form the self-assembled monolayer.

[0195] Example 3. The method according to Example 1, further includes: removing the self-assembled monolayer after forming the second-type metal layer.

[0196] Example 4. The method according to Example 3, wherein after removing the self-assembled monolayer, a residue of the self-assembled monolayer remains on the first-type metal layer.

[0197] Example 5. The method according to Example 3, wherein removing the self-assembled monolayer includes: performing a thermal decomposition operation on the self-assembled monolayer to decompose hydrocarbon chains of the self-assembled monolayer.

[0198] Example 6. The method according to Example 5, wherein performing the thermal decomposition operation includes: heating the self-assembled monolayer to a temperature included in a range of about 300 degrees Celsius to about 500 degrees Celsius.

[0199] Example 7. The method according to Example 3, wherein removing the self-assembled monolayer film comprises: performing a plasma treatment operation on the self-assembled monolayer film to remove the self-assembled monolayer film.

[0200] Example 8. The method according to Example 1, wherein forming the self-assembled monolayer film comprises: forming the self-assembled monolayer film into a discontinuous thin film.

[0201] Example 9. A method comprising: forming a first plurality of nanostructured channel layers arranged in a direction substantially perpendicular to a semiconductor substrate of a semiconductor device; forming a second plurality of nanostructured channel layers arranged in the direction substantially perpendicular to the semiconductor substrate; forming a gate dielectric layer surrounding the first plurality of nanostructured channel layers and surrounding the second plurality of nanostructured channel layers; forming a self-assembled monolayer film on the gate dielectric layer surrounding the second plurality of nanostructured channel layers; forming a p-type metal layer of a first gate structure on the first plurality of nanostructured channel layers, wherein the material of the self-assembled monolayer film inhibits the p-type metal layer from adsorbing on the gate dielectric layer surrounding the second plurality of nanostructured channel layers; and after forming the p-type metal layer, forming an n-type metal layer of a second gate structure on the second plurality of nanostructured channel layers.

[0202] Example 10. The method according to Example 9, wherein the self-assembled monolayer film is a first self-assembled monolayer film; and wherein the method further comprises: before forming the n-type metal layer, depositing a solution onto the p-type metal layer on the first plurality of nanostructured channels, wherein the solution comprises a material dissolved in a solvent; curing the solution to form a second self-assembled monolayer film comprising the material on the p-type metal layer, and wherein the material of the second self-assembled monolayer film comprises side chain groups that inhibit the n-type metal layer from adsorbing on the p-type metal layer.

[0203] Example 11. The method according to Example 10, wherein the material of the second self-assembled monolayer film comprises an anchoring group that promotes the adsorption of the material of the second self-assembled monolayer film on the p-type metal layer; and wherein the anchoring group comprises at least one of the following: amino group, thiol group, carboxyl group, carbonyl group, trichlorosilane (SiCl3) or phosphonate.

[0204] Example 12. The method according to Example 10, further comprising: after forming the n-type metal layer, removing the second self-assembled monolayer film, wherein after removing the second self-assembled monolayer film, self-assembled monolayer film residues remain on the p-type metal layer, and wherein the self-assembled monolayer film residues comprise at least one of the following: sulfur (S) ligand, silicon (Si) ligand, phosphorus (P) ligand.

[0205] Example 13. The method according to Example 10, wherein the solvent comprises at least one of the following: a γ-butyrolactone (GBL) solvent, a diethylformamide (DEF) solvent, a propylene glycol methyl ether acetate (PGMEA) solvent, or a propylene glycol methyl ether (PGME) solvent.

[0206] Example 14. The method according to Example 9, further comprising: removing the self-assembled monolayer from the gate dielectric layer surrounding the second plurality of nanostructured channel layers before forming the n-type gate structure on the second plurality of nanostructured channel layers.

[0207] Example 15. The method according to Example 9, wherein the self-assembled monolayer comprises a material that promotes adsorption of the self-assembled monolayer to the gate dielectric layer and inhibits adsorption of a precursor of the p-type metal layer on the gate dielectric layer.

[0208] Example 16. The method according to Example 9, wherein forming the self-assembled monolayer on the gate dielectric layer surrounding the second plurality of nanostructured channel layers comprises: forming the self-assembled monolayer on the gate dielectric layer surrounding the second plurality of nanostructured channel layers and surrounding the first plurality of nanostructured channel layers; forming a mask layer over the second plurality of nanostructured channel layers; and removing the self-assembled monolayer from the first plurality of nanostructured channel layers while the mask layer prevents the self-assembled monolayer from being removed from the second plurality of nanostructured channel layers.

[0209] Example 17. A semiconductor device, comprising: a first plurality of nanostructured channel layers arranged in a direction substantially perpendicular to a semiconductor substrate of the semiconductor device; a second plurality of nanostructured channel layers adjacent to the first plurality of nanostructured channel layers and arranged in a direction substantially perpendicular to the semiconductor substrate; a first gate structure surrounding the first plurality of nanostructured channel layers, the first gate structure comprising: a p-type metal layer; and a residue on the p-type metal layer, the residue comprising a ligand of at least one of the following: sulfur (S), silicon (SI), or phosphorus (P); and a second gate structure surrounding each of the second plurality of nanostructured channel layers, the second gate structure comprising an n-type metal layer.

[0210] Example 18. The semiconductor device according to Example 17, wherein an aluminum (Al) concentration in the second gate structure is greater than an aluminum concentration in the first gate structure.

[0211] Example 19. The semiconductor device according to Example 17, wherein the residue is a discontinuous thin film on the p-type metal layer.

[0212] Example 20. The semiconductor device according to Example 17, wherein the material of the n-type metal layer is also included on the p-type metal layer; and wherein the thickness of the material of the n-type metal layer on the p-type metal layer is less than the thickness of the n-type metal layer on the second gate structure.

[0213] The terms "about" and "substantially" may mean that the value of a given quantity varies within 5% of that value (e.g., ±1%, ±2%, ±3%, ±4%, ±5% of that value). These values are merely examples and are not intended to be limiting. It should be understood that, according to the present disclosure, the terms "about" and "substantially" may refer to a percentage of the value of a given quantity.

[0214] The features of several embodiments are outlined above so that those skilled in the art can better understand aspects of the present disclosure. Those skilled in the art should appreciate that they can readily use the present disclosure as a basis for designing or modifying other processes and structures for performing the same purposes and / or achieving the same advantages as the embodiments described herein. Those skilled in the art should also recognize that these equivalent constructs do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and alterations without departing from the spirit and scope of the present disclosure.

Claims

1. A method, comprising: forming a first plurality of nanostructured channel layers arranged along a direction substantially perpendicular to a semiconductor substrate of a semiconductor device; forming a second plurality of nanostructured channel layers arranged along the direction substantially perpendicular to the semiconductor substrate; forming a first type of metal layer surrounding each of the first plurality of nanostructured channel layers; forming a self-assembled monolayer on the first type of metal layer; and forming a second type of metal layer on the second plurality of nanostructured channel layers, wherein the self-assembled monolayer inhibits the formation of the second type of metal layer on the first type of metal layer.

2. The method according to claim 1, wherein, Forming the self-assembled monolayer comprises: depositing a solution containing a material of the self-assembled monolayer by spin coating; and performing a spin drying operation to cure the solution to form the self-assembled monolayer.

3. The method according to claim 1, further comprising: removing the self-assembled monolayer after forming the second type of metal layer.

4. The method according to claim 3, wherein, After removing the self-assembled monolayer, residues of the self-assembled monolayer remain on the first type of metal layer.

5. The method according to claim 3, wherein Removing the self-assembled monolayer comprises: performing a thermal decomposition operation on the self-assembled monolayer to decompose hydrocarbon chains of the self-assembled monolayer.

6. The method according to claim 5, wherein, Performing the thermal decomposition operation comprises: heating the self-assembled monolayer to a temperature included in a range of about 300 degrees Celsius to about 500 degrees Celsius.

7. The method according to claim 3, wherein Removing the self-assembled monolayer comprises: performing a plasma treatment operation on the self-assembled monolayer to remove the self-assembled monolayer.

8. The method according to claim 1, wherein, Forming the self-assembled monolayer comprises: forming the self-assembled monolayer as a discontinuous thin film.

9. A method, comprising: forming a first plurality of nanostructured channel layers arranged along a direction substantially perpendicular to a semiconductor substrate of a semiconductor device; forming a second plurality of nanostructured channel layers arranged along the direction substantially perpendicular to the semiconductor substrate; forming a gate dielectric layer surrounding the first plurality of nanostructured channel layers and surrounding the second plurality of nanostructured channel layers; forming a self-assembled monolayer on the gate dielectric layer surrounding the second plurality of nanostructured channel layers; forming a p-type metal layer of a first gate structure on the first plurality of nanostructured channel layers, wherein a material of the self-assembled monolayer inhibits the p-type metal layer from adsorbing on the gate dielectric layer surrounding the second plurality of nanostructured channel layers; and forming an n-type metal layer of a second gate structure on the second plurality of nanostructured channel layers after forming the p-type metal layer.

10. A semiconductor device, comprising: a first plurality of nanostructured channel layers arranged along a direction substantially perpendicular to a semiconductor substrate of the semiconductor device; a second plurality of nanostructured channel layers adjacent to the first plurality of nanostructured channel layers and arranged along the direction substantially perpendicular to the semiconductor substrate; a first gate structure surrounding the first plurality of nanostructured channel layers, the first gate structure comprising: a p-type metal layer; and residues on the p-type metal layer, the residues comprising ligands of at least one of the following: sulfur (S), silicon (Si), or phosphorus (P); and A second gate structure, surrounding each of the second plurality of nanostructure channel layers, the second gate structure including an n-type metal layer.

Images