Application of sensing, storage and calculation integrated image recognition phototransistor

Abstract

The invention discloses an image recognition phototransistor with sensing, storage and calculation integration. The phototransistor shows the performance advantage of integration of sensing, storage and calculation: the photoactivation ion layer (PbI2) initiates a controllable ion migration effect under illumination, WSe2 channel conductivity is dynamically modulated through the HfO2 dielectric layer, and optical signal sensing and nonvolatile conductivity state storage are synchronously realized; on the basis of the simulated conductance gradient regulated and controlled by the grid voltage, the convolution operation of a photo-generated signal can be directly completed on the device level, and the whole process integration of light input, conductance calculation and result output in a single device is realized. By utilizing the performance of integrating the array structure and the device sensing, storage and calculation, the data output after sharpening calculation of the 3 * 3 device array is used for learning and training, and the target identification accuracy rate of 99.3% can be realized in the efficient learning process only needing four training periods, which is obviously superior to that of a device which is not sharpened.

Description

Technical Field

[0001] This technology belongs to the field of new semiconductor devices and intelligent sensors, focusing on the intersection of optoelectronic devices and edge computing. Specifically, it involves innovative research on integrating optical sensing, non-volatile storage, and neural network computing into a single transistor architecture, aiming to achieve full-stack low-power image recognition of optical signal acquisition-storage-processing on terminal devices, and can be applied to fields such as artificial retinas, Internet of Things vision chips, and brain-inspired computing systems. Background Art

[0002] The mainstream architecture of current image recognition phototransistors is still based on the design mode of separating sensing, storage, and computing units. For example, traditional CMOS image sensors need to capture optical signals through a photodiode array, and after analog-to-digital conversion, transmit them to independent storage units such as DRAM and computing units such as CPU / GPU, resulting in frequent data migration between physically separated modules, causing power consumption as high as 10 mW / frame and delays of dozens of milliseconds 27. To alleviate such problems, in recent years, the technology of integrating sensing, storage, and computing has gradually developed, but its hardware implementation still faces multiple challenges:

[0003] 1. Insufficient device integration: Existing solutions mostly rely on the cooperation of multiple devices. For example, the ferroelectrically regulated p-n junction photodiode array developed by the Fudan University team can achieve optical signal detection and weight storage through ferroelectric domain polarization, but still requires an external gate voltage circuit to dynamically adjust the device responsivity, resulting in increased system complexity and power consumption; the optoelectronic memristor array proposed by Tsinghua University integrates 1024 1T-1OEM units into a silicon-based CMOS circuit, but relies on multi-layer oxide structures such as the TiOx / ZnO interface layer to enhance stability, with high process complexity.

[0004] 2. Limited dynamic adjustment ability: Traditional phototransistors rely on fixed doping, such as n / p-type semiconductors. Once manufactured, their optoelectronic response characteristics, such as sensitivity and response speed, are difficult to dynamically adjust. For example, the sensing, storage, and computing devices based on floating-gate transistors need to change the threshold voltage through charge injection, but there are long-term stability problems caused by charge leakage.

[0005] 3. Process compatibility and cost: Advanced sensing, storage, and computing devices, such as those based on ferroelectric materials or memristors, often require non-standard process steps, such as ferroelectric thin film deposition or oxide interface engineering, which have poor compatibility with mainstream CMOS production lines and drive up manufacturing costs. For example, the double-layer oxide optoelectronic memristor of the Fudan team needs to use a Pd / TiOx / ZnO / TiN heterostructure, with a complex preparation process and difficult yield control.

[0006] This technology addresses the above bottlenecks and proposes a fully integrated method of optical sensing-non-volatile storage-analog computing within a single transistor to solve the problems of insufficient energy efficiency and flexibility of existing architectures. Summary of the Invention

[0007] The present invention discloses an image recognition optoelectronic transistor with integrated sensing, storage, and computing. The optoelectronic transistor of the present invention exhibits the performance advantages of integrated sensing, storage, and computing: on the one hand, the photoactivated ion layer (PbI2) induces a controllable ion migration effect under light illumination, and dynamically modulates the WSe2 channel conductance through the HfO2 dielectric layer, synchronously realizing optical signal sensing and non-volatile conductance state storage; on the other hand, based on the analog conductance gradient regulated by the gate voltage, the convolution operation of the photo-generated signal can be directly completed at the device level, realizing the full-process integration of "optical input - conductance calculation - result output" within a single device. Utilizing the array structure and the performance of the device with integrated sensing, storage, and computing, the data output after sharpening calculation by a 3×3 device array is used for learning and training, and a target recognition accuracy rate of up to 99.3% can be achieved in an efficient learning process that only requires 4 training cycles, which is significantly better than that without sharpening processing. The present invention effectively avoids the data transfer bottleneck between the sensing, storage, and computing modules in the von Neumann architecture through the cooperative mechanism of the multi-physical fields of light - electricity - ions, providing a new idea for high-energy-efficiency neuromorphic image recognition.

[0008] In order to solve the technical problems of the present invention, the technical solution proposed is: an application of an image recognition optoelectronic transistor with integrated sensing, storage, and computing, and the device structure of the optoelectronic transistor is, from bottom to top in sequence, a gate electrode Si, a dielectric layer HfO2, a photoactivated ion layer PbI2, a channel WSe2, and source-drain electrodes Au;

[0009] The optoelectronic transistor has the functional characteristic of storage, which is reflected in that the photoactivated ion layer PbI2 induces a controllable ion migration effect under light illumination, and dynamically modulates the WSe2 channel conductance through the HfO2 dielectric layer, synchronously realizing optical signal sensing and non-volatile conductance state storage;

[0010] The optoelectronic transistor has the functional characteristic of computing, which is to simulate "1" and "0" of a traditional transistor based on the positive and negative optoelectronic response functional characteristics of the optoelectronic transistor for calculation; using the device array to perform sharpening processing on pictures, and using the data after sharpening processing for learning and training can improve the target recognition accuracy rate, which is better than that without sharpening processing. Using the optoelectronic transistor array with integrated sensing, storage, and computing to recognize the target in an image can effectively reduce the training cycle and improve the accuracy rate of image recognition;

[0011] The application of the optoelectronic transistor in image recognition is to utilize the computing function of the transistor and use the convolutional neural network CNN for simulation calculation to realize the functions of image processing and recognition.

[0012] Preferably, a 3×3 device array is used to sharpen the picture, and the sharpened data is used for learning and training. A target recognition accuracy of up to 99.3% can be achieved in an efficient learning process that only requires 4 training cycles, which is significantly better than those without sharpening.

[0013] Preferably, the phototransistor has photosensitive functional characteristics, which are reflected in that the PbI2 material is used as the photoactivated ion layer, enhancing the separation efficiency of photo-generated electron-hole pairs; while the WSe2 material is used as the photoactivated layer, with its excellent carrier mobility and high light absorption coefficient, further amplifying the photoelectric signal, enabling the entire device to maintain stable photoelectric conversion performance.

[0014] Preferably, the sharpening process is to perform convolution calculation through the device to highlight the features of the target in a photo at a specific wavelength, enhance the edge of the target in the picture, and implement the sharpening calculation of the picture in the device through a 3×3 device array. Then, the data after sharpening is used for training to achieve a higher-precision target recognition function and reduce the training cycle.

[0015] Preferably, the phototransistor can perform convolutional neural network (CNN) simulation calculations. By applying a specific voltage pulse sequence to the memristor units in the array through the source meter 2612B, precise regulation of the conductance value can be achieved. By continuously applying voltage pulses, a series of continuously changing conductance states can be obtained, which are used to map the weight values of the neural network. The specific operation is as follows: Apply 30 positive pulses of 0.3V for 50ms to enhance the conductance value, and apply 50 negative pulses of -0.3V for 50ms to reduce the conductance value; after modulation, normalize the conductance value and map it to the weight value in the range of 0-1.

[0016] The long-term change trend of the conductance G with the increase in the number of pulses under the stimulation of light with different wavelengths by the phototransistor reflects the characteristics of the conversion between short-term memory (STM) and long-term memory (LTM) similar to biological synapses.

[0017] Preferably, the phototransistor has the characteristics of positive and negative photoelectric responses. After inserting the photoactivated ion layer PbI2, its photoactivated characteristics form a heterojunction structure with the channel layer WSe2. Under photoelectric action, due to ion doping, PbI2 generates photo-generated carriers and electron-hole pairs, and the electrons will transition to the defect energy level of I - , and the excess holes will be doped into WSe2 from the heterojunction interface, thus generating a positive photoelectric response; in the saturation region, due to ion trapping, the majority carriers of holes are trapped by ions, resulting in a decrease in the components participating in conduction and a decrease in current, generating a negative photoelectric response.

[0018] Preferably, the preparation steps of the phototransistor are as follows:

[0019] Step 1: Clean the substrate: Ultrasonically clean the HfO2 / Si substrate in acetone, isopropyl alcohol, and anhydrous ethanol successively in an ultrasonic machine, and then dry it with high-purity nitrogen for standby;

[0020] Step 2: Prepare the photoactivated ion layer by thermal evaporation: Place the PbI2 powder in a clean source boat and prepare PbI2 by thermal evaporation;

[0021] Step 3: Prepare the heterojunction: Under a nitrogen atmosphere, transfer the two-dimensional WSe2 nanosheet onto the surface of the two-dimensional PbI2 nanosheet through the van der Waals integration process to ensure that the interfaces of the two layers of materials are clean and in close contact;

[0022] Step 4: Prepare the source and drain electrodes: On the surface of the WSe2 material, prepare the metal electrode Au through the EBL method and the thermal evaporation coating process.

[0023] Preferably, for the image recognition phototransistor with integrated sensing, storage, and computing, the thicknesses of the dielectric layer HfO2, the photoactivated ion layer PbI2, the channel WSe2, and the source and drain electrodes Au are 8 - 10 nm, 1 - 5 nm, 0.7 - 3.5 nm, and 60 - 80 nm, respectively.

[0024] Preferably, the steps for cleaning the substrate are as follows:

[0025] Ultrasonically clean the HfO2 / Si substrate in acetone, isopropyl alcohol, and anhydrous ethanol successively in an ultrasonic machine for 10 minutes each, and then dry it with high-purity nitrogen for standby.

[0026] Preferably, the steps for preparing the photoactivated ion layer by thermal evaporation are as follows:

[0027] Place the PbI2 powder in a clean source boat, control the pressure in the boat to be 10 -5 -10 -6 Pa, and prepare PbI2 by thermal evaporation in an environment with a temperature of 150 °C.

[0028] Preferably, the steps for preparing the heterojunction are as follows:

[0029] Step 1: Prepare the WSe2 nanosheet: Directly exfoliate the mechanically exfoliated WSe2 onto the PDMS to obtain WSe2 / PDMS;

[0030] Step 2: Transfer WSe2: Under the microscope field of view, align the target WSe2 with the target PbI2 and keep them in contact at 90 °C for 2 - 3 minutes;

[0031] Step 3: Obtain the WSe2 / PbI2 heterojunction: Lift the thermal release tape to make the WSe2 fall on the PbI2 film to complete the preparation of the heterojunction.

[0032] Preferably, the steps of preparing the source and drain electrodes are as follows:

[0033] Step 1: Spin-coat photoresists PMMA-A4 and PMMA-A5 on the surface of the substrate with the WSe2 / PbI2 heterojunction in sequence, and bake them on a hot plate at 180 °C for 100 s respectively;

[0034] Step 2: Find the area around the sample in the scanning electron microscope and engrave alignment marks, develop the exposed alignment marks, take pictures with a microscope and record them to locate the sample and the engraved pattern;

[0035] Step 3: Align the marks and expose the sample;

[0036] Step 4: After development, dry it with a nitrogen gun and deposit the Au electrode by thermal evaporation.

[0037] Beneficial effects

[0038] The present invention proposes an image recognition transistor with integrated sensing, storage and computing functions, which is simple to prepare and low in cost. The PbI2 / WSe2 heterojunction can be prepared only by simple methods such as mechanical exfoliation and chemical synthesis.

[0039] Based on the functional characteristics of its integrated sensing, storage and computing architecture, convolutional neuromorphic-based image recognition can be realized.

[0040] The phototransistor described in the present invention exhibits the performance advantages of integrated sensing, storage and computing: on the one hand, the photoactivated ion layer (PbI2) triggers a controllable ion migration effect under light illumination, and dynamically modulates the WSe2 channel conductance through the HfO2 dielectric layer to synchronously realize optical signal sensing and non-volatile conductance state storage; on the other hand, based on the simulated conductance gradient regulated by the gate voltage, the convolution operation of the photo-generated signal can be directly completed at the device level to realize the full-process integration of "optical input-conductance calculation-result output" within a single device. Utilizing the array structure and the performance of the device's integrated sensing, storage and computing, the data output after sharpening calculation by a 3×3 device array is used for learning and training, and a target recognition accuracy of up to 99.3% can be achieved in an efficient learning process that only requires 4 training cycles, which is significantly better than that without sharpening. Through the synergistic mechanism of the multi-physical fields of light-electricity-ions, the present invention effectively avoids the data transfer bottleneck between the sensing, storage and computing modules in the von Neumann architecture, providing a new idea for high-energy-efficiency neuromorphic image recognition.

[0041] 1. Having positive and negative photoelectric responses

[0042] As attached Figure 2As shown, the phototransistor has operational functional characteristics. Based on the positive and negative photoelectric response functional characteristics of the phototransistor, it simulates "1" and "0" of a traditional transistor for calculation. Moreover, for lights of different wavelengths, the present invention has different positive and negative photoelectric responses. Therefore, when processing an image dataset, the calculation characteristics of the device itself are used to sharpen the picture dataset, and the processed data is then used for training. For example, Figure 7 As shown, a target recognition accuracy of up to 99.3% can be achieved in an efficient learning process that only requires 4 training cycles, which is significantly better than those without sharpening processing.

[0043] 2. Having the functional characteristics of simulating a synapse

[0044] By applying a specific voltage pulse sequence to the transistor units in the array through a source meter (2612B), precise regulation of the conductance value is achieved. For example, Figure 3 As shown, by continuously applying voltage pulses, a series of continuously changing conductance states can be obtained, which are used to map the weight values of a neural network. The specific operation is as follows: Apply 30 positive pulses (0.3V, 50ms) to increase the conductance value, and apply 50 negative pulses (-0.3V, 50ms) to decrease the conductance value; after modulation, normalize the conductance value and map it to a weight value in the range of 0-1.

[0045] For example, Figure 3 As shown, under the stimulation of lights of different wavelengths, the long-term change trend of the conductance (G) of the phototransistor with the increase in the number of pulses reflects the characteristics of the conversion between short-term memory (STM) and long-term memory (LTM) similar to biological synapses.

[0046] 3. Simple and low-cost process manufacturing

[0047] In the present invention, PbI2 nanosheets are prepared by thermal evaporation deposition method. The formed nanosheets have regular shapes, high yields, and low costs. Two-dimensional WSe2 nanosheets are prepared by mechanical exfoliation method, and the method is simple and easy to implement. The dry transfer precisely constructs a heterojunction, ensuring the repeatability of device preparation and the possibility of mass production. Compared with the phototransistors prepared by relying on complex processes in the prior art, the process of the present invention is simpler and cheaper, and has high practicability and popularization value.

[0048] 4. The mechanism of positive and negative photoelectric responses

[0049] As shown in the appendix Figure 4 As shown, the functional characteristics of the positive and negative photoelectric responses of the present invention mainly come from the formation of a heterojunction structure between the photoactivation characteristics and the channel layer (WSe2) after inserting a photoactivated ion layer (PbI2). Under photoelectric action, due to ion doping, PbI2 generates photoinduced carriers and electron-hole pairs, and electrons will transition to I -At the defect energy level, the excess holes will be doped from the heterojunction interface into WSe2, resulting in a positive optoelectronic response; in the saturation region, due to ion trapping, the majority carriers of holes are trapped by ions, leading to a decrease in the components participating in conduction and a decrease in current, resulting in a negative optoelectronic response. Brief Description of the Drawings

[0050] Figure 1 : Device structure diagram of a two-dimensional PbI2 / WSe2 heterojunction optoelectronic transistor

[0051] Figure 2 : Bar graph of the optoelectronic response intensities of PbI2 / WSe2 heterojunction and pure WSe2 at each wavelength band

[0052] Figure 3 : Graph showing the change trend of conductance (G) with the increase in the number of pulses

[0053] Figure 4 : Mechanism diagram of the optoelectronic transistor generating positive and negative optoelectronic responses

[0054] Figure 5 : Schematic diagram of a convolutional neural network (CNN)

[0055] Figure 6 : Processing and recognition of images using a convolutional neural network (CNN)

[0056] Figure 7 : Comparison graph of accuracy and training cycles with and without sharpening processing on the image dataset Detailed Implementation Manner

[0057] Next, the technical solutions in the embodiments of the present invention will be clearly and completely

[0058] described in conjunction with the embodiments of the invention. Among them, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments

[0059] Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts

[0060] fall within the scope of protection of the present invention.

[0061] Embodiment 1

[0062] As Figure 1 shown, the hardware implementation process of the convolutional neural network of the present invention includes setting the working state of the transistor array unit as the weights of the convolutional neural network, obtaining an image from the processed image and inputting the pixel features of the image in the form of voltage, and obtaining the output current after the array transmission operation as the result of the convolutional operation. In Figure 5The basic working principle of the transistor array is shown. Each square in the matrix represents a transistor working unit, and its conductance value corresponds to the weight of the neural network. The input voltage is applied through the row lines, and the output current is read through the column lines, which conforms to the formula I = ∑G ij V j , realizing matrix multiplication operation.

[0063] Step 1: This embodiment proposes an image recognition transistor with integrated sensing and computing and its preparation method, which can process and recognize images based on a convolutional neural network (CNN). The specific preparation steps are as follows:

[0064] (1): Clean the HfO2 / Si substrate (Suzhou Jingxi Electronics Technology): Ultrasonically clean the HfO2 / Si substrate with acetone, isopropyl alcohol, and absolute ethanol in an ultrasonic machine for 10 minutes each in turn, and then dry it with high-purity nitrogen for standby.

[0065] (2): Prepare the photoactivated ion layer by thermal evaporation: Place the PbI2 powder in a clean source boat, control the temperature in the boat to be 150 °C, and the pressure to be 10 -5 -10 -6 Pa in a low-pressure environment, and prepare PbI2 by thermal evaporation.

[0066] (3): Prepare the heterojunction:

[0067] Prepare WSe2 nanosheets in a nitrogen environment: Directly peel the mechanically exfoliated WSe2 onto PDMS (the WSe2 crystal is provided by Shanghai Angwei Technology) to obtain WSe2 / PDMS.

[0068] Then transfer WSe2. Under the microscope field of view, align the target WSe2 with the target PbI2 and keep it in contact at 90 °C for 2 - 3 minutes. Finally, lift the thermal release tape so that WSe2 falls on the PbI2 film to complete the preparation of the heterojunction.

[0069] (4): Spin-coat photoresists PMMA - A4 and PMMA - A5 on the surface of the substrate with the heterojunction in sequence, and bake them on a hot plate at 180 °C for 90 s respectively; find the surrounding area of the sample in the scanning electron microscope and engrave alignment marks. Develop the exposed alignment marks, take pictures with a microscope for recording, position the sample and engrave the pattern; perform the alignment of the marks and the exposure of the sample; after development, dry it with a nitrogen gun. Through the EBL method, combined with the Auto CVD software, design electrode patterns with reasonable structures and sizes on the surface of the WSe2 / PbI2 heterojunction, and deposit metal electrodes (Au) on the surface of the heterojunction through the thermal evaporation coating process; and control the thickness of the Au electrodes to be 60 - 80 nm.

[0070] The device structure of the heterojunction phototransistor prepared through the above experimental steps is a three-terminal transistor. As Figure 1 shown, from bottom to top, they are the gate electrode (Si), the dielectric layer (HfO2) with a thickness of 8 - 10 nm, the photo-activated ion layer (PbI2) with a thickness of 1 - 5 nm, the channel (WSe2) with a thickness of 0.7 - 3.5 nm, and the source-drain electrode (Au) with a thickness of 60 - 80 nm.

[0071] The phototransistor has photosensitive functional characteristics, which are reflected in that the PbI2 material as the photo-activated ion layer enhances the separation efficiency of photo-generated electron-hole pairs; while the WSe2 material as the photo-activated layer further amplifies the photoelectric signal with its excellent carrier mobility and high light absorption coefficient, enabling the entire device to maintain stable photoelectric conversion performance.

[0072] The phototransistor has storage functional characteristics, which are reflected in that the photo-activated ion layer PbI2 triggers a controllable ion migration effect under light illumination, dynamically modulating the WSe2 channel conductance through the HfO2 dielectric layer, and synchronously realizing optical signal sensing and non-volatile conductance state storage;

[0073] As shown in the appendix Figure 2 shown, the phototransistor has computing functional characteristics, which are based on the positive and negative photoelectric response functional characteristics of the phototransistor to simulate "1" and "0" of traditional transistors for calculation. And for lights of different wavelengths, the present invention has different positive and negative photoelectric responses. Therefore, when processing an image data set, the calculation characteristics of the device itself are used to sharpen the picture data set, and the processed data is then used for training. As Figure 7 shown, a target recognition accuracy of up to 99.3% can be achieved in an efficient learning process with only 4 training cycles, which is significantly better than that without sharpening processing. The application of the phototransistor to image recognition is based on the computing function of the transistor, and the convolutional neural network CNN is used for simulation calculation to realize the functions of image processing and recognition.

[0074] Step 2: Transistor conductance state regulation. A specific voltage pulse sequence is applied to the transistor units in the array through a source meter (2612B) to achieve precise regulation of the conductance value. As Figure 3 shown, by continuously applying voltage pulses, a series of continuously changing conductance states can be obtained for mapping the weight values of the neural network. The specific operation is as follows: 30 positive pulses (0.3V, 50ms) are applied to enhance the conductance value, and 50 negative pulses (-0.3V, 50ms) are applied to reduce the conductance value; after modulation, the conductance value is normalized and mapped to the weight value in the range of 0 - 1.

[0075] As Figure 3As shown, the conductance (G) of the phototransistor under different wavelength light stimuli shows a long-term change trend with the increase in the number of pulses, which reflects the characteristics of the conversion between short-term memory (STM) and long-term memory (LTM) similar to biological synapses.

[0076] As shown in the appendix Figure 4 The functional characteristics of the positive and negative photoelectric responses of the present invention mainly come from the formation of a heterojunction structure between the photoactivation characteristics of the inserted photoactivated ion layer (PbI2) and the channel layer (WSe2). Under the action of light and electricity, due to ion doping, PbI2 generates photoexcited carriers and electron-hole pairs. Electrons will transition to the defect energy level of I - and the excess holes will be doped into WSe2 from the heterojunction interface, thus generating a positive photoelectric response; in the saturation region, due to ion trapping, the majority carriers of holes are trapped by ions, resulting in a decrease in the components participating in conduction and a decrease in current, generating a negative photoelectric response.

[0077] Step 3: Convolutional neural network design and mapping. As Figure 5 shown, in this embodiment, a convolutional neural network structure for pedestrian recognition is designed, including a 3×3 input layer (corresponding to a pedestrian image of H×W pixels), 32 hidden convolutional layers, and output nodes. The weights of the convolutional kernels are directly mapped to the conductance values of the transistor array, and the data output of matrix multiplication and addition operations is realized through Kirchhoff's law and Ohm's law.

[0078] Step 4: Training process. As Figure 6 Convert the pedestrian image into a 3×3 pixel matrix, input it into the row lines of the array through a voltage signal (adjust the magnitude and polarity of the device gate voltage according to the magnitude and polarity of the input optical signal); measure the output current of the column lines, compare it with the target value to calculate the error; calculate the weight gradient through the backpropagation algorithm; apply corresponding voltage pulses to adjust the transistor conductance value according to the direction and magnitude of the gradient; repeat the above training process until the recognition accuracy reaches the preset requirement or the accuracy improvement is less than the preset threshold (0.2%) for three consecutive cycles.

[0079] Step 5: Training effect evaluation. As Figure 6 shown, the outline of the pedestrian can be clearly seen in the image output after the device array, realizing the accurate recognition of the target in the image.

[0080] Comparative Example 1

[0081] The preparation process of the comparative device used in this comparative example is the same as that of Example 1, and the only difference is that: when preparing the comparative device, it is not necessary to thermally evaporate PbI2, and only WSe2 needs to be transferred to the HfO2 / Si substrate.

[0082] As Figure 2As shown in the figure, the optoelectronic responses of two devices were tested for performance. It was found that the pure WSe2 transistor only had a positive optoelectronic response, while the PbI2 / WSe2 heterojunction had high positive and negative optoelectronic responses at different wavelengths. Therefore, the pure WSe2 transistor cannot perform data operations within the device, so the pure WSe2 transistor cannot perform sharpening processing on the image dataset.

[0083] Comparative Example 2

[0084] In this comparative example, no comparative device was used. Instead, the differences in the number of training cycles caused by learning and training using the data output from the device array and directly learning and training on the original dataset were compared.

[0085] As Figure 5 shown, when the built convolutional neural network model was used to process the image dataset as Figure 5 shown, the data after sharpening processing by the 3×3 device array was used for learning and training, and then compared with directly using the image dataset for learning and training. The results were as Figure 7 shown. The image dataset with sharpening processing could reach an accuracy of 99.3% when the training cycle was 4; while the image dataset without sharpening processing could only reach a similar accuracy when the training cycle was 11.

[0086] It can be seen from this that the optoelectronic transistor described in the present invention helps to shorten the training cycle and provides a new improvement idea for neuromorphic image recognition.

Claims

1. Application of an image recognition optoelectronic transistor with integrated sensing and computing, characterized in that: The device structure of the described phototransistor is, from bottom to top, a gate electrode Si, a dielectric layer HfO2, a photo-activated ion layer PbI2, a channel WSe2, and source-drain electrodes Au; The described phototransistor has a storage functional characteristic, which is reflected in that the photo-activated ion layer PbI2 triggers a controllable ion migration effect under light illumination, dynamically modulates the WSe2 channel conductance through the HfO2 dielectric layer, and synchronously realizes optical signal sensing and non-volatile conductance state storage; The described phototransistor has an arithmetic functional characteristic. Based on the positive and negative photoresponse functional characteristics of the phototransistor, it simulates "1" and "0" of a traditional transistor for calculation; using a device array to perform sharpening processing on a picture and using the sharpened data for learning and training can improve the target recognition accuracy rate, which is better than that without sharpening processing. Using a phototransistor array with integrated sensing and computing to recognize targets in an image can effectively reduce the training cycle and improve the accuracy rate of image recognition; The application of the described phototransistor in image recognition is based on the arithmetic function of the transistor, and uses a convolutional neural network CNN simulation calculation to realize the functions of image processing and recognition.

2. The application of the image recognition photoelectric transistor with integrated sensing and computing according to claim 1, characterized in that: Using a 3×3 device array to perform sharpening processing on a picture and using the sharpened data for learning and training, a target recognition accuracy rate of up to 99.3% can be achieved in an efficient learning process that only requires 4 training cycles, which is significantly better than that without sharpening processing.

3. The application of the image recognition photoelectric transistor with integrated sensing and computing according to claim 1, characterized in that: The described phototransistor has a photosensitive functional characteristic, which is reflected in that the PbI2 material, as a photo-activated ion layer, enhances the separation efficiency of photo-generated electron-hole pairs; while the WSe2 material, as a photo-activated layer, with its excellent carrier mobility and high light absorption coefficient, further amplifies the optical signal, enabling the entire device to maintain stable photoelectric conversion performance.

4. The application of the image recognition optoelectronic transistor with integrated sensing and computing according to claim 1, characterized in that: The described sharpening processing is to highlight the features of the target in a photo at a specific wavelength through convolution calculation by the device, enhance the edge of the target in the picture, realize the sharpening calculation of the picture in the device through a 3×3 device array, and then perform training with the sharpened data to achieve a higher-precision target recognition function and reduce the training cycle.

5. The application of the image recognition optoelectronic transistor with integrated sensing and computing according to claim 1, characterized in that: The described phototransistor can perform convolutional neural network CNN simulation calculation. By applying a specific voltage pulse sequence to the memristor units in the array through a source meter 2612B, precise regulation of the conductance value can be achieved. By continuously applying voltage pulses, a series of continuously changing conductance states can be obtained, which are used to map the weight values of the neural network. The specific operation is as follows: apply 30 positive pulses of 0.3V for 50ms to enhance the conductance value, and apply 50 negative pulses of -0.3V for 50ms to reduce the conductance value; After modulation, the conductance value is normalized and mapped to a weight value in the range of 0-1; Under the stimulation of light with different wavelengths, the long-term change trend of the conductance G with the increase in the number of pulses of the described phototransistor reflects the characteristics of the conversion between short-term memory STM and long-term memory LTM similar to that of biological synapses.

6. The application of the image recognition optoelectronic transistor with integrated sensing and computing according to claim 1, characterized in that: The described phototransistor has the characteristics of positive and negative photoelectric responses. After inserting the photoactive ion layer PbI2, its photoactive characteristics form a heterojunction structure with the channel layer WSe2. Under the action of light, due to ion doping, PbI2 generates photo-generated carriers and electron-hole pairs, and electrons will transition to the defect energy level of I - and the excess holes will be doped into WSe2 from the heterojunction interface, thus generating a positive photoelectric response; In the saturation region, holes, which are the majority carriers, are trapped by ions due to ion trapping, resulting in a decrease in the components participating in conduction and a subsequent decrease in current, thereby generating a negative optoelectronic response.

7. The application of the image recognition optoelectronic transistor with integrated sensing and computing according to claim 1, wherein: The preparation steps of the phototransistor are as follows: Step 1: Clean the substrate: Ultrasonically clean the HfO2 / Si substrate in acetone, isopropyl alcohol, and absolute ethanol successively in an ultrasonic cleaner, and then dry it with high-purity nitrogen for standby; Step 2: Prepare the photoactive ion layer by thermal evaporation: Place the PbI2 powder in a clean source boat and prepare PbI2 by thermal evaporation; Step 3: Prepare the heterojunction: Under a nitrogen atmosphere, transfer the two-dimensional WSe2 nanosheet to the surface of the two-dimensional PbI2 nanosheet through the van der Waals integration process to ensure that the interfaces of the two layers of materials are clean and in close contact; Step 4: Prepare the source and drain electrodes: By the EBL method, prepare the metal electrode Au on the surface of the WSe2 material through the thermal evaporation coating process.

8. The application of the image recognition optoelectronic transistor with integrated sensing and computing according to claim 1, characterized in that: For the image recognition phototransistor with integrated sensing and computing, the thicknesses of the dielectric layer HfO2, the photoactive ion layer PbI2, the channel WSe2, and the source and drain electrodes Au are 8 - 10 nm, 1 - 5 nm, 0.7 - 3.5 nm, and 60 - 80 nm respectively.

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