Image sensor

Abstract

An image sensor includes a semiconductor substrate, a color filter group, a microlens layer at least partially covering the color filter group, and an uppermost planarization layer. The semiconductor substrate includes a first surface, a second surface opposite the first surface, and a pixel array region including a center pixel region and an edge pixel region at least partially surrounding the center pixel region in a plan view. The color filter group includes a plurality of color filters including a center color filter on the center pixel region and an edge color filter on the edge pixel region. The microlens layer includes a lens planarization layer in contact with the color filter group and a microlens on the lens planarization layer. The uppermost planarization layer includes an upper recessed portion and a recessed center point in the center pixel region and the edge pixel region.

Description

Technical Field

[0001] The present disclosure generally relates to an image sensor and a method of manufacturing the same, and more particularly, to a complementary metal oxide semiconductor (CMOS) image sensor and a method of manufacturing the CMOS image sensor. Background Art

[0002] An image sensor may refer to a semiconductor device configurable to convert an optical image into an electrical signal. With the recent development of the computer and communication industries, there may be an increasing demand for high-performance image sensors in various applications such as, but not limited to, digital cameras, video cameras, personal communication systems, gaming consoles, security cameras, miniature cameras for medical applications, robots, and the like. Image sensors may be classified into two types, for example, a charge-coupled device (CCD) type and a complementary metal oxide semiconductor (CMOS) type. A CMOS-type image sensor may be referred to as a CIS. A CIS device may include a plurality of pixels arranged two-dimensionally. Each pixel may include a photodiode (PD) configurable to convert incident light into an electrical signal. The pixels may be defined by deep isolation patterns provided therebetween. A plurality of devices in each pixel may be separated from each other by device isolation patterns. Summary of the Invention

[0003] One or more example embodiments of the present disclosure provide an image sensor configured to minimize signal differences between pixels sharing a color filter and a method of manufacturing the same.

[0004] In addition, one or more example embodiments of the present disclosure provide a high-sensitivity image sensor having improved light reflection efficiency and a method of manufacturing the same.

[0005] In addition, one or more example embodiments of the present disclosure provide an image sensor that can be easily integrated and a method of manufacturing the same.

[0006] According to one aspect of the present disclosure, an image sensor includes a semiconductor substrate, a color filter group, a microlens layer at least partially covering the color filter group, and a top planarization layer in contact with the top surface of the microlens layer. The semiconductor substrate includes a first surface, a second surface opposite the first surface, and a pixel array region. The pixel array region includes a central pixel region and an edge pixel region at least partially surrounding the central pixel region in a plan view. The color filter group includes a plurality of color filters, the plurality of color filters including a central color filter on the central pixel region and an edge color filter on the edge pixel region. The microlens layer includes a lens planarization layer in contact with the color filter group and microlenses on the lens planarization layer. The top planarization layer includes an upper recessed portion and a recess center point in each of the central pixel region and the edge pixel region. The upper recessed portion is recessed toward the semiconductor substrate. The recess center point is defined at the lowermost portion of the upper recessed portion. In the central pixel region, a center point of the exposed flat top surface of the lens planarization layer at least partially vertically overlaps with the recess center point. In the edge pixel region, the center point of the flat top surface lies on a vertical line different from the recess center point.

[0007] According to one aspect of the present disclosure, an image sensor includes a semiconductor substrate, a color filter group, a microlens layer at least partially covering the color filter group, and a top planarization layer on the microlens layer. The semiconductor substrate includes a first surface, a second surface opposite the first surface, and a pixel array region. The pixel array region includes a central pixel region and an edge pixel region at least partially surrounding the central pixel region in a plan view. The color filter group includes a plurality of color filters, the plurality of color filters including a central color filter on the central pixel region and an edge color filter on the edge pixel region. The microlens layer includes a lens planarization layer in contact with the color filter group and microlenses on the lens planarization layer. The top planarization layer includes an upper recessed portion and a recess center point in each of the central pixel region and the edge pixel region. The upper recessed portion is recessed toward the semiconductor substrate. The recess center point is defined at the lowermost portion of the upper recessed portion. The microlens includes a lens center point defined at the uppermost portion of the microlens. A first vertical distance from the first surface to the recess center point is less than a second vertical distance from the first surface to the lens center point.

[0008] According to one aspect of the present disclosure, an image sensor includes a semiconductor substrate, deep device isolation patterns, a photoelectric conversion region, a color filter group on a second surface, a transfer gate on a first surface, a microlens layer at least partially covering at least one of the color filter group, and a top planarization layer on the microlens layer. The semiconductor substrate includes a light receiving region, a light blocking region, and a pad region, and has a first surface and a second surface opposite to the first surface. The deep device isolation patterns are disposed in the semiconductor substrate and configured to define pixel regions in the light receiving region and the light blocking region. The photoelectric conversion region is disposed in the light receiving region and the light blocking region of the semiconductor substrate. The light receiving region includes a central pixel region and an edge pixel region at least partially surrounding the central pixel region in a plan view. The microlens layer includes a lens planarization layer in contact with the color filter group and microlenses on the lens planarization layer. The top planarization layer includes an upper recessed portion and a recess center point. The upper recessed portion is recessed toward the semiconductor substrate. The recess center point is defined at the lowermost portion of the upper recessed portion. The microlens includes a lens center point at the uppermost portion of the microlens. A first vertical distance from the first surface to the recess center point is less than a second vertical distance from the first surface to the lens center point.

[0009] Additional aspects may be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the presented embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The above and other aspects, features, and advantages of certain embodiments of the present disclosure will become more apparent from the following description taken in conjunction with the drawings, in which:

[0011] Figure 1 is a block diagram schematically showing an image sensor according to an embodiment;

[0012] Figure 2 is a circuit diagram showing an active pixel sensor array of an image sensor according to an embodiment;

[0013] Figure 3A is a plan view showing an image sensor according to an embodiment;

[0014] Figure 3B is showing according to an embodiment Figure 3A an enlarged plan view of a light receiving region;

[0015] Figure 4 is according to an embodiment along Figure 3B a cross-sectional view taken along line A-A';

[0016] Figure 5 is according to an embodiment along Figure 3B a cross-sectional view taken along line B-B';

[0017] Figure 6 is a cross-sectional view taken along line A-A' according to an embodiment; Figure 3B of;

[0018] Figure 7 is a cross-sectional view taken along line B-B' according to an embodiment; Figure 3B of;

[0019] Figure 8 is a cross-sectional view taken along line A-A' according to an embodiment; Figure 3B of;

[0020] Figure 9 is a cross-sectional view taken along line B-B' according to an embodiment; Figure 3B of;

[0021] Figure 10A and Figure 11A is a cross-sectional view corresponding to a cross-section taken along line A-A' according to an embodiment to show a method of manufacturing an image sensor; Figure 3B of;

[0022] Figure 10B and Figure 11B is a cross-sectional view corresponding to a cross-section taken along line B-B' according to an embodiment to show a method of manufacturing an image sensor; Figure 3B of;

[0023] Figure 12A 、 Figure 13A 、 Figure 14A and Figure 15A is a cross-sectional view corresponding to a cross-section taken along line A-A' according to an embodiment to show a method of manufacturing an image sensor; Figure 3B of;

[0024] Figure 12B 、 Figure 13B 、 Figure 14B and Figure 15B is a cross-sectional view corresponding to a cross-section taken along line B-B' according to an embodiment to show a method of manufacturing an image sensor; Figure 3B of;

[0025] Figure 16 is a cross-sectional view taken along line A-A' according to an embodiment; Figure 3B of;

[0026] Figure 17 is a cross-sectional view taken along line B-B' according to an embodiment; Figure 3B of;

[0027] Figure 18 is a cross-sectional view taken along line A-A' according to an embodiment; and Figure 3B of;

[0028] Figure 19 is a cross-sectional view taken along line B-B' according to an embodiment. Figure 3B Specific Embodiments

[0029] The following description with reference to the drawings is provided to assist in a comprehensive understanding of embodiments of the present disclosure defined by the claims and their equivalents. Various specific details are included to assist in the understanding, but these details are considered to be merely exemplary. Thus, those of ordinary skill in the art will recognize that various changes and modifications can be made to the embodiments described herein without departing from the scope and spirit of the present disclosure. In addition, descriptions of well-known functions and configurations are omitted for clarity and conciseness.

[0030] Regarding the description of the drawings, like reference numerals may be used to refer to like or related elements. It will be understood that a singular form of a noun corresponding to an item may include one or more things unless the relevant context clearly indicates otherwise. As used herein, each of the phrases such as "A or B", "at least one of A and B", "at least one of A or B", "A, B, or C", "at least one of A, B, and C", and "at least one of A, B, or C" may include any possible combination of the items listed together in the respective one of the phrases. As used herein, terms such as "first" and "second" or "1st" and "2nd" may be used simply to distinguish a corresponding component from another component and do not otherwise limit the component (e.g., in terms of importance or order). It will be understood that if an element (e.g., a first element) is referred to as "coupled to", "coupled with", "connected to", or "connected with" another element (e.g., a second element), with or without the terms "operatively" or "communicatively", it means that the element can be directly (e.g., wired), wirelessly, or via a third element coupled to the other element.

[0031] It will be understood that when an element or layer is referred to as "on", "above", "over", "under", "beneath", "below", "connected to", or "coupled to" another element or layer, it can be directly on, directly above, directly over, directly under, directly beneath, directly below, directly connected to, or directly coupled to the other element or layer, or there can be intervening elements or layers. In contrast, when an element is referred to as "directly on", "directly above", "directly over", "directly under", "directly beneath", "directly below", "directly connected to", or "directly coupled to" another element or layer, there are no intervening elements or layers.

[0032] The terms "upper", "intermediate", "lower", etc. may be replaced with terms such as "first", "second", "third" for describing the relative positions of elements. The terms "first", "second", "third" can be used to describe various elements, but the elements are not limited by the terms, and a "first element" can be referred to as a "second element". Optionally or additionally, the terms "first", "second", "third", etc. can be used to distinguish components from each other and do not limit the present disclosure. For example, the terms "first", "second", "third", etc. may not necessarily involve any form of order or numerical meaning.

[0033] As used herein, when an element or layer is referred to as "covering", "overlapping" or "surrounding" another element or layer, the element or layer can cover at least a portion of the other element or layer, where the portion can include a small portion of the other element or can include the entirety of the other element. Similarly, when an element or layer is referred to as "penetrating" another element or layer, the element or layer can penetrate at least a portion of the other element or layer, where the portion can include a small portion of the other element or can include the entire dimension (e.g., length, width, depth) of the other element.

[0034] References to "one embodiment", "an embodiment", "an example embodiment", or similar language throughout this disclosure may indicate that a particular feature, structure, or characteristic described in connection with the indicated embodiment is included in at least one embodiment of the present technical solution. Thus, the phrases "in one embodiment", "in an embodiment", "in an example embodiment", and similar language throughout this disclosure may, but do not necessarily, all refer to the same embodiment. The embodiments described herein are example embodiments, and thus, this disclosure is not limited thereto and may be implemented in various other forms.

[0035] As used herein, each of the terms "Al2O3", "HfO", "PTEOS", "SiN", "SiO", "SiO2", "SiON", etc. may refer to a material made of the elements included in each term and is not a chemical formula representing a stoichiometric relationship.

[0036] Hereinafter, various embodiments of the present disclosure will be described with reference to the accompanying drawings.

[0037] Figure 1 is a block diagram schematically showing an image sensor according to an embodiment.

[0038] Referring to Figure 1 , the image sensor 1000 may include an active pixel sensor array 1001, a row decoder 1002, a row driver 1003, a column decoder 1004, a timing generator 1005, a correlated double sampler (CDS) 1006, an analog-to-digital converter (ADC) 1007, and an input / output (I / O) buffer 1008.

[0039] The active pixel sensor array 1001 may include a plurality of unit pixels, which may be arranged two-dimensionally (2D) and may be configured to convert an optical signal into an electrical signal. The active pixel sensor array 1001 may be driven by a plurality of driving signals (such as, but not limited to, a pixel selection signal, a reset signal, and a charge transfer signal) that can be sent from the row driver 1003. In addition, the converted electrical signal may be provided to the correlated double sampler 1006.

[0040] The row driver 1003 may be configured to provide driving signals for driving the plurality of unit pixels to the active pixel sensor array 1001 based on the result decoded by the row decoder 1002. In the case where the unit pixels are arranged in a matrix shape (e.g., arranged in rows and columns), the driving signals may be provided to the corresponding rows.

[0041] The timing generator 1005 may be configured to provide timing signals and control signals to the row decoder 1002 and the column decoder 1004.

[0042] The correlated double sampler 1006 can be configured to receive an electrical signal generated in the active pixel sensor array 1001 and perform a hold and sample operation on the received electrical signal. For example, the correlated double sampler 1006 can perform a double sampling operation on a specific noise level and a signal level of the electrical signal, and can output a difference level corresponding to the difference between the noise level and the signal level.

[0043] The analog-to-digital converter 1007 can be configured to convert an analog signal corresponding to the level output from the correlated double sampler 1006 into a digital signal and output the converted digital signal to the I / O buffer 1008.

[0044] The input / output buffer 1008 can be configured to latch the digital signal and sequentially output the latched digital signal to the image signal processing unit based on the result decoded by the column decoder 1004.

[0045] Figure 2 is a circuit diagram showing an active pixel sensor array of the image sensor 1000 according to an embodiment.

[0046] Referring to Figure 1 and Figure 2 , the active pixel sensor array 1001 can include a plurality of pixel regions PX that can be arranged in a matrix shape. Each pixel region PX can include a transfer transistor TX. Each pixel region PX can further include a logic transistor. The logic transistor can include a reset transistor RX, a selection transistor SX, or a source follower transistor DX. The transfer transistor TX can include a transfer gate TG. Each pixel region PX can further include a photoelectric conversion section PD and a floating diffusion region FD. In an embodiment, the logic transistors RX, SX, and DX can be shared by the pixel region PX.

[0047] The photoelectric conversion section PD can be configured to generate and store photo charges whose amount can be proportional to the amount of light incident from the outside. The photoelectric conversion section PD can be and / or can include, but is not limited to, a photodiode, a phototransistor, a photogate, a pinned photodiode, or any combination thereof. The transfer transistor TX can be configured to transfer the charges that can be generated in the photoelectric conversion section PD to the floating diffusion region FD. The floating diffusion region FD can be configured to receive and cumulatively store the charges that can be generated in the photoelectric conversion section PD. The source follower transistor DX can be controlled based on the amount of photo charges stored in the floating diffusion region FD.

[0048] The reset transistor RX including a reset gate electrode RG can be configured to periodically release and / or reset the photo charges accumulated in the floating diffusion region FD. The reset transistor RX can include a reset gate electrode RG that can be respectively connected to the floating diffusion region FD and the power supply voltage V DDThe drain electrode and the source electrode. When the reset transistor RX is turned on, the power supply voltage V that can be connected to the source electrode of the reset transistor RX DD can be applied to the floating diffusion region FD. Therefore, if the reset transistor RX is turned on, the charge accumulated in the floating diffusion region FD can be released. That is, the floating diffusion region FD can be reset.

[0049] The source follower transistor DX including the source follower gate electrode SF can be used as a source follower buffer amplifier. The source follower transistor DX can be configured to amplify the potential change of the floating diffusion region FD and output the amplified signal to the output line V OUT .

[0050] The selection transistor SX including the selection gate electrode SEL can be used to select one row in the rows of the pixel region PX during a read operation. When the selection transistor SX is turned on, the power supply voltage V DD can be applied to the drain electrode of the source follower transistor DX.

[0051] Figure 3A is a plan view showing an image sensor according to an embodiment. Figure 3B is a plan view showing an embodiment according to Figure 3A the enlarged light receiving region. Figure 4 is a cross-sectional view taken along Figure 3B line A-A' of an embodiment. Figure 5 is a cross-sectional view taken along Figure 3B line B-B' of an embodiment. Line A-A' and B-B' can be parallel to the fifth direction D5, and the fifth direction D5 can be perpendicular to the sixth direction D6.

[0052] When viewed in a vertical cross-section, the image sensor 1000 may include a photoelectric conversion layer 10, a pixel circuit layer 20, and an optically transparent layer 30. When viewed in a vertical cross-section, the photoelectric conversion layer 10 may be disposed between the pixel circuit layer 20 and the optically transparent layer 30. The photoelectric conversion layer 10 may be configured to convert light incident from the outside into an electrical signal.

[0053] The photoelectric conversion layer 10 may include a device isolation layer 105, a deep device isolation pattern DTI, a photoelectric conversion portion (also referred to as a photoelectric conversion region) PD, and a floating diffusion region FD.

[0054] Referring to Figure 3A and Figure 3B , the image sensor may include a pixel array region R1 and a pad region R2.

[0055] The pixel array region R1 may include a plurality of pixels P, and the plurality of pixels P may be two-dimensionally arranged in a third direction D3 and a fourth direction D4 that may not be parallel to each other. Each pixel P may include a photoelectric conversion device and at least one readout device. Each pixel P in the pixel array region R1 may be configured to output an electrical signal generated by incident light. The pad region R2 may include a plurality of pads CP.

[0056] The pixel array region R1 may include a light receiving region AR and a light blocking region OB. When observed in a plan view, the light blocking region OB may be configured to surround the light receiving region AR. That is, when observed in a plan view, the light blocking region OB may be provided to surround the light receiving region AR in four (4) different directions (e.g., an upper direction, a lower direction, a left direction, and a right direction). In an embodiment, a reference pixel P into which light may not enter may be provided in the light blocking region OB. In this case, by comparing the amount of charge that can be obtained from a unit pixel P in the light receiving region AR with a reference charge generated in the reference pixel P, the magnitude of the electrical signal generated by the unit pixel P can be calculated.

[0057] The light receiving region AR of the pixel array region R1 may include a central pixel region X and an edge pixel region Y. A plurality of pixels may be provided in the central pixel region X, and the edge pixel region Y may be provided to surround the central pixel region X in a plan view. When observed in a plan view, the edge pixel region Y may be provided to surround the central pixel region X in four (4) different directions (e.g., an upper direction, a lower direction, a left direction, and a right direction). In such an embodiment, light rays may be incident on the edge pixel region Y and the central pixel region X at different angles, respectively.

[0058] A color filter and a microlens may be provided on the pixel array region R1.

[0059] The color filter may be provided on the pixel array region R1 to cover the reference pixel P, respectively. The color filters may be arranged in n rows and n columns to form a plurality of color filter groups, where n is a positive integer greater than zero (0).

[0060] The color filter groups may include a central color filter group on the central pixel region X and an edge color filter group on the edge pixel region Y. The central color filter group may include a central color filter CFx, and the edge color filter group may include an edge color filter CFy.

[0061] The color filter may include a red color filter, a green color filter, and a blue color filter. The red color filter, the green color filter, and the blue color filter may be configured to selectively allow incident light to pass through.

[0062] The microlens may be configured to collect incident light that may enter from the outside. When observed in a plan view, the microlenses may be two-dimensionally (2D) arranged in a third direction D3 and a fourth direction D4 that may not be parallel to each other.

[0063] In an embodiment, each microlens may be provided to cover one of the color filter groups. In an embodiment, each microlens may cover a color filter group in which the color filters are arranged in two (2) rows and two (2) columns. The color filters and the microlenses are described with reference to Figures 4 to 9 further description.

[0064] The image sensor 1000 may include a substrate (also referred to as a semiconductor substrate) 100. For example, the substrate 100 may be and / or may include a single crystal silicon wafer, a silicon epitaxial layer, or a silicon-on-insulator (SOI) substrate. In an embodiment, the substrate 100 may be doped with impurities of a first conductivity type (e.g., p-type). The substrate 100 may include a first surface 100A and a second surface 100B that may be opposite to each other. The outward direction perpendicular to the first surface 100A may be referred to as a first direction D1, and the outward direction perpendicular to the second surface 100B may be referred to as a second direction D2. The first direction D1 and the second direction D2 may be opposite to each other.

[0065] In each pixel region PR (which may be the pixel region PX described with reference to Figure 2 ), the device isolation layer 105 may be provided adjacent to the first surface 100A of the substrate 100. The device isolation layer 105 may be provided in a device isolation trench, and the device isolation trench may be formed by recessing the first surface 100A of the substrate 100. The device isolation layer 105 may include an insulating material. The device isolation layer 105 may define an active portion in the first surface 100A of the substrate 100. For example, the device isolation layer 105 may define a first active portion and a second active portion in the substrate 100. The first active portion and the second active portion may be spaced apart from each other in each pixel region PR and may have different sizes from each other.

[0066] The deep device isolation pattern DTI may be placed in the substrate 100. The pixel regions may be separated from each other by the deep device isolation pattern DTI. The deep device isolation pattern DTI may be configured to define the pixel regions PR in the light receiving region AR and the light blocking region OB. The deep device isolation pattern DTI may be provided between the pixel regions PR to penetrate the substrate 100 in the second direction D2.

[0067] The deep device isolation pattern DTI may be provided in a trench that may extend from the first surface 100A toward the second surface 100B. When viewed in a plan view, the deep device isolation pattern DTI may have a grid shape and / or a mesh shape that may be formed by a linear pattern extending in a third direction D3 and a fourth direction D4.

[0068] The deep device isolation pattern DTI can extend from the first surface 100A into the substrate 100 and can be interposed between pixel regions PR. The deep device isolation pattern DTI can define a plurality of photoelectric conversion portions. The deep device isolation pattern DTI can be provided to penetrate the substrate 100 in a direction from the first surface 100A toward the second surface 100B. The deep device isolation pattern DTI can be provided to penetrate a part of the device isolation layer 105.

[0069] The deep device isolation pattern DTI can have a lower width at the level of the first surface 100A of the substrate 100 and can have an upper width at the level of the second surface 100B of the substrate 100. The upper width can be smaller than the lower width. For example, as the distance from the first surface 100A of the substrate 100 increases in the direction toward the second surface 100B, the width of the deep device isolation pattern DTI can gradually decrease. The deep device isolation pattern DTI can have a length in the second direction D2. The length of the deep device isolation pattern DTI can be substantially similar to and / or equal to the vertical thickness of the substrate 100.

[0070] A line passing through the center of the deep device isolation pattern DTI can be referred to as the device isolation center line DTICL. That is, a vertical line passing through the deep device isolation pattern DTI and spaced the same distance from two opposite ends of the deep device isolation pattern DTI can be referred to as the device isolation center line DTICL.

[0071] The deep device isolation pattern DTI can include a pad insulating pattern 111, a semiconductor pattern 113, and a cap insulating pattern 115.

[0072] The semiconductor pattern 113 can be provided to penetrate at least a part of the substrate 100 in the second direction D2. The pad insulating pattern 111 can be provided between the semiconductor pattern 113 and the substrate 100. The cap insulating pattern 115 can be provided on the semiconductor pattern 113.

[0073] The top surface of the semiconductor pattern 113 based on Figure 4 the orientation can be located at a level substantially similar to and / or the same as the second surface 100B of the substrate 100. Based on Figure 4 the orientation, the bottom surface of the semiconductor pattern 113 can be in direct contact with the top surface of the cap insulating pattern 115. There can be air gaps and / or voids in the semiconductor pattern 113. In an embodiment, the semiconductor pattern 113 can be formed of and / or include polysilicon.

[0074] Based on Figure 4 the orientation, the top surface of the cap insulating pattern 115 can be located at a level higher than or equal to the top surface of the device isolation layer 105. The top surface of the cap insulating pattern 115 can have a rounded shape. Based on Figure 4In the orientation where the bottom surface of the cover insulating pattern 115 can be located at a level substantially similar and / or identical to the bottom surface of the device isolation layer 105 (e.g., the first surface 100A of the substrate 100). The pad insulating pattern 111 can conformally cover (e.g., with a substantially constant and / or identical thickness) the side surfaces of the semiconductor pattern 113 and the side surfaces of the cover insulating pattern 115. In an embodiment, the pad insulating pattern 111 and the cover insulating pattern 115 can be formed of at least one of silicon oxide (SiO), silicon oxynitride (SiON), or silicon nitride (SiN), and / or include at least one of silicon oxide (SiO), silicon oxynitride (SiON), or silicon nitride (SiN).

[0075] The photoelectric conversion region PD can be provided in the semiconductor substrate 100 and in each pixel region PR. The photoelectric conversion region PD can generate photo charges proportional to the intensity of incident light. The photoelectric conversion region PD can be formed by injecting impurities into the substrate 100, and the impurities can be of a second conductivity type different from that of the substrate 100. The photoelectric conversion region PD of the second conductivity type and the substrate 100 of the first conductivity type can form a PN junction serving as a photodiode. In an embodiment, each photoelectric conversion region PD can be provided with a doping concentration difference between the portions adjacent to the first surface 100A and the second surface 100B, so as to have a non-zero potential gradient between the first surface 100A and the second surface 100B of the semiconductor substrate 100. For example, the photoelectric conversion region PD can include a plurality of impurity regions that can be vertically stacked.

[0076] The pixel circuit layer 20 can be disposed on the first surface 100A of the substrate 100. The pixel circuit layer 20 can include pixel circuits (e.g., metal oxide semiconductor (MOS) transistors) that can be electrically connected to the photoelectric conversion region PD. For example, the pixel circuit layer 20 can include a dual conversion gain transistor and a reset transistor RX, a selection transistor SX, and a source follower transistor SF that can be the pixel transistors described with reference to Figure 2 description.

[0077] In each pixel region PR, a transfer gate TG can be provided on the first surface 100A of the substrate 100. In an embodiment, a part of the transfer gate TG can be buried in the substrate 100. The transfer gate TG can be of a vertical type. In an embodiment, the transfer gate TG can be a planar or flat-shaped pattern that can be provided on the first surface 100A of the substrate 100.

[0078] A gate insulating pattern GI may be interposed between a transfer gate TG and a substrate 100. A floating diffusion region FD may be provided in a portion of the substrate 100 adjacent to the transfer gate TG. The floating diffusion region FD may be provided in a first active portion located on one side of the transfer gate TG. The floating diffusion region FD may be formed by implanting impurities into the semiconductor substrate 100 and may have a conductivity type different from that of the semiconductor substrate 100. For example, the floating diffusion region FD may be an impurity region of a second conductivity type.

[0079] In an embodiment, light may be incident on the substrate 100 through a second surface 100B of the substrate 100. Electron-hole pairs may be generated in a PN junction by the incident light. Electrons that may be generated by this process may be transferred to a photoelectric conversion portion PD. The electrons may be transferred to the floating diffusion region FD by applying a voltage to the transfer gate TG.

[0080] An interlayer insulating layer ILD may be provided on a first surface 100A of the substrate 100 to cover the first surface 100A. The interlayer insulating layer ILD may be a composite layer including, but not limited to, at least one of silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), or a porous low-k dielectric material. An interconnect line 60 may be provided in the interlayer insulating layer ILD. In an embodiment, the floating diffusion region may be connected to the interconnect line 60. The interconnect line 60 and the interlayer insulating layer ILD may constitute a pixel circuit layer 20. The pixel circuit layer 20 may be provided on the first surface 100A of the substrate 100.

[0081] An optically transparent layer 30 may be disposed on the second surface 100B of the substrate 100. The optically transparent layer 30 may include an antireflection layer 42, a grating structure (e.g., a first grating structure GPx or a second grating structure GPy), a color filter (e.g., a center color filter CFx and an edge color filter CFy), and a microlens layer (e.g., a first microlens layer MLLx or a second microlens layer MLLy). The optically transparent layer 30 may be configured to perform an operation of focusing and / or filtering light that may be incident from the outside and supply the light to the photoelectric conversion layer 10.

[0082] The antireflection layer 42 may be disposed on a deep trench isolation pattern DTI. The antireflection layer 42 may be provided on the second surface 100B of the substrate 100 to cover the second surface 100B. The antireflection layer 42 may include, for example, an oxide material. In an embodiment, the antireflection layer 42 may be formed of at least one of Al2O3, HfO, SiO2, phosphorous tetraethyl orthosilicate (PTEOS), or may include at least one of Al2O3, HfO, SiO2, phosphorous tetraethyl orthosilicate (PTEOS).

[0083] The first grating structure GPx or the second grating structure GPy may be disposed on the antireflection layer 42. The first grating structure GPx or the second grating structure GPy may be interposed between color filters. The first grating structure GPx or the second grating structure GPy may include a light-blocking pattern (e.g., the first light-blocking pattern 48x or the second light-blocking pattern 48y) and a low-refraction pattern (e.g., the first low-refraction pattern 50x or the second low-refraction pattern 50y). The low-refraction pattern (e.g., the first low-refraction pattern 50x or the second low-refraction pattern 50y) may be disposed on the light-blocking pattern (e.g., the first light-blocking pattern 48x or the second light-blocking pattern 48y).

[0084] A line passing through the center of the grating structure (e.g., the first grating structure GPx or the second grating structure GPy) may be referred to as a grating center line (e.g., the first grating center line GPxCL or the second grating center line GPyCL). That is, a vertical line passing through the first grating structure GPx and spaced the same distance from two opposite ends of the first grating structure GPx may be referred to as the first grating center line GPxCL, and a vertical line passing through the second grating structure GPy and spaced the same distance from two opposite ends of the second grating structure GPy may be referred to as the second grating center line GPyCL.

[0085] In an embodiment, when observed in a plan view, the light-blocking pattern (e.g., the first light-blocking pattern 48x or the second light-blocking pattern 48y) and the low-refraction pattern (e.g., the first low-refraction pattern 50x or the second low-refraction pattern 50y) may overlap with the deep device isolation pattern DTI and may have a grating shape.

[0086] In an embodiment, when observed in a plan view, the light-blocking pattern (e.g., the first light-blocking pattern 48x or the second light-blocking pattern 48y) and the low-refraction pattern (e.g., the first low-refraction pattern 50x or the second low-refraction pattern 50y) may not overlap with the deep device isolation pattern DTI and may have a grating shape. In an embodiment, the first light-blocking pattern 48x or the second light-blocking pattern 48y may include, for example, titanium (Ti). The first low-refraction pattern 50x and the second low-refraction pattern 50y may have substantially similar and / or the same thickness and may be formed of substantially similar and / or the same organic material. The first low-refraction pattern 50x or the second low-refraction pattern 50y may have a refractive index lower than that of the color filter. The light-blocking pattern (e.g., the first light-blocking pattern 48x or the second light-blocking pattern 48y) and the low-refraction pattern (e.g., the first low-refraction pattern 50x or the second low-refraction pattern 50y) may prevent a crosstalk problem from occurring between adjacent pixel regions PR in the pixel region PR.

[0087] The central color filter CFx or the peripheral color filter CFy may be disposed on the antireflection layer 42. The central color filter CFx or the peripheral color filter CFy may constitute a color filter group. That is, the color filter group may include the central color filter CFx on the central pixel region and the peripheral color filter CFy on the peripheral pixel region.

[0088] The microlens layer (e.g., the first microlens layer MLLx or the second microlens layer MLLy) may be disposed on the color filter (e.g., the central color filter CFx or the peripheral color filter CFy) and the grating structure (e.g., the first grating structure GPx or the second grating structure GPy). The first microlens layer MLLx or the second microlens layer MLLy may be disposed to cover the color filter group.

[0089] The first microlens layer MLLx or the second microlens layer MLLy may include a lens planarization layer (e.g., the first lens planarization layer PLx or the second lens planarization layer PLy) in contact with the color filter group and microlenses (e.g., the first microlens MLx or the second microlens MLy) on the first lens planarization layer PLx or the second lens planarization layer PLy. The first lens planarization layer PLx or the second lens planarization layer PLy may include a recessed lens portion (e.g., the first recessed lens portion 47x or the second recessed lens portion 47y) that may be recessed toward the substrate 100. The first microlens MLx or the second microlens MLy may be spaced apart from each other.

[0090] In an embodiment, each microlens (e.g., the first microlens MLx or the second microlens MLy) may overlap a corresponding one of the photoelectric conversion portions PD in the photoelectric conversion unit PD. In an embodiment, each microlens (e.g., the first microlens MLx or the second microlens MLy) may overlap a corresponding plurality of the photoelectric conversion portions PD in the photoelectric conversion unit PD. For example, each microlens (e.g., the first microlens MLx or the second microlens MLy) may overlap four (4) photoelectric conversion portions PD that may be arranged in a clockwise direction.

[0091] Refer to Figure 4 and Figure 5 The image sensor 1000 in the central pixel region X and the peripheral pixel region Y will be further described.

[0092] Refer to Figure 4 The image sensor 1000 in the central pixel region X will be further described below. In an embodiment, the pixel region in the central region of the substrate 100 when viewed in a plan view may be referred to as the central pixel region X. The central pixel region X may include a central color filter group on the central pixel region X. The central color filter group may include a plurality of central color filters CFx. The central pixel region X may include the central color filter CFx and the corresponding photoelectric conversion portion PD.

[0093] In the central pixel region X, the photoelectric conversion unit PD and the central color filter CFx may overlap with each other. The central color filter CFx may be provided such that the central color filter CFx can completely overlap with the photoelectric conversion unit PD. For example, in the central pixel region X, the photoelectric conversion unit PD may be provided between adjacent deep device isolation patterns DTI in the deep device isolation pattern DTI, and the central color filter CFx may be provided between adjacent first grid structures GPx in the first grid structure GPx that can overlap with the deep device isolation pattern DTI. In the central pixel region X, the first grid structure GPx may include a first light blocking pattern 48x and a first low refractive index pattern 50x.

[0094] In the central pixel region X, the first microlens layer MLLx may be provided on the central color filter CFx.

[0095] In the central pixel region X, the first microlens MLx may be provided on the first lens planarization layer PLx. There may be no interface between the first lens planarization layer PLx and the first microlens MLx. The first lens planarization layer PLx and the first microlens MLx may be connected to physically form a single object.

[0096] In the central pixel region X, the first lens planarization layer PLx of the first microlens layer MLLx may include a first concave lens portion 47x. The depression and / or hole formed by making the first lens planarization layer PLx concave toward the substrate 100 may be referred to as the first concave lens portion 47x. In a plan view, the first concave lens portion 47x may be provided between the first microlenses MLx that can be adjacent to and spaced apart from each other.

[0097] In an embodiment, the first concave lens portion 47x may be shaped like an ellipse that is partially cut. In this case, the inner surface of the first concave lens portion 47x may have a curved surface. The curvature of the first microlens MLx may be different from the curvature of the first concave lens portion 47x. In an embodiment, the curvature of the first microlens MLx may be smaller than the curvature of the first concave lens portion 47x.

[0098] In an embodiment, the first concave lens portion 47x may have a width that uniformly decreases as the distance to the substrate 100 decreases. In this case, the inner surface of the first concave lens portion 47x may be a flat surface.

[0099] The center point 47CPx of the first concave lens can be provided at the lowermost part of the concave portion of the first concave lens part 47x. The vertical distance from the center point 47CPx of the first concave lens to the top surface of the first lens planarization layer PLx can be referred to as the first concave lens height 47xH. The first height PLxH of the first lens planarization layer PLx can be greater than the first concave lens height 47xH. The first concave lens part 47x can be spaced apart from the first grid structure GPx and the center color filter CFx. The first lens planarization layer PLx can be in contact with the first grid structure GPx and the center color filter CFx.

[0100] In the center pixel region X, the first concave lens part 47x, the first grid structure GPx, and the deep device isolation pattern DTI can overlap with each other.

[0101] In the center pixel region X, the first grid center line GPxCL of the first grid structure GPx, the center point 47CPx of the first concave lens, and the device isolation center line DTICL of the deep device isolation pattern DTI can be located on the same vertical line. In the center pixel region X, the first grid center line GPxCL of the first grid structure GPx, the center point 47CPx of the first concave lens, and the device isolation center line DTICL of the deep device isolation pattern DTI can overlap with each other.

[0102] Referring to Figure 5 , the image sensor 1000 in the edge pixel region Y will be further described below. The region surrounding the center pixel region X of the substrate when observed in a plan view can be referred to as the edge pixel region Y. The edge pixel region Y can include an edge color filter group on the edge pixel region Y. The edge color filter group can include a plurality of edge color filters CFy. The edge pixel region Y can include the edge color filter CFy and the corresponding photoelectric conversion part PD.

[0103] In the edge pixel region Y, the photoelectric conversion part PD and the edge color filter CFy can be offset from each other. The edge color filter CFy can be provided to partially overlap with the photoelectric conversion part PD. For example, in the edge pixel region Y, the photoelectric conversion part PD can be provided between adjacent deep device isolation patterns DTI in the deep device isolation pattern DTI, and the edge color filter CFy can be provided between adjacent second grid structures GPy in the second grid structure GPy that can overlap with the deep device isolation pattern DTI. In the edge pixel region Y, the second grid structure GPy can include a second light blocking pattern 48y and a second low refractive index pattern 50y.

[0104] In the edge pixel region Y, the edge color filter CFy can overlap with the deep device isolation pattern DTI and the photoelectric conversion part PD. The photoelectric conversion part PD can overlap with the second grid structure GPy.

[0105] In the edge pixel region Y, the second microlens layer MLLy can be provided on the edge color filter CFy.

[0106] In the edge pixel region Y, the second microlens MLy can be provided on the second lens planarization layer PLy. There may be no interface between the second lens planarization layer PLy and the second microlens MLy. The second lens planarization layer PLy and the second microlens MLy can be connected to physically form a single object.

[0107] In the edge pixel region Y, the second lens planarization layer PLy of the second microlens layer MLLy can include a second concave lens portion 47y. The recesses and / or holes formed by recessing the second lens planarization layer PLy toward the substrate 100 can be referred to as the second concave lens portion 47y. In a plan view, the second concave lens portion 47y can be disposed between second microlenses MLy that can be adjacent to and spaced apart from each other.

[0108] In an embodiment, the second concave lens portion 47y can be shaped like a partially cut ellipse. In this case, the inner surface of the second concave lens portion 47y can have a curved surface. The curvature of the second microlens MLy can be different from the curvature of the second concave lens portion 47y. In an embodiment, the curvature of the second microlens MLy can be less than the curvature of the second concave lens portion 47y.

[0109] In an embodiment, the second concave lens portion 47y can have a width that uniformly decreases as the distance to the substrate 100 decreases. In this case, the inner surface of the second concave lens portion 47y can have a flat surface.

[0110] In the edge pixel region Y, the second concave lens center point 47yCP can be provided at the lowermost part of the recessed portion of the second concave lens portion 47y. The vertical distance from the second concave lens center point 47yCP to the top surface of the second lens planarization layer PLy can be referred to as the second concave lens height 47yH. The second height PLyH of the second lens planarization layer PLy can be greater than the second concave lens height 47yH. The second concave lens portion 47y can be spaced apart from the second grid structure GPy and the edge color filter CFy. The second lens planarization layer PLy can be in contact with the second grid structure GPy and the edge color filter CFy.

[0111] In the edge pixel region Y, the second concave lens portion 47y may not overlap with the deep device isolation pattern DTI. The second concave lens portion 47y can overlap with the edge color filter CFy. The second concave lens portion 47y can overlap with the photoelectric conversion unit PD. The second concave lens portion 47y may not be aligned with the second grid structure GPy.

[0112] In the edge pixel region Y, the second grating structure GPy may overlap with the photoelectric conversion unit PD. The second grating structure GPy may overlap with the second microlens MLy. The second grating structure GPy may not be aligned with the deep device isolation pattern DTI.

[0113] In the edge pixel region Y, the second grating center line GPyCL of the second grating structure GPy and the device isolation center line DTICL of the deep device isolation pattern DTI may be located on different vertical lines from each other. The second grating center line GPyCL and the second recessed lens center point 47yCP may be located on different vertical lines from each other. In the edge pixel region Y, the second grating center line GPyCL of the second grating structure GPy, the second recessed lens center point 47yCP, and the device isolation center line DTICL of the deep device isolation pattern DTI may not overlap with each other. The second recessed lens center point 47yCP may overlap with the edge color filter CFy and the photoelectric conversion unit PD. The device isolation center line DTICL may overlap with the edge color filter CFy. The second grating center line GPyCL may overlap with the second microlens MLy and the photoelectric conversion unit PD.

[0114] Figure 6 is a cross-sectional view taken along line A-A' Figure 3B according to an embodiment. Figure 7 is a cross-sectional view taken along line B-B' Figure 3B according to an embodiment. Figure 6 and Figure 7 The regions X and Y may include and / or may be similar in many respects to the regions X and Y described above with reference to Figure 4 and Figure 5 respectively, and may include additional features not mentioned above. Therefore, for the sake of brevity, the repeated descriptions of the regions X and Y described above with reference to Figure 4 and Figure 5 may be omitted.

[0115] Referring to Figure 6 and Figure 7 , an image sensor 1000 may be provided.

[0116] When observed in a vertical cross-section, the image sensor 1000 includes a photoelectric conversion layer 10, a pixel circuit layer 20, and an optically transparent layer 30.

[0117] The photoelectric conversion layer 10 may include a device isolation layer 105, a deep device isolation pattern DTI, a photoelectric conversion region PD, and a floating diffusion region FD.

[0118] The pixel circuit layer 20 may include interconnection lines 60 and an interlayer insulating layer ILD.

[0119] The optical transparent layer 30 may include an antireflection layer 42, a grating structure (e.g., a first grating structure GPx or a second grating structure GPy), a center color filter CFx or an edge color filter CFy, a microlens layer (e.g., a first microlens layer MLLxa or a second microlens layer MLLya), and a topmost planarization layer (e.g., a first topmost planarization layer TLxa or a second topmost planarization layer TLya) on the first microlens layer MLLxa or the second microlens layer MLLya. The first topmost planarization layer TLxa or the second topmost planarization layer TLya may include an upper recessed portion (e.g., a first upper recessed portion 57xa or a second upper recessed portion 57ya) recessed toward the substrate.

[0120] The refractive index of the topmost planarization layer (e.g., the first topmost planarization layer TLxa or the second topmost planarization layer TLya) may be lower than the refractive index of the microlens layer (e.g., the first microlens layer MLLxa or the second microlens layer MLLya), and may be higher than the refractive index of air.

[0121] Each microlens (e.g., a first microlens MLxa or a second microlens MLya) may correspond to one of the photoelectric conversion portions PD.

[0122] Figure 6 The detailed structure of the image sensor in the center pixel region X is shown. The first microlens layer MLLxa may include a first lens planarization layer PLxa in contact with the color filter group and a first microlens MLxa on the first lens planarization layer PLxa. The first lens planarization layer PLxa may have a first flat top surface FSxa that can be exposed. In an embodiment, a plurality of first microlenses MLxa may be spaced apart from each other. The first flat top surface FSxa of the first lens planarization layer PLxa may be provided between the plurality of first microlenses MLxa that can be spaced apart from each other. The first flat top surface FSxa of the first lens planarization layer PLxa may have a flat surface.

[0123] The first microlens MLxa may have a first lens center point MLxaTP that can be provided at the uppermost portion of the first microlens MLxa. When viewed in a plan view, the first lens center point MLxaTP may be located at the center of the first microlens MLxa.

[0124] The center point of the first flat top surface FSxa of the first lens planarization layer PLxa may be referred to as the first center point FSxaCP of the first flat top surface FSxa. That is, the point on the first flat top surface FSxa that can be spaced apart from two opposite ends of the first flat top surface FSxa by the same distance may be referred to as the first center point FSxaCP of the first flat top surface FSxa.

[0125] The first top planarization layer TLxa may be provided on the first microlens layer MLLxa. The first top planarization layer TLxa may be provided to be in contact with the entire first microlens layer MLLxa. The top planarization layer TLxa may be in contact with the entire top surface of the first microlens layer MLLxa. The top surface of the first microlens MLxa may be in direct contact with the first top planarization layer TLxa.

[0126] The first top planarization layer TLxa may include an upper recessed portion 57xa. The recess and / or hole formed by recessing a part of the first top planarization layer TLxa toward the substrate 100 may be referred to as the upper recessed portion 57xa. The first upper recessed portion 57xa may have a first recess center point 57xaCP provided at the lowermost part of the first upper recessed portion 57xa. The point of the first upper recessed portion 57xa closest to the substrate 100 may be referred to as the first recess center point 57xaCP.

[0127] The first upper recessed portion 57xa may be shaped like a part of an ellipse. The first upper recessed portion 57xa may have a curved shape recessed toward the substrate 100. The inner surface of the first upper recessed portion 57xa may have a curved surface. The inner surface of the first upper recessed portion 57xa may include a curved and rounded part. The curvature of the first microlens MLxa may be different from the curvature of the first upper recessed portion 57xa. In an embodiment, the curvature of the first microlens MLxa may be less than the curvature of the first upper recessed portion 57xa.

[0128] The vertical distance from the first surface 100A of the substrate 100 to the first recess center point 57xaCP of the first upper recessed portion 57xa may be referred to as the first distance L1. The vertical distance from the first surface 100A of the substrate 100 to the first lens center point MLxaTP of the first microlens MLxa may be referred to as the second distance L2. The first distance L1 may be less than the second distance L2. That is, the vertical distance from the first surface 100A of the substrate 100 to the first recess center point 57xaCP of the first upper recessed portion 57xa may be less than the vertical distance from the first surface 100A of the substrate 100 to the first lens center point MLxaTP of the first microlens MLxa. In a plan view, the first lens center point MLxaTP of the first microlens MLxa may be disposed between the first recess center points 57xaCP adjacent to and spaced apart from each other. The first recess center points 57xaCP adjacent to and spaced apart from each other may be spaced apart from the first lens center point MLxaTP therebetween by substantially similar and / or the same distance.

[0129] In the central pixel region X, the first upper recessed portion 57xa, the first flat top surface FSxa, and the deep device isolation pattern DTI can at least partially overlap each other. The first recess center point 57xaCP of the first upper recessed portion 57xa, the first center point FSxaCP of the first flat top surface FSxa, and the device isolation center line DTICL of the deep device isolation pattern DTI can be located on the same vertical line. When observed in a plan view, the first microlens MLxa can be disposed between the first recess center points 57xaCP that can be adjacent to and spaced apart from each other. The first grating structure GPx can at least partially overlap the first flat top surface FSxa of the first lens planarization layer PLxa and the first upper recessed portion 57xa. The first lens center point MLxaTP can overlap with the central color filter CFx.

[0130] Figure 7 The detailed structure of the image sensor 1000 in the edge pixel region Y is shown.

[0131] In the edge pixel region Y, the photoelectric conversion portion PD and the edge color filter CFy can be offset from each other. The edge color filter CFy and the second microlens layer MLLya can be offset from each other. The second microlens layer MLLya and the second topmost planarization layer TLya can be offset from each other.

[0132] In the edge pixel region Y, the second upper recessed portion 57ya, the second flat top surface FSya, and the deep device isolation pattern DTI can be misaligned with each other. The second recess center point 57yaCP of the second upper recessed portion 57ya, the second center point FSyaCP of the first flat top surface FSxa, and the device isolation center line DTICL of the deep device isolation pattern DTI can be located on different vertical lines from each other.

[0133] In the edge pixel region Y, the second upper recessed portion 57ya, the second microlens MLya, the edge color filter CFy, and the photoelectric conversion portion PD can overlap each other. The second grating structure GPy can overlap with the photoelectric conversion portion PD and the second microlens MLya. The deep device isolation pattern DTI can overlap with the edge color filter CFy and the second microlens MLya.

[0134] The curvature of the first upper recessed portion 57xa in the central pixel region X can be different from the curvature of the second upper recessed portion 57ya in the edge pixel region Y. For example, the curvature of the first upper recessed portion 57xa in the central pixel region X can be greater than the curvature of the second upper recessed portion 57ya in the edge pixel region Y. The width of the uppermost portion of the first upper recessed portion 57xa in the central pixel region X can be smaller than the width of the uppermost portion of the second upper recessed portion 57ya in the edge pixel region Y.

[0135] In a plan view, a second lens center point MLya of a second microlens MLya may be disposed between second recess center points 57yaCP that are adjacent to each other and spaced apart. The second recess center points 57yaCP that are adjacent to each other and spaced apart may be spaced apart from the second lens center point MLya therebetween by different distances. The second lens center point MLya may overlap with an edge color filter CFy.

[0136] Since the uppermost planarization layer (e.g., the first uppermost planarization layer TLxa or the second uppermost planarization layer TLya) includes an upper recessed portion (e.g., the first upper recessed portion 57xa or the second upper recessed portion 57ya), light that can pass through the optically transparent layer 30 and can be incident on the photoelectric conversion layer 10 can be refracted, and thus, a crosstalk problem can be suppressed.

[0137] Figure 8 is a cross-sectional view taken along line A-A' according to an embodiment. Figure 3B Figure 9 is a cross-sectional view taken along line B-B' according to an embodiment. Figure 3B Figure 8 and Figure 9 Regions X and Y of may include and / or may be similar in many respects to regions X and Y described above with reference to Figures 4 to 7 respectively, and may include additional features not mentioned above. Thus, for the sake of brevity, the repeated description of regions X and Y described above with reference to Figures 4 to 7 may be omitted.

[0138] Referring to Figure 8 and Figure 9 Image sensor 1000 according to an embodiment is further described. When viewed in a vertical cross-section, image sensor 1000 may include a photoelectric conversion layer 10, a pixel circuit layer 20, and an optically transparent layer 30.

[0139] The optically transparent layer 30 may include an antireflection layer 42, a grating structure (e.g., a first grating structure GPx or a second grating structure GPy), a center color filter CFx or an edge color filter CFy, a microlens layer (e.g., a first microlens layer MLLxb or a second microlens layer MLLyb), and an uppermost planarization layer (e.g., a first uppermost planarization layer TLxb or a second uppermost planarization layer TLyb) on the first microlens layer MLLxb or the second microlens layer MLLyb. The first uppermost planarization layer TLxb or the second uppermost planarization layer TLyb may include an upper recessed portion (e.g., a first upper recessed portion 57xb or a second upper recessed portion 57yb) that may be recessed toward the substrate.

[0140] Figure 8 Shows a detailed structure of the image sensor in the central pixel region X.

[0141] In the central pixel region X, the color filter group, the first microlens layer MLLxb, and the first top planarization layer TLxb may not be offset from each other.

[0142] The first microlens layer MLLxb may include a first lens planarization layer PLxb in contact with the color filter group and a first microlens MLxb on the first lens planarization layer PLxb. The first lens planarization layer PLxb may have a first planar top surface FSxb that can be exposed.

[0143] The first microlens MLxb may have a first lens center point MLxbTP. The center point of the first planar top surface FSxb of the first lens planarization layer PLxb may be referred to as the first center point FSxbCP of the first planar top surface FSxb.

[0144] The first top planarization layer TLxb may be provided on the first microlens layer MLLxb. The first top planarization layer TLxb may include a first upper recessed portion 57xb. The first upper recessed portion 57xb may have a first recess center point 57xbCP that can be provided at the lowermost portion of the first upper recessed portion 57xb. The point of the first upper recessed portion 57xb closest to the substrate 100 may be referred to as the first recess center point 57xbCP.

[0145] In the central pixel region X, the first microlenses MLxb may be disposed between the first upper recessed portions 57xb that are adjacent to and spaced apart from each other. The first lens center point MLxbTP may be located between the first recess center points 57xbCP that are adjacent to and spaced apart from each other. The first lens center point MLxbTP may overlap with the first grid structure GPx. The first lens center point MLxbTP may overlap with the first grid center line GPxCL of the first grid structure GPx.

[0146] The first upper recessed portion 57xb, the first planar top surface FSxb, and the deep device isolation pattern DTI may overlap with each other. The first recess center point 57xbCP of the first upper recessed portion 57xa, the first center point FSxbCP of the first planar top surface FSxb, and the device isolation center line DTICL of the deep device isolation pattern DTI may be located on the same vertical line. Each first microlens MLxb may overlap with a plurality of photoelectric conversion portions PD. Each first microlens MLxb may overlap with a plurality of central color filters CFx. For example, each first microlens MLxb may overlap with at least four (4) photoelectric conversion portions PD.

[0147] Figure 9 The detailed structure of the image sensor 1000 in the edge pixel region Y is shown.

[0148] In the edge pixel region Y, the color filter group, the second microlens layer MLLyb, and the second topmost planarization layer TLyb may be offset from each other.

[0149] The second lens center point MLybTP of the second microlens MLyb on the second lens planarization layer PLyb may not overlap with the second grid structure GPy. The second lens center point MLybTP may overlap with the edge color filter CFy. The second grid structure GPy may overlap with the second microlens MLyb. For example, each second microlens MLyb may overlap with a plurality of second grid structures GPy.

[0150] The second upper recessed portion 57yb, the second flat top surface FSyb, and the deep device isolation pattern DTI may not be aligned with each other. The second recess center point 57ybCP of the second upper recessed portion 57yb, the second center point FSybCP of the second flat top surface FSyb, and the device isolation center line DTICL of the deep device isolation pattern DTI may be located on different vertical lines from each other. Each second microlens MLyb may overlap with a plurality of photoelectric conversion portions PD. Each second microlens MLyb may overlap with a plurality of edge color filters CFy. For example, each second microlens MLyb may overlap with at least four (4) photoelectric conversion portions PD. As another example, each second microlens MLyb may overlap with at least four (4) edge color filters CFy.

[0151] Figure 10A and Figure 11A is a cross-sectional view corresponding to a cross-section taken along line A-A' of Figure 3B to show a method of manufacturing an image sensor. Figure 10B and Figure 11B is a cross-sectional view corresponding to a cross-section taken along line B-B' of Figure 3B to show a method of manufacturing the image sensor 1000. Figures 10A to 11B The regions X and Y of Figures 4 to 9 may include and / or may be similar in many respects to the regions X and Y described above with reference to Figures 4 to 9 and may include additional features not mentioned above. Therefore, for the sake of brevity, the repeated descriptions of the regions X and Y described above with reference to

[0152] Referring to Figure 10A 、 Figure 10B 、 Figure 11A and Figure 11B further describes Figures 4 to 5 the manufacturing method of the image sensor. That is, referring to Figure 10A and Figure 11A further describes the manufacturing method of the image sensor 1000 in the central pixel region X, referring to Figure 10B andFigure 11B A method of manufacturing an image sensor in the edge pixel region Y is further described.

[0153] Referring to Figure 10A , a photoelectric conversion layer 10, a pixel circuit layer 20, an antireflection layer 42 on the photoelectric conversion layer 10, a first grating structure GPx, and a central color filter CFx on the antireflection layer 42 can be provided in the central pixel region X. A first preliminary microlens layer pMLLx can be formed on the first grating structure GPx and the central color filter CFx. The first preliminary microlens layer pMLLx can be coated to cover the entire first grating structure GPx and the central color filter CFx.

[0154] A first mask pattern MSx and a first barcode mask pattern BMSx can be formed on the first preliminary microlens layer pMLLx. The first mask pattern MSx and the first barcode mask pattern BMSx can be spaced apart from each other. The first mask pattern MSx and the first barcode mask pattern BMSx can be alternately formed to be spaced apart from each other.

[0155] Each first mask pattern MSx can be composed of a single photoresist pattern. Each first barcode mask pattern BMSx can include a plurality of separated photoresist patterns. The width of each photoresist pattern in the first mask pattern MSx can be greater than the width of each of the separated photoresist patterns in the first barcode mask pattern BMSx. In an embodiment, the separated photoresist patterns of each first barcode mask pattern BMSx can be provided such that the width of the photoresist pattern at the outer position is greater than the width of the photoresist pattern at the inner position.

[0156] The first barcode mask pattern BMSx can be provided to overlap with the first grating structure GPx. The first mask pattern MSx can be provided to overlap with the central color filter CFx. The center of the first barcode mask pattern BMSx can be provided to overlap with the first grating center line GPxCL of the first grating structure GPx.

[0157] Referring to Figure 10B , a photoelectric conversion layer 10, a pixel circuit layer 20, an antireflection layer 42 on the photoelectric conversion layer 10, a second grating structure GPy, and an edge color filter CFy can be provided in the edge pixel region Y.

[0158] A second mask pattern MSy and a second barcode mask pattern BMSy can be formed on the second preliminary microlens layer pMLLy.

[0159] In the edge pixel region Y, the second barcode mask pattern BMSy can be provided to overlap with the second grating structure GPy. The second mask pattern MSy can be provided to overlap with the edge color filter CFy. The center of the second barcode mask pattern BMSy may not overlap with the second grating center line GPyCL of the second grating structure GPy. That is, the second barcode mask pattern BMSy and the second mask pattern MSy can be offset together with the second preliminary microlens layer pMLLy.

[0160] Referring to Figure 11A and Figure 11B , the mask pattern and the barcode mask pattern can be reflowed. The photoresist patterns included in the mask pattern and the barcode mask pattern can be melted by the reflow process.

[0161] Referring to Figure 11A , the first mask pattern MSx and the first barcode mask pattern BMSx in the center pixel region X can be reflowed. As a result, the first lens mask pattern LMSx can be formed. The top surface of the first lens mask pattern LMSx may include a curved surface.

[0162] The reflowed portion of the first barcode mask pattern BMSx may include the first lens mask pattern LMSx that can be recessed toward the substrate (e.g., in the first direction D1) and may have a concave shape.

[0163] The reflowed portion of the first mask pattern MSx may include the first lens mask pattern LMSx that can protrude in the opposite direction of the substrate (e.g., in the second direction D2).

[0164] The protruding first lens mask pattern LMSx may overlap with the center color filter CFx. The recessed first lens mask pattern LMSx may overlap with the first grating structure GPx. The first grating center line GPxCL of the first grating structure GPx, the first center point LxCP at the lowermost part of the recessed first lens mask pattern LMSx, and the device isolation center line DTICL of the deep device isolation pattern DTI may overlap with each other.

[0165] Thereafter, the first lens mask pattern LMSx can be used as a mask to perform an etch-back process. For example, the first microlens layer MLLx in the center pixel region X of Figure 4 can be formed by the etch-back process.

[0166] Referring to Figure 11B, the second mask pattern MSy and the second barcode mask pattern BMSy in the edge pixel region Y can be reflowed. As a result, the second lens mask pattern LMSy can be formed. The top surface of the second lens mask pattern LMSy can include a curved surface. The reflowed portion of the second barcode mask pattern BMSy can include the second lens mask pattern LMSy that can be recessed toward the substrate (e.g., in the first direction D1) and can have a concave shape.

[0167] The reflowed portion of the second mask pattern MSy can include the second lens mask pattern LMSy that can protrude in the opposite direction of the substrate (e.g., in the second direction D2).

[0168] The protruding second lens mask pattern LMSy can overlap with the edge color filter CFy. The recessed second lens mask pattern LMSy can overlap with the second grating structure GPy. The second grating center line GPyCL of the second grating structure GPy, the second center point LyCP at the lowermost part of the recessed second lens mask pattern LMSy, and the device isolation center line DTICL of the deep device isolation pattern DTI may not overlap with each other.

[0169] Thereafter, the second lens mask pattern LMSy can be used as a mask to perform a re-etching process. For example, the Figure 5 second microlens layer MLLy in the edge pixel region Y can be formed by the re-etching process.

[0170] Figure 12A 、 Figure 13A 、 Figure 14A and Figure 15A are cross-sectional views corresponding to the cross-section taken along line A-A' of Figure 3B to show a method of manufacturing an image sensor according to an embodiment. Figure 12B 、 Figure 13B 、 Figure 14B and Figure 15B are cross-sectional views corresponding to the cross-section taken along line B-B' of Figure 3B to show a method of manufacturing an image sensor according to an embodiment. Figures 12A to 15B The regions X and Y of Figures 4 to 11B can include and / or can be similar in many aspects to the regions X and Y described above with reference to Figures 4 to 11B respectively, and can include additional features not mentioned above. Therefore, for the sake of brevity, the repeated description of the regions X and Y described above with reference to Figures 4 to 11B can be omitted.

[0171] Refer to Figures 12A to 15B for a further description of Figures 6 to 7 the method of manufacturing the image sensor. That is, refer to Figure 、 ​ 、 ​ and​ Further description ​ of the manufacturing method of the image sensor 1000 in the central pixel region X, referring to ​ , ​ , ​ and ​ further describes the manufacturing method of the image sensor 1000 in the edge pixel region Y.

[0172] Referring to ​ , a photoelectric conversion layer 10, a pixel circuit layer 20, an antireflection layer 42 on the photoelectric conversion layer 10, and a first grid structure GPx and a central color filter CFx on the antireflection layer 42 can be provided in the central pixel region X. A first preliminary microlens layer pMLLxa can be formed on the first grid structure GPx and the central color filter CFx. The first preliminary microlens layer pMLLxa can be coated to cover the entire first grid structure GPx and the central color filter CFx.

[0173] A first mask pattern MSxa can be provided on the first preliminary microlens layer pMLLxa to be spaced apart from each other. The first mask pattern MSxa can be provided to expose a part of the top surface of the first preliminary microlens layer pMLLxa.

[0174] The first mask pattern MSxa can overlap with the central color filter CFx. The center of the first mask pattern MSxa can overlap with the center of the central color filter CFx.

[0175] Referring to ​ , a photoelectric conversion layer 10, a pixel circuit layer 20, an antireflection layer 42 on the photoelectric conversion layer 10, and a second grid structure GPy and an edge color filter CFy on the antireflection layer 42 can be provided in the edge pixel region Y.

[0176] A second mask pattern MSya can be provided on the second preliminary microlens layer pMLLya. The second mask pattern MSya can overlap with the edge color filter CFy. The center of the second mask pattern MSya can not overlap with the center of the edge color filter CFy.

[0177] Referring to ​ , in the central pixel region X, the first mask pattern MSxa can be reflowed. As a result of the reflow of the first mask pattern MSxa, a first lens mask pattern LMSxa can be formed. The top surface of the first lens mask pattern LMSxa can include a curved surface. The reflowed part of the first mask pattern MSxa can include the first lens mask pattern LMSxa that can protrude in the opposite direction of the substrate (e.g., in the second direction D2).

[0178] In an embodiment, a plurality of first lens mask patterns LMSxa may be spaced apart from each other. The first lens mask pattern LMSxa may overlap with the center color filter CFx. The center of the first lens mask pattern LMSxa may overlap with the center of the center color filter CFx.

[0179] Referring to ​ , in the edge pixel region Y, the second mask pattern MSya may be reflowed. As a result, a second lens mask pattern LMSya may be formed. The top surface of the second lens mask pattern LMSya may include a curved surface. The reflowed portion of the second mask pattern MSya may include the second lens mask pattern LMSya that may protrude in opposite directions of the substrate (e.g., in the second direction D2).

[0180] The protruding second lens mask pattern LMSya may overlap with the edge color filter CFy. The center of the second lens mask pattern LMSya may not overlap with the center of the edge color filter CFy.

[0181] Referring to ​ , in the center pixel region X, the first lens mask pattern LMSxa may be used as a mask to perform an etch-back process. As a result, a first microlens layer MLLxa may be formed in the center pixel region X. The first microlens layer MLLxa may form a first lens planarization layer PLxa and a first microlens MLxa. The first microlens layer MLLxa may be formed to expose a first flat top surface FSxa between the first microlenses MLxa. The first microlens layer MLLxa may be formed such that a first center point FSxaCP of the first flat top surface FSxa overlaps with a first grid center line GPxCL of the first grid structure GPx.

[0182] Referring to ​ , in the edge pixel region Y, the second lens mask pattern LMSya may be used as a mask to perform an etch-back process. As a result, a second microlens layer MLLya may be formed in the edge pixel region Y. The second microlens layer MLLya may form a second lens planarization layer PLya and a second microlens MLya. The second microlens layer MLLya may be formed to expose a second flat top surface FSya between the second microlenses MLya. The second microlens layer MLLya may be formed such that a second center point FSyaCP of the second flat top surface FSya does not overlap with a second grid center line GPyCL of the second grid structure GPy. The second microlens layer MLLya may be formed to be offset from the edge color filter CFy.

[0183] Referring to ​, in the central pixel region X, a first preliminary top planarization layer TPLxa can be formed on the first microlens layer MLLxa. The first preliminary top planarization layer TPLxa can be formed to completely cover the first microlens layer MLLxa. A first top barcode mask TBMxa can be formed on the first preliminary top planarization layer TPLxa. A plurality of first top barcode masks TBMxa can be formed to be spaced apart from each other. A part of the first preliminary top planarization layer TPLxa can be exposed.

[0184] Each first top barcode mask TBMxa can include a plurality of separated first photoresist patterns. In an embodiment, the separated first photoresist patterns of each first top barcode mask TBMxa can be provided such that the width of the first photoresist pattern at the outer position is greater than the width of the first photoresist pattern at the inner position.

[0185] The first top barcode mask TBMxa can be provided to overlap with the first grid structure GPx. The first top barcode mask TBMxa can be provided to overlap with the central color filter CFx. The center of the first top barcode mask TBMxa can overlap with the first grid center line GPxCL of the first grid structure GPx. The center of the first top barcode mask TBMxa can overlap with the first center point FSxaCP of the first flat top surface FSxa.

[0186] Thereafter, similar to ​ the embodiment, the first top barcode mask TBMxa can be reflowed to form a mask pattern that may have a recessed portion in the first direction D1, and the recessed mask pattern can be used as a mask to perform an etch-back process. As a result, ​ the first upper recessed portion 57xa can be formed. The image sensor 1000 in the central pixel region X can be formed in this way.

[0187] Referring to ​ , in the edge pixel region Y, a second preliminary top planarization layer TPLya can be formed on the second microlens layer MLLya. The second preliminary top planarization layer TPLya can be formed to completely cover the second microlens layer MLLya. A second top barcode mask TBMya can be formed on the second preliminary top planarization layer TPLya. In an embodiment, a plurality of second top barcode masks TBMya can be formed to be spaced apart from each other. A part of the second preliminary top planarization layer TPLya can be exposed.

[0188] Each second top barcode mask TBMya may include a plurality of separated second photoresist patterns. In an embodiment, the separated second photoresist patterns of each second top barcode mask TBMya may be provided such that the width of the second photoresist pattern at the outer position is greater than the width of the second photoresist pattern at the inner position.

[0189] The second top barcode mask TBMya may be formed such that it may not overlap with the second grating center line GPyCL of the second grating structure GPy. The center of the second top barcode mask TBMya may not overlap with the second center point FSyaCP of the second flat top surface FSya. The center of the second top barcode mask TBMya may not overlap with the uppermost end of the second microlens MLya. As used herein, the expression "the elements or points do not overlap with each other" may mean that the elements and / or points are located on different vertical lines from each other.

[0190] Thereafter, similar to ​ the embodiment of, the second top barcode mask TBMya may be reflowed to form a mask pattern that may have a recessed portion in the first direction D1, and the recessed mask pattern may be used as a mask to perform an etch-back process. As a result, ​ the second upper recessed portion 57ya may be formed. The image sensor in the edge pixel region Y may be formed in this way.

[0191] ​ is a cross-sectional view taken along line ​ A-A' according to an embodiment. ​ is a cross-sectional view taken along line ​ B-B' according to an embodiment. ​ and 17 The regions X and Y may include and / or may be similar in many respects to the regions X and Y described above with reference to ​ respectively, and may include additional features not mentioned above. Therefore, for the sake of brevity, the repeated descriptions of the regions X and Y described above with reference to ​ may be omitted.

[0192] Referring to ​ and ​ the image sensor 1000 according to an embodiment is further described. When observed in a vertical cross-section, the image sensor 1000 may include a photoelectric conversion layer 10, a pixel circuit layer 20, and an optically transparent layer 30.

[0193] The optical transparent layer 30 may include an antireflection layer 42, a grating structure (e.g., a first grating structure GPx or a second grating structure GPy), a center color filter CFx or an edge color filter CFy, a microlens layer (e.g., a first microlens layer MLLxc or a second microlens layer MLLyc), and a topmost planarization layer (e.g., a first topmost planarization layer TLxc or a second topmost planarization layer TLyc) on the first microlens layer MLLxc or the second microlens layer MLLyc. The first topmost planarization layer TLxc or the second topmost planarization layer TLyc may include an upper recessed portion (e.g., a first upper recessed portion 57xc or a second upper recessed portion 57yc) that can be recessed toward the substrate.

[0194] ​ The detailed structure of the image sensor 1000 in the center pixel region X is shown. The first microlens layer MLLxc may include a first lens planarization layer PLxc and a first microlens MLxc. The first topmost planarization layer TLxc may be provided on the first microlens layer MLLxc. The first topmost planarization layer TLxc may include a first upper recessed portion 57xc. The first upper recessed portion 57xc may have a first recess center point 57xcCP that can be provided at the lowermost portion of the first upper recessed portion 57xc. The point of the first upper recessed portion 57xc closest to the substrate 100 may be referred to as the first recess center point 57xcCP.

[0195] The width of the first upper recessed portion 57xc may decrease as the distance to the substrate 100 decreases. As the distance to the substrate 100 decreases, the width of the first upper recessed portion 57xc may decrease at a constant rate of change. The side surface of the first upper recessed portion 57xc may have a first inclined side surface 57xcSS. The first inclined side surface 57xcSS may have a flat surface. The first upper recessed portion 57xc may have a first recess angle θx. For example, the first recess angle θx may be in the range from about 0° to about 180°.

[0196] The width of the first upper recessed portion 57xc may decrease at a constant rate of change as the distance to the substrate 100 decreases, and since the first inclined side surface 57xcSS may not include a curved surface, the first inclined side surface 57xcSS may be inclined at the first recess angle θx.

[0197] The first upper recessed portion 57xc, the first grating structure GPx, and the deep device isolation pattern DTI may overlap each other. The first recess center point 57xcCP, the first center point FSxcCP of the first flat top surface FSxc of the first lens planarization layer PLxc, the first grating center line GPxCL of the first grating structure GPx, and the device isolation center line DTICL of the deep device isolation pattern DTI may be located on the same vertical line.

[0198] ​ Shows the detailed structure of the image sensor 1000 in the edge pixel region Y. The second microlens layer MLLyc may include a second lens planarization layer PLyc and a second microlens MLyc. The second topmost planarization layer TLyc may be provided on the second microlens layer MLLyc. The second topmost planarization layer TLyc may include a second upper recessed portion 57yc. The second upper recessed portion 57yc may have a second recess center point 57ycCP provided at the lowermost portion of the second upper recessed portion 57yc. The second recess center point 57ycCP may be the point of the second upper recessed portion 57yc closest to the substrate 100.

[0199] The width of the second upper recessed portion 57yc may decrease as the distance to the substrate 100 decreases. As the distance to the substrate 100 decreases, the width of the second upper recessed portion 57yc may decrease at a constant rate of change. The side surface of the second upper recessed portion 57yc may have a second inclined side surface 57ycSS. The second inclined side surface 57ycSS may have a flat surface. The second upper recessed portion 57yc may have a second recess angle θy. In an embodiment, the second recess angle θy may be in the range from about 0° to about 180°.

[0200] The width of the second upper recessed portion 57yc may decrease at a constant rate of change as the distance to the substrate 100 decreases, and since the second inclined side surface 57ycSS may not have a curved surface, the second inclined side surface 57ycSS may be inclined at the second recess angle θy.

[0201] In the edge pixel region Y, the second microlens layer MLLyc and the second topmost planarization layer TLyc may be offset from each other.

[0202] In the edge pixel region Y, the second upper recessed portion 57yc, the second flat top surface FSyc, and the deep device isolation pattern DTI may not be aligned with each other. The second recess center point 57ycCP of the second upper recessed portion 57yc, the second center point FSycCP of the second flat top surface FSyc, and the device isolation center line DTICL of the deep device isolation pattern DTI may be located on different vertical lines from each other.

[0203] In the center pixel region X, the width of the uppermost portion of the first upper recessed portion 57xc may be different from the width of the uppermost portion of the second upper recessed portion 57yc in the edge pixel region Y. As an example, the width of the uppermost portion of the first upper recessed portion 57xc in the center pixel region X may be smaller than the width of the uppermost portion of the second upper recessed portion 57yc in the edge pixel region Y. The first recess angle θx in the center pixel region X may be smaller than the second recess angle θy in the edge pixel region Y.

[0204] ​ is a cross-sectional view taken along line A-A' ​ according to an embodiment. ​ is a cross-sectional view taken along line B-B' ​ according to an embodiment. ​ and ​ regions X and Y of may include and / or may be similar in many respects to regions X and Y described above with reference to ​ respectively, and may include additional features not mentioned above. Therefore, for the sake of brevity, the repeated descriptions of regions X and Y described above with reference to ​ may be omitted.

[0205] Referring to ​ and ​ Image sensor 1000 according to an embodiment is further described. When viewed in a vertical cross-section, image sensor 1000 may include a photoelectric conversion layer 10, a pixel circuit layer 20, and an optically transparent layer 30.

[0206] The optically transparent layer 30 may include an antireflection layer 42, a grating structure (e.g., a first grating structure GPx or a second grating structure GPy), a central color filter CFx or an edge color filter CFy, a microlens layer (e.g., a first microlens layer MLLxd or a second microlens layer MLLyd), and an uppermost planarization layer (e.g., a first uppermost planarization layer TLxd or a second uppermost planarization layer TLyd) on the first microlens layer MLLxd or the second microlens layer MLLyd. The first uppermost planarization layer TLxd or the second uppermost planarization layer TLyd may include an upper recessed portion (e.g., a first upper recessed portion 57xd or a second upper recessed portion 57yd) that may be recessed toward the substrate.

[0207] ​ shows a detailed structure of image sensor 1000 in the central pixel region X. The first microlens layer MLLxd may include a first lens planarization layer PLxd and a first microlens MLxd. The first uppermost planarization layer TLxd may be provided on the first microlens layer MLLxd. The first uppermost planarization layer TLxd may include a first upper recessed portion 57xd. The first upper recessed portion 57xd may have a first recessed center point 57xdCP provided at the center of the lowermost surface of the first upper recessed portion 57xd. The point of the first upper recessed portion 57xd closest to the substrate 100 may be referred to as the first recessed center point 57xdCP.

[0208] The first width 57xWd of the first upper recessed portion 57xd may be substantially constant and / or the same value regardless of the distance from the substrate 100. The side surface of the first upper recessed portion 57xd may be perpendicular to the substrate 100.

[0209] The first upper recess portion 57xd, the first grating structure GPx, and the deep device isolation pattern DTI may overlap with each other. The first recess center point 57xdCP, the first center point FSxdCP of the first flat top surface FSxd of the first lens planarization layer PLxd, the first grating center line GPxCL of the first grating structure GPx, and the device isolation center line DTICL of the deep device isolation pattern DTI may be located on the same vertical line.

[0210] ​ The detailed structure of the image sensor 1000 in the edge pixel region Y is shown. The second microlens layer MLLyd may include a second lens planarization layer PLyd and a second microlens MLyd. The second topmost planarization layer TLyd may be provided on the second microlens layer MLLyd. The second topmost planarization layer TLyd may include a second upper recess portion 57yd. The second upper recess portion 57yd may have a second recess center point 57ydCP that may be provided at the center of the lowermost surface of the second upper recess portion 57yd. The point of the second upper recess portion 57yd closest to the substrate 100 may be referred to as the second recess center point 57ydCP.

[0211] The second width 57yWd of the second upper recess portion 57yd may be a substantially constant and / or the same value regardless of the distance from the substrate 100. The side surface of the second upper recess portion 57yd may be perpendicular to the substrate 100.

[0212] In the edge pixel region Y, the second microlens layer MLLyd and the second topmost planarization layer TLyd may be offset from each other.

[0213] In the edge pixel region Y, the second upper recess portion 57yd, the second flat top surface FSyd, and the deep device isolation pattern DTI may not be aligned with each other. The second recess center point 57ydCP of the second upper recess portion 57yd, the second center point FSydCP of the second flat top surface FSyd, and the device isolation center line DTICL of the deep device isolation pattern DTI may be located on different vertical lines from each other.

[0214] The first width 57xWd of the first upper recess portion 57xd in the central pixel region X may be different from the second width 57yWd of the second upper recess portion 57yd in the edge pixel region Y. For example, the first width 57xWd of the first upper recess portion 57xd in the central pixel region X may be smaller than the second width 57yWd of the second upper recess portion 57yd in the edge pixel region Y.

[0215] According to an embodiment, the image sensor 1000 may include a central pixel region and an edge pixel region. The microlenses covering the central pixel region and the edge pixel region may include a recessed lens portion that may be recessed toward the substrate. A top planarization layer may be additionally provided on the microlenses covering the central pixel region and the edge pixel region, and the top planarization layer may include an upper recessed portion that may be recessed toward the substrate.

[0216] Light incident on the image sensor may be refracted by the recessed lens portion and the upper recessed portion, which may suppress crosstalk problems in the image sensor. That is, light may be effectively incident on the photoelectric conversion region, and the sensitivity and color reproducibility of the image sensor may be improved.

[0217] According to an embodiment, the offset distance between the recessed portion of the microlens and the planarization layer may increase as the distance to the edge pixel region decreases. In this case, the optical reflection efficiency may be improved, thereby potentially improving the sensitivity of the image sensor 1000.

[0218] Although example embodiments of the present disclosure have been specifically shown and described, those of ordinary skill in the art will understand that changes in form and detail may be made therein without departing from the spirit and scope of the appended claims.

[0219] This application claims the priority benefit of Korean Patent Application No. 10-2024-0012576, filed with the Korean Intellectual Property Office on January 26, 2024, the disclosure of which is incorporated herein by reference in its entirety.

Claims

1. An image sensor, comprising: A semiconductor substrate, including a first surface, a second surface opposite to the first surface, and a pixel array region, the pixel array region including a central pixel region and a peripheral pixel region, the peripheral pixel region at least partially surrounding the central pixel region in a plan view; A color filter group, including a plurality of color filters, the plurality of color filters including a central color filter on the central pixel region and a peripheral color filter on the peripheral pixel region; A microlens layer, at least partially covering the color filter group; And An uppermost planarization layer, in contact with the top surface of the microlens layer, Wherein, the microlens layer includes a lens planarization layer in contact with the color filter group and microlenses on the lens planarization layer, Wherein, the uppermost planarization layer includes an upper recessed portion and a recessed center point in each of the central pixel region and the peripheral pixel region, the upper recessed portion being recessed toward the semiconductor substrate, and the recessed center point being defined at the lowermost part of the upper recessed portion, Wherein, in the central pixel region, the center point of the exposed flat top surface of the lens planarization layer at least partially vertically overlaps with the recessed center point, and Wherein, in the peripheral pixel region, the center point of the flat top surface is located on a vertical line different from the recessed center point.

2. The image sensor according to claim 1, wherein, The inner surface of the upper recessed portion includes a curved and rounded portion, and Wherein, the curvature of the upper recessed portion in the central pixel region is different from the curvature of the upper recessed portion in the peripheral pixel region.

3. The image sensor according to claim 1, wherein, The upper recessed portion has an inclined side surface inclined at an angle, and Wherein, the width of the upper recessed portion decreases as the distance to the semiconductor substrate decreases.

4. The image sensor according to claim 1, wherein, The width of the upper recessed portion decreases at a constant rate of change, and Wherein, the width of the uppermost end of the upper recessed portion in the central pixel region is smaller than the width of the uppermost end of the upper recessed portion in the peripheral pixel region.

5. The image sensor according to claim 1, further comprising: A plurality of photoelectric conversion portions, respectively corresponding to the color filter group, Wherein, the microlenses at least partially overlap with at least four of the plurality of photoelectric conversion portions.

6. The image sensor according to claim 1, wherein, The microlens includes a lens center point defined at the uppermost part of the microlens, and Wherein, a first vertical distance from the first surface of the semiconductor substrate to the recessed center point is smaller than a second vertical distance from the first surface of the semiconductor substrate to the lens center point.

7. The image sensor according to claim 1, wherein, The microlenses of the microlens layer include a plurality of microlenses spaced apart from each other, and Wherein, the plurality of microlenses have a top surface in direct contact with the uppermost planarization layer.

8. The image sensor according to claim 1, further comprising: A plurality of photoelectric conversion portions, respectively corresponding to the color filter group, and Deep device isolation patterns, defining the plurality of photoelectric conversion portions, Wherein, in the central pixel region, the recessed center point of the upper recessed portion at least partially overlaps with the deep device isolation patterns, and Among them, in the edge pixel region, the depression center point of the upper depression part is misaligned with the deep device isolation pattern.

9. The image sensor according to claim 1, wherein, The refractive index of the uppermost planarization layer is lower than that of the microlens layer, and Among them, the refractive index of the uppermost planarization layer is higher than that of air.

10. An image sensor, comprising: A semiconductor substrate, including a first surface, a second surface opposite to the first surface, and a pixel array region, the pixel array region including a central pixel region and an edge pixel region, the edge pixel region at least partially surrounding the central pixel region in a plan view; A color filter group, including a plurality of color filters, the plurality of color filters including a central color filter on the central pixel region and an edge color filter on the edge pixel region; A microlens layer, at least partially covering the color filter group; And An uppermost planarization layer, on the microlens layer, Among them, the microlens layer includes a lens planarization layer in contact with the color filter group and microlenses on the lens planarization layer, Among them, the uppermost planarization layer includes an upper depression part and a depression center point in each of the central pixel region and the edge pixel region, the upper depression part being recessed toward the semiconductor substrate, and the depression center point being defined at the lowermost part of the upper depression part, Among them, the microlens includes a lens center point defined at the uppermost part of the microlens, and Among them, a first vertical distance from the first surface to the depression center point is less than a second vertical distance from the first surface to the lens center point.

11. The image sensor according to claim 10, wherein, In the central pixel region, the center point of the exposed flat top surface of the lens planarization layer at least partially vertically overlaps with the depression center point, and Among them, in the edge pixel region, the center point of the flat top surface is located on a vertical line different from the depression center point.

12. The image sensor according to claim 10, further comprising: A grid structure, interposed between the color filters of the color filter group, Among them, in the central pixel region, the grid structure at least partially overlaps with the flat top surface of the lens planarization layer and the upper depression part, Among them, in the edge pixel region, the grid structure at least partially overlaps with the microlens, and Among them, the flat top surface includes at least a partially exposed top surface of the lens planarization layer.

13. The image sensor according to claim 10, further comprising: A plurality of photoelectric conversion parts, corresponding to the color filter group respectively; And Deep device isolation patterns, defining the plurality of photoelectric conversion parts, Among them, in the central pixel region, the deep device isolation patterns at least partially overlap with the exposed flat top surface of the lens planarization layer and the upper depression part, and Among them, in the edge pixel region, the deep device isolation patterns at least partially overlap with the edge color filter and the microlens.

14. The image sensor according to claim 10, wherein, The upper depression part has an inclined side surface inclined at an angle, and Among them, the width of the upper depression part decreases as the distance to the semiconductor substrate decreases.

15. The image sensor according to claim 14, wherein, The width of the uppermost part of the upper recessed portion in the central pixel region is smaller than the width of the uppermost part of the upper recessed portion in the edge pixel region.

16. The image sensor according to claim 10, wherein, The inner surface of the upper recessed portion includes a portion that is curved and rounded, and wherein, the curvature of the upper recessed portion in the central pixel region is different from the curvature of the upper recessed portion in the edge pixel region.

17. The image sensor according to claim 10, wherein, The refractive index of the uppermost planarization layer is lower than the refractive index of the microlens layer, and wherein, the refractive index of the uppermost planarization layer is higher than the refractive index of air.

18. An image sensor, comprising: A semiconductor substrate, including a light receiving region, a light blocking region, and a pad region, and having a first surface and a second surface opposite to the first surface; A deep device isolation pattern, disposed in the semiconductor substrate and configured to define pixel regions in the light receiving region and the light blocking region; A photoelectric conversion region, disposed in the light receiving region and the light blocking region of the semiconductor substrate; A color filter group, on the second surface; A transfer gate, on the first surface; A microlens layer, at least partially covering at least one of the color filter group; And An uppermost planarization layer, on the microlens layer, wherein, the light receiving region includes: A central pixel region; and An edge pixel region, at least partially surrounding the central pixel region in a plan view, wherein, the microlens layer includes a lens planarization layer in contact with the color filter group and a microlens on the lens planarization layer, wherein, the uppermost planarization layer includes an upper recessed portion and a recess center point, the upper recessed portion is recessed toward the semiconductor substrate, and the recess center point is defined at the lowermost part of the upper recessed portion, wherein, the microlens includes a lens center point at the uppermost part of the microlens, and wherein, a first vertical distance from the first surface to the recess center point is smaller than a second vertical distance from the first surface to the lens center point.

19. The image sensor according to claim 18, wherein, In the central pixel region, the deep device isolation pattern at least partially overlaps with the exposed flat top surface of the lens planarization layer and the upper recessed portion, and wherein, in the edge pixel region, the deep device isolation pattern at least partially overlaps with the microlens.

20. The image sensor according to claim 18, wherein, The upper recessed portion has an inclined side surface inclined at an angle, and wherein, the width of the upper recessed portion decreases as the distance to the semiconductor substrate decreases.

Images