Structures including boron arsenide layers of high thermal conductivity and methods of manufacture

Abstract

A structure for microelectronic applications, which extends along a plane of extension, comprises a crystalline layer of boron arsenide Bas (BAslay) having two dimensions respectively along two directions perpendicular to each other and in the plane of extension, each dimension being at least 2 cm.

Description

Technical Field

[0001] The present invention relates to a semiconductor crystal with high thermal conductivity, in the form of a substrate, for applications in the semiconductor industry, particularly for the thermal management of semiconductor devices formed on such a substrate. Background Art

[0002] Heat dissipation is one of the most important issues in the electronics and semiconductor industries. The high power and high density of components in integrated circuits increase the temperature of the electronic devices containing them, leading to overheating and failures. To improve the reliability of these devices, it is necessary to quickly dissipate and remove the heat generated in the integrated circuits, which is an aspect of electronic devices called thermal management.

[0003] Materials with high thermal conductivity have been proposed to remove the heat generated by integrated circuits. Particular mention may be made of aluminum nitride (AlN) and silicon carbide (SiC), with respective thermal conductivities of approximately 285 W / m.K and 300 W / m.K, which are insufficient for satisfactory thermal management. Diamond has a high thermal conductivity of approximately 2000 W / m.K, but it is costly and difficult to implement in integrated devices.

[0004] In this context, the thermal properties of boron arsenide (BAs) have proven to be attractive, particularly with a theoretically evaluated thermal conductivity of approximately 1400 W / m.K and an experimentally measured thermal conductivity of approximately 1200 W / m.K, thus being much higher than the materials conventionally used in the art, such as copper with a thermal conductivity of approximately 400 W / m.K.

[0005] However, it is well known that boron arsenide is difficult to synthesize and can only provide its maximum thermal conductivity in a perfect crystalline form, without defects and impurities that scatter phonons in the material, reducing its thermal conductivity significantly to only a few hundred watts per meter kelvin. Regarding this topic, see the publication by Fei Tian and Zhifeng Ren, "High Thermal Conductivity in Boron Arsenide: From Prediction to Reality", Angew. Chem. 2019, 131, 2 - 10.

[0006] Document US2021 / 0035885A1 describes an integrated circuit disposed in or on a BAs substrate, and a method for crystal growth of BAs single crystals. The BAs growth method uses chemical vapor transport technology, in the presence of a boron phosphide BP single crystal as a seed crystal, at a temperature of approximately 1000 °C, in a sealed quartz tube for a reaction cycle of more than 5 weeks, repeating the cycle until a high-quality BAs crystal with a thermal conductivity of up to 1300 W / m.K at room temperature is obtained.

[0007] The document US2021 / 0269318A1 describes a similar method, in which micron-sized single crystals of BAs are used as seeds in a quartz tube, and a first chemical vapor transport reaction is carried out at a temperature of about 800 °C for 2 weeks, and then a second reaction similar to the first reaction is carried out, using the crystals of better quality obtained after the first reaction as seeds to obtain millimeter-sized BAs crystals.

[0008] It has been observed that there is a great need to provide high-quality crystalline forms, preferably single-crystalline forms, of boron arsenide that are suitable for the production of electronic circuits, especially for the thermal management of these circuits. More specifically, it is particularly desirable to provide boron arsenide in the form of a substrate or a layer that can be transferred onto a substrate, the substrate being capable of accommodating a plurality of electronic circuits, such as 6″, 8″ or 12″ silicon wafers. Summary of the Invention

[0009] A first object of the present invention is to provide a structure for microelectronic applications, which is at least partially composed of a layer of boron arsenide crystals having the zinc blende structure and the chemical formula BAs. A second object is to provide a manufacturing method for obtaining such a structure, which structure is capable of accommodating a plurality of electronic circuits or has such circuits already provided thereon.

[0010] To achieve this object, a first aspect of the present invention is a structure for microelectronic applications, which structure extends along an extension plane (xy) and includes a crystalline boron arsenide BAs layer, the crystalline boron arsenide BAs layer having two dimensions respectively along two directions perpendicular to each other and contained in the extension plane, each dimension being at least 2 cm.

[0011] An advantage of the structure according to the present invention stems from the fact that it has a very high thermal conductivity, while having a geometry suitable for placing it in close contact with a plurality of electronic circuits in a collective fabrication process compatible with the conventional manufacturing techniques of the microelectronic industry. Therefore, the structure can effectively discharge the heat generated by the electronic circuits integrated on the structure or by the electronic circuits placed in close contact with the structure, thus improving the reliability of these electronic circuits.

[0012] Additional non-limiting features according to the first aspect of the present invention, considered individually or in any technically feasible combination:

[0013] - The crystalline boron arsenide BAs layer can be single-crystalline;

[0014] - The structure can further include a 3C polytype silicon carbide layer in direct contact with the boron arsenide BAs layer;

[0015] - One of the crystalline boron arsenide BAs layer and the 3C polytype silicon carbide layer may include an implanted layer comprising hydrogen and / or helium;

[0016] - The structure may include a temporary support attached to the crystalline boron arsenide BAs layer;

[0017] - The temporary support may be a sticky thermal tape; and

[0018] - The structure may include a stress source material layer between the temporary support and the crystalline boron arsenide BAs layer.

[0019] The invention extends to an electronic device incorporating the structure. Additional non-limiting features of the electronic device according to the invention, considered individually or in any technically feasible combination:

[0020] - The electronic device may include a semiconductor substrate integrating at least one electronic circuit juxtaposed with the crystalline boron arsenide BAs layer;

[0021] - The crystalline boron arsenide BAs layer may be bonded to the semiconductor substrate by direct bonding;

[0022] - The electronic device may include a transistor configured to include a channel formed in the crystalline boron arsenide BAs layer.

[0023] A second aspect of the invention relates to the manufacture of a structure comprising a crystalline boron arsenide layer of formula BAs, in order to facilitate and economically produce a boron arsenide BAs layer whose dimensions are compatible with the industrial requirements of the semiconductor industry.

[0024] To achieve this purpose, a first aspect of the invention is a method of manufacturing a structure for microelectronic applications, the method comprising the steps of: providing a 3C polytype silicon carbide layer having a flat surface, and growing a crystalline boron arsenide BAs layer on the silicon carbide layer, the silicon carbide layer (3C-SiC lay ) and the crystalline boron arsenide BAs layer having two dimensions respectively along two directions perpendicular to each other and contained in an extension plane parallel to the flat surface of the silicon carbide layer, each dimension being at least 2 cm.

[0025] The method according to the invention is advantageous because it makes it possible to obtain a large-sized boron arsenide BAs layer, with dimensions in the centimeter range or in the range of several tens of centimeters, by using techniques well known in the semiconductor industry. The method makes it possible to envisage the standardization and mass manufacture of structures comprising a boron arsenide BAs layer, which is suitable for integration in a method of manufacturing electronic circuits. The dimensions of the obtained layer make it possible to envisage the collective manufacture of a plurality of semiconductor circuits on the same boron arsenide BAs layer obtained by the method according to the invention.

[0026] According to additional non-limiting features of the second aspect of the present invention, considered alone or in any technically feasible combination:

[0027] - The method may further include forming a detachment layer and detaching at least a portion of the crystalline boron arsenide BAs layer relative to at least a portion of the silicon carbide layer at the detachment layer;

[0028] - The formation of the detachment layer may include the steps of introducing a light substance into the silicon carbide layer before the step of growing the crystalline boron arsenide BAs layer so as to define a weakening plane therein, and then performing a heat treatment to divide the silicon carbide layer into two parts at the weakening plane;

[0029] - The step of growing the crystalline boron arsenide BAs layer on the silicon carbide layer may be carried out at a temperature below 850 °C;

[0030] - The crystalline boron arsenide BAs layer may be grown to a thickness of 100 μm to 2000 μm;

[0031] - The formation of the detachment layer may include the steps of introducing a light substance into the crystalline boron arsenide BAs layer so as to define a weakening plane therein, and then performing a heat treatment to divide the boron arsenide BAs layer into two parts at the weakening plane;

[0032] - The crystalline boron arsenide BAs layer may be grown to a thickness of 0.5 μm to 5 μm;

[0033] - The formation of the detachment layer may include the step of covering the silicon carbide substrate with a van der Waals material layer (vdW lay ) before the step of growing the crystalline boron arsenide BAs layer;

[0034] - The van der Waals material layer may include a graphene layer; and

[0035] - The method may further include the step of detaching the boron arsenide BAs layer from the silicon carbide layer by applying a traction to an intermediate support attached to the boron arsenide BAs layer.

[0036] The present invention extends to a method for manufacturing a microelectronic circuit, including the method for manufacturing the above-described structure, and further including the steps of bonding the crystalline boron arsenide BAs layer to a semiconductor substrate in which a plurality of electronic circuits are integrated, and separating the electronic circuits from each other after the bonding step. Description of the Drawings

[0037] Other features and advantages of the present invention will become apparent from the following detailed description of the present invention given with reference to the accompanying drawings, in which:

[0038] Figure 1 Figure 1 ​​A first structure including a crystalline boron arsenide layer according to the present invention and a method for manufacturing the same;

[0039] Figure 2 Figure 2 A second structure including a crystalline boron arsenide layer according to the present invention and a method for manufacturing the same;

[0040] Figure 3 Figure 3 A third structure including a crystalline boron arsenide layer according to the present invention and a method for manufacturing the same;

[0041] Figure 4 Figure 4 A fourth structure including a crystalline boron arsenide layer according to the present invention and a method for manufacturing the same;

[0042] Figure 5 Figure 5 Represents a specific embodiment of a structure from Figure 4 ;

[0043] Figure 6 Figure 6 A fifth structure including a crystalline boron arsenide layer according to the present invention and a method for manufacturing the same; and

[0044] Figure 7 Figure 7 Represents a first specific embodiment of a structure from Figures 1 to 6 ;

[0045] Figure 8 Figure 8 Represents a second specific embodiment of a structure from Figures 1 to 6 ; and

[0046] Figure 9 Figure 9 Shows the geometry of the crystalline boron arsenide layer from Figures 1 to 6 . Detailed Description

[0047] As seen in the background art section of the present invention, one difficulty in growing crystals and crystalline layers of boron arsenide BAs is that there is no substrate that can be used as a seed crystal for the crystal growth of this material in the form of a thin film or wafer, which can be used for the integration of electronic circuits. In fact, so far, micron-sized seed crystals have usually been used, resulting in the slow growth of crystals with uncontrolled geometries.

[0048] ​​​​​​​​​​​​​​​​However, the applicant has recognized that a known but little used material in the semiconductor industry has crystal parameters compatible with boron arsenide and can therefore be used as a basis for its crystal growth: this is the 3C polytype of zinc blende-type silicon carbide, also known as β-SiC or 3C-SiC. It should be noted in particular that the lattice parameter of 3C-SiC is sufficiently close to that of BAs used as a seed crystal for crystal growth.

[0049] For example, this material can be fabricated by growing it on a single-crystalline silicon Si substrate with a (001) crystal orientation, which is typically in the form of a substantially circular wafer with dimensions compatible with conventional processes in the semiconductor industry, such as 6 inches, 8 inches, 12 inches, or 300 mm. Specifically, due to the good compatibility between 3C-SiC and Si, especially their thermal expansion coefficients of 3.8×10 -6 K -1 and 2.6×10 -6 K -1 respectively, it is easy to increase the size of the substrate of the 3C-SiC / Si composite structure. As is well known in the semiconductor industry, a wafer can consist of an insulating or semiconductor substrate in the form of a disc, having two substantially parallel and flat opposing surfaces, and a notch or flat spot at the periphery, which can be used as a marker for the crystal orientation of the substrate if required.

[0050] First Embodiment

[0051] Figure 1 The first embodiment of the present invention is shown.

[0052] In (A), Figure 1 an intermediate structure Struct 中间 obtained by a method including the steps detailed below is represented.

[0053] On a support Sprt, such as a (001)-oriented single-crystalline silicon substrate, a layer of 3C-SiC lay is grown to a thickness of 0.3 to 5 μm, preferably 0.5 to 1.5 μm, according to a conventional heteroepitaxial method, such as by CVD or MOCVD (chemical vapor deposition and metalorganic chemical vapor deposition, respectively).

[0054] On the 3C-SiC layOn the layer, by means of the atmospheric pressure MOCVD method, using boron precursor gases such as diborane B2H6 evaporated in hydrogen or triethylboron B(C2H5)3, and arsine (AsH3) or tert-butylarsine (TBAs) or trimethylarsine (TMAs), with hydrogen used as the carrier gas, at a reduced pressure and a growth temperature of 450 °C to 800 °C, preferably 500 °C to 750 °C, a crystalline layer of boron arsenide BAs of chemical formula BAs is grown. lay .

[0055] As an alternative to the MOCVD or MBE methods, a crystalline BAs layer BAs can be grown on a 3C-SiC lay layer by a CVT (chemical vapor transport) method similar to the method described by Tian and mentioned in the "Background Art" section. lay , with the important difference being the fact that the 3C-SiC layer serves as a seed crystal. To achieve this, arsenic and boron in elemental form or in the form of boron arsenide BAs can be used as sources of arsenic and boron, optionally combined with iodine I2 and used as a transport agent, with iodine I2 capable of reversibly forming boron triiodide BI3 with elemental form B boron and boron arsenide BAs, and in the same way capable of forming arsenic triiodide AsI3. In addition to iodine I2, ammonium iodide NH4I and tellurium tetraiodide TeI4 can be used as transport agents. Placing the 3C-SiC layer, the said sources and the transport agent in a sealed reactor with a temperature gradient results in the growth of BAs in crystal form on the 3C-SiC layer placed on the cold side of the reactor, thus forming a BAs layer in crystal form. Temperature ranges such as 613 °C - 850 °C or 613 °C - 900 °C, or 727 °C - 850 °C or 727 °C - 900 °C can be considered.

[0056] According to either the MOCVD method or the CVT method, a crystalline layer, preferably a single crystal layer, of BAs with a thickness of 300 to 1000 μm, preferably 500 to 800 μm, is grown. Such a thickness enables a BAs layer to be obtained that will be self-supporting: it will not require the use of a temporary support for handling it.

[0057] The advantage of this method over the prior art methods is that a 3C-SiC layer epitaxially grown on a silicon substrate is used as a seed crystal, which makes it possible to obtain a crystal with a relatively large surface area and preferably a single crystal BAs layer, for example by using silicon wafers with diameters of 6 inches, 8 inches, 12 inches (i.e., 150 mm, 200 mm or even 300 mm) as the surface for forming the 3C-SiC layer. Thus, if wafers of these diameters are used, a boron arsenide crystal layer with a size of at least 2 cm in a given direction can be obtained, and depending on the size of the substrate used, such as 4 inches, 6 inches, 8 inches, 12 inches, i.e., 100 mm, 150 mm, 200 mm or even 300 mm respectively, the shape of the 3C-SiC layer is not limited to the typical circular shape of semiconductor substrate wafers. The boron arsenide crystal layer according to the present invention can also have an area greater than 1 cm 2 and preferably greater than 10 cm 2 and more preferably greater than 100 cm 2 of a flat surface. The boron arsenide crystal layer according to the present invention can also have a flat surface in which a circle with a diameter greater than 2 cm, preferably greater than 5 cm, preferably greater than 10 cm is inscribed.

[0058] At this stage, it is desirable to be able to separate the layer BAs TM from the support Sprt, for example by performing the Smart Cut lay method. To this end, before the growth of the BAs lay layer, the 3C-SiC lay layer can be prepared by introducing one or more light substances such as hydrogen or helium therein. This introduction can correspond to hydrogen implantation, i.e., hydrogen ion bombardment through the plane of the 3C-SiC lay layer. This plane can optionally be provided with a protective layer formed before ion bombardment, and the protective layer can optionally be removed thereafter. As is known per se, and as shown in (A), the implanted H + hydrogen ions form an implanted layer Imp in the 3C-SiC lay layer and are intended to form a weakened plane Frgl SiC defined by this implanted layer, and to divide the 3C-SiC lay layer into two parts, one part on the support side and the other part on the BAs lay layer side, and the BAs lay layer will be separated from the support at this weakened plane at a later stage. The implanted layer Imp is considered as a layer for separating the layer BAs lay from a part of its support Sprt and the layer 3C-SiC lay .

[0059] The properties, dose, and implantation energy of the implanted material are selected according to the thickness of the layer in which the transfer is desired. In the case of a 3C-SiC lay layer, a hydrogen dose of 10 16 to 5×10 17 at / cm2 can be selected, with an energy of 30 to 300 keV, in order to define a weakened plane at a depth of approximately 200 to 2000 nm. When carrying out such a method, including forming the weakened plane, it is preferable to keep the growth temperature of the BAs layer below 850 °C, for example between 613 °C and 850 °C or between 727 °C and 850 °C, in order to limit the risk of uncontrolled cleavage of the 3C-SiC lay layer.

[0060] Figure 1 In (B), the structure Struct is shown, which includes a crystalline boron arsenide layer BAS obtained after peeling off the support Sprt lay , and which is in the form of a wafer.

[0061] The step of peeling off the support Sprt is carried out by splitting at the weakened plane Frgl SiC , which can be achieved by subjecting the intermediate structure Struct 中间 to a heat treatment in a temperature range between 850 °C and 920 °C, preferably between 900 °C and 920 °C, so that the BAS lay layer can be peeled off while avoiding the phase transition of the BAS layer to the B 12 As6 layer. In addition, it is preferable to carry out this heat treatment in an atmosphere with an overpressure of arsenic (AsH3, TBAs, TMAs) in order to avoid the desorption of arsenic. Instead of or in addition to the heat treatment, this step can include applying a blade or jet of a gaseous or liquid fluid or any other mechanical force to the weakened plane Frgl SiC .

[0062] As an alternative to carrying out the Smart Cut TM process detailed above, the step of peeling off a part of the donor substrate can be replaced by a step of mechanical-chemical thinning of the support Sprt and optionally all or part of the 3C-SiC lay layer.

[0063] If the removal of a part of the thickness of the donor substrate is carried out by thinning or by splitting, then it is feasible to apply any type of finishing treatment to the structure Struct thus formed in order to match the layer BAS lay to thickness, thickness uniformity, roughness, or crystal quality specifications or any other specifications.

[0064] In the case of using Smart Cut by splitting the 3C-SiC layer TMIn this example of the process, the structure Struct consists of a part of a 3C-SiC layer and a crystalline boron arsenide layer BAs lay and a part of the 3C-SiC layer is used as a seed for its growth. Of course, the 3C-SiC layer can be completely removed, for example, by mechanical-chemical thinning, in which case the structure Struct consists only of the crystalline boron arsenide layer BAs lay and consists.

[0065] The example adopted in this embodiment consists of a BAs layer with a thickness between 200 μm and 1000 μm. Alternatively, the thickness can be between 0.5 μm and 2000 μm. The thick layer is self-supporting, and the thin layer may have a certain flexibility during processing, depending on its lateral dimensions. Therefore, it may need to be directly bonded to a permanent support or temporarily bonded to a flexible or rigid auxiliary support to facilitate its processing. This scenario will be addressed in the following embodiments, particularly the second and fourth embodiments, which can be combined with this first embodiment.

[0066] The finally obtained crystalline boron arsenide layer BAs lay reproduces the shape and size of the 3C-SiC layer, and the 3C-SiC layer is used as a seed for growing it. And, if appropriate, the 3C-SiC layer itself reproduces the shape and size of the silicon substrate that serves as the substrate for its formation. It is convenient and appropriate to use a substantially circular silicon wafer that is widely available from semiconductor material suppliers; however, any type of support on which a 3C-SiC layer can be grown is suitable, whether it is a part of a silicon substrate or any other material of any shape, preferably extending in a plane so as to grow a BAs layer having a flat geometry suitable for the semiconductor industry. For example, the layer obtained according to the present invention can be characterized as forming a wafer, that is, characterized as a component having two dimensions in two directions perpendicular to each other in the same extended plane, and each of the two dimensions is at least ten times, preferably at least one hundred times, more preferably at least 1000 times, even more preferably at least 10000 times larger than the thickness of the element, and the thickness is considered to be the dimension of the element in the direction perpendicular to the plane or perpendicular to the two directions orthogonal to each other. This vertical direction is also perpendicular to the flat surface of the 3C-SiC layer and the flat surface of its substrate (in this example, the silicon wafer). In addition, each of the two dimensions is preferably greater than 2 cm, more preferably greater than 5 cm, and even more preferably greater than 10 cm.

[0067] Figure 9 shows such a geometry, in which the crystalline boron arsenide layer BAs obtained by any of the above embodiments lay extends in the plane xy perpendicular to the direction z, and the plane xy is defined by the directions x and y, and the directions x, y, and z form a right-handed Cartesian system. In (a), Figure 9Shows layer BAs as seen in the z direction lay , the xy plane lies in the plane of the figure; in (b), Figure 9 illustrates a cross-sectional view of the xz plane of layer BAs along the axis AA’ defined in (a). lay

[0068] Second Embodiment

[0069] Figure 2 Shows a second embodiment of the present invention, which is similar to the first embodiment. Therefore, the following description will focus on the differences from the first embodiment, and for common elements, reference can be made to the description of the first embodiment.

[0070] In this embodiment, layer BAs is thinner than in the first embodiment, with a thickness between 0.5 μm and 5 μm, preferably between 1 μm and 2 μm. Additionally, as shown in (A) of Figure 2 , the splitting plane for separating layer BAs lay from the support Sprt is not defined in layer 3C-SiCA lay , but is defined within layer BAs lay itself, and is then denoted as Frgl Figure 2 in BAs , such that the splitting as explained in the first embodiment occurs within layer BAs lay , and only a part of this layer, BAs splt.lay , will ultimately remain, as shown in (B) of Figure 2 . The injection layer Imp of the first embodiment is formed in layer BAs lay this time, and this time serves as a layer for stripping only a part (part BAs lay defined below) of layer BAs lay relative to the support of layer BAs splt.lay .

[0071] In this embodiment, before the step of stripping the support Sprt, layer BAs lay is bonded to the back side of the semiconductor substrate Sub, on the front side of which a plurality of electronic circuits Crct are integrated, which makes it possible to avoid the difficulties associated with handling a layer of this thickness, which is typically flexible and fragile. These circuits are intended to be separated from each other during a step called "dicing", which involves separating the various electronic circuits formed on a common support. When referring to the integration of electronic circuits on the face of a semiconductor substrate, this can mean that the electronic circuits include transistors whose channels are formed in the volume of the semiconductor substrate, which can consist of a wafer of semiconductor material or a layer of semiconductor material supported by a support, as in the case of an SOI-type structure. ​

[0072] Preferably, before the bonding step, the semiconductor substrate Sub, on which the circuit is integrated, is thinned via its back side, for example to less than 300 μm, preferably 200 μm, in order to facilitate heat dissipation. The semiconductor substrate may consist of any semiconductor material commonly used in the semiconductor industry, such as a silicon wafer, optionally having a crystal orientation (100). In the case where the circuit is fabricated on a substrate of the SOI (silicon-on-insulator) type, which includes a semiconductor layer supported by a base substrate through an electrically insulating layer, the entire base substrate can also be chemically removed and the chemical etching can be selectively stopped at the electrically insulating layer.

[0073] Layer BAs lay can be bonded to the substrate Sub of the electronic circuit Crct through an adhesive material that is a good thermal conductor, such as including silver. Preferably, the bonding can be carried out by direct bonding through close contact at the interface between one face of the BAs layer and the back side of the semiconductor substrate Sub. In advance, the free face of the layer BAs lay and the back side of the substrate Sub can be prepared to allow direct bonding through close contact placement (e.g., through molecular adhesion). Thus, a dielectric layer, such as a silica layer (not shown here), can be formed on one or the other or both of the contact surfaces of the circuit Crct and the layer BAs lay to facilitate the bonding.

[0074] As is well known per se, during the molecular adhesion process, the surfaces to be bonded to each other, which are completely clean, flat, and smooth (one and / or the other optionally covered with a dielectric layer), are brought into close contact to facilitate the formation of molecular bonds (such as van der Waals or covalent type molecular bonds). Thus, the bonding of the two bodies is achieved without using an adhesive. The bonding may include applying a low-temperature heat treatment (e.g., between 50 °C and 300 °C, typically 100 °C), so that the binding energy can be enhanced. After the bonding and the splitting step at the weakening plane, a part of the layer BAs lay of BAs splt.lay remains attached to the circuit Crct, as shown in (B) of Figure 2 .

[0075] One advantage of using direct bonding is to avoid forming an adhesive layer between the circuit Crct and the layer BAS splt.lay , which is a worse conductor than the latter. If this solution is not feasible for technical or economic reasons, an adhesive layer can of course be used, even though it is not the best technical solution from the perspective of heat exchange.

[0076] In this embodiment, as an alternative to bonding the BAs layer to an electronic circuit, the BAs layer can be bonded to a rigid support (e.g., a wafer of semiconductor material) or a flexible support (e.g., a sticky thermal tape), as can be seen in the case of the fourth embodiment shown in Figure 4 The BAs layer can also be bonded to the front side rather than the back side of the semiconductor substrate.

[0077] An example employed in this embodiment consists of a BAs layer having a thickness between 0.5 μm and 5 μm. Alternatively, the thickness can be between 0.5 μm and 2 μm.

[0078] Third Embodiment

[0079] Figure 3 The third embodiment showing the formation of the structure Struct, which is in the form of a BAs wafer, is presented. Different from the first and second embodiments, this third embodiment is based on the 2DLT technology (2D material-based layer transfer technology). This is a technology developed for the production of components (such as single crystal layers, thin films or more complex structures) that exist in a form separated from the substrate on which they are formed. For this purpose, a material called van der Waals 2D material (2D because it is essentially two-dimensional) is inserted between the component in question and its substrate, thus allowing subsequent peeling. In the current case, the van der Waals material is used to separate the BAs layer from the substrate on which the BAs layer is grown. For elements common between the embodiments, reference can be made to the explanations given for the first embodiment. In particular, the growth method described in the first embodiment is applicable, and for these aspects of the present embodiment, reference can be made to that first embodiment.

[0080] As Figure 3 shown in (A) of lay a material layer called a van der Waals material is formed on the 3C-SiC layer of 3C-SiC carried by the support Sprt. The van der Waals material is defined as a material composed of atoms that are strongly bonded to each other only by covalent or ionic bonds in the plane of material formation, without strong bonds perpendicular to this plane. From a practical point of view, therefore, one or more layers of graphene or 2D materials, preferably a single layer, can be used to remove the structure formed on top of the graphene layer from the support located below the graphene layer, as detailed, for example, by Celesta Chang et al. in "Remote Epitaxy", Nature Methods, June 2022, or in the document WO2017 / 044577A1.

[0081] Figure 3 the intermediate structure Struct shown in (A) of中间 Formed to successively include a support body Sprt (such as single-crystalline silicon), 3C-SiC of 3C-SiC lay layer, a van der Waals material layer vdW such as a graphene layer lay , BAs layer BAS lay and a temporary support body Temp Sprt (such as a thermal tape). Optionally, a layer Stres of a material (such as nickel or copper) involving high mechanical stress can be inserted between the BAS layer and the temporary support body lay , which promotes subsequent delamination at the layer vdW lay , as Figure 3 shown. When the BAS layer has a thickness similar to that of the layer of the first embodiment, the BAS layer is considered thick enough here to be self-supporting.

[0082] The graphene layer can be obtained, for example, by a method of wet-transferring a layer obtained by CVD onto a catalytic metal substrate or by graphitizing a SiC layer by sublimation of silicon. It should be noted that when the 3C-SiC layer is thin enough, preferably 1 to less than 10, preferably 1 to 3 graphene sheets, the crystal pattern of the 3C-SiC layer can guide the crystal of the BAS layer to grow through the graphene layer.

[0083] Figure 3 The result of a simple traction of the temporary support body is shown in (B): the layer BAS lay has been delaminated from the substrate at the layer vdW lay , and then if the temporary substrate is a sticky thermal tape, the temporary substrate has been peeled off by applying heat, and the layer Stres lay has been chemically removed in a conventional manner. Then, the self-supporting body layer BAS lay itself forms a structure Struct. Depending on the application targeted by the practitioner, the layer Stres lay can be left on the layer BAS lay . The vdW lay layer is considered to be the layer for delaminating the layer BAS lay from its support body Sprt and the 3C-SiC layer 3C-SiC of 3C-SiC lay .

[0084] Fourth Embodiment

[0085] Figure 4 The fourth embodiment of the present invention is shown. Similar to the third embodiment, the following description will focus on the differences from the third embodiment, and for the common elements, reference can be made to the description of the third embodiment.

[0086] Unlike the third embodiment, on the graphene layer, BAs with a reduced thickness of only 0.5 μm to 5 μm, preferably between 1 μm and 2 μm, are grown, such that the layer of BAs lay is not self-supporting or is too fragile to be easily handled alone without auxiliary support.

[0087] In this case, at the vdW layer lay the layer of BAs is exfoliated lay and then the temporary support Temp Sprt is not exfoliated and the layer Stres lay is not removed, but the layer of BAs lay remains attached to the temporary support Temp Sprt until its final use. In this embodiment, the layer of BAs of BAs lay is supported by the temporary support Temp Sprt

[0088] Fifth embodiment

[0089] Figure 5 shows the use of a layer of BAs bonded to a temporary support as shown in Figure 4 (B). This example can be said to be a combination of the second embodiment (aspects related to bonding the layer of BAs lay to the electronic circuit Crct), the fourth embodiment (aspects related to obtaining the layer of BAs attached to the temporary support), and the third embodiment (aspects related to removing the temporary support and the layer Stres lay ). lay

[0090] In other words, one or another of the bonding techniques mentioned in the second embodiment can be applied to bond the layer of BAs of the fourth embodiment lay to one or more electronic circuits Crct integrated in the semiconductor substrate Sub, while the layer of BAs Sprt is brought into contact during processing by means of its temporary support Temp lay as shown in Figure 5 (A), and the support and the layer Stres lay are removed after bonding to the electronic circuit in order to obtain the device Dev shown in Figure 5 (B). Different from the configuration shown in Figure 2 (B), the layer of BAs lay is bonded to the front side of the semiconductor substrate Sub, that is, to the side on which the electronic circuit Crct is integrated. For the second embodiment, after bonding, the step of separating the electronic circuits from each other can be performed during an operation called "dicing" in the microelectronics industry. ​​

[0091] Sixth Embodiment

[0092] Figure 6 The sixth embodiment of the present invention is shown, which is similar to Figure 3 and Figure 4 the third and fourth embodiments shown, but its distinguishing feature is that the intermediate structure includes not only a single BAs layer, but a stack of BAs layers, each BAs layer being separated from each other by a van der Waals material layer (such as graphene). For common elements, reference may be made to these embodiments.

[0093] Therefore Figure 6 In (A), an intermediate structure Struct lay-x with n BAs layers BAs lay-x and n van der Waals material layers vdW 中间 is shown, where x is an integer from 1 to n, which increases with the distance from the support Sprt, and the layer BAs lay-n farthest from the support Sprt lay-n is formed on the van der Waals material layer vdW lay-n and is provided with a stress source material layer Stres Sprt to which a temporary support Temp lay-n is attached.

[0094] As in the third embodiment, the layer BAs lay-n can be separated from the intermediate structure. Subsequently, the van der Waals material layer vdW lay-n is removed, and then a new stress source material layer is deposited on the layer BAs lay-(n-1) , then exposed, and a new temporary support is attached thereto. Then the process is repeated until n BAs layers have been removed from the intermediate structure and formed into many BAs structures in the form of wafers. The advantage of this process is that it allows for higher productivity in the manufacture of BAs wafers.

[0095] As Figure 6 shown in (B) of lay-x , the BAs layers can be separated from their respective temporary supports and cleared from their stress source material layers. This option is suitable when the layer BAs Figure 4 is thick enough to be self-supporting. Alternatively, when the layer is too thin to be easily handled, they can remain attached to their temporary supports, as shown in the case of (B) of

[0096] Seventh Embodiment

[0097] One application of the BAs layer described in the foregoing embodiments is to remove heat from an integrated electronic circuit. Conventionally, an integrated electronic circuit is equipped with a heat sink, which is optionally provided with heat dissipation fins, Fin, in order to limit the heat generation of the electronic circuit during its operation by removing the heat generated by the electronic circuit.

[0098] In the context of the present invention, as Figure 7 shown, the BAs layer, BAs, obtained according to any of the above embodiments lay can be inserted between the electronic circuit and the heat sink. The advantage is that heat can be removed as close as possible to the circuit, and the appearance of hot spots and local heat islands on the circuit surface is restricted. Compared with known solutions, the high thermal conductivity of the BAs layer and its proximity to the circuit greatly improve the efficiency of removing heat from the electronic circuit.

[0099] The BAs layer lay can be located on the back or front of the integrated circuit chip and can be attached thereto by direct bonding (without adding an intermediate adhesive material layer) or by means of an adhesive, which is preferably a good thermal conductor. In order to ensure close contact between the BAs and the electronic circuit and to promote heat exchange between the circuit and the BAs layer, direct bonding is preferred. When compared with the BAs crystalline layer according to the present invention, which is a better thermal conductor, the adhesive (even if it is a relatively good thermal conductor) will represent a thermal barrier.

[0100] Eighth embodiment

[0101] The application examples given so far consist in using the high thermal conductivity of crystalline BAs to help remove the heat generated by a circuit integrated into another semiconductor substrate, such as silicon.

[0102] This embodiment consists in using the semiconductor properties of BAs, which is a III-V semiconductor, by integrating a device, Dev, including an electronic circuit therein, the electronic circuit including at least one transistor configured to include a channel formed in a BAs layer formed according to any of the above processes, as Figure 8 shown, wherein the transistor, Tr, is integrated into the BAs layer, BAs, according to any of the foregoing embodiments lay therein.

[0103] The transistor, Tr, includes a source, S, a drain, D, and a gate, G, which can be formed of metal, two doped regions, Dop, surrounding the gate, and a channel formation region, Ch, located between the two doped regions, and a dielectric layer, Diel, the doped regions, Dop, being surface-formed in the volume of the layer BAs lay and being in electrical contact with the source and the drain respectively, the channel formation region, Ch, being surface-located in the layer BAs layIn the volume, the dielectric layer Diel insulates the gate from the channel formation region.

[0104] This results in optimally removing the heat generated at any hot spot of the circuit, increasing its reliability and limiting the use of components dedicated to heat removal, and simplifies the design and manufacture of such a circuit compared to circuits based on other semiconductors.

[0105] In this document, the drawings are not necessarily drawn to scale. Some features and components may be enlarged or shown in a slightly schematic form relative to other components, and some details of conventional elements may not be shown for clarity and conciseness.

[0106] The present invention is of course not limited to the described embodiments, and implementation variations can be applied without departing from the scope of the present invention defined by the claims.

Claims

1. A structure for microelectronic applications, which extends along an extended plane (xy) and includes a crystalline boron arsenide BAs layer (BAs lay , BAs splt.lay ), the crystalline boron arsenide BAs layer (BAs lay , BAs splt.lay ) has two dimensions respectively along two directions (x, y) perpendicular to each other and included in the extended plane (xy), and each dimension is at least 2 cm.

2. The structure according to claim 1, wherein, The crystalline boron arsenide BAs layer (BAs lay , BAs splt.lay ) is single crystal.

3. The structure according to claim 1 or 2, further comprising a 3C polytype silicon carbide layer (3C-SiC lay , BAs splt.lay ) in direct contact with the boron arsenide BAs layer (BAs lay , 3C-SiC splt.lay ).

4. The structure according to claim 3, wherein, The crystalline boron arsenide BAs layer (BAs lay ,BAs splt.lay ) and the 3C polytype silicon carbide layer (3C-SiC lay ,3C-SiC splt.lay ) includes an injection layer (Imp), which includes hydrogen and / or helium.

5. The structure according to any one of claims 1 to 3, comprising a temporary support (Temp lay , BAs splt.lay ) attached to the crystalline boron arsenide BAs layer (BAs Sprt ).

6. The structure according to claim 5, wherein The temporary support (Temp Sprt ) is a sticky thermal tape.

7. The structure according to claim 5 or 6, comprising a stress source material layer (Stres Sprt ) between the temporary support (Temp lay ) and the crystalline boron arsenide BAs layer (BAs lay ).

8. An electronic device (Dev) incorporating the structure according to any one of claims 1 to 3.

9. The electronic device (Dev) according to claim 8, comprising a semiconductor substrate (Sub), the semiconductor substrate (Sub) integrating at least one electronic circuit (Crct) juxtaposed with the crystalline boron arsenide BAs layer (BAs lay , BAs splt.lay ).

10. The electronic device according to claim 9, wherein, The crystalline boron arsenide BAs layer (BAs lay , BAs splt.lay ) is bonded to the semiconductor substrate (Sub) by direct bonding.

11. The electronic device (Dev) according to claim 8, comprising a transistor (Tr), the transistor (Tr) being configured to include a channel formed in the crystalline boron arsenide BAs layer (BAs lay , BAs splt.lay ).

12. A method for manufacturing a structure for microelectronic applications, the method comprising the following steps: - Provide a 3C polytype silicon carbide layer (3C-SiC lay ) with a flat surface; and - Growing a crystalline boron arsenide BAs layer (BAs lay ) on the silicon carbide layer (3C-SiC lay ), the silicon carbide layer (3C-SiC lay ) and the crystalline boron arsenide BAs layer (BAs lay ) having two dimensions respectively along two directions perpendicular to each other and contained in a plane of extension parallel to the flat surface of the silicon carbide layer, each dimension being at least 2 cm.

13. The method according to claim 12, further comprising forming a release layer (Imp, vdW lay ), and at the release layer, peeling off at least a portion (BAs lay ) of the crystalline boron arsenide BAs layer (BAs lay , BAs splt.lay ) relative to at least a portion of the silicon carbide layer (3C-SiC lay ).

14. The manufacturing method according to claim 13, wherein: The formation of the peeling layer (Imp) includes the following steps: Before the step of growing the crystalline boron arsenide layer, introducing a light substance into the silicon carbide layer so as to define a weakening plane (Frgl SiC ) therein, and then performing a heat treatment to divide the silicon carbide layer into two parts at the weakening plane.

15. The manufacturing method according to claim 14, wherein, Perform the step of growing the crystalline boron arsenide BAs layer (BAs lay ) on the silicon carbide layer (3C-SiC lay ) at a temperature below 850 °C.

16. The manufacturing method according to claim 14 or 15, wherein, growing the crystalline boron arsenide BAs layer to a thickness of 100 μm to 2000 μm.

17. The manufacturing method according to claim 13, wherein, The formation of the release layer (Imp) includes the following steps: introducing light substances into the crystalline boron arsenide BAs layer to define a weakening plane (Frgl BAs ) therein, and then performing a heat treatment to divide the boron arsenide layer into two parts at the weakening plane.

18. The manufacturing method according to claim 17, wherein, growing the crystalline boron arsenide BAs layer to a thickness of 0.5 μm to 5 μm.

19. The manufacturing method according to claim 13, wherein, The formation of the release layer includes covering the silicon carbide substrate with a van der Waals material layer (vdW lay ) prior to the step of growing the crystalline boron arsenide BAs layer.

20. The method according to claim 19, wherein, The van der Waals material layer includes a graphene layer.

21. The method according to claim 19 or 20, further comprising applying to an intermediate support (Temp) with the boron arsenide layer Sprt ) is attached by pulling the boron arsenide BAs layer (BAs lay ) and the silicon carbide layer (3C-SiC lay ) peeling step.

22. A method for manufacturing a microelectronic circuit, comprising the method for manufacturing a structure for microelectronic applications according to claim 12, and further comprising the following steps: - bonding the crystalline boron arsenide BAs layer to a semiconductor substrate (Sub) in which a plurality of electronic circuits (Crct) are integrated; and - separating the electronic circuits from each other after the bonding step.

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