Transmitting / receiving circuit and signal transmission system formed by same

Abstract

The present invention relates to a transmit / receive circuit comprising: a receiver circuit (PHY-R) having a signal input (rx1, rx2) for a differential voltage signal and having a data output (Dout) for a data signal; a transmitter circuit (PHY-T) having an (electron) current source with two electrodes (+,-), having a data input (Din) for a data signal and having an (LVDS) signal output (tx1, tx2) with connection poles (tx1, tx2) for a differential voltage signal; two (bipolar) resistive elements (R1, R2); and a connection device (for connecting a signal cable having a pair of signal conductors) having two connection poles (tr1, tr2). Each of the connection poles (tx1, tx2) is electrically connected to one of the connection poles (tr1, tr2) between which one of the resistive elements is connected. The transmitter circuit (PHY-T) has at least two modes of operation (T-I, T-II) such that the transmitter circuit (PHY-T) is configured to convert a data signal at the data input (Din) into a differential voltage signal at the signal output in a first mode of operation (T-I # imgabs0 # transmission operation), and in a second operating mode (T-II # imgabs1 # termination mode), the connection poles (tx1, tx2) are electrically short-circuited or kept short-circuited.

Description

Technical Field

[0001] The present invention relates to a transmitting / receiving circuit (transceiver) for (data) signal transmission, in particular compatible with ANSI / TIA / EIA-644-1995 (LVDS), and a signal transmission system formed thereby. Background Art

[0002] Differential voltage levels are also used in (industrial) measurement and / or control systems for fast (point-to-point) transmission of digital (measurement and / or operation) data at bit rates exceeding 500 kbit / s (kilobits per second); in particular, signal transmission systems compatible with the ANSI / TIA / EIA-644-1995 standard (LVDS - Low Voltage Differential Signaling) are also used, for example, for serial transmission of digital (payload) data such as measurement and / or operation data within an (independent) measurement device or measurement system formed by means of at least one sensor and an electrically connected transducer electronics device and / or from such a measurement system to an external data processing system.

[0003] For example, signal transmission systems of the type discussed or data processing systems formed therefrom are described in DE-A 102017200687, US-A 2002 / 0126542, US-A 2009 / 0203333, US-A2015 / 0247747, US-A 2016 / 0290847, US-A 2018 / 0328774, US-A 2019 / 0107425 or the (previously unpublished) international patent application PCT / EP2022 / 084226.

[0004] As shown in US-A 2002 / 0126542, such a signal transmission system compatible with the ANSI / TIA / EIA-644-1995 standard or suitable for LVDS transmission can include two or more transmitting / receiving circuits (transceivers), each formed by a transmitter circuit (sometimes also referred to as an LVDS driver), a receiver circuit, two or more termination resistors, and one or more (twisted pair) signal cables, wherein each transmitter circuit has a data input for the (digital) data signal to be transmitted, a bipolar (LVDS) signal output for the differential (LVDS) voltage signal, and an electronic (DC) power supply, and each receiver circuit has a bipolar (LVDS) signal input for the differential (LVDS) voltage signal, which has an input resistance (usually greater than 1 MΩ), and a data output for the (digital) data signal.

[0005] The data signal transmitted or output by means of a signal transmission system of the type under discussion can be, for example, an ANSI / TIA / EIA-485 (UART - Universal Asynchronous Receiver / Transmitter) - compatible serial digital signal, i.e., such a binary (1-bit) data signal by means of which the actual (measured and / or manipulated) data is transmitted in the form of a serial bit stream with a fixed frame (corresponding to a fixed number of transmitted bits), which fixed frame typically consists of a start bit (depending on the protocol) of five to at most nine (payload) data bits, an optional parity bit for detecting transmission errors, and one or two stop bits. Thus, the data transmission can be, for example, asynchronous or byte - synchronous.

[0006] The transmitter circuit of each of the above - mentioned transmit / receive circuits is designed to be electrically connected to the receiver circuit of another transmit / receive circuit by means of a pair of signal conductors (of the above - mentioned signal cable), where the same signal conductors are also electrically connected to the corresponding receiver - circuit - side (corresponding) line end via one of the above - mentioned termination resistors, which termination resistor typically has a value greater than 20 Ω (ohms) and less than 1 kΩ (kilo - ohms), for example, approximately 100 Ω, and where the signal output of the transmitter circuit and the signal input of the receiver circuit are electrically connected to each other by means of a pair of signal conductors; this in particular enables the formation of a current loop that involves the corresponding signal output, the pair of signal conductors, a voltage divider formed by means of the termination resistor (appropriately adapted to the wave impedance of the signal cable), and the corresponding signal input. For connecting the signal conductors or the signal cable formed therewith, the corresponding transmit / receive circuit can have corresponding connection means - for example, formed by means of connection pads or plugs arranged on a printed circuit board.

[0007] The transmitter circuit of a signal transmission system of the type under discussion is particularly used, in the transmit mode of the corresponding transmitter circuit or the transmit / receive circuit formed therewith, to convert the (digital) data signal at the data input into a differential (LVDS) voltage signal at the (LVDS) signal output, in particular ANSI / TIA / EIA - 644 - 1995 (LVDS) - compatible, which can, if required, be selected or activated by means of a value - discrete selection signal at the control input of the transmitter circuit. Furthermore, the individual receiver circuits (connected to the transmitter circuit) are used to convert the (LVDS) voltage signal supplied to the (LVDS) signal input into a (digital) data signal at the data output by establishing a transmission channel in the receive mode of the receiver circuit or the transmit / receive circuit formed therewith (simultaneously selected or activated with the above - mentioned transmit mode).

[0008] For this purpose, the transmitter circuit is configured to electrically connect or keep interconnected the positive pole (+) of the current source to one of the two connection poles of the (LVDS) signal output according to the signal state of the data signal (at the data input), and complementarily electrically connect or keep interconnected the negative pole (-) of the current source to the other of the two connection poles of the (LVDS) signal output, or, according to the signal edge of the data signal (mediating between two signal states), exchange the electrical connections established between the first and second (current source) poles and different connection poles of the two connection poles of the (LVDS) signal output. Thus, in the above current loop, a (loop) current having a predeterminable, typically between 3 mA (milliamperes) and 10 mA, and possibly adjustable (signal) current intensity and a predeterminable current direction is driven by the current source of the transmitter circuit in the transmission mode such that the (loop) current flows in an alternating current direction in the current loop, wherein the (loop) current of the input signal having a first signal state (high 1) has a first current direction, and the (loop) current of the input signal having a second signal state (low 0) has a second current direction opposite to the first current direction. The (loop) current modulated accordingly by the data signal in turn causes a (signal) voltage drop across the terminating resistor, which serves as the input voltage of the receiver circuit and is uniformly modulated with the data signal, the voltage level of which is proportional to the (signal) current intensity of the (loop) voltage and the polarity depends on the current direction of the (loop) current. In addition, the receiver circuit is configured to convert the (signal) voltage at the signal input into a corresponding output voltage, i.e., the (signal) voltage at the signal output of the receiver circuit, such that in the case of a (positive) input voltage, the output voltage of the receiver circuit exhibits or has a non-zero first voltage level, wherein the voltage level exceeds (non-zero positive) a first switching voltage threshold value or is higher than the first switching voltage threshold value.

[0009] As shown, inter alia, in US-A 20020126542, a signal transmission system of the type discussed can operate (bidirectionally) in half-duplex (HDX), such that at least two transmit / receive circuits of the corresponding signal transmission system are allowed to alternately operate in transmit and receive modes in the above-described manner, in order to establish first and second transmission channels with opposite transmission directions. To ensure that at most one of the above-described first and second transmission channels is activated at any given time, the transmitter circuit is typically also configured to be in an alternative operating mode of the transmit mode, and wherein the transmitter circuit does not process the data signal at the data input section, or does not deliver the (LVDS) voltage signal at the (LVDS) signal output section. Alternatively or additionally, the receiver circuit is configured to not convert the differential (LVDS) voltage signal at the (LVDS) signal input section into the data signal at the data output section, or not output the data signal at the data output section, in an alternative operating mode of the receive mode.

[0010] By means of a signal transmission system of this type, for a given (transmission) length of the signal conductor, the (signal) quality of the (signal) voltage across the corresponding terminating resistor can be achieved at a specified transmission rate, where the (signal) quality is determined not only by the electrical properties of the signal conductor or the (signal) cable formed therewith (such as in particular the (wave) impedance or attenuation), but also by the voltage of the differential (LVDS) voltage signal at the (LVDS) signal input section, i.e., the (DC) current of the (loop) current and its shunt within the above-described shunt resistor.

[0011] On the other hand, the electrical power available for operating such a signal transmission system, i.e., the electrical (transmission) power that can actually be fed or fed to the signal conductor by means of the corresponding transmission circuit, is to a large extent limited or accidental; especially when used in measuring devices for industrial measurement and automation technology, which typically require the above-described high transmission rate of not less than 500 kbits / s, i.e., a low bit duration of not more than 2 µs (microseconds), for example, a (two-wire) measuring device with a low power consumption of at least temporarily less than 50 mW (milliwatts) or a measuring device conforming to US-A 2018 / 0328774; furthermore, for example, in such a way that the (loop) current can only be permanently set to a current less than 10 mA, and may also be at least temporarily less than 5 mA, or a corresponding (transmission) power less than 10 mW can be obtained, and may also be at least temporarily less than 5 mW. Therefore, the (signal) transmission distance that can be bridged by means of a conventional signal transmission system of the type discussed is typically limited to a few meters, but especially less than 20 meters.

[0012] In particular, the terminating resistors of each transmit / receive circuit, which are crucial for the transmission and conversion of (LVDS) voltage signals, cause the (loop) current fed in by one of the transmit circuits (during its transmission operation) to be shunted between the above-mentioned shunt and another terminating resistor connected in parallel; this is achieved in such a way that, depending on the (ohmic) resistance level of the signal conductor and the wave impedance (line characteristic impedance) of the signal cable thus formed, usually less than 70%, in particular approximately 50%, of the (loop) current is available for the input of the receiver circuit or can be converted into an (LVDS) voltage signal at the (LVDS) signal input. Summary of the Invention

[0013] Based on the above prior art, an object of the present invention is to improve a signal transmission system of the type discussed such that digital (measurement and / or operation) data can be transmitted at a transmission rate exceeding 500 kbit / s over a transmission distance greater than 20 m, in particular also greater than 30 m, despite a relatively low overall available electrical power, in particular not greater than 10 mW, or the (transmission) power can be temporarily further reduced to less than 10 mW.

[0014] To achieve this object, the present invention consists of a transmit / receive circuit (transceiver) for the transmission of (data) signals that are particularly ANSI / TIA / EIA-644-1995 (LVDS) compatible, comprising:

[0015] • A receiver circuit having an (LVDS) signal input for differential (LVDS) voltage signals that are particularly ANSI / TIA / EIA-644-1995 (LVDS) compatible, said (LVDS) signal input having an input resistance greater than 1 MΩ (megaohm), and having a data output for data signals that are particularly ANSI / TIA / EIA-485 (UART) compatible and / or binary;

[0016] • A transmitter circuit having a particularly controllable electronic (DC) current source with a (positive) first electrical (current source) pole (+) and a (negative) second electrical (current source) pole (-), having a data input for data signals that are particularly ANSI / TIA / EIA-485 (UART) compatible and / or binary (UART), and having an (LVDS) signal output for differential (LVDS) voltage signals that are particularly ANSI / TIA / EIA-644-1995 (LVDS) compatible, said (LVDS) signal output having a first connection pole and a second connection pole;

[0017] • A first (two-pole) resistive element having an ohmic resistance particularly greater than 10 Ω (ohm);

[0018] • A second (bipolar) resistive element, in particular having an ohmic resistance greater than 10 Ω and / or the same as the first resistive element;

[0019] • And a connection device (for connecting a signal cable having a pair of signal conductors), the connection device having a first connection pole and a second connection pole;

[0020] • Wherein the first connection pole of the transmitter circuit is in particular permanently electrically connected to the first connection pole of the connection device, the first resistive element is connected between the first connection pole of the transmitter circuit and the first connection pole of the connection device, and the second connection pole of the transmitter circuit is in particular permanently electrically connected to the second connection pole of the connection device, and the second resistive element is connected between the second connection pole of the transmitter circuit and the second connection pole of the connection device;

[0021] • And wherein the transmitter circuit has at least two operating modes (T-I, T-II), in particular each operating mode can be selected or activated by means of at least one value-discrete selection signal at the control input of the transmitter circuit, such that

[0022] The transmitter circuit (PHY-T) in the first operating mode (T-I Transmission mode) is configured to convert a particularly ANSI / TIA / EIA-485 (UART) compatible and / or binary (UART) data signal - in particular a 1-bit data signal - at the data input (Din) into a particularly ANSI / TIA / EIA-644-1995 (LVDS) compatible differential (LVDS) voltage signal at the (LVDS) signal output, that is, depending on the signal state of the data signal (at the data input), electrically connect or keep interconnected the first (current source) pole to one of the first and second connection poles of the (LVDS) signal output, and complementarily electrically connect or keep interconnected the second (current source) pole to the other of the first and second connection poles, or, depending on the signal edge of the data signal (at the data input) that mediates between the two signal states of the data signal, exchange the electrical connections established between the first (current source) pole and the second (current source) pole and different ones of the first and second terminals of the (LVDS) signal output,

[0023] And the transmitter circuit in the second operating mode (T-II Termination operation) is configured to electrically short-circuit or keep short-circuited the first and second terminals of the (LVDS) signal output, in particular such that the first resistive element and the second resistive element are electrically connected in series.

[0024] Furthermore, the present invention relates to a signal transmission system formed by means of such a transmitting / receiving circuit, for example, a (serial) signal transmission system for two-way (point-to-point) transmission of digital (payload) data.

[0025] According to a first embodiment of the present invention, it is further provided that the transmitter circuit is configured in a first operating mode to electrically connect in series or keep electrically connected in series a current source with a first resistive element and a second resistive element.

[0026] According to a second embodiment of the present invention, it is further provided that when the transmitter circuit operates in the first operating mode, each of the first resistive element and the second resistive element forms a series resistance of the transmitter circuit between the current source and the respective connection pole of the LVDS signal output section, for example, limiting the (nominal) short-circuit current.

[0027] According to a third embodiment of the present invention, it is further provided that the transmitter circuit is configured in a second operating mode to electrically isolate or keep electrically isolated at least one of the first and second connection poles of the (LVDS) signal output section from the current source.

[0028] According to a fourth embodiment of the present invention, it is further provided that the transmitter circuit is configured in the second operating mode to electrically isolate or keep electrically isolated the (LVDS) signal output section from at least one of the first (current source) pole and the second (current source) pole.

[0029] According to a fifth embodiment of the present invention, it is further provided that the transmitter circuit is configured in the second operating mode to electrically connect in series or keep electrically connected in series the first resistive element and the second resistive element.

[0030] According to a sixth embodiment of the present invention, it is further provided that the receiver circuit has at least two operating modes, each of which can be selected or activated by means of a discrete-value selection signal at the control input section of the receiver circuit, such that the receiver circuit is configured in the first operating mode (receiving mode) to, for example, convert an ANSI / TIA / EIA-644-1995 (LVDS)-compatible differential (LVDS) voltage signal at the (LVDS) signal input section into, for example, an ANSI / TIA / EIA-485 (UART)-compatible and / or binary (UART) data signal, such as a 1-bit data signal, at the data output section (Dout), and the receiver circuit is configured in the second operating mode to, for example, not convert an ANSI / TIA / EIA-644-1995 (LVDS)-compatible differential (LVDS) voltage signal at the (LVDS) signal input section into a data signal at the data output section, or not output a data signal at the data output section.

[0031] According to a seventh embodiment of the present invention, it is further provided that the (LVDS) signal input part of the receiver circuit has a first connection pole and a second connection pole.

[0032] According to an eighth embodiment of the present invention, it is further provided that the transmitter circuit is designed as an integrated circuit, for example, as a component of an application specific integrated circuit (ASIC).

[0033] According to a ninth embodiment of the present invention, it is further provided that the receiver circuit is designed as an integrated circuit, for example, as a component of an application specific integrated circuit (ASIC).

[0034] According to a tenth embodiment of the present invention, it is further provided that the transmitter circuit and the receiver circuit are components of the same, for example, application specific integrated circuit.

[0035] According to an eleventh embodiment of the present invention, it is further provided that the transmitter circuit has an (H-) bridge circuit formed by means of first, second, third, and fourth (semiconductor) switches, a power input part of the bridge circuit is electrically connected to a current source, and bridge branches of the bridge circuit are electrically connected to the first and second connection poles, for example, such that a series circuit of the first and second switches is electrically connected in parallel with a series circuit of the third and fourth switches, and / or such that the first and fourth switches are electrically connected to a first (current source) pole, and the second and third switches are electrically connected to a second (current source) pole. In a further development of this embodiment, it is further provided that the transmitter circuit is configured in a first operating mode to close or keep closed the first and third (mutually diagonal) switches of the (bridge circuit) when the data signal at the data input part has a first signal state corresponding to, for example, logic one, and to open or keep open the second and fourth (mutually diagonal) switches of the (bridge circuit); and the transmitter circuit is configured in the first operating mode to open or keep open the first and third switches of the (bridge circuit) when the data signal at the data input part has a second signal state deviating from the first signal state and corresponding to, for example, logic zero, and to close or keep closed the second and fourth switches of the (bridge circuit). Furthermore, the transmitter circuit is configured in the first operating mode to open and keep open the first and third switches of the (bridge circuit) when the data signal at the data input part has a signal edge transitioning from the first signal state to the second signal state, and to close or keep closed the second and fourth switches of the (bridge circuit), and the transmitter circuit is configured in the first operating mode to close and keep closed the first and third switches of the (bridge circuit) when the data signal at the data input part has a signal edge transitioning from the second signal state to the first signal state, and to open or keep open the second and fourth switches of the (bridge circuit).

[0036] According to a twelfth embodiment of the present invention, it is provided that the transmitter circuit has an (H-) bridge circuit formed by means of first, second, third, and fourth (semiconductor) switches, a power input of the bridge circuit is electrically connected to a power supply, and a bridge branch of the bridge circuit is electrically connected to first and second connection poles. For example, a series circuit of the first and second switches is electrically connected in parallel with a series circuit of the third and fourth switches, and / or the first and fourth switches are electrically connected to a first (power) pole, and the second and third switches are electrically connected to a second (power) pole. It is further provided that the transmitter circuit has (hardware) control logic for the first, second, third, and fourth (semiconductor) control outputs for respectively controlling the first, second, third, and fourth (semiconductor) switches of the (H-) bridge circuit. In a further development of this embodiment, the control logic is further configured in a first operating mode of the transmitter circuit to close or keep closed the first and third switches and to open or keep open the second and fourth switches if a data signal at the data input has a first signal state, for example corresponding to logic one; and the control logic is further configured in the first operating mode of the transmitter circuit to open or keep open the first and third switches and to close or keep closed the second and fourth switches if the data signal at the data input has a second signal state different from the first signal state, for example corresponding to logic zero. For this purpose, each of the first, second, third, and fourth (semiconductor) switches further includes a control terminal, and each of the first, second, third, and fourth (semiconductor) switches is (exactly) electrically connected to one of the associated (first, second, third, and fourth) control outputs of the control logic, and vice versa; and / or the control logic includes a first control input and a second control input. For example, the first control input forms or is electrically coupled to a control input of the transmit / receive circuit, and / or the second control input forms or is electrically coupled to a data input of the transmitter circuit, and / or the first and second operating modes of the transmitter circuit can each be selected or activated by means of at least one value-discrete (binary) selection signal at the control input of the transmitter circuit.

[0037] According to a further development of the present invention, the transmit / receive circuit further includes: a third (two-pole) resistive element having, for example, an ohmic resistance greater than 100 Ω, and a fourth (two-pole) resistive element having, for example, an ohmic resistance greater than 100 Ω and / or the same ohmic resistance as the third resistive element. According to an embodiment of this further development of the present invention, the (LVDS) signal input of the receiver circuit further includes a first connection pole and a second connection pole, and it is further provided that the third resistive element electrically connects the first connection pole of the receiver circuit to the first connection pole of the connection device, and the fourth resistive element electrically connects the second connection pole of the receiver circuit to the second connection pole of the connection device, in particular permanently.

[0038] In a further development of the signal transmission system according to the invention, the system further comprises: additional transmit / receive circuitry, for example, which is of the same type or structure as the transmit / receive circuitry PHY and / or is configured for signal transmission in accordance with ANSI / TIA / EIA-644-1995, and a signal cable having at least a pair of signal conductors, in particular a signal cable having similar and / or identical electrical properties and / or being stranded together.

[0039] According to a first embodiment of this further development of the signal transmission system, it is provided that two transmit / receive circuits are electrically connected by means of a signal cable (STP) to form a current loop.

[0040] According to a second embodiment of this further development of the signal transmission system, it is provided that the signal cable has a (transmission) length greater than 20 m (meters), for example also greater than 50 m.

[0041] According to a third embodiment of the further development of the signal transmission system, it is provided that the signal cable has a characteristic impedance (line characteristic impedance) of not less than 20 Ω and in particular not exceeding 500 Ω.

[0042] The basic idea of the invention is that during the transmission operation of the associated transmitter circuit (transmit / receive circuit), the shunt formed by the terminating resistor at the input of the receiver circuit in a transmit / receive circuit of the type in question is cancelled, or is configured only when the transmitter circuit is not operating in the transmit mode. This enables the entire (loop) current actually fed by the same transmitter circuit to be transmitted to another transmitter / receiver circuit or its receiver circuit, so that a correspondingly higher proportion of the (transmitted) power invested by the transmitter / receiver circuit can be converted to form the (LVDS) voltage signal received by the receiver circuit.

[0043] One advantage of the invention is that, in the transmit mode of the transmitter circuit, the resistive element of the transmit / receive circuit required to form the terminating resistor can alternatively also be used as a (fault) current-limiting series resistor. Another advantage of the invention is that both the transmitter circuit and the receiver circuit can be designed using conventional (commercially available) integrated circuits or as components of the same (special) integrated circuit, so that the transmitter / receiver circuit according to the invention can also be produced at a low manufacturing cost or at a manufacturing cost comparable to that of conventional transmitter / receiver circuits. Description of the Drawings

[0044] The present invention and its advantageous embodiments will be explained in more detail below on the basis of the exemplary embodiments shown in the drawings. In all the drawings, components that are the same or have the same function or perform the same function are provided with the same reference signs; for the sake of clarity or if it seems reasonable for other reasons, the reference signs mentioned above are omitted in the subsequent drawings. Further advantageous embodiments or developments, in particular combinations of parts of the invention that were initially only explained separately, also emerge from the drawings and / or the claims themselves.

[0045] In the figures, in detail:

[0046] Figure 1 or Figure 2 an exemplary embodiment of a transmit / receive circuit (transceiver) according to the invention is shown;

[0047] Figure 3 is shown (by means of a transmit / receive circuit according to Figure 1 or Figure 2 formed) an exemplary embodiment of a signal transmission system according to the invention;

[0048] Figure 4 or Figure 5 shows an embodiment of a transmit / receive circuit according to Figure 1 ; and

[0049] Figure 6 shows an embodiment of a transmit / receive circuit according to Figure 2 . Detailed Description

[0050] Figure 1 and Figure 2 schematically shows an exemplary embodiment of a transmit / receive circuit (transceiver) PHY according to the invention, for example, an external and / or battery-powered transmit / receive circuit for (data) signal transmission, in particular for the transmission of ANSI / TIA / EIA-644-1995 (LVDS)-compatible (voltage) signals.

[0051] For example, the transmit / receive circuit PHY according to the invention can be used as a component of a (serial) signal transmission system (2PHY) for the bi-directional (point-to-point) transmission of digital (payload) data in an electronic data processing system, in particular in an (industrial) measurement and / or control system, and / or in an (industrial) measurement device, in particular with a bit rate exceeding 500 kbit / s (kilobits per second) and / or over a distance greater than 20 m (meters). Figure 3Exemplary embodiments of such a 2PHY signal transmission system are schematically shown. In addition to the transmit / receive circuit PHY, the signal transmission system 2PHY further includes another transmit / receive circuit PHY', for example, which has the same type or structure as the transmit / receive circuit PHY and / or is configured for ANSI / TIA / EIA-644-1995-compatible signal transmission, and a signal cable STP having at least a pair of signal conductors, in particular a signal cable having similar and / or identical electrical properties and / or twisted together; this particularly enables the two transmit / receive circuits (PHY, PHY') to be electrically connected by means of the signal cable STP to form a current loop. The signal cable STP can advantageously be a symmetric and / or shielded signal cable or a signal cable suitable for symmetric signal transmission, such as a twisted pair cable. According to another embodiment of the present invention, the signal cable STP also has a (transmission) length greater than 20 m (meters), for example also greater than 50 m, possibly also greater than 100 m, and / or the wave impedance (line characteristic impedance) of the signal cable is not less than 20 Ω, in particular also not greater than 500 Ω. Alternatively, or in addition, or also in order to achieve the above wave impedance, each signal conductor of the signal cable STP can advantageously have a (length-)specific ohmic resistance less than 50 Ω / m (ohms per meter). According to another embodiment of the present invention, the signal cable STP is also configured to transmit (LVDS) voltage signals, for example, ANSI / TIA / EIA-644-1995-compatible and / or having symmetric and / or differential voltage levels. For example, the signal transmission system can operate (bidirectionally) in half-duplex (HDX), such that the two transmit / receive circuits (PHY, PHY') are allowed to operate alternately in the transmit and receive modes in order to establish first and second transmission channels with opposite transmission directions.

[0052] The transmit / receive circuit PHY according to the present invention, for example, is powered by a (monopolar) DC voltage Un, especially within a voltage range between 1.5 V (volts) and 3.5 V. The transmit / receive circuit PHY includes: a receive circuit PHY-R having (LVDS) signal input parts (rx1, rx2) for differential (LVDS) voltage signals that are especially ANSI / TIA / EIA-644-1995 (LVDS) compatible, the (LVDS) signal input parts having an input resistance of especially greater than 1 MΩ (megaohm), and having a data output part Dout (forming the data output part of the transmit / receive circuit) for data signals that are especially ANSI / TIA / EIA-485 (UART) compatible and / or binary; and a transmitter circuit PHY-T having a controllable electronic (DC) current source with a (positive) first electrical (current source) pole (+) and a (negative) second electrical (current source) pole (-), having a data input part Din (forming the digital input part of the transmit / receive circuit) for data signals that are especially ANSI / TIA / EIA-485 (UART) compatible and / or binary (UART), and having (LVDS) signal output parts (tx1, tx2) for differential (LVDS) voltage signals that are especially ANSI / TIA / EIA644-1995 (LVDS) compatible, the (LVDS) signal output parts having a first connection pin tx1 and a second connection pin tx2.

[0053] According to another embodiment of the present invention, the (LVDS) signal input parts (rx1, rx2) of the receiver circuit PHY-R also have a first connection pole rx1 and a second connection pole rx2. The transmitter circuit PHY-T and / or the receiver circuit PHY-R can also advantageously each be designed as an integrated circuit, for example, as a component of an application-specific integrated circuit (ASIC). For example, it is also such that the transmitter circuit PHYT and the receiver circuit PHY-R are components of the same (specific) integrated circuit.

[0054] In addition to the transmitter and receiver circuits (PHY-T, PHY-R), the transmit / receive circuit PHY according to the present invention also includes a first (two-pole) resistance element R1, for example having an ohmic resistance (value) greater than 10 Ω (ohms), a second (two-pole) resistance element R2, for example having an ohmic resistance (value) not less than 10 Ω and / or the same as that of the first resistance element, and a (cable) connection device having a first connection pole tr1 and a second connection pole tr2 (for connecting a signal cable having a pair of signal conductors). The connection device can be formed, for example, by means of a plug, pins, or spring strips (arranged on the printed circuit board of the transmit / receive circuit), by means of soldering pins, and / or by means of (PCB) terminals. As Figure 1 and Figure 2As shown, the connection pole tx1 of the transmitter circuit PHY-T is permanently electrically connected, for example, to the first connection pole tr1 of the connection device, with a first resistor element connected therebetween, and the connection pole tx2 of the transmitter circuit PHY-T is permanently electrically connected, for example, to the connection pole tr2 of the connection device, with a second resistor element connected therebetween. To limit the (maximum) fault current (of the receiver circuit), in particular to limit the (short-circuit) current value compatible with IEC60079-11:2011, the transmit / receive circuit PHY according to another embodiment of the present invention further includes a third (two-pole) resistor element R3, for example, having an ohmic resistance greater than 100 Ω, and a fourth (two-pole) resistor element R4, for example, having an ohmic resistance greater than 100 Ω and / or the same as that of the third resistor element, wherein the third resistor element electrically connects the first connection pole rx1 of the receiver circuit PHY-R to the first connection end tr1 of the connection device, and the fourth resistor element electrically connects the second connection pole rx2 of the receive circuit PHY-R to the second connection end tr2 of the connection device, especially permanently.

[0055] The transmitter circuit PHY-T of the transmit / receive circuit PHY according to the present invention further includes at least two operating modes (T-I, T-II), each of which can be selected or activated, for example, by means of at least one value-discrete selection signal at the (first) control input of the transmitter circuit PHY-T. In particular, the transmit circuit PHY-T is configured in the first operating mode T-I (transmission mode) to convert the (UART) data signal din (e.g., a 1-bit data signal) at the data input Din, which is especially ANSI / TIA / EIA-485 (UART) compatible and / or binary, into a differential (LVDS) voltage signal at the (LVDS) signal output, which is especially ANSI / TIA / EIA-644-1995 (LVDS) compatible and / or symmetric, i.e., also as Figure 1Schematically shown, according to the signal state of the data signal (at the data input section), the first (current source) pole (+) is electrically connected or kept interconnected to one of the first and second connection poles (tx1, tx2) of the (LVDS) signal output section, and complementarily, the second (current source) pole (-) is electrically connected or kept interconnected to the other of the first and second connection poles (tx1, tx2) of the (LVDS) signal output section, or, according to the signal edge of the data signal (at the data input section) that mediates between two signal states of the data signal, the electrical connections established between the first and second (current source) poles and different ones of the first and second connection poles (tx1, tx2) of the (LVDS) signal output section are swapped. In the above case, the transmit / receive circuit PHY is electrically connected via a signal cable (STP) to another transmit / receive circuit (PHY’), and a (loop) current iLVDS having a predeterminable, in particular at least temporarily constant current intensity can be driven or applied in the current loop, —— here at least involving the current source, the two signal conductors of the signal cable STP, and the transmit / receive circuit PHY’; this is in particular in such a way that when the data signal din has a first signal state (high 1), the above (loop) current iLVDS has a first current direction (+), and when the (UART) data signal has a second signal state (low 0) that is different from the first signal state (high), the (loop) current iLVDS has a second current direction (-) opposite to the first current direction (+), whereby the (UART) data signal din is modulated into the (loop) current iLVDS, or the transmitter circuit PHY-T serves as an LVDS driver that converts the data signal din provided via the signal input section Din into a voltage signal having differential voltage levels or ANSI / TIA / EIA-644-1995 compatible voltage signals. In order to limit the above (loop) current iLVDS or the (maximum) fault current of the (transmitter circuit) to a (short-circuit) current value compliant with IEC 60079-11:2011, according to another embodiment of the present invention, the transmitter circuit PHY-T is also configured in a first operating mode to electrically connect the current source in series with the first and second resistance elements (R1, R2) or keep them electrically connected in series, and / or it is stipulated that when the transmitter circuit (PHY-T) operates in the first operating mode, each of the first and second resistance elements forms a series resistance of the transmitter circuit (PHY-T) between the current source and the corresponding connection pole (tx1, tx2) of the (LVDS) signal output section, in particular a series resistance that limits the (nominal) short-circuit current.

[0056] Also as Figure 2Schematically shown in the figure, the transmitter circuit PHY-T of the transmit / receive circuit PHY according to the present invention is also configured in a second operating mode T-II (termination operation) to electrically short-circuit or keep short-circuited the first and second terminals (tx1, tx2) of the (LVDS) signal output; in particular, such that the first and second resistance elements are electrically connected in series (for forming a shunt related to the (LVDS) signal input). In the above case, the transmit / receive circuit PHY is electrically connected via a signal cable (STP) to another transmit / receive circuit (PHY'), forming a termination resistor, which is electrically connected to the signal conductor at the (corresponding) line end on the PHY-R side of the receiver circuit. The termination resistor formed by the first and second resistance elements is here particularly used to establish a voltage drop at the input of the receiver circuit PHY-R, which serves as a (LVDS) voltage signal (the voltage level of which is proportional to the current flowing therein and the polarity depends on the current direction). Then, for example, the voltage drop can be generated by means of a (loop) current iLVDS driven by the above-mentioned transmit / receive circuit PHY' or its transmitter circuit, and can also be modulated in the same manner as above (by means of the transmitter circuit PHY-T). Advantageously, the resistance of the first and second resistance elements can also be selected such that their (resistance) sum matches the wave impedance of the above-mentioned signal cable (STP) (the first and second connection poles to be connected to the transmit / receive circuit or the connecting device), or the first and first resistance elements (R1, R2) connected in series form a correspondingly optimized termination resistor for the signal cable. According to another embodiment of the present invention, the (LVDS) signal input of the receiver circuit PHY-R (rx1, rx2) has a high input resistance greater than 1 MΩ (megaohm), especially in order to allow as low a (partial) current as possible to flow through the signal input compared to the (partial) current flowing through the above-mentioned termination resistor during operation. According to another embodiment of the present invention, the transmitter circuit PHY-T is also configured in the second operating mode to electrically isolate or keep electrically isolated a current source from at least one - especially each - of the first and second connection poles (tx1, tx2) of the (LVDS) signal output, and / or to electrically isolate or keep electrically isolated the (LVDS) signal output from at least one of the first and second (current source) poles (+, -).

[0057] According to another embodiment of the present invention, the receiver circuit PHY-R also has at least two operating modes (R-I, R-II). For example, each operating mode can be selected or activated by means of a value-discrete selection signal at the control input of the receiver circuit PHY-R. The receiver circuit PHY-R is particularly configured in the first operating mode R-I (receiving mode) to process a differential (LVDS) voltage signal at the (LVDS) signal inputs (rx1, rx2) having in particular an ANSI / TIA / EIA-644-1995 (LVDS)-compatible and / or symmetric differential voltage level (uLVDS), i.e., to receive the signal and convert it into a data signal at the data output Dout that is in particular ANSI / TIA / EIA-485 (UART)-compatible and / or binary (UART), in particular a 1-bit data signal, or to operate as an LVDS receiver. For this purpose, according to another embodiment of the present invention, the receiver circuit PHY-R is also (in its first operating mode R-I) configured to convert the input voltage uLVDS applied to the (LVDS) signal inputs (rx1, rx2) into a corresponding output voltage at the signal output Dout, which corresponding output voltage serves as the data signal dout of the receiver circuit; this is particularly done in such a way that (only) when the voltage level exceeds a (positive) first switching voltage threshold value (different from zero), for example a (positive) input voltage uLVDS (uLVDS +uLVDS) not less than +5 mV (millivolts), the output voltage assumes a (positive) first voltage level, in particular different from zero and / or not less than +500 mV, or has (continues to have) the first voltage level when the voltage level is higher than the same switching voltage threshold value. Advantageously, the receiver circuit PHY-R can also be configured in such a way that its above-mentioned switching voltage threshold value is not less than +5 mV, for example, also greater than +7 mV and / or less than +200 mV. Additionally, the receiver circuit PHY-R is also (in its first operating mode R-I) configured to convert the input voltage uLVDS into the above-mentioned output voltage (dout) such that (only) when the voltage level drops below a second switching voltage threshold value (different from the above-mentioned first switching voltage threshold value and different from zero) of the (negative) input voltage uLVDS (uLVDS When in the -uLVDS mode, the output voltage is assumed to deviate from the first voltage level of the output voltage. For example, it is zero or also different from zero (negative), or has a second voltage level if the voltage level is lower than the second switching current threshold value. Thus, the above-mentioned second switching voltage threshold value can be lower than the above-mentioned first switching voltage threshold value. Advantageously, the receiver circuit PHY-R can also be configured in such a way that its second switching voltage threshold value does not exceed -5 mV, for example, is less than -7 mV and / or greater than -200 mV. In addition, the receiver circuit PHY-R can also be configured in such a way that the first and second switching voltage threshold values (representing different polarities of the input voltage uLVDS) have different signs from each other. For example, in such a way that the first switching voltage threshold value has a positive sign (+) and the second switching voltage threshold value has a negative sign (-); thus, the first switching voltage threshold value is correspondingly higher than zero, and the second switching voltage threshold value is also correspondingly lower than zero, especially in a way that the first and second switching voltage threshold values are equal in magnitude.

[0058] According to another embodiment of the present invention, the receiver circuit PHY-R is also configured in the second operating mode not to convert the differential (LVDS) voltage signal at the (LVDS) signal input part (rx1, rx2), such as an ANSI / TIA / EIA-644-1995 (LVDS) compatible voltage signal, into a data signal at the data output part Dout, or is configured not to output a data signal at the data output part Dout in the second operating mode.

[0059] To select the above-mentioned first and second operating modes (T-I, T-II), the transmitter circuit PHY-T can have a (first) control input DE for a value-discrete (e.g., binary) (operating mode) selection signal. In addition, the receiver circuit PHY-R can also have a control input RE for a discrete-value (e.g., binary) (operating mode) selection signal, which is useful for selecting its previously specified first and second operating modes (R-I, R-II).

[0060] To connect the first and second resistance elements R1, R2 in the above-mentioned way, according to Figure 4 、 Figure 5 and Figure 6 Another embodiment of the present invention schematically shown in, the transmitter circuit PHY-T includes an (H-) bridge circuit formed by means of a first (semiconductor) switch T1, a second (semiconductor) switch T2, a third (semiconductor) switch T3, and a fourth (semiconductor) switch T4. According to another embodiment of the present invention, each of the first, second, third, and fourth (semiconductor) switches has at least one control terminal. As Figure 4 、 Figure 5 or Figure 6As schematically shown, the power input of the bridge circuit is electrically connected to a current source, and the bridge arms of the bridge circuit are electrically connected to the first and second connection poles of the (LVDS) signal output section (tx1, tx2); this particularly enables the series circuit of the first and second switches and the series circuit of the third and fourth switches to be electrically connected in parallel, or the first and fourth switches to be electrically connected to the first (current source) pole (+), and the second and third switches to be electrically connected to the second (current source pole (-). In particular, the transmitter circuit (PHY-T) is also configured in a first operating mode such that when the data signal at the data input section Din has a first signal state (high) corresponding to, for example, logic one (..1..), also as Figure 4 shown in, close or keep closed the first switch T1 and the third switch T3 (which are diagonally opposite each other), and open the second switch T2 and the fourth switch T4 (which are diagonally opposite each other), and also as Figure 5As shown in; when the data signal at the data input section Din has a second signal state (low), for example corresponding to logic zero, which is different from the first signal state (high), the first switch T1 and the third switch T3 are turned off or kept off, and the second and fourth switches (of the bridge circuit) are turned on or kept on. Further, the transmitter circuit PHY-T in the first operation mode is configured such that when the data signal at the data input section Din has a signal edge that transitions from the above-mentioned first signal state (high) to the second signal state (low), the first switch T1 and the third switch T3 are turned off or kept off, and correspondingly the second switch T2 and the fourth switch T4 are turned on or kept on; or when the data signal at the data input section Din has a signal edge that transitions from the second signal state (low) to the first signal state (high), the first switch T1 and the third switch T3 are turned on or kept on, and the second switch T2 and the fourth switch T4 are turned off or kept off. To control the bridge circuit, the transmitter circuit PHY-T according to another embodiment of the present invention includes (hardware) control logic (LOGIC) having first, second, third, and fourth control output sections for controlling the first, second, third, and fourth (semiconductor) switches. The control logic is also specifically designed such that in the first operation mode of the transmitter circuit PHY-T, when there is a data signal having the above-mentioned first signal state at the data input section Din, the first switch and the third switch are turned on or kept on, and the second switch and the fourth switch are turned off or kept off. Further, the control logic is also designed such that when there is a data signal having the above-mentioned second signal state at the data input section Din, the first switch and the third switch are turned off or kept off, and the second switch and the fourth switch are turned on or kept on. For this purpose, according to a further embodiment, each of the first, second, third, and fourth control output sections (of the control logic) is (exactly) electrically connected to a respective control terminal of one of the first, second, third, and fourth (semiconductor) switches, and vice versa. Alternatively or additionally, the control logic further includes a first control input section and a second control input section, wherein the first control input section forms the above-mentioned (first) control input section DE of the transmit / receive circuit PHY, and the second control input section forms or is electrically coupled to the data input section Din of the transmitter circuit PHY-T.

Claims

1. A transmit / receive circuit (transceiver) for (data) signal transmission, in particular compatible with ANSI / TIA / EIA-644-1995 (LVDS), said transmit / receive circuit comprising the following: - A receiver circuit (PHY-R), said receiver circuit -- Having a (LVDS) signal input section (rx1, rx2) for a differential (LVDS) voltage signal, in particular compatible with ANSI / TIA / EIA-644-1995 (LVDS), said (LVDS) signal input section having an input resistance of greater than 1 MΩ (megohm) in particular, -- And having a data output section (Dout) for a data signal, in particular compatible with ANSI / TIA / EIA-485 (UART) and / or binary; - A transmitter circuit (PHY-T), said transmitter circuit -- Having a particularly controllable electronic (DC) current source with a (positive) first electrical (current source) pole (+) and a (negative) second electrical (current source) pole (-), -- Having a data input section (Din) for a data signal, in particular compatible with ANSI / TIA / EIA-485 (UART) and / or binary (UART), -- And having a (LVDS) signal output section (tx1, tx2) for a differential (LVDS) voltage signal, in particular compatible with ANSI / TIA / EIA-644-1995 (LVDS), said (LVDS) signal output section having a first connection pole (tx1) and a second connection pole (tx2); - A first (two-pole) resistance element having an ohmic resistance of greater than 10 Ω (ohm) in particular; - A second (two-pole) resistance element having an ohmic resistance of greater than 10 Ω and / or the same ohmic resistance as said first resistance element; - And a connection device (for connecting a signal cable having a pair of signal conductors), said connection device having a first connection pole (tr1) and a second connection pole (tr2); - Among them, The first connection pole (tx1) of said transmitter circuit (PHY-T) is in particular permanently electrically connected to the first connection pole (tr1) of said connection device, the first resistance element being connected between the first connection pole of said transmitter circuit and the first connection pole of said connection device, and the second connection pole (tx2) of said transmitter circuit (PHY-T) is in particular permanently electrically connected to the second connection pole (tr2) of said connection device, the second resistance element being connected between the second connection pole of said transmitter circuit and the second connection pole of said connection device; - And wherein said transmitter circuit (PHY-T) has at least two operating modes (T-I, T-II), in particular each operating mode being selectable or activatable by means of at least one value-discrete selection signal at a control input of said transmitter circuit (PHY-T), such that -- The transmitter circuit (PHY-T) is configured in a first operating mode (T-I transmission mode) to convert a data signal that is particularly ANSI / TIA / EIA-485 (UART) compatible and / or binary (UART) data signal, in particular a 1-bit data signal, at the data input section (Din) into a differential (LVDS) voltage signal that is particularly ANSI / TIA / EIA-644-1995 (LVDS) compatible at the (LVDS) signal output section, i.e., --- Electrically connect or keep interconnected the first (current source) pole (+) to one of the first connection pole (tx1) and the second connection pole (tx2) of the (LVDS) signal output section according to the signal state of the data signal (at the data input section), and complementarily electrically connect or keep interconnected the second (current source) pole (-) to the other of the first connection pole (tx1) and the second connection pole (tx2). --- Alternatively, according to the signal edge of the data signal (at the data input section) that mediates between two signal states of the data signal, exchange the electrical connections established between the first (current source) pole and the second (current source) pole and different ones of the first connection pole (tx1) and the second connection pole (tx2) of the (LVDS) signal output section. -- and the transmitter circuit (PHY-T) is configured in a second operating mode (T-II termination operation) to electrically short-circuit or keep short-circuited the first connection pole (tx1) and the second connection pole (tx2) of the (LVDS) signal output section, in particular such that the first resistance element and the second resistance element are electrically connected in series.

2. The transmit / receive circuit according to any one of the preceding claims. - Among them, The transmitter circuit (PHY-T) is configured in the first operating mode to electrically connect or keep electrically connected in series the current source with the first resistor element and the second resistor element; and / or - Wherein, when the transmitter circuit (PHY-T) operates in the first operating mode, each of the first resistor element and the second resistor element forms a series resistor of the transmitter circuit (PHY-T) between the current source and the corresponding connection pole (tx1, tx2) of the (LVDS) signal output section, in particular a series resistor that limits the (nominal) short-circuit current.

3. The transmit / receive circuit according to any one of the preceding claims. - Among them, The transmitter circuit (PHY-T) is configured in the second operating mode to electrically isolate or keep electrically isolated the current source from at least one of the first terminal pole (tx1) and the second terminal pole (tx2) of the (LVDS) signal output section; and / or - Wherein, the transmitter circuit (PHY-T) is configured in the second operating mode to electrically separate or keep electrically separated the (LVDS) signal output section from at least one of the first (current source) pole (+) and the second (current source) pole (-).

4. The transmit / receive circuit according to any one of the preceding claims, wherein, The transmitter circuit (PHY-T) is configured in the second operating mode to electrically connect or keep electrically connected in series the first resistor element and the second resistor element.

5. The transmit / receive circuit according to any one of the preceding claims. - Wherein, the receiver circuit (PHY-R) has at least two operating modes (R-I, R-II), in particular each operating mode can be selected or activated by means of a value-discrete selection signal at the control input section of the receiver circuit (PHY-R), such that -- The receiver circuit (PHY-R) is configured in a first operating mode (R-I receive mode) to convert an ANSI / TIA / EIA-644-1995 (LVDS)-compatible differential (LVDS) voltage signal at the (LVDS) signal input section (rx1, rx2) into a data signal that is particularly ANSI / TIA / EIA-485 (UART)-compatible and / or binary (UART), in particular a 1-bit data signal, at the data output section (Dout). -- And the receiver circuit (PHY-R) is configured in a second operating mode not to convert a differential (LVDS) voltage signal, which is in particular ANSI / TIA / EIA-644-1995 (LVDS) compatible, at the (LVDS) signal input section (rx1, rx2) into a data signal at the data output section (Dout), or not to output a data signal at the data output section (Dout).

6. The transmitting / receiving circuit according to any one of the preceding claims, wherein, The (LVDS) signal input section (rx1, rx2) of the receiver circuit (PHY-R) has a first connection pole (rx1) and a second connection pole (rx2).

7. The transmit / receive circuit according to any one of the preceding claims, further comprising: - A third (two-pole) resistance element, which in particular has an ohmic resistance greater than 100 Ω; And - A fourth (two-pole) resistance element, which in particular has an ohmic resistance greater than 100 Ω and / or the same ohmic resistance as the third resistance element.

8. The transmit / receive circuit according to claims 6 and 7, wherein, The third resistance element electrically connects the first connection pole (rx1) of the receiver circuit (PHY-R) to the first connection pole (tr1) of the connection device, and the fourth resistance element electrically connects the second connection pole (rx2) of the receiver circuit (PHY-R) to the second connection pole (tr2) of the connection device, in particular permanently.

9. The transmit / receive circuit according to any one of the preceding claims, - Among them, The transmitter circuit (PHY-T) is designed as a component of an integrated circuit, in particular an application-specific integrated circuit (ASIC); and / or - Wherein, the receiver circuit (PHY-R) is designed as a component of an integrated circuit, in particular an application-specific integrated circuit (ASIC); and / or - Wherein, the transmitter circuit (PHY-T) and the receiver circuit (PHY-R) are part of the same - in particular dedicated - integrated circuit.

10. The transmit / receive circuit according to any one of the preceding claims, wherein, The transmitter circuit (PHY-T) has an (H-) bridge circuit formed by means of a first (semiconductor) switch (T1), a second (semiconductor) switch (T2), a third (semiconductor) switch (T3) and a fourth (semiconductor) switch (T4), the power input section of the bridge circuit is electrically connected to the current source, and the bridge branches of the bridge circuit are electrically connected to the first connection pole (tx1) and the second connection pole (tx2), in particular such that the series circuit of the first switch and the second switch is electrically connected in parallel with the series circuit of the third switch and the fourth switch, and / or such that the first switch and the fourth switch are electrically connected to the first (current source) pole (+), and the second switch and the third switch are electrically connected to the second (current source) pole (-).

11. The transmit / receive circuit according to claim 10, - Among them, The transmitter circuit (PHY-T) is configured in the first operating mode to close or keep closed the first switch and the third switch (of the bridge circuit) and to open or keep open the second switch and the fourth switch (of the bridge circuit) if the data signal at the data input (Din) has a first signal state corresponding in particular to logic one; - and wherein the transmitter circuit (PHY-T) is configured in the first operating mode to open or keep open the first switch and the third switch (of the bridge circuit) and to close or keep closed the second switch and the fourth switch (of the bridge circuit) if the data signal at the data input (Din) has a second signal state different from the first signal state (high) corresponding in particular to logic zero.

12. The transmit / receive circuit according to the preceding claim, - Among them, The transmitter circuit (PHY-T) is configured in the first operating mode to open and keep open the first switch and the third switch (of the bridge circuit) and to close and keep closed the second switch and the fourth switch (of the bridge circuit) if the data signal at the data input (Din) has a signal edge transitioning from the first signal state (high) to the second signal state; - and wherein the transmitter circuit (PHY-T) is configured in the first operating mode to close or keep closed the first switch and the third switch (of the bridge circuit) and to open or keep open the second switch and the fourth switch (of the bridge circuit) if the data signal at the data input (Din) has a signal edge transitioning from the second signal state (low) to the first signal state.

13. The transmit / receive circuit according to any one of claims 10 to 12, wherein, The transmitter circuit (PHY-T) comprises (hardware) control logic having first, second, third, and fourth control outputs for respectively controlling the first (semiconductor) switch, the second (semiconductor) switch, the third (semiconductor) switch, and the fourth (semiconductor) switch of the (H-) bridge circuit.

14. The transmit / receive circuit according to the preceding claim, - Among them, The control logic is configured in the first operating mode of the transmitter circuit (PHY-T) to close or keep closed the first switch and the third switch and to open or keep open the second switch and the fourth switch if the data signal at the data input (Din) has a first signal state corresponding in particular to logic one; - And wherein, in the first operating mode of the transmitter circuit (PHY-T), the control logic is configured to open or keep open the first switch and the third switch and to close or keep closed the second switch and the fourth switch if the data signal at the data input (Din) has a second signal state different from the first signal state, in particular corresponding to logic zero.

15. The transmit / receive circuit according to claim 13 or 14, - Among them, each of the first (semiconductor) switch, the second (semiconductor) switch, the third (semiconductor) switch and the fourth (semiconductor) switch has a control terminal, and each of the first control output, the second control output, the third control output and the fourth control output is (exactly) electrically connected to a control terminal associated with one of the first to fourth (semiconductor) switches, and vice versa; and / or - wherein the control logic has a first control input (DE) and a second control input, in particular such that the first control input (DE) forms or is electrically coupled to the control input of the transmit / receive circuit, and / or the second control input forms or is electrically coupled to the data input (Din) of the transmitter circuit (PHY-T).

16. The transmit / receive circuit according to the previous claim, wherein, The first operating mode (T-I) and the second operating mode (T-II) of the transmitter circuit (PHY-T) can each be selected or activated by means of at least one value-discrete - in particular binary - selection signal at the control input of the transmitter circuit (PHY-T), in particular such that the first operating mode is selected or activated by means of a first signal state (de 1), and the second operating mode is selected or activated by means of a second signal state (de 0).

17. A signal transmission system, in particular a (serial) signal transmission system for the two-way (point-to-point) transmission of digital (payload) data, comprising: At least one transmit / receive circuit (PHY) according to any one of the preceding claims.

18. The signal transmission system according to the previous claim, further comprising: - an additional transmit / receive circuit (PHY'), in particular a transmit / receive circuit of the same type or structure as the transmit / receive circuit PHY and / or configured for signal transmission according to ANSI / TIA / EIA-644-1995, - and a signal cable (STP) having at least one pair of signal conductors, in particular having the same and / or exactly the same electrical properties and / or being stranded together.

19. The signal transmission system according to the previous claim, - wherein the two transmit / receive circuits (PHY, PHY') are electrically connected via the signal cable (STP) to form a current loop; and / or - Among them, the signal cable has a (transmission) length greater than 20 m (meters), in particular greater than 50 m; and / or - wherein the signal cable has a wave impedance (line characteristic impedance) of not less than 20 Ω and in particular not exceeding 500 Ω.

Images