Active clamping circuit and semiconductor device

Abstract

An active clamp circuit (10) is provided with: a clamp voltage control switch (20), the first main electrode of which is electrically connected to the main electrode of a main switch (Q1) and the second main electrode of which is electrically connected to the control electrode of the main switch (Q1); and a clamp voltage determination unit (30), one terminal of which is electrically connected to the first main electrode of the clamp voltage control switch (20) and the other terminal of which is electrically connected to the control electrode of the clamp voltage control switch (20), the clamp voltage determination unit (30) having a plurality of groups (31) comprising a temperature characteristic adjustment resistor (32), a Zener diode (33), and a diode (34). The plurality of groups 31 are connected in series. According to the active clamp circuit of the present invention, the surge voltage can be absorbed and the voltage can be clamped without using a large diode, and the operation of the switching circuit can be more stable.

Description

Technical Field

[0001] The present invention relates to an active clamp circuit and a semiconductor device. Background Art

[0002] Conventionally, in a switching circuit (especially a high-frequency switching circuit), a surge voltage is generated during switching due to the parasitic inductance of the wiring. To prevent problems such as damage to the main switch caused by this surge voltage, various countermeasures have been taken in the past.

[0003] Figure 11 It is a circuit diagram of a first switching circuit 800 as a prior art. In Figure 11 it, the symbol Vcc represents an external power supply, the symbol C represents an input capacitor, the symbols T1, T2, T3 represent output terminals, and the symbols VBH, VBL represent terminals for sending signals for turning on / off the main switches Q1, Q2 to the gate electrodes G1, G2 of the main switches Q1, Q2.

[0004] In the conventional first switching circuit 800, when it is desired to clamp the surge voltage during switching, it is necessary to add a clamp circuit 810. This clamp circuit 810 needs to connect clamping diodes 812, 814 having a breakdown voltage slightly lower than or substantially equal to the breakdown voltages of Q1, Q2 in parallel to the first main switch Q1 and the second main switch Q2, respectively. The anode of the clamping diode 812 is connected to the connection point of the first main switch Q1 and the second main switch Q2, and the cathode of the clamping diode 812 is connected to the drain electrode D1 of the first main switch Q1. The anode of the clamping diode 814 is connected to the source electrode S2 of the second main switch Q2, and the cathode of the clamping diode 814 is connected to the connection point of the first main switch Q1 and the second main switch Q2.

[0005] According to the conventional first switching circuit 800, since it has the clamping diodes 812, 814, the clamping diodes 812, 814 can be used to absorb the surge voltage and clamp the drain-source voltage of the first main switch Q1 and the second main switch Q2.

[0006]

Prior Art Documents

[0007]

Patent Document 1

[0008] However, in the conventional first switching circuit 800, since the current flowing through the main switches Q1 and Q2 is bypassed to the clamping circuit 810 to clamp the drain-source voltage, the current flowing through the clamping circuit 810 increases. Therefore, it is necessary to use clamping diodes 812 and 814 of the clamping circuit 810 that can withstand large currents, that is, large diodes are required. In addition, since a large current flows through the clamping diodes 812 and 814, the variation of the clamping voltage caused by the operating resistance (impedance) of the clamping diodes 812 and 814 (refer to Figure 6 the dotted line) becomes large, the temperature rise of the clamping diodes 812 and 814 becomes large, and the variation of the clamping voltage becomes large. Therefore, there is also a problem that the function of clamping the surge voltage cannot operate as intended, and ultimately the operation of the switching circuit becomes unstable. Therefore, a conventional second switching circuit 900 in which an active clamping circuit 910 is provided between the drain electrodes D1 and D2 and the gate electrodes G1 and G2 of the main switches Q1 and Q2 is conventionally known (refer to Figure 12 (a). For example, refer to Patent Document 1).

[0009] Figure 12 FIG. is a circuit diagram showing the conventional second switching circuit 900. In the second switching circuit 900, the active clamping circuit 910 includes a plurality of groups 941 in which a Zener diode 943 and a diode 944 are connected with opposite characteristics (see Figure 12 (b)).

[0010] In the conventional second switching circuit 900, when the drain-source voltage of the main switch Q1 (Q2) is greater than the sum of the Zener voltage of the Zener diode 943, the forward voltage VF of the diode 944, and the threshold voltage VTH of the gate electrode G1 (G2) of the main switch Q1 (Q2), the feedback capacitance of the main switch Q1 (Q2) is charged, and the main switch Q1 (Q2) that is turned off at the timing when the drain-source voltage starts to increase is turned on again. Therefore, the main switch Q1 (Q2) flows a drain current in a state where the drain-source voltage is applied, and thus the surge voltage can be absorbed in a state where the current flowing into the clamping circuit is smaller than that of the conventional first switching circuit 800.

[0011] However, in technical fields such as inverter circuits and power supplies, there is a need for an active clamping circuit that can further reduce the current flowing through the clamping diode and make the operation of the switching circuit more stable.

[0012] Therefore, the present invention has been made in view of the above circumstances, and an object thereof is to provide an active clamping circuit and a semiconductor device that can clamp the voltage by absorbing the surge voltage without using a large diode and can make the operation of the switching circuit more stable. Summary of the Invention

[0013] The first active clamping circuit of the present invention is connected between the control electrode and the main electrode of the main switch and is used to control the clamping voltage of the main switch. It is characterized by including: a switch for controlling the clamping voltage, which has a first main electrode, a second main electrode, and a control electrode. The second main electrode is electrically connected to the main electrode of the main switch, and the first main electrode is electrically connected to the control electrode of the main switch; and a clamping voltage determining section, one end of which is electrically connected to the second main electrode of the switch for controlling the clamping voltage, and the other end of which is electrically connected to the control electrode of the switch for controlling the clamping voltage. Among them, the clamping voltage determining section has a plurality of groups composed of a temperature characteristic adjusting resistor, a Zener diode connected to one end of the temperature characteristic adjusting resistor, and a diode connected to the other end of the temperature characteristic adjusting resistor in a manner opposite to the characteristic of the Zener diode, and the groups are connected in series.

[0014] The second active clamping circuit of the present invention is connected between the control electrode and the main electrode of the main switch and is used to control the clamping voltage of the main switch. It is characterized by including: a bypass diode, which has an anode and a cathode. The anode is electrically connected to the control electrode of the main switch, and the cathode is electrically connected to the main electrode of the main switch; and a clamping voltage determining section, one terminal of which is electrically connected to the cathode of the bypass diode, and the other terminal of which is electrically connected to the anode of the bypass diode and the control electrode of the main switch. Among them, the clamping voltage determining section has a plurality of groups composed of a temperature characteristic adjusting resistor, a Zener diode connected to one end of the temperature characteristic adjusting resistor, and a diode connected to the other end of the temperature characteristic adjusting resistor in a manner opposite to the characteristic of the Zener diode, and the groups are connected in series.

[0015] The first semiconductor device of the present invention is connected between the control electrode and the main electrode of a main switch, and constitutes an active clamping circuit for controlling the clamping voltage of the main switch. It is formed on a semiconductor substrate that defines a device region and a breakdown voltage isolation region formed around the device region. It is characterized in that: in the device region, it includes: the semiconductor substrate; a first main electrode formed on the surface on the surface side of the semiconductor substrate; a gate pad formed on the surface on the surface side of the semiconductor substrate at a position separated from the first main electrode; and a second main electrode formed on the surface on the back side of the semiconductor substrate. Among them, a MOS structure is formed in the region where the first main electrode is formed. In the breakdown voltage isolation region, it includes: the semiconductor substrate; the second main electrode formed on the surface on the back side of the semiconductor substrate; an insulating film formed on the surface of the semiconductor substrate; and a clamping voltage determination part. On the insulating film, in a region surrounding the device region in a top view, a plurality of first first conductivity type regions and a plurality of first second conductivity type regions are adjacent to each other and alternately arranged, one end of which is electrically connected to the gate pad and the other end is electrically connected to the second main electrode. Among them, in the clamping voltage determination part, the total amount of impurities in the first first conductivity type region sandwiched between two of the first second conductivity type regions is less than the total amount of impurities in any one of the two first second conductivity type regions adjacent to the first first conductivity type region.

[0016] The second semiconductor device of the present invention is connected between the control electrode and the main electrode of a main switch, and constitutes an active clamping circuit for controlling the clamping voltage of the main switch. It is formed on a semiconductor substrate that defines a device region and a breakdown voltage isolation region formed around the device region. It is characterized in that: in the device region, it includes: the semiconductor substrate; a first main electrode formed on the surface on the surface side of the semiconductor substrate; and a second main electrode formed on the surface on the back side of the semiconductor substrate. Among them, a diode structure is formed in the region where the first main electrode is formed. In the breakdown voltage isolation region, it includes: the semiconductor substrate; the second main electrode formed on the surface on the back side of the semiconductor substrate; an insulating film formed on the surface of the semiconductor substrate; and a clamping voltage determination part. On the insulating film, in a region surrounding the device region in a top view, a plurality of first first conductivity type regions and a plurality of first second conductivity type regions are adjacent to each other and alternately arranged, one end of which is electrically connected to the first main electrode and the other end is electrically connected to the second main electrode. Among them, in the clamping voltage determination part, the total amount of impurities in the first first conductivity type region sandwiched between two of the first second conductivity type regions is less than the total amount of impurities in any one of the two first second conductivity type regions adjacent to the first first conductivity type region.

[0017] Advantages of the Invention

[0018] According to the first active clamping circuit of the present invention, since it includes a clamping voltage control switch and a clamping voltage determination unit having one terminal electrically connected to the second main electrode and the other terminal electrically connected to the control electrode, like the conventional switching circuit, it can absorb the surge voltage. In addition, the clamping voltage control switch functions as a driver for sending a conduction signal to the control electrode of the main switch. Therefore, the drive current is small, and the current flowing through the clamping voltage determination unit that determines the trigger cut-off voltage can be reduced. Since the main switch can be used as a current path for voltage clamping during the period when the clamping voltage control switch or the main switch is turned on and a surge voltage is generated, a large diode does not need to be used.

[0019] According to the second active clamping circuit of the present invention, since it includes a bypass diode and a clamping voltage determination unit having one terminal electrically connected to the cathode of the bypass diode and the other terminal electrically connected to the anode of the bypass diode and the control electrode of the main switch, like the conventional switching circuit, it can absorb the surge voltage and clamp the voltage. In addition, in addition to reducing the current flowing through the clamping voltage determination unit, during the period when the main switch is turned on and a surge is generated, the main switch can be used as a current path for voltage clamping, so that a large diode does not need to be used.

[0020] In addition, according to the first and second active clamping circuits of the present invention, since they include a clamping voltage control switch or a bypass diode and a clamping voltage determination unit, as described above, the current flowing through the clamping circuit becomes smaller, and the operating resistance (impedance) of the Zener diode also becomes smaller. Therefore, the variation of the clamping voltage caused by the operating resistance (impedance) of the Zener diode (refer to the dotted line in Figure 6 ) also becomes smaller. In addition, since the current flowing through the clamping circuit becomes smaller, the temperature rise of the Zener diode becomes smaller, and the variation of the clamping voltage can be reduced. Therefore, the function of clamping the surge voltage can be made to operate according to the set target, thereby stabilizing the operation of the switching circuit.

[0021] According to the first and second active clamping circuits of the present invention, since the clamping voltage determination unit has a temperature characteristic adjustment resistor, the influence of the temperature characteristic of the forward voltage of the diode (the characteristic of decreasing with temperature rise) can be offset by the temperature characteristic of the temperature characteristic adjustment resistor (the characteristic of increasing with temperature rise), thereby suppressing the temperature variation of the clamping voltage.

[0022] According to the first semiconductor device of the present invention, since a MOS structure is formed in the region where the first main electrode is formed, and in the breakdown voltage isolation region, a clamping voltage determination unit is provided in which a plurality of first regions of a first conductivity type and a plurality of first regions of a second conductivity type are adjacent to each other and alternately arranged, it is possible to configure an active clamping circuit including a clamping voltage control switch; and a clamping voltage determination unit, one terminal of which is electrically connected to the first main electrode of the clamping voltage control switch, and the other terminal of which is electrically connected to the control electrode of the clamping voltage control switch. Therefore, like the first active clamping circuit, it is possible to absorb a surge voltage. In addition, since this clamping voltage control switch (MOS structure) has a function as a driver that sends a conduction signal to the control electrode of the main switch, the drive current is small, and the current flowing through the clamping voltage determination unit that determines the trigger cutoff voltage can be reduced. Since the main switch can be used as a current path for voltage clamping during the period when the clamping voltage control switch or the main switch is turned on and a surge voltage is generated, a large-sized diode does not need to be used.

[0023] According to the second semiconductor device of the present invention, since a diode structure is formed in the region where the first main electrode is formed, and it includes a clamping voltage determination unit in which a plurality of first regions of a first conductivity type and a plurality of first regions of a second conductivity type are adjacent to each other and alternately arranged, it is possible to configure an active clamping circuit including a bypass diode; and a clamping voltage determination unit, one terminal of which is electrically connected to the first main electrode of the bypass diode, and the other terminal of which is electrically connected to the second electrode of the bypass diode. Therefore, it is possible to absorb a surge voltage to clamp the voltage. In addition, since the current flowing into the clamping voltage determination unit can also be reduced, during the period when a surge is generated when the main switch is turned on, the main switch can be used as a current path for voltage clamping, and a large-sized diode does not need to be used.

[0024] According to the first and second semiconductor devices of the present invention, a MOS structure or a diode structure is formed in the region where the first main electrode is formed, and in the breakdown voltage isolation region, a clamping voltage determination unit is provided in which a plurality of first regions of a first conductivity type and a plurality of first regions of a second conductivity type are adjacent to each other and alternately arranged. Therefore, the current flowing through the active clamping circuit and the Zener diode becomes small, and thus the operating resistance (impedance) of the Zener diode becomes small, preventing fluctuations in the clamping voltage caused by the operating resistance (impedance) of the Zener diode (refer to the dashed line in Figure 6 . In addition, the temperature rise of the Zener diode becomes small, and fluctuations in the clamping voltage caused by the temperature rise of the Zener diode can be reduced. Therefore, the function of clamping the surge voltage can be made to operate as desired, and the operation of the switching circuit can be stabilized.

[0025] In the first and second semiconductor devices according to the present invention, in the clamping voltage determination section, the total amount of impurities in the first first conductivity type region sandwiched between two first second conductivity type regions is less than the total amount of impurities in the two first second conductivity type regions adjacent to the first first conductivity type region. Therefore, the internal resistance of the first first conductivity type region can be made larger than that of the first second conductivity type region, and thus the internal resistance of the first first conductivity type region can be used as the temperature characteristic adjustment resistance of the clamping voltage determination section. Therefore, the influence of the temperature characteristic (the characteristic of decreasing with temperature rise) of the forward voltage of the diode formed between the first first conductivity type region and the first second conductivity type region can be offset by the temperature characteristic (the characteristic of increasing with temperature rise) of the internal resistance of the first first conductivity type region, thereby suppressing the temperature change of the clamping voltage. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 It is a circuit diagram showing the switch circuit 1 and the active clamping circuit 10 in Embodiment 1.

[0027] Figure 2 It is a graph and a curve diagram showing the temperature characteristics of the resistance value of the temperature characteristic adjustment resistance 32, the forward voltage of the diode 34, the Zener voltage of the Zener diode 33, and the clamping voltage of the active clamping circuit 10 in Embodiment 1.

[0028] Figure 3 It is a plan view for explaining the semiconductor device 100 according to Embodiment 1.

[0029] Figure 4 It is Figure 3 The cross-sectional view taken along line A-A of

[0030] Figure 5 It is Figure 3 The cross-sectional view taken along line B-B of

[0031] Figure 6 It is a schematic diagram showing the relationship between the clamping voltage of the active clamping circuit and the current of the diode.

[0032] Figure 7 It is a circuit diagram of the active clamping circuit 10a according to Embodiment 2.

[0033] Figure 8 It is a plan view of the semiconductor device 200 according to Embodiment 2.

[0034] Figure 9 It is a cross-sectional view of the semiconductor device 200 according to Embodiment 2.

[0035] Figure 10 It is a diagram for explaining the active clamping circuit 10b and the semiconductor device 101 according to Embodiment 3.

[0036] Figure 11 is the circuit diagram of the first switching circuit 800 of the prior art.

[0037] Figure 12 is the circuit diagram of the second switching circuit 900 of the prior art. Detailed Embodiments

[0038] Hereinafter, the active clamp circuit and the semiconductor device of the present invention will be described based on the embodiments shown in the drawings. The embodiments described below do not limit the invention of the appended claims. In addition, all combinations of the elements described in the embodiments are not necessarily required for the solution means of the present invention.

[0039] [Embodiment 1]

[0040] 1. Structure of the switching circuit 1 in Embodiment 1

[0041] Figure 1 is the circuit diagram showing the switching circuit 1 and the active clamp circuit 10 in Embodiment 1. Among them, Figure 1 (a) is the circuit diagram showing the switching circuit 1, Figure 1 (b) is the circuit diagram showing the active clamp circuit 10. The symbol 50 represents a pull-down resistor, the symbol Vcc represents an external power supply, the symbols T1, T2, and T3 represent output terminals, and the symbols VBH and VBL represent terminals for sending signals for turning on / off the main switches Q1 and Q2 to the gates G1 and G2.

[0042] The switching circuit 1 according to Embodiment 1 is as Figure 1 (a) shows, and includes a high-side first main switch Q1, a low-side second main switch Q2 connected in series with the first main switch Q1, an input capacitor C, and two active clamp circuits 10. As the main switches Q1 and Q2, appropriate transistors such as MOSFETs and IGBTs can be used. The source electrode S1 of the first main switch Q1 is connected to the drain electrode D2 of the second main switch Q2, and the drain electrode D1 of the first main switch Q1 is connected to the external power supply Vcc. The source electrode S2 of the second main switch Q2 is connected to the reference potential.

[0043] 2. Configuration of the active clamp circuit 10 in Embodiment 1

[0044] The two active clamp circuits 10 are respectively connected at one end to the drain electrodes D1 and D2 of the main switches Q1 and Q2, and at the other end to the gate electrodes G1 and G2 of the main switches Q1 and Q2. In addition, since the two active clamp circuits 10 have the same characteristics, hereinafter, the active clamp circuit 10 connected to the first main switch Q1 will be described, and the description of the active clamp circuit 10 connected to the second main switch Q2 will be omitted.

[0045] The active clamping circuit 10 clamps the voltage across the drain and source of the first main switch Q1. As Figure 1 (b) shows, the active clamping circuit 10 includes a clamping voltage control switch 20, a clamping voltage determination unit 30, and a gate protection unit 40.

[0046] The clamping voltage control switch 20 is a switching element having three terminals: a drain electrode D3 (first main electrode), a source electrode S3 (second main electrode), and a gate electrode G3 (control electrode). In Embodiment 1, although a MOSFET is used, an IGBT can also be used, or other suitable switching elements can be used. In the clamping voltage control switch 20, the drain electrode D3 is electrically connected to the external power supply Vcc and the drain electrode D1 of the first main switch Q1, and the source electrode S3 is electrically connected to the gate electrode G1 of the first main switch Q1.

[0047] One terminal of the clamping voltage determination unit 30 is electrically connected to the drain electrode D3 of the clamping voltage control switch 20, the external power supply Vcc, and the drain electrode D1 of the first main switch Q1, and the other terminal is electrically connected to the gate electrode G3 of the clamping voltage control switch 20. The clamping voltage determination unit 30 has a plurality of groups 31, and each group 31 is composed of a temperature characteristic adjustment resistor 32, a Zener diode 33 connected to one end of the temperature characteristic adjustment resistor 32, and a diode 34 connected to the other end of the temperature characteristic adjustment resistor 32 in a manner opposite to the characteristic of the Zener diode 33, and the groups 31 are connected in series with the Zener diode 33 on the side of the drain electrode D3.

[0048] The structures within the plurality of (multistage) groups 31 that make up the clamping voltage determination unit 30 are respectively: combining a temperature characteristic adjustment resistor 32 whose resistance (voltage drop caused by the resistor) has a positive correlation with temperature rise, a diode 34 whose forward voltage has a negative correlation with temperature rise, and a Zener diode 33 whose Zener voltage has a positive or negative correlation with temperature rise, and adjusting the temperature coefficient of the voltage applied to the group 31, so that the temperature characteristic of the group 31 is substantially constant with respect to temperature rise (refer to Figure 2 described later). In other words, the temperature characteristic adjustment resistor 32 has a temperature characteristic of reducing the temperature change of the superimposed voltage obtained by superimposing the Zener voltage of the Zener diode 33 of the group 31 having the temperature characteristic adjustment resistor 32 and the forward voltage of the diode 34.

[0049] One end of the gate protection unit 40 is connected to the gate electrode G3 of the clamping voltage control switch 20, and the other end is connected to the source electrode S3 of the clamping voltage control switch 20 and the gate electrode G1 of the main switch Q1. The gate protection unit 40 includes a plurality of groups 41. Each group 41 is composed of a temperature characteristic adjustment resistor 42 for gate protection, a Zener diode 43 for gate protection connected to one end of the temperature characteristic adjustment resistor 42 for gate protection, and a diode 44 for gate protection connected to the other end of the temperature characteristic adjustment resistor 42 for gate protection with a characteristic opposite to that of the Zener diode 43 for gate protection, and they are connected in series with the Zener diode 43 for gate protection located on the side of the gate electrode G3. The gate protection unit 40 connects the groups 41 in series in a necessary number of stages so that the voltage is greater than or equal to the gate oxide film at the gate drive voltage used and the gate insulating film will not be insulation-damaged (prevent the gate insulating film (refer to Figure 4 the symbol 122 in

[0050] from being electrostatically damaged).

[0051] The active clamping circuit 10 operates as follows. That is, regarding the drain-source voltage of the first main switch Q1, when the voltage set by the clamping voltage determination unit 30 is greater than or equal to "(Zener voltage of the Zener diode 33 + forward voltage VF of the diode 34 + voltage drop of the temperature characteristic adjustment resistor 32) × number of stages + threshold voltage of the clamping voltage control switch 20", the clamping voltage control switch 20 becomes conductive, and while starting to suppress the further rise of the voltage, the gate of the main switch Q1 is driven, and then the main switch Q1 also becomes conductive, thereby suppressing the rise of the drain voltage, that is, becoming a voltage clamping state.

[0052] 3. Regarding the temperature characteristic adjustment resistor 32 in Embodiment 1

[0053] Next, the temperature characteristic adjustment resistor 32 of the clamping voltage determination unit 30 will be described in detail. Figure 2 It is a diagram and a graph showing the temperature characteristics of the resistance value R of the temperature characteristic adjustment resistor 32, the forward voltage VF of the diode 34, the Zener voltage Vz of the Zener diode 33, and the clamping voltage of the active clamping circuit 10 in Embodiment 1. Among them, Figure 2 (a) shows the temperature characteristic of the resistance value R of the temperature characteristic adjustment resistor 32, Figure 2 (b) shows the temperature characteristic of the forward voltage VF of the diode 34, Figure 2 (c) shows the temperature characteristic of the Zener voltage Vz of the Zener diode 33, Figure 2 (d) shows the temperature characteristic of the group 31 of the clamping voltage determination unit 30, Figure 2(e) represents the temperature characteristic of the clamping voltage of the clamping voltage determination unit 30.

[0054] Since the clamping voltage determination unit 30 is composed of a group 31 of temperature characteristic adjustment resistors 32, Zener diodes 33, and diodes 34 connected in series in multiple stages (refer to Figure 2 (d)), the clamping voltage is determined by superimposing the resistance value R (voltage drop caused by the resistance) of the temperature characteristic adjustment resistor 32, the forward voltage VF of the diode 34, and the Zener voltage Vz of the Zener diode 33. For this reason, the temperature characteristic of the clamping voltage is also affected by the temperature characteristics of the above three elements.

[0055] The temperature characteristic of the forward voltage VF of the diode 34 decreases to the right as the temperature increases (refer to Figure 2 (b)). Therefore, by making the temperature characteristic adjustment resistor 32 have a temperature characteristic that rises to the right as the temperature increases, it is possible to make it have a temperature characteristic that reduces the temperature change of the forward voltage of the diode 34. By doing so, the temperature change of the clamping voltage of the clamping voltage determination unit 30 can be reduced.

[0056] In addition, the temperature characteristic of the Zener voltage Vz of the Zener diode 33 varies according to the characteristics of the Zener diode (refer to Figure 2 (c)). Therefore, by using the temperature characteristic of the Zener voltage Vz of the Zener diode 33 to change the slope of the temperature characteristic adjustment resistor 32 with respect to temperature change, the temperature change of the clamping voltage of the clamping voltage determination unit 30 can be further reduced, so that the clamping voltage can be maintained approximately constant even at high temperatures (refer to Figure 2 (e)).

[0057] 4. Structure of the semiconductor device 100 in Embodiment 1

[0058] The device structure of the active clamping circuit 10 is described below. In the conventional first switching circuit 800 and the conventional second switching circuit 900, it was also considered to insert the clamping circuit and the main switch Q1 in one chip, but this would bring the disadvantage that the chip size of the main switch Q1 would increase accordingly. Therefore, in Embodiment 1, the active clamping circuit 10 is formed on a chip different from the main switch Q1 to prevent the chip size of the main switch Q1 from increasing.

[0059] Figure 3This is a plan view for explaining the semiconductor device 100 of Embodiment 1. The clamping voltage determination unit 180 has a structure in which a plurality of first N-type regions 182 and a plurality of first P-type regions 184 are adjacent to each other and arranged alternately. However, for simplicity of explanation, only the first P-type region 184 closest to the device region A1 side and the adjacent first N-type region 182, and only the first P-type region 184 closest to the device region A1 side and the adjacent first N-type region 182, as well as the first P-type region 184 and the adjacent first N-type region 182 located in the middle position are illustrated, and the other first P-type regions 184 and first N-type regions 182 are omitted from the illustration. Similarly, only two gates 120 are shown, and the illustration of other gates is omitted. In addition, in the source 130 and the gate pad 140, the pad portions for external connection are shown in white, and the other portions (polysilicon portions) are hatched. In addition, in Figure 3 the gate wiring appears as one line, but as Figure 4 shown, it is separated from the first gate wiring 145 and the second gate wiring 147.

[0060] Figure 4 is Figure 3 the A-A cross-sectional view of

[0061] As Figure 3 shown, the semiconductor device 100 of Embodiment 1 is formed in the semiconductor substrate 110. In the semiconductor substrate 110, a device region A1 formed in the central portion and a breakdown voltage isolation region A2 formed around the device region A1 are defined. And a switch 20 for clamping voltage control is formed in the device region A1, and a clamping voltage determination unit 30 is formed in the breakdown voltage isolation region A2. That is, the semiconductor device 100 of Embodiment 1 is connected between the gate electrode and the drain electrode of the main switches Q1 and Q2, constitutes an active clamping circuit 10 for controlling the clamping voltage of the main switches Q1 and Q2, and realizes the function as a device.

[0062] (1) Regarding the device region A1

[0063] A switch 20 for clamping voltage control is formed in the device region A1. The device region A1 is composed of an active region A11 (refer to Figure 4 ) in which a MOS structure is formed in the region overlapping with the source electrode 130, and a peripheral region A12 (refer to Figure 5 ) formed around the active region A11 and in which the gate pad 140, the first gate wiring 145, and the second gate wiring 147 are formed.

[0064] (1-1) Regarding the active region A11

[0065] In the active region A11 of the device region A1, as Figure 3 andFigure 4 As shown, the semiconductor device 100 of Embodiment 1 includes a semiconductor substrate 110, a gate electrode 120, a gate insulating film 122, an interlayer insulating film 124, a source electrode 130 (first main electrode), a drain electrode 150 (second main electrode), and a protective insulating film 160. The semiconductor device 100 of Embodiment 1 is a planar gate type MOSFET having a MOS structure with a gate electrode 120, a gate insulating film 122, and a semiconductor substrate 110 in a region of the source electrode 130 where a device region A1 is formed. Alternatively, a trench gate type MOSFET may be used instead of the planar gate type.

[0066] As Figure 4 shown, the semiconductor substrate 110 includes an N+-type low-resistance semiconductor layer 111, an N-type drift layer 112 formed above the low-resistance semiconductor layer 111, a P-type base region 113 formed in a predetermined region on the surface of the drift layer 112, and an N+-type source region 114 formed on a part of the surface of the base region 113 and separated from the drift layer 112. As the material of the semiconductor substrate 110, silicon can be used, but materials such as silicon carbide (SiC), gallium nitride (GaN), and gallium oxide (Ga2O3) that enable high-speed switching are also applicable.

[0067] The thickness of the low-resistance semiconductor layer 111 is, for example, in the range of 100 μm to 400 μm, and the impurity concentration of the low-resistance semiconductor layer 111 is, for example, in the range of 1×10 19 cm -3 to 1×10 20 cm -3 The thickness of the drift layer 112 is, for example, in the range of 5 μm to 120 μm. The impurity concentration of the drift layer 112 is, for example, in the range of 5×10 13 cm -3 to 1×10 16 cm -3 The depth position of the deepest part of the base region 113 is, for example, in the range of 0.5 μm to 4.0 μm, and the impurity concentration of the base region 113 is, for example, in the range of 5×10 16 cm -3 to 1×10 18 cm -3 The depth position of the deepest part of the source region 114 is, for example, in the range of 0.1 μm to 1.5 μm, and the impurity concentration of the source region 114 is, for example, in the range of 5×10 19 cm -3 to 2×10 20 cm -3 The range.

[0068] As Figure 4As shown in region A1 in [description], the gate electrode 120 is disposed on the semiconductor substrate 110 with the gate insulating film 122 interposed therebetween, and is opposed to the base region 113 sandwiched by the source region 114 and the drift layer 112 with the gate insulating film 122 interposed therebetween. As Figure 3 shown, the gate electrode 120 is arranged in a striped pattern on the semiconductor substrate 110 in a horizontal and vertical manner at a prescribed interval in a plan view, and both end portions thereof are connected to the first gate wiring 145 via a lead-out wiring 146 (refer to Figure 4 ).

[0069] An interlayer insulating film 124 is formed on the upper and side portions of the gate electrode 120, and insulates the gate electrode 120 from the source electrode 130. The interlayer insulating film 124 is formed of an insulating film such as a phosphorus oxide film or an oxide film containing phosphorus and boron having a thickness of 0.5 μm to 2.0 μm formed by CVD method, for example, but other appropriate insulating films may also be used.

[0070] The source electrode 130 is formed on the interlayer insulating film 124, and is connected to the source region 114 and the base region 113 on the surface of the semiconductor substrate 110 via contact grooves formed on the interlayer insulating film 124 or the like. The source 130 is made of, for example, an Al film or an Al alloy film (e.g., AlSi film), and the thickness of the source electrode 130 is 1 μm to 10 μm (e.g., 3 μm).

[0071] The drain electrode 150 is disposed on the entire surface on the back side of the semiconductor substrate 110 (on the entire surface of the low-resistance semiconductor layer 111). The drain electrode 150 is composed of a laminated film formed by laminating Ti, Ni, Au (or Ag) in this order from the semiconductor substrate 110 side, and the thickness of the drain electrode 150 is 0.2 μm to 1.5 μm (e.g., 1 μm).

[0072] The protective insulating film 160 is formed on the entire surface of the semiconductor substrate 110 except for the pad portion of the source electrode 130 ( Figure 3 the central white rectangular portion) and the dicing region for separating the chip from the gate pad 140. The material of the protective insulating film 160 is, for example, polyimide.

[0073] (1-2) Regarding the peripheral region A12

[0074] Figure 5 is Figure 3 a cross-sectional view taken along line B-B. In the peripheral region A12 of the device region A1, as Figure 3 and Figure 5 shown, a gate pad 140, a first gate wiring 145, and a second gate wiring 147 are provided on the semiconductor substrate 110. The interlayer insulating film 124 is formed on the gate lead-out wiring 146 and the gate protection portion 40. As Figure 5As shown, the gate pad 140 is arranged outside one short side of the rectangular source electrode and at a position separated from the source electrode 130. The first gate wiring 145 and the second gate wiring 147 are arranged so as to substantially surround the source electrode 130 with the first gate wiring 145 being the inner side and the second gate wiring 147 being the outer side (see FIG. Figure 3 and Figure 4 ) and connected to the gate pad 140.

[0075] The gate pad 140 is arranged via the polysilicon layer 141 formed on the field insulating film 170 (see Figure 3 and Figure 5 The gate pad 140 is connected to the source electrode 130 through the polysilicon layer 141 and the gate protection portion 142 described later. In addition, the gate pad 140 is also connected to the first gate wiring 145 and the second gate wiring 147 (for the connection between the second gate wiring 147 and the gate pad 140, refer to Figure 5 ) In addition, the polysilicon layer 141 is formed by, for example, introducing N-type impurities into the polysilicon layer formed by CVD by ion implantation.

[0076] The first gate wiring 145 is arranged on the lead wiring 146 arranged on the interlayer insulating film 124 (see Figure 4 ). The lead wiring 146 is connected to the end of the gate electrode 120 configured in a stripe shape. The first gate wiring 145 is connected to the lead wiring 146 and is connected to the gate electrode 120 via the lead wiring 146. Incidentally, the lead wiring 146 is formed by introducing impurities into polysilicon.

[0077] The second gate wiring 147 is connected to the clamp voltage determining section 180 of the withstand voltage isolation region A2. The gate pad 140, the first gate wiring 145, and the second gate wiring 147 are formed together with the source electrode 130.

[0078] In the peripheral area A12 of the device area A1, as shown in FIG. Figure 5 As shown, the semiconductor device 100 of the first embodiment includes a semiconductor substrate 110, a field insulating film 170, a gate protection portion 142, a drain electrode 150, and a protective insulating film 160. The drain electrode 150 and the protective insulating film 160 have the same structure as the active region A11.

[0079] like Figure 5As shown, the semiconductor substrate 110 has an N+-type low-resistance semiconductor layer 111, an N-type semiconductor layer 115 formed above the low-resistance semiconductor layer 111, and a P-type semiconductor layer 119. The N+-type low-resistance semiconductor layer 111 has the same structure as the low-resistance semiconductor layer 111 in the active region A11. The N-type semiconductor layer 115 has the same structure as the drift layer 112 in the active region A11. The P-type semiconductor layer 119 has the same depth as the base region 113 in the active region A11.

[0080] The field insulating film 170 is an oxide film and other appropriate insulating films formed on the surface of the semiconductor substrate 110.

[0081] On the field insulating film 170, when viewed from above, the gate protection portion 142 is disposed in a region surrounding the gate pad 140 (strictly speaking, the polysilicon layer 141 under the gate pad 140) for one week. Therefore, the gate pad 140 is electrically connected to the source electrode 130 through the gate protection portion 142 (refer to the right side of Figure 5 ), and is electrically connected to the first gate wiring 145 through the gate protection portion 142 (not shown).

[0082] At least one second N-type region 143 and at least two second P-type regions 144 in the gate protection portion 142 are adjacent to each other and alternately arranged. In the gate protection portion 142, the total amount of impurities in the second P-type region 144 sandwiched by two second N-type regions 143 is smaller than any one of the total amounts of impurities in the two second N-type regions 143 adjacent to the second P-type region 144. Therefore, the internal resistance of the second P-type region 144 can be used as the temperature characteristic adjustment resistor 42 for gate protection. In addition, a Zener diode 43 for gate protection can be formed by the second P-type region 144 and one second N-type region 143, and a diode 44 for gate protection can be formed by the second P-type region 144 and the other second N-type region 143.

[0083] (2) Regarding the breakdown voltage isolation region A2

[0084] The breakdown voltage isolation region A2 is a region where the clamping voltage determination portion 30 is formed.

[0085] As Figures 3 to 5 shown, the semiconductor device 100 of Embodiment 1 includes a semiconductor substrate 110, a field insulating film 170, a clamping voltage determination portion 180, a channel stopper electrode 190, and a drain electrode 150 in the breakdown voltage isolation region A2. The drain electrode 150 and the field insulating film 170 have the same configuration as the device region A1. In addition, an interlayer insulating film 124 is formed on the clamping voltage determination portion 180.

[0086] The semiconductor substrate 110 has an N+-type low-resistance semiconductor layer 111 in the breakdown isolation region A2, an N-type semiconductor layer 115 formed above the low-resistance semiconductor layer 111, a P-type surface electric field reducing region 116 formed on the surface of the N-type semiconductor layer 115, and a channel stopper region 117. In addition, from the device region A1 to the breakdown isolation region A2, there is a P-type boundary semiconductor region 118 formed so as to cover the end portion of the base region 113. In addition, the N+-type low-resistance semiconductor layer 111 has the same structure as the low-resistance semiconductor layer 111 in the device region A1. The N-type semiconductor layer 115 has the same structure as the drift layer 112 in the active region A11. The depth of the boundary semiconductor region 118 is formed to a depth position deeper than the base region 113, but may also be the same depth as the base region 113.

[0087] The surface electric field reducing region 116 is formed in at least the region overlapping with the clamping voltage determining portion 180, and its depth is equal to or shallower than that of the P-type region 118. The end portion of the surface electric field reducing region 116 is connected to the base region 113 and the P-type boundary semiconductor region 118 in the device region A1. The channel stopper region 117 is an N+-type semiconductor region formed on the outermost peripheral surface of the semiconductor substrate 110, and is connected to the channel stopper electrode 190.

[0088] As Figure 3 shown, when viewed from above, the clamping voltage determining portion 180 surrounds the device region A1 throughout the circumference, and as Figure 4 shown, it is connected to the second gate wiring 147 on the device region A1 side, and on the outermost peripheral side, it is connected to the channel stopper electrode 190 having the same potential as the drain electrode 150 in terms of structure. Therefore, one end (device region A1 side) of the clamping voltage determining portion 180 is connected to the gate pad 140 through the second gate wiring 147, and the other end (outermost peripheral side) is electrically connected to the drain electrode 150.

[0089] On the field insulating film 170, a plurality of first P-type regions 184 and a plurality of first N-type regions 182 of the clamping voltage determining portion 180 are adjacent to each other and alternately arranged. The clamping voltage determining portion 180 has a structure corresponding to the clamping voltage determining portion 30 of the active clamping circuit 10. That is, a diode 34 is formed between the first P-type region 184 and the first P-type region 184 on the device region A1 side, and a Zener diode 33 is formed between the first P-type region 184 and the first P-type region 184 on the outer peripheral side.

[0090] The first N-type region 182 and the first P-type region 184 are formed by introducing P-type impurities or N-type impurities into a prescribed region of the same polysilicon layer. Moreover, in the clamping voltage determination section 180, the total amount of impurities in the first P-type region 184 sandwiched by two first N-type regions 182 is smaller than the total amount of impurities in any one of the two first N-type regions 182 adjacent to the first P-type region 184. Therefore, the internal resistance of the first P-type region 184 becomes high, and thus the temperature characteristic adjustment resistor 32 can be formed. In addition, in the first embodiment, the clamping voltage determination section 180, the polysilicon layer 141, the lead wiring 146, and the gate protection section 142 are formed integrally.

[0091] In the clamping voltage determination section 180, the internal resistance of the first P-type region 184 sandwiched by two first N-type regions 182 has a temperature characteristic that can cancel out the temperature change of the voltage after overlapping the forward voltage of the diode formed by the first P-type region 184 and the first N-type region 182 adjacent to one side of the first P-type region 184 and the Zener voltage of the Zener diode formed by the first P-type region 184 and the first N-type region 182 adjacent to the other side of the first P-type region 184. The internal resistance of the first P-type region 184 is determined by the impurity concentration of the first P-type region 184, the length of the first P-type region 184 in the direction along the current path ( Figure 4 the lateral length), and the cross-sectional area of the first P-type region 184 with respect to the current path (the cross-sectional area of the surface orthogonal to the current path).

[0092] In the first embodiment, the impurity concentration of the first P-type region 184 is lower than the impurity concentration of the first N-type region 182. Therefore, since there are fewer carriers, from the viewpoint of impurity concentration, the internal resistance of the first P-type region 184 is larger than the internal resistance of the first N-type region 182. In addition, the first P-type region 184 Figure 3 and Figure 5 the lateral width (the length in the radial direction = the length of the current path) in is longer than the lateral width of the first N-type region 182. This is because it is not easy to strictly control the internal resistance by adjusting the impurity concentration introduced into the first P-type region 184, so the internal impurity concentration of the first P-type region 184 is adjusted by adjusting the lateral width (the length in the radial direction = the length of the current path) of the first P-type region 184. Therefore, although the lateral width (the length in the radial direction = the length of the current path) of the first P-type region 184 is longer than the lateral width of the first N-type region 182, from the viewpoint of internal resistance, the internal resistance of the first P-type region 184 is larger than the internal resistance of the first N-type region 182.

[0093] The channel stop electrode 190 is formed to surround the semiconductor substrate 110 once at the outermost periphery of the semiconductor substrate 110, and is electrically connected to the drain electrode 150.

[0094] 5. Effects of the active clamp circuit 10 and the semiconductor device 100 in Embodiment 1

[0095] For the active clamp circuit 10 according to Embodiment 1, since it includes the clamp voltage control switch 20 and the clamp voltage determination unit 30 with one terminal electrically connected to the drain electrode and the other terminal electrically connected to the gate electrode, like the conventional switch circuit, it can absorb the surge voltage. In addition, since the clamp voltage control switch 20 functions as a driver for sending a conduction signal to the gate electrodes G1 and G2 of the main switches Q1 and Q2, in addition to a small drive current, during the period when the clamp voltage control switch or the main switch is turned on and a surge is generated, the main switches Q1 and Q2 can be used as a current path for voltage clamping, so a large diode can be dispensed with.

[0096] Figure 6 It is a schematic graph showing the relationship between the clamp voltage and the diode current in the active clamp circuit of Embodiment 1 and the conventional second active clamp circuit. Figure 6 The dotted line in shows the relationship between the clamp voltage and the diode current in the conventional active clamp circuit, and the solid line shows the relationship between the clamp voltage and the diode current in the active clamp circuit of Embodiment 1.

[0097] In the second active clamp circuit 910 of the prior art, since the current flowing through the main switch Q1 is bypassed and clamped, the current flowing through the Zener diode 943 becomes larger, and the operating resistance (impedance) of the Zener diode becomes larger. Therefore, the variation in the clamp voltage caused by the operating resistance (impedance) of the Zener diode (refer to Figure 6 the dotted curve) becomes larger. In addition, the temperature rise of the Zener diode also becomes larger, and the variation in the clamp voltage also becomes larger. Therefore, it is difficult to make the function of clamping the surge voltage operate as desired, and it is difficult to make the operation of the switch circuit stable.

[0098] In contrast, for the active clamp circuit 10 according to Embodiment 1, since it includes the clamp voltage control switch 20 and the clamp voltage determination unit 30, the current flowing through the clamp voltage determination unit 30 and the Zener diode 33 becomes smaller, and the operating resistance (impedance) of the Zener diode will decrease. Therefore, the change in the clamp voltage caused by the operating resistance (impedance) of the Zener diode 33 can be reduced (see Figure 6 the solid line in). In addition, since the current flowing into the clamp voltage determination unit 30 and the Zener diode 33 becomes smaller, the temperature rise of the Zener diode becomes smaller, and the variation in the clamp voltage can be reduced. Therefore, the function of clamping the surge voltage can be made to operate as desired, and the operation of the switch circuit can be made stable.

[0099] In the active clamp circuit 10 according to Embodiment 1, since it has the temperature characteristic adjustment resistor 32, by mutually canceling the influence of the decrease in the forward voltage of the diode 34 having a characteristic of decreasing with temperature rise and the influence of the increase in the resistance value of the temperature characteristic adjustment resistor 32 having a characteristic of increasing with temperature rise, it is possible to suppress the temperature variation of the clamp voltage (refer to Figure 6 ).

[0100] In the active clamp circuit 10 according to Embodiment 1, since the gate protection unit 40 has a group in which the gate protection Zener diode 43 and the gate protection diode 44 are connected in opposite polarities, it is possible to prevent an erroneous signal from being transmitted to the gate electrode due to the surge voltage of the switch, thereby improving the breakdown tolerance.

[0101] In the active clamp circuit 10 according to Embodiment 1, since the group 41 of the gate protection unit 40 each has a structure in which a gate protection temperature characteristic adjustment resistor 42 is provided between the gate protection Zener diode 43 and the gate protection diode 44, it is also possible to absorb the variation of the clamp voltage caused by temperature change at the gate protection unit 40. As a result, even with temperature change, the gate is not easily damaged.

[0102] In the active clamp circuit 10 according to Embodiment 1, since the temperature characteristic adjustment resistor 32 has a temperature characteristic of reducing the temperature change of the voltage obtained by overlapping the Zener voltage of the Zener diode 33 of the group 31 having the temperature characteristic adjustment resistor 32 and the forward voltage of the diode 34, it is possible to mutually cancel the influence of the decrease in the forward voltage of the diode having a characteristic of decreasing with temperature rise and the influence of the increase in the resistance value of the resistor having a characteristic of increasing with temperature rise, and moreover, it is also possible to cope with the temperature characteristic of the Zener voltage of the Zener diode 33, thereby more effectively suppressing the temperature variation of the clamp voltage of the group 31.

[0103] In the semiconductor device 100 according to Embodiment 1, since a MOS structure is formed in the region where the source electrode 130 is formed, and in the breakdown voltage isolation region A2, there is a clamping voltage determination unit 180 in which a plurality of N-type regions 182 and a plurality of P-type regions 184 are adjacent to each other and alternately arranged, an active clamping circuit including a switching element for clamping voltage control and a clamping voltage determination unit, one terminal of which is electrically connected to the first main electrode of the switching element for clamping voltage control, and the other terminal of which is electrically connected to the control electrode of the switching element for clamping voltage control can be constituted. Therefore, a surge voltage can be absorbed. In addition, since the switching element for clamping voltage control (MOS structure) has a function as a driver for sending a conduction signal to the control electrode of the main switch, the drive current is small, and the current flowing through the clamping voltage determination unit serving as a trigger can also be reduced. Thus, it is possible to use only the main switch as a current path for voltage clamping during the generation of a surge, without using a large-sized diode.

[0104] In the semiconductor device 100 according to Embodiment 1, since a MOS structure is formed in the region where the source electrode 130 is formed, and in the breakdown voltage isolation region A2, there is a clamping voltage determination unit 180 in which a plurality of N-type regions 182 and a plurality of P-type regions 184 are adjacent to each other and alternately arranged, the switching element 20 for clamping voltage control and the clamping voltage determination unit 30 of the active clamping circuit can be constituted. Therefore, since the current flowing through the active clamping circuit 10 and the Zener diode becomes small, the operating resistance (impedance) of the Zener diode 33 becomes small, and the variation in the clamping voltage caused by the operating resistance (impedance) of the Zener diode 33 ( Figure 6 dotted line) can be reduced. In addition, since the current flowing through the active clamping circuit 10 and the Zener diode becomes small, the temperature rise of the Zener diode 33 becomes small, and the variation in the clamping voltage can be reduced. Therefore, the function of clamping the surge voltage can be made to operate as desired, and the operation of the switching circuit can be stabilized.

[0105] Furthermore, in the semiconductor device 100 according to Embodiment 1, in the clamping voltage determination unit 180, since the total amount of impurities in the first P-type region 184 sandwiched between two first N-type regions 182 is smaller than the total amount of impurities in the two first N-type regions 182 adjacent to the first P-type region 184, the internal resistance of the first P-type region 184 can be made larger than that of the first N-type region 182, and thus the internal resistance of the first P-type region 184 can be used as a temperature characteristic adjustment resistor of the clamping voltage determination unit 180. Therefore, the influence of the temperature characteristic (the characteristic of decreasing with temperature rise) of the forward voltage of the diode formed between the first P-type region 184 and the first N-type region 182 can be offset by the temperature characteristic (the characteristic of increasing with temperature rise) of the internal resistance of the first P-type region 184, thereby suppressing the temperature electromotive force of the clamping voltage.

[0106] In addition, in the semiconductor device 100 according to Embodiment 1, since the region surrounding the gate pad 140 in a plan view on the field insulating film 170 has a gate protection portion 142 in which at least one second N-type region 143 and at least two second P-type regions 144 are adjacent to each other and alternately arranged, the breakdown tolerance can be improved. Further, as the device is miniaturized, the electrostatic breakdown tolerance of the gate voltage may decrease. However, since the gate protection portion 142 is provided, the electrostatic breakdown tolerance can be maintained even when the device is reduced.

[0107] In the semiconductor device 100 according to Embodiment 1, since the total amount of impurities in the second P-type region 144 sandwiched between the two second N-type regions 143 is smaller than any one of the total amounts of impurities in the two second N-type regions 143 adjacent to the second P-type region 144, the internal resistance of the second P-type region 144 is increased, and the internal resistance of the second P-type region 144 becomes a temperature characteristic adjustment resistor for gate protection. Therefore, the influence of the temperature characteristic (characteristic of decreasing as the temperature rises) of the forward voltage of the diode formed between the second P-type region 144 and the second N-type region 143 can be offset by the temperature characteristic (characteristic of increasing as the temperature rises) of the internal resistance of the second P-type region 144, thereby suppressing the temperature variation of the protection voltage of the gate protection portion 142.

[0108] In the semiconductor device 100 according to Embodiment 1, in the clamping voltage determination portion 180, since the internal resistance of the first P-type region 184 sandwiched between the two first N-type regions 182 has a temperature characteristic that can cancel the temperature change of the voltage after overlapping the forward voltage of the diode formed by the first P-type region 184 and the first N-type region 182 adjacent to one side of the first P-type region 284 and the Zener voltage of the Zener diode formed by the first P-type region 184 and the first N-type region 182 adjacent to the other side of the first P-type region 184, the temperature change of the clamping voltage can be suppressed with higher accuracy.

[0109] In the semiconductor device 100 according to Embodiment 1, since the clamping voltage determination portion 180 surrounds the device region A1 over the entire circumference in a plan view, the cross-sectional area of the current path (cross-sectional area from the center to the outer peripheral side) becomes large, and a relatively large current can flow. Therefore, the impedance becomes small, and the clamping voltage can be prevented from rising easily. In this way, a clamping voltage more within the desired range can be applied.

[0110] However, in the breakdown voltage isolation region A2, when multiple P-type guard rings are formed on the surface of the semiconductor substrate 110, since the region without a guard ring between adjacent guard rings is prone to electric field concentration, the density of the electric field may occur, resulting in a reduction in the surrounding breakdown voltage. To prevent this, it is necessary to reduce the interval between the guard rings, but in practice, it is difficult to form the guard rings with a fine pitch. In addition, there is also a problem that it may affect the Zener voltage of the clamping voltage determination unit 180 on the field insulating film 170. In contrast, in the semiconductor device 100 according to Embodiment 1, since a P-type surface electric field reduction region is formed on the surface of the semiconductor substrate 110 in the breakdown voltage isolation region A2, the potential distribution becomes flat, and electric field concentration is not easily caused, so a stable surrounding breakdown voltage can be obtained.

[0111] In the semiconductor device 100 according to Embodiment 1, since a P-type boundary semiconductor region 118 is formed to cover the boundary between the base region 113 and the surface electric field reduction region 116, the potential distribution near the boundary between the device region A1 and the breakdown voltage isolation region A2 becomes flat, and it is easy to maintain the breakdown voltage. In addition, since it is formed to the same depth position as or deeper than the surface electric field reduction region 116, the potential distribution near the boundary becomes even flatter, and it is easier to maintain the breakdown voltage.

[0112] In the semiconductor device 100 according to Embodiment 1, in the clamping voltage determination unit 180, since the impurity concentration of the first P-type region 184 sandwiched between the two first N-type regions 182 is smaller than that of any one of the two first N-type regions 182 adjacent to the first P-type region 184, the total amount of impurities in the first P-type region 184 can be reduced, and thus the resistance value of the internal resistance of the first P-type region 184 can be reduced.

[0113] [Embodiment 2]

[0114] Figure 7 It is a circuit diagram showing the active clamping circuit 10a of the second embodiment. Figure 8 It is a plan view of the semiconductor device 200 of Embodiment 2. Figure 9 It is a cross-sectional view of the semiconductor device 200 of Embodiment 2. In Figure 9 it, the symbol 213 represents the anode region, the symbol 230 represents the anode electrode, and the symbol 250 represents the cathode electrode.

[0115] The active clamping circuit 10a and the semiconductor device 200 of Embodiment 2 have a configuration that is basically the same as that of the active clamping circuit 10 and the semiconductor device 100 according to Embodiment 1, but the difference from the case of the active clamping circuit 10 and the semiconductor device 100 of Embodiment 1 is that it has a bypass diode instead of the lamp voltage control switch (refer to Figures 7 to 9)。In the active clamp circuit 10a according to Embodiment 2, there is no gate protection unit 40 or resistor 50.

[0116] The bypass diode 60 has an anode A and a cathode K. The anode A is electrically connected to the gate electrode G1 of the main switch Q1, and the cathode K is electrically connected to the drain electrode D1 of the main switch Q1. One end of the clamp voltage determination unit 30 is electrically connected to the cathode K of the bypass diode 60, and the other end is electrically connected to the anode A of the bypass diode 60.

[0117] The semiconductor device 200 according to Embodiment 2 does not have a gate pad 140, a first gate wiring 145, and a second gate wiring 147 in the device region A1 (refer to Figure 8 ).

[0118] In the device region A1, as Figure 9 shown, the semiconductor substrate 210 has a low-resistance semiconductor layer 211, an N-type semiconductor region 212 (drift region), and a P-type anode region 213, and has a diode structure located between the anode region 213 and the drift region 212.

[0119] In the breakdown voltage isolation region A2, the clamp voltage determination unit 280 is on the field insulating film 270. A plurality of N-type regions 282 and a plurality of P-type regions 284 are adjacent to each other and alternately arranged. The N-type region 282 closest to the device region A1 is electrically connected to the anode, and the N-type region 282 farthest from the device region A1 is electrically connected to the cathode.

[0120] As described above, although the active clamp circuit 10a and the semiconductor device 200 according to Embodiment 2 are different from the active clamp circuit 10 and the semiconductor device 100 according to Embodiment 1 in that a bypass diode is used instead of the clamp voltage control switch, since it includes: a bypass diode 60; and a clamp voltage determination unit 30, one terminal of which is electrically connected to the anode A of the bypass diode 60 and the other terminal of which is electrically connected to the cathode K of the bypass diode 60, it can absorb the surge voltage and clamp the voltage. In addition, the current flowing through the clamp voltage determination unit 30 can also be reduced, and during the period when the main switch is turned on and a surge is generated, the main switch can be used as a current path for voltage clamping, so that a large diode does not have to be used.

[0121] In the semiconductor device 200 according to Embodiment 2, since a diode structure is formed in the region where the anode electrode 230 is formed, and the clamping voltage determination unit 280 in which a plurality of first P-type regions 284 and a plurality of first N-type regions 282 are adjacent to each other and alternately arranged is provided, it can be used as an active clamping circuit 10a of the clamping voltage determination unit 30 having a bypass diode 60; one terminal is electrically connected to the anode A of the bypass diode 60, and the other terminal is electrically connected to the cathode K of the bypass diode 60. Therefore, a surge voltage can be absorbed to clamp the voltage. In addition, the current flowing through the clamping voltage determination unit 30 can also be reduced, and during the period when the main switch is turned on and a surge voltage is generated, the main switch can be used as a current path for voltage clamping, so a large-sized diode does not have to be used.

[0122] Since the active clamping circuit 10a and the semiconductor device 200 according to Embodiment 2 have the same configuration as the active clamping circuit 10 and the semiconductor device 100 according to Embodiment 1, except for the difference that a bypass diode is provided instead of the clamping voltage control switch, they have the same effects as those of the active clamping circuit 10 and the semiconductor device 100 according to Embodiment 1.

[0123] [Embodiment 3]

[0124] Figure 10 It is a view of the active clamping circuit 10b and the semiconductor device 101 according to Embodiment 3. Figure 10 (a) is a circuit diagram for explaining the active clamping circuit 10b, Figure 10 b is a cross-sectional view for explaining the semiconductor device 101.

[0125] The active clamping circuit 10b according to Embodiment 3 has a configuration substantially the same as that of the active clamping circuit 10 according to Embodiment 1, but is different from the case of the active clamping circuit 10 according to Embodiment 1 in that it has a second temperature characteristic adjustment resistor (refer to Figure 10 (a)). That is, the clamping voltage determination unit 30a has a second temperature characteristic adjustment resistor 35 for adjusting the temperature characteristic on the drain D1 side of the main switch Q1. Although the second temperature characteristic adjustment resistor 35 is provided on the drain D1 side of the main switch Q1, it can also be provided on the gate G3 side of the clamping voltage control switch 20, or between the groups 31 and 31. In addition, two or more second temperature characteristic adjustment resistors 35 can be provided.

[0126] In the clamping voltage determination unit 30a of Embodiment 3, the temperature characteristic adjustment resistor 32 and the second temperature characteristic adjustment resistor 35 have temperature characteristics that reduce the temperature variation of the forward voltage of the diode 34. Specifically, in the clamping voltage determination unit 30, the temperature variation of the forward voltage of the diode 34 and the temperature variation of the Zener voltage of the Zener diode 33 can be adjusted to an arbitrary temperature coefficient by the combined resistance of the temperature characteristic adjustment resistor 32 and the second temperature characteristic adjustment resistor 35. Thereby, the variation of the threshold voltage VTH of the main switches Q1 and Q2 with respect to temperature can be eliminated. [[ID=?]]

[0127] The semiconductor device 101 of Embodiment 3 basically has the same structure as the semiconductor device 100 of Embodiment 1, but is different from the semiconductor device 100 of Embodiment 1 in that it has a second temperature characteristic adjustment resistor (see Figure 10 (b)). That is, the clamping voltage determination unit 180 further has a second P-type region 186 for adjusting the temperature characteristic at the outer peripheral end portion.

[0128] The second P-type region 186 can be provided on the device region A1 side, or can be provided at an appropriate position of the clamping voltage determination unit 180. In addition, the second P-type region 186 can surround the entire circumference of the device region A1, or can be partially formed to adjust the resistance component. Furthermore, additives or other materials different from those of the first P-type region can also be used.

[0129] As described above, although the active clamping circuit 10b (semiconductor device 101) of Embodiment 3 is different from the active clamping circuit 10 (semiconductor device 100) of Embodiment 1 in that the active clamping circuit 10b (semiconductor device 101) includes a second temperature characteristic adjustment resistor 35 (second P-type region 186), since it also has a clamping voltage control switch 20 and a clamping voltage determination unit 30 with one terminal electrically connected to the drain electrode and the other terminal electrically connected to the gate electrode, it can absorb the surge voltage. In addition, since the clamping voltage control switch 20 has a function as a driver for sending a conduction signal to the gate electrodes G1 and G2 of the main switches Q1 and Q2, the drive current is small, and the current flowing through the clamping voltage determination unit that determines the turn-off voltage as a flip-flop can be reduced. Moreover, after the clamping voltage control switch and the main switch are turned on, the main switches Q1 and Q2 can be used as a current path for voltage clamping during the period when a surge occurs. Therefore, a large diode does not need to be used.

[0130] Since the clamping voltage determination unit 30 includes the second temperature characteristic adjustment resistor 35 that adjusts the temperature characteristic, it is possible not only to reduce the temperature dependence of the clamping voltage by the temperature characteristic adjustment resistor 32, but also to adjust the second temperature characteristic adjustment resistor 35 to have a temperature characteristic that cancels out the temperature dependence of the threshold voltages VTH of the main switches Q1 and Q2. Thereby, it is possible to cancel out the temperature dependence of the clamping voltage of the clamping voltage control switch 20 and the threshold voltages VTH of the main switches Q1 and Q2.

[0131] The active clamping circuit 10b (semiconductor device 101) of Embodiment 3 has the same configuration as that of the active clamping circuit 10 (semiconductor device 100) of Embodiment 1, except that it includes the second temperature characteristic adjustment resistor 35 (second P-type region 186). Therefore, it also has the related effects of the active clamping circuit 10 (semiconductor device 100) of Embodiment 1.

[0132] As described above, the present invention has been described based on the above embodiments, but the present invention is not limited to the above embodiments. It can be implemented in various ways without departing from the concept. For example, the following modifications can be made.

[0133] (1) The positions, connections, quantities, etc. described in the above embodiments are merely examples and can be changed within the range that does not impair the effects of the present invention.

[0134] (2) In the above embodiments, although the total amount of impurities is adjusted by adjusting the impurity concentration of the first P-type region and the length along the current path to adjust the internal resistance, the present invention is not limited thereto. The total amount of impurities can also be adjusted by adjusting either the impurity concentration of the first P-type region or the length along the current path, or by adjusting the cross-sectional area of the plane perpendicular to the current path. Specifically, the first P-type region can be formed in a part of the device region A1 instead of forming a first P-type region around the device region A1. In addition, the internal resistance can also be adjusted by introducing other materials or other additives.

[0135] (3) Although the gate protection unit is provided in the above Embodiments 1 and 3, the present invention is not limited thereto. The gate protection unit may not be provided. In addition, as the resistor of the gate protection unit, a temperature characteristic adjustment resistor is used, but a general resistor that does not have the function of adjusting the temperature characteristic can also be used, or a resistor may not be used.

[0136] (4) In each of the above-described embodiments, the boundary semiconductor region 118 is formed in such a manner that the base region 113 is in contact with the surface electric field reducing region 116 and covers the boundary between the base region 113 and the surface electric field reducing region 116. However, the present invention is not limited thereto. The base region 113 may not be in contact with the surface electric field reducing region 116. In this case, the boundary semiconductor region 118 is formed between the base region 113 and the surface electric field reducing region 116. In this case, the depth of the boundary semiconductor region 118 is preferably the same as or deeper than the depth of the surface electric field reducing region 116. This is because, by doing so, the potential distribution near the boundary between the device region A1 and the breakdown voltage isolation region A2 becomes gentle, and it is easy to maintain the breakdown voltage.

[0137] (5) In each of the above-described embodiments, the gate protection portion is provided, but the present invention is not limited thereto. The gate protection portion may not be provided. Further, as the resistor of the gate protection portion, a temperature characteristic adjusting resistor is used, but a general resistor that does not have a function of adjusting the temperature characteristic may be used, or a resistor may not be used.

[0138]

Symbol Explanation

[0139] 1…Switching circuit; 10, 10a, 10b…Active clamping circuit; 20…Switch for clamping voltage control; 30, 30a…Clamping voltage determining section; 31…Group; 32…Temperature characteristic adjusting resistor; 33…Zener diode; 34…Zener diode; 35…Second temperature characteristic adjusting resistor; 40…Gate protection section; 41…Group; 42…Temperature characteristic adjusting resistor; 43…Zener gate protection diode; 44…Diode; 50…Resistor; 60…Bypass diode; 100, 101, 200…Semiconductor device; 110…Semiconductor substrate; 111, 211…Low-resistance semiconductor layer; 112, 212…Drift layer; 113…Base region; 114…Source region; 115…N-type semiconductor layer; 116…Surface electric field reducing region; 117…Channel stop region; 118…Boundary semiconductor region; 119…P-type semiconductor layer; 120…Gate electrode; 122…Gate insulating film; 124…Interlayer insulating film; 130…Source electrode; 120…Gate electrode; 140…Gate pad; 141…Polysilicon layer; 142…Gate protection section; 143…Second N-type region; 144…Second P-type region; 145…Gate wiring; 146…Gate lead wiring; 147…Second gate wiring; 150…Drain electrode; 160…Protection insulating film; 170, 270…Field insulating film; 172…Polysilicon layer; 180, 280…Clamping voltage determining section; 182, 282…First N-type region; 184, 284…First P-type region; 186…Third P-type region; 190…Channel stop electrode; 213…Anode region; 230…Anode electrode; A1…Device region; A11…Active region; A12…Peripheral region; A2…Breakdown voltage isolation region; Q1…First main switch; Q2…Second main switch; Vcc…External power supply.

Claims

1. An active clamping circuit, connected between a control electrode and a main electrode of a main switch, for controlling the clamping voltage of the main switch, characterized in that: include: a clamp voltage control switch having a first main electrode, a second main electrode, and a control electrode, wherein the second main electrode is electrically connected to the main electrode of the main switch, and the first main electrode is electrically connected to the control electrode of the main switch; as well as a clamp voltage determination unit having one end electrically connected to the second main electrode of the clamp voltage control switch and the other end electrically connected to the control electrode of the clamp voltage control switch; The clamp voltage determination unit includes a plurality of groups consisting of a temperature characteristic adjustment resistor, a Zener diode connected to one end of the temperature characteristic adjustment resistor, and a diode connected to the other end of the temperature characteristic adjustment resistor in a manner opposite to the characteristics of the Zener diode, and the groups are connected in series.

2. The active clamping circuit according to claim 1, wherein , further including: a gate protection unit having one end connected to the control electrode of the clamp voltage control switch and the other end electrically connected to the control electrode of the main switch and the first main electrode of the clamp voltage control switch; The gate protection unit includes at least one gate protection Zener diode and a gate protection diode connected in opposite polarities.

3. The active clamping circuit according to claim 2, wherein: in, Each of the groups of the gate protection parts has a structure in which a gate protection temperature characteristic adjustment resistor is electrically connected between the gate protection Zener diode and the gate protection diode.

4. An active clamping circuit, connected between the control electrode and the main electrode of the main switch, for controlling the clamping voltage of the main switch, characterized in that, include: a bypass diode having an anode electrode and a cathode electrode, wherein the anode electrode is electrically connected to the control electrode of the main switch, and the cathode electrode is electrically connected to the main electrode of the main switch; as well as a clamp voltage determination unit having one terminal electrically connected to the cathode electrode of the bypass diode and another terminal electrically connected to the anode electrode of the bypass diode and the control electrode of the main switch; The clamp voltage determination unit includes a plurality of groups consisting of a temperature characteristic adjustment resistor, a Zener diode connected to one end of the temperature characteristic adjustment resistor, and a diode connected to the other end of the temperature characteristic adjustment resistor in a manner opposite to the characteristics of the Zener diode, and the groups are connected in series.

5. The active clamping circuit according to any one of claims 1 to 4, characterized in that: Among them, The temperature characteristic adjusting resistor has a temperature characteristic that reduces temperature changes in the Zener voltage of the Zener diode in the group not including the temperature characteristic adjusting resistor and in a voltage obtained by superimposing the forward voltage of the diode.

6. The active clamping circuit according to any one of claims 1 to 4, characterized in that: in, The clamp voltage determination unit further includes a second temperature characteristic adjustment resistor configured to adjust the temperature characteristic of at least one of the end portion and two adjacent groups.

7. A semiconductor device, connected between a control electrode and a main electrode of a main switch, constituting an active clamping circuit for controlling a clamping voltage of the main switch, the device being formed on a semiconductor substrate defining a device region and a voltage-withstand isolation region formed around the device region, characterized in that: The device region includes: the semiconductor substrate; a first main electrode formed on a surface of the semiconductor substrate; a gate pad formed on the surface of the semiconductor substrate at a position separated from the first main electrode; and A second main electrode is formed on the surface of the back side of the semiconductor substrate, A MOS structure is formed in the region where the first main electrode is formed, and in the voltage-resistant isolation region, the structure includes: the semiconductor substrate; The second main electrode is formed on the surface of the back side of the semiconductor substrate; an insulating film formed on a surface of the semiconductor substrate; and a clamp voltage determining portion, wherein a plurality of first first conductivity type regions and a plurality of first second conductivity type regions are adjacent to each other and alternately arranged in a region surrounding the device region in a plan view on the insulating film, one end of the clamp voltage determining portion being electrically connected to the gate pad and the other end being electrically connected to the second main electrode, In the clamp voltage determination section, a total amount of impurities in the first first conductive type region sandwiched between two first second conductive type regions is smaller than a total amount of impurities in either of the two first second conductive type regions adjacent to the first first conductive type region.

8. The semiconductor device according to claim 7, wherein, Further including: The gate protection portion includes a region on the insulating film surrounding the gate pad when viewed from above, wherein at least one second first conductivity type region and at least two second second conductivity type regions are adjacent to each other and alternately arranged.

9. The semiconductor device according to claim 8, wherein: Among them, In the gate protection portion, a total amount of impurities in the second first conductivity type region sandwiched between two second second conductivity type regions is smaller than a total amount of impurities in either of the two second second conductivity type regions adjacent to the second first conductivity type region.

10. A semiconductor device, connected between a control electrode and a main electrode of a main switch, constituting an active clamping circuit for controlling a clamping voltage of the main switch, the device being formed on a semiconductor substrate defining a device region and a withstand voltage isolation region formed around the device region, characterized in that: The device region includes: the semiconductor substrate; a first main electrode formed on a surface on the surface side of the semiconductor substrate; and A second main electrode is formed on the surface of the back side of the semiconductor substrate, A diode structure is formed in the region where the first main electrode is formed, and in the voltage-resistant isolation region, the structure includes: the semiconductor substrate; The second main electrode is formed on the surface of the back side of the semiconductor substrate; an insulating film formed on a surface of the semiconductor substrate; and a clamp voltage determining portion, wherein a plurality of first first conductivity type regions and a plurality of first second conductivity type regions are adjacent to each other and alternately arranged in a region surrounding the device region in a plan view on the insulating film, one end of the clamp voltage determining portion being electrically connected to the first main electrode and the other end being electrically connected to the second main electrode; In the clamping voltage determination section, the total amount of impurities in the first first conductive type region sandwiched between the two first second conductive type regions is less than the total amount of impurities in either of the two first second conductive type regions adjacent to the first first conductive type region.

11. The semiconductor device according to any one of claims 7 to 10, wherein: Among them, In the clamp voltage determination unit, the internal resistance of the first first conductivity type region sandwiched between the two first second conductivity type regions has a temperature characteristic. This temperature characteristic is used to offset the temperature change of the voltage after the forward voltage of the diode formed by the first first conductive type region and the first second conductive type region adjacent to one side of the first first conductive type region is overlapped with the Zener voltage of the Zener diode formed by the first first conductive type region and the first second conductive type region adjacent to the other side of the first first conductive type region.

12. The semiconductor device according to any one of claims 7 to 10, wherein: in, The clamp voltage determination portion surrounds the device region over its entire circumference in a plan view.

13. The semiconductor device according to any one of claims 7 to 10, wherein: Among them, In the withstand voltage isolation region, a first conductivity type resurf region is formed on the surface of the semiconductor substrate.

14. The semiconductor device according to claim 13, wherein: Among them, A surface first conductive type region is formed on the surface of the device region. A first conductivity type boundary semiconductor region is formed so as to cover a boundary between the surface first conductivity type region and the resurf region.

15. The semiconductor device according to claim 13, wherein: in, A surface first conductive type region is formed on the surface of the device region. A first conductive type boundary semiconductor region is formed between the surface first conductive type region and the reduced surface electric field region, which is formed to a depth position that is the same as or deeper than either the surface first conductive type region and the reduced surface electric field region of the semiconductor base.

16. The semiconductor device according to any one of claims 7 to 10, wherein: in, In the clamp voltage determination section, the impurity concentration of the first first conductivity type region sandwiched between two first second conductivity type regions is lower than the impurity concentration of either of the two first second conductivity type regions adjacent to the first first conductivity type region.

17. The semiconductor device according to any one of claims 7 to 10, wherein: in, The clamp voltage determination section further includes a third first conductivity type region for adjusting temperature characteristics of at least one of the end portion and adjacent groups.

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