Novel drive-by-wire EMB system architecture and method

Abstract

The invention discloses a novel drive-by-wire EMB system architecture and method. The novel drive-by-wire EMB system architecture comprises a controller PCBA, and the controller PCBA comprises three microprocessor modules, a plurality of bus switches and a plurality of bus drivers; the microprocessor module is connected with the bus switch through a bus signal 1; a watchdog module is also arranged between the microprocessor module and the bus switch, and the watchdog module transmits an enable signal to the redundant bus switch for controlling the on or off of the redundant bus switch; the bus switch is connected with the bus driver to ensure communication realization; according to the novel drive-by-wire EMB system architecture and method, the design compactness is improved; meanwhile, three microprocessor modules are used as redundant backups, two of the microprocessor modules respectively control two diagonal wheel side brake motors, and the other microprocessor module is used as a backup module after a conventional microprocessor module fails, so that the safety redundancy of the design is greatly improved, and the driving safety is improved.

Description

Technical Field

[0001] The present invention belongs to the field of automotive chassis electro-mechanical brakes (EMB), and particularly relates to a new EMB system architecture and method for wire control. Background Art

[0002] Traditional EMB systems usually include four sets of electrical systems for wheel-side brake controllers and two sets of electrical systems for brake domain controllers. Although this design can provide sufficient redundancy, the system structure is complex, the number of components is large, resulting in great difficulty in system integration. Moreover, due to the large number of components, the number of failure points also increases correspondingly, resulting in a greater impact on the reliability and stability of the system.

[0003] At the same time, for a design with a large number of wheel-side brake controllers and brake domain controllers but lacking sufficient redundancy, once a certain controller fails, it may cause the entire braking system to fail, thus endangering driving safety.

[0004] In addition, in complex road conditions or emergency braking situations, traditional EMB systems may have unstable braking effects due to controller failures or uneven braking force distribution, thereby affecting driving safety.

[0005] Therefore, the above problems need to be solved urgently. Summary of the Invention

[0006] Object of the Invention: To overcome the above deficiencies, the object of the present invention is to provide a new EMB system architecture and method for wire control, which proposes a new EMB architecture in which a centralized control unit controls four wheel-side brake motors respectively to achieve wire control braking, improving the compactness of the design; at the same time, using three microprocessor modules as redundant backups, where two microprocessor modules control two diagonal wheel-side brake motors respectively, and the other microprocessor module is used as a backup module after the failure of the conventional microprocessor module, greatly improving the safety redundancy of the design and enhancing driving safety.

[0007] Technical solution: To achieve the above object, the present invention provides a novel wire-controlled EMB system architecture, including: a controller PCBA, the controller PCBA includes a first microprocessor module, a second microprocessor module, a third microprocessor module, a first bus switch, a second bus switch, a third bus switch, a fourth bus switch, a first bus driver and a second bus driver; the first microprocessor module is connected to the first bus switch through bus signal 1; the third microprocessor module is connected to the second bus switch through bus signal 2; the second microprocessor module is connected to the fourth bus switch through bus signal 3; the third microprocessor module is connected to the fourth bus switch through bus signal 4. By connecting different microprocessor modules to different bus switches and bus drivers, when a failure occurs in a certain microprocessor module or bus switch in the system, it can continue to operate through other paths, thereby improving the fault tolerance and reliability of the system; at the same time, three microprocessor modules are used as redundant backups, two of which are used for control, and the other microprocessor module is used as a backup module after the normal microprocessor module fails, greatly improving the safety redundancy of the design and enhancing the driving safety.

[0008] Further, a first watchdog module is further provided between the first microprocessor module and the second bus switch, and the first watchdog module transmits an enable signal 1 to the second bus switch to control its opening or closing; a second watchdog module is further provided between the third microprocessor module and the first bus switch, and the second watchdog module transmits an enable signal 2 to the first bus switch to control its opening or closing; a third watchdog module is further provided between the second microprocessor module and the third bus switch, and the third watchdog module transmits an enable signal 3 to the third bus switch to control its opening or closing; a fourth watchdog module is further provided between the third microprocessor module and the fourth bus switch, and the fourth watchdog module transmits an enable signal 4 to the fourth bus switch to control its opening or closing. The watchdog module is independent of the microprocessor module and can monitor the operating state of the microprocessor in real time. If the microprocessor has a dead loop, gets stuck or other abnormal conditions, the watchdog module can trigger a reset operation in time to restore the normal operation of the system; and, by controlling the bus switch through the watchdog module, once an abnormality is detected, the communication link of the faulty module can be quickly cut off to prevent the spread of the fault; at the same time, multiple watchdog modules respectively monitor different microprocessor modules and bus switches, further enhancing the redundancy of the system. Further, both the first bus switch and the second bus switch are connected to the first bus driver to ensure communication; both the third bus switch and the fourth bus switch are connected to the second bus driver to ensure communication. The bus switch can achieve the shortest propagation delay, ensure the rapid transmission of signals on the bus, and improve the response speed of the system.

[0009] Furthermore, the controller PCBA further includes a first PMSM motor pre-driver, a second PMSM motor pre-driver, a third PMSM motor pre-driver, a fourth PMSM motor pre-driver, a first MOS three-phase bridge, a second MOS three-phase bridge, a third MOS three-phase bridge, and a fourth MOS three-phase bridge; the first PMSM motor pre-driver and the second PMSM motor pre-driver are both connected to the first bus driver; the third PMSM motor pre-driver and the fourth PMSM motor pre-driver are both connected to the second bus driver; the first MOS three-phase bridge, the second MOS three-phase bridge, the third MOS three-phase bridge, and the fourth MOS three-phase bridge are respectively connected to the first PMSM motor pre-driver, the second PMSM motor pre-driver, the third PMSM motor pre-driver, and the fourth PMSM motor pre-driver. The energy conversion efficiency of the PMSM motor pre-driver exceeds 95%, having high efficiency and high power density, improving the space utilization rate in application scenarios such as limited space, and optimizing the dynamic response and efficiency of the motor; by connecting several PMSM motor pre-drivers to different bus drivers, the system realizes redundant design. Even if a certain pre-driver module fails, other modules can still work normally, improving the reliability and safety of the system; at the same time, the MOS three-phase bridge has high reliability and low failure rate in the three-phase power converter, further enhancing the stability of the system.

[0010] Furthermore, it further includes a right front brake motor, a left rear brake motor, a left front brake motor, and a right rear brake motor; the right front brake motor, the left rear brake motor, the left front brake motor, and the right rear brake motor are respectively connected to the first MOS three-phase bridge, the second MOS three-phase bridge, the third MOS three-phase bridge, and the fourth MOS three-phase bridge through a wire harness; the wire harness includes U, V, and W three-phase drive signals and motor position sensor signals. The right front, left rear, left front, and right rear four brake motors are all controlled by independent MOS three-phase bridges, achieving precise control of the braking force of each wheel, and by connecting the brake motors to different three-phase bridges, the diagonal control logic is realized; at the same time, the risk of single-point failure is reduced. If a certain three-phase bridge fails, the braking functions of other motors can still work normally, thereby improving the overall reliability of the system.

[0011] Furthermore, the controller PCBA further includes a first CAN transceiver, a second CAN transceiver, a third CAN transceiver, a fourth CAN transceiver, a first power management PMIC and a 4-wheel speed signal processing module, a second power management PMIC and a 4-wheel speed signal processing module, and a wheel speed current signal 4-to-8 processing module; the first CAN transceiver and the second CAN transceiver are both connected to the first microprocessor module; the second CAN transceiver and the third CAN transceiver are both connected to the second microprocessor module; the wheel speed current signal 4-to-8 processing module is connected to the first microprocessor module and the second microprocessor module respectively through the first power management PMIC and the 4-wheel speed signal processing module and the second power management PMIC and the 4-wheel speed signal processing module. By configuring multiple CAN transceivers and connecting them to different microprocessor modules respectively, communication redundancy of the system is achieved, effectively preventing communication interruption caused by the failure of a single CAN transceiver and enhancing the fault tolerance of the system; at the same time, through the wheel speed current signal 4-to-8 processing module, the system efficiently processes and converts the signals of the four wheel speed sensors, provides more accurate wheel speed information for the microprocessor module, greatly improves the anti-interference ability and accuracy of the signals, and thus enhances the braking control performance of the vehicle.

[0012] Furthermore, it further includes a connector module; the first CAN transceiver, the second CAN transceiver, the third CAN transceiver, the fourth CAN transceiver, the first microprocessor module and the second microprocessor module are all connected to the connector module. By centrally managing communication and power connections through the connector module, the complexity and cost of wiring are reduced; at the same time, as the connection center, the connector module enables each CAN transceiver and microprocessor module to be quickly connected and replaced, facilitating system integration and maintenance.

[0013] Furthermore, the controller PCBA further includes a power supply switching switch, a first redundant power supply switching logic module and a second redundant power supply switching logic module; the first redundant power supply switching logic module and the second redundant power supply switching logic module are connected to the first microprocessor module and the second microprocessor module respectively; the power supply switching switch is connected to the power supply switching switch; the power supply switching switch is respectively connected to the first MOS three-phase bridge, the second MOS three-phase bridge, the third MOS three-phase bridge and the fourth MOS three-phase bridge. By setting two redundant power supply switching logic modules and connecting them to the two microprocessor modules respectively, it is ensured that when the main power supply module fails, the backup module can seamlessly take over, thereby improving the reliability of the system; at the same time, the power supply switching switch can achieve efficient power supply switching, reduce energy loss during the power supply switching process, and ensure the efficient operation of the system in the low-power mode.

[0014] Further, the connector module further includes Power Supply 1 and Power Supply 2; both Power Supply 1 and Power Supply 2 are connected to the power supply switching switch. By designing two independent power inputs, the redundant power supply design is improved. Even if one power supply fails, the other power supply can still continue to supply power to the system, significantly improving the reliability of the system.

[0015] Further, the connector module further includes Pedal Signal 1 and Pedal Signal 2; Pedal Signal 1 and Pedal Signal 2 are respectively connected to the first microprocessor module and the second microprocessor module through Heterogeneous Pedal Signal 1 and Heterogeneous Pedal Signal 2. Heterogeneous Pedal Signal 1 and Heterogeneous Pedal Signal 2 adopt different coding methods, enhancing the fault tolerance of the system. Even if one signal is affected by a specific type of interference, the other signal can still work normally, reducing the risk of a single point of failure.

[0016] Further, the first microprocessor module, the second microprocessor module and the third microprocessor module are also connected to each other through information interaction channels. The information interaction channels support data sharing and synchronization between the microprocessor modules, ensuring that the redundant module design has a high response rate and improving the collaborative working ability of the system.

[0017] The present invention also provides a new method for wire-controlled EMB for implementing a new wire-controlled EMB system architecture provided by the present invention, including: S1): The first bus switch, the second bus switch, the third bus switch, and the fourth bus switch are in the normally open mode and turn off when an input enable signal is received; the bus switches are defaulted to the normally open mode and only turn off when receiving the enable signal. This design ensures that the bus switches are in a safe default state when the system starts or resets, avoiding communication failures caused by accidental signals; S2): When the first microprocessor module is working normally, the first microprocessor module provides an enable signal through the first watchdog module to turn off the second bus switch, and the third microprocessor module does not provide a watchdog signal. At this time, the first bus switch is normally open, and the first microprocessor module communicates with the first PMSM motor pre-driver and the second PMSM motor pre-driver through the first bus switch and the first bus driver to achieve motor drive; the first microprocessor module controls the turn-off of the second bus switch through the first watchdog module, ensuring the independent control of the first bus switch by the first microprocessor module and providing a redundant mechanism for the system. Even if the second bus switch fails, the first bus switch can still work normally; S3): When the second microprocessor module is working properly, the second microprocessor module provides an enabling signal through the third watchdog module to turn off the third bus switch. The third microprocessor module does not provide a watchdog signal. At this time, the fourth bus switch is normally turned on. The second microprocessor module communicates with the third PMSM motor pre-driver and the fourth PMSM motor pre-driver through the fourth bus switch and the second bus driver to achieve motor drive. The second microprocessor module controls the turn-off of the third bus switch through the third watchdog module, ensuring the independent control of the second microprocessor module over the fourth bus switch and providing a redundant mechanism for the system. Even if the third bus switch fails, the fourth bus switch can still work properly. S4): When the first microprocessor module fails or malfunctions, the output watchdog signal is interrupted and the first watchdog module stops working. At this time, the second bus switch is turned on, and the third microprocessor module starts to intervene, replacing the first microprocessor module to provide a watchdog signal. It provides an enabling signal through the second watchdog module to turn off the first bus switch and communicates with the first PMSM motor pre-driver and the second PMSM motor pre-driver through the first bus driver to achieve motor drive. When the first microprocessor module fails or malfunctions, the first watchdog module stops working and the second bus switch is automatically turned on. After the system detects a fault, it quickly switches to the backup module, reducing the impact of the fault on the system operation. S5): When the second microprocessor module fails or malfunctions, the output watchdog signal is interrupted and the third watchdog module stops working. At this time, the third bus switch is turned on, and the third microprocessor module starts to intervene, replacing the second microprocessor module to provide a watchdog signal. It provides an enabling signal through the fourth watchdog module to turn off the fourth bus switch and communicates with the third PMSM motor pre-driver and the fourth PMSM motor pre-driver through the second bus driver to achieve motor drive. When the second microprocessor module fails or malfunctions, the third watchdog module stops working and the third bus switch is automatically turned on. After the system detects a fault, it quickly switches to the backup module, reducing the impact of the fault on the system operation.

[0018] From the above technical solutions, it can be seen that the present invention has the following beneficial effects: 1. The novel wire-controlled EMB system architecture and method of the present invention proposes a new EMB architecture in which a centralized control unit controls four in-wheel braking motors respectively to achieve wire-controlled braking, improving the compactness of the design. 2. The novel wire-controlled EMB system architecture and method of the present invention uses three microprocessor modules as redundant backups. Two of the microprocessor modules control two in-wheel braking motors on the diagonal respectively, and the other microprocessor module serves as a backup module after the failure of the conventional microprocessor module, greatly improving the safety redundancy of the design and enhancing the driving safety. Description of the Drawings

[0019] Figure 1 It is the overall schematic diagram of a novel wire-controlled EMB system architecture and method according to the present invention; In the figure: 1000 - Connector module; 1001 - Wheel speed current signal 4-to-8 processing module; 1002 - First CAN transceiver; 1003 - Second CAN transceiver; 1004 - Third CAN transceiver; 1005 - Fourth CAN transceiver; 1006 - First power management PMIC and 4-wheel speed signal processing module; 1007 - Second power management PMIC and 4-wheel speed signal processing module; 1008 - First microprocessor module; 1009 - Second microprocessor module; 1010 - Power supply switching switch; 1011 - First PMSM motor pre-driver; 1012 - Second PMSM motor pre-driver; 1013 - Third PMSM motor pre-driver; 1014 - Fourth PMSM motor pre-driver; 1015 - First MOS three-phase bridge; 1016 - Second MOS three-phase bridge; 1017 - Third MOS three-phase bridge; 1018 - Fourth MOS three-phase bridge; 1019 - Right front brake motor; 1020 - Left rear brake motor; 1021 - Left front brake motor; 1022 - Right rear brake motor; 1023 - Third microprocessor module; 1024 - First bus switch; 1025 - Second bus switch; 1026 - First bus driver; 1027 - Third bus switch; 1028 - Fourth bus switch; 1029 - Second bus driver; 1030 - First watchdog module; 1031 - Second watchdog module; 1032 - Fourth watchdog module; 1033 - Third watchdog module; 1035 - First redundant power supply switching logic module; 1036 - Second redundant power supply switching logic module; 1100 - Controller PCBA; 1: 1010 - Power supply switching switch; 2: 1035 - First redundant power supply switching logic module; 3: 1036 - Second redundant power supply switching logic module. Detailed implementation manners

[0020] The embodiments of the present invention will be described in detail below. Examples of the embodiments are shown in the drawings, where the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the drawings are exemplary and are intended to explain the present invention, and should not be construed as a limitation to the present invention. Embodiment

[0021] In this embodiment, as Figure 1, the present invention discloses a novel wire-controlled EMB system architecture, including: a controller PCBA1100, where the controller PCBA1100 includes a first microprocessor module 1008, a second microprocessor module 1009, a third microprocessor module 1023, a first bus switch 1024, a second bus switch 1025, a third bus switch 1027, a fourth bus switch 1028, a first bus driver 1026, and a second bus driver 1029; the first microprocessor module 1008 is connected to the first bus switch 1024 through a bus signal 1; the third microprocessor module 1023 is connected to the second bus switch 1025 through a bus signal 2; the second microprocessor module 1009 is connected to the fourth bus switch 1028 through a bus signal 3; the third microprocessor module 1023 is connected to the fourth bus switch 1028 through a bus signal 4.

[0022] Specifically, as a preference, the first microprocessor module 1008, the second microprocessor module 1009, and the third microprocessor module 1023 can integrate real-time monitoring and diagnosis functions, and the operation status of the system is monitored in real time through the first bus driver 1026 and the second bus driver 1029 to detect and handle faults in a timely manner.

[0023] In this embodiment, as Figure 1 , a first watchdog module 1030 is further provided between the first microprocessor module 1008 and the second bus switch 1025, and the first watchdog module 1030 transmits an enable signal 1 to the second bus switch 1025 to control its opening or closing; a second watchdog module 1031 is further provided between the third microprocessor module 1023 and the first bus switch 1024, and the second watchdog module 1031 transmits an enable signal 2 to the first bus switch 1024 to control its opening or closing; a third watchdog module 1033 is further provided between the second microprocessor module 1009 and the third bus switch 1027, and the third watchdog module 1033 transmits an enable signal 3 to the third bus switch 1027 to control its opening or closing; a fourth watchdog module 1032 is further provided between the third microprocessor module 1023 and the fourth bus switch 1028, and the fourth watchdog module 1032 transmits an enable signal 4 to the fourth bus switch 1028 to control its opening or closing.

[0024] Specifically, the first microprocessor module 1008, the second microprocessor module 1009, and the third microprocessor module 1023 operate independently as triple-redundant backup microprocessor modules and interact with each other in the form of a bus. The third microprocessor module 1023 serves as a backup microprocessor module for the first microprocessor module 1008 and the second microprocessor module 1009. When the first microprocessor module 1008 or the second microprocessor module 1009 fails, the system sends a fault message and the third microprocessor module 1023 takes over, which can greatly ensure driving safety.

[0025] In this embodiment, as Figure 1 , the first bus switch 1024 and the second bus switch 1025 are both connected to the first bus driver 1026 to ensure communication; the third bus switch 1027 and the fourth bus switch 1028 are both connected to the second bus driver 1029 to ensure communication.

[0026] Specifically, the first bus driver 1026 and the second bus driver 1029 can preferably use a design that supports multiple communication protocols, such as CANopen, EtherCAT, Modbus, etc.

[0027] In this embodiment, as Figure 1 , the controller PCBA 1100 further includes a first PMSM motor pre-driver 1011, a second PMSM motor pre-driver 1012, a third PMSM motor pre-driver 1013, a fourth PMSM motor pre-driver 1014, a first MOS three-phase bridge 1015, a second MOS three-phase bridge 1016, a third MOS three-phase bridge 1017, and a fourth MOS three-phase bridge 1018; the first PMSM motor pre-driver 1011 and the second PMSM motor pre-driver 1012 are both connected to the first bus driver 1026; the third PMSM motor pre-driver 1013 and the fourth PMSM motor pre-driver 1014 are both connected to the second bus driver 1029; the first MOS three-phase bridge 1015, the second MOS three-phase bridge 1016, the third MOS three-phase bridge 1017, and the fourth MOS three-phase bridge 1018 are respectively connected to the first PMSM motor pre-driver 1011, the second PMSM motor pre-driver 1012, the third PMSM motor pre-driver 1013, and the fourth PMSM motor pre-driver 1014.

[0028] Specifically, the PMSM motor pre-driver can process control signals from the microprocessor module, such as PWM signals, to control the speed and direction of the motor.

[0029] Particularly, in order to avoid the direct connection between the upper and lower bridge arms, a dead time needs to be configured. It is preferred to select a carrier frequency in the range of 15KHz to 20KHz and set the initial value of the dead time to 4us.

[0030] Specifically, for each PMSM motor pre-driver, a model integrated with functions such as overcurrent protection and short-circuit protection is preferably selected to prevent damage to the motor or the driver.

[0031] In this embodiment, as Figure 1 , it further includes a right front brake motor 1019, a left rear brake motor 1020, a left front brake motor 1021, and a right rear brake motor 1022; the right front brake motor 1019, the left rear brake motor 1020, the left front brake motor 1021, and the right rear brake motor 1022 are respectively connected to the first MOS three-phase bridge 1015, the second MOS three-phase bridge 1016, the third MOS three-phase bridge 1017, and the fourth MOS three-phase bridge 1018 through wiring harnesses; the wiring harnesses include U, V, and W three-phase drive signals and motor position sensor signals.

[0032] Specifically, each MOS three-phase bridge includes at least three upper-bridge MOS transistors and three lower-bridge MOS transistors, which respectively control the U / V / W three phases of the motor; according to the received control signal, the upper-bridge and lower-bridge MOS transistors corresponding to the phase of the motor rotation are turned on with the power supply.

[0033] Specifically, the wiring harness is preferably selected from twisted pair wires, shielded wires, etc. as an example, and the design should be easy to assemble, and interference should be reduced considering the wiring direction of the wiring harness.

[0034] In this embodiment, as Figure 1 , the controller PCBA 1100 further includes a first CAN transceiver 1002, a second CAN transceiver 1003, a third CAN transceiver 1004, a fourth CAN transceiver 1005, a first power management PMIC and a 4-wheel speed signal processing module 1006, a second power management PMIC and a 4-wheel speed signal processing module 1007, and a wheel speed current signal 4-to-8 processing module 1001; the first CAN transceiver 1002 and the second CAN transceiver 1003 are both connected to the first microprocessor module 1008; the second CAN transceiver 1003 and the third CAN transceiver 1004 are both connected to the second microprocessor module 1009; the wheel speed current signal 4-to-8 processing module 1001 is respectively connected to the first microprocessor module 1008 and the second microprocessor module 1009 through the first power management PMIC and the 4-wheel speed signal processing module 1006 and the second power management PMIC and the 4-wheel speed signal processing module 1007.

[0035] Specifically, two-way vehicle CAN signals are used as communication redundancy backups and communicate with the first microprocessor module 1008 through the first CAN transceiver 1002 and the second CAN transceiver 1003 respectively.

[0036] Specifically, the two sets of vehicle CAN signals are used as communication redundancy backups and communicate with the second microprocessor module 1009 through the third CAN transceiver 1004 and the fourth CAN transceiver 1005 respectively.

[0037] Specifically, a dual-channel CAN transceiver can be used as an option. The dual-channel CAN transceiver consists of two completely independent transceivers, which can provide two interfaces between the CAN protocol controller of the controller area network and the physical two-wire CAN bus to achieve high-speed communication, and at the same time has a low-power mode and a silent mode.

[0038] In this embodiment, as Figure 1 , it further includes a connector module 1000; the first CAN transceiver 1002, the second CAN transceiver 1003, the third CAN transceiver 1004, the fourth CAN transceiver 1005, the first microprocessor module 1008 and the second microprocessor module 1009 are all connected to the connector module 1000.

[0039] Specifically, each microprocessor module can independently monitor the corresponding CAN transceiver and trigger the corresponding switching mechanism when an abnormality is detected.

[0040] Specifically, each microprocessor module can integrate real-time monitoring and diagnosis functions, and monitor the operating status of the system in real time through each CAN transceiver to detect and handle faults in a timely manner.

[0041] In this embodiment, as Figure 1 , the controller PCBA 1100 further includes a power supply switching switch 1010, a first redundant power supply switching logic module 1035 and a second redundant power supply switching logic module 1036; the first redundant power supply switching logic module 1035 and the second redundant power supply switching logic module 1036 are respectively connected to the first microprocessor module 1008 and the second microprocessor module 1009; the power supply switching switch 1010 is also connected to the power supply switching switch 1010; the power supply switching switch 1010 is respectively connected to the first MOS three-phase bridge 1015, the second MOS three-phase bridge 1016, the third MOS three-phase bridge 1017 and the fourth MOS three-phase bridge 1018.

[0042] Specifically, each redundant power supply switching logic module can independently monitor the corresponding microprocessor module and trigger the power supply switching switch 1010 to perform power supply switching when an abnormality is detected.

[0043] Specifically, the first redundant power supply switching logic module 1035 and the second redundant power supply switching logic module 1036 can integrate fault detection functions. When a power supply abnormality is detected, not only the switching is triggered, but also an alarm signal can be sent to remind the maintenance personnel to check.

[0044] In this embodiment, as Figure 1 , the connector module 1000 further includes a power supply 1 and a power supply 2; both the power supply 1 and the power supply 2 are connected to the power supply switching switch 1010.

[0045] Specifically, the power supply switching switch 1010 can monitor the status of the two power supplies in real time and automatically switch to the standby power supply when a main power supply failure is detected. This seamless switching mechanism ensures that the system can still operate normally during a power supply failure and avoids system failure caused by power interruption.

[0046] In this embodiment, as Figure 1 , the connector module 1000 further includes a pedal signal 1 and a pedal signal 2; the pedal signal 1 and the pedal signal 2 are respectively connected to the first microprocessor module 1008 and the second microprocessor module 1009 through a heterogeneous pedal signal 1 and a heterogeneous pedal signal 2.

[0047] Specifically, the two microprocessor modules 1008 and 1009 process different pedal signals respectively. For example, one microprocessor can focus on real-time signal processing, while the other can be used for signal verification and fault diagnosis, so as to achieve more accurate signal processing and analysis.

[0048] In this embodiment, as Figure 1 , the first microprocessor module 1008, the second microprocessor module 1009 and the third microprocessor module 1023 are also connected to each other through an information interaction channel.

[0049] Specifically, each microprocessor module can monitor the status of other microprocessor modules in real time through the information interaction channel. Once a fault is detected, the system can quickly switch to the standby module, reducing system failure caused by single-point faults.

[0050] In this embodiment, the present invention also discloses a new method for wire-controlled EMB, which is used to implement a new wire-controlled EMB system architecture disclosed by the present invention, including: S1): The first bus switch 1024, the second bus switch 1025, the third bus switch 1027, and the fourth bus switch 1028 are in the normally open mode, and the switches are turned off when an input enable signal is received; in particular, the first bus switch 1024, the second bus switch 1025, and the third bus switch 1027 can be remotely controlled and their status can be monitored by using a network interface such as Ethernet or CAN bus, which is convenient for system maintenance and fault troubleshooting; S2): When the first microprocessor module 1008 is operating normally, the first microprocessor module 1008 provides an enabling signal through the first watchdog module 1030 to turn off the second bus switch 1025, and the third microprocessor module 1023 does not provide a watchdog signal. At this time, the first bus switch 1024 is normally turned on, and the first microprocessor module 1008 communicates with the first PMSM motor pre-driver 1011 and the second PMSM motor pre-driver 1012 through the first bus switch 1024 and the first bus driver 1026 to achieve motor drive. Specifically, during the communication process, data can be encrypted in real time as an option to ensure the security and integrity of the data and prevent data tampering; S3): When the second microprocessor module 1009 is operating normally, the second microprocessor module 1009 provides an enabling signal through the third watchdog module 1033 to turn off the third bus switch 1027, and the third microprocessor module 1023 does not provide a watchdog signal. At this time, the fourth bus switch 1028 is normally turned on, and the second microprocessor module 1009 communicates with the third PMSM motor pre-driver 1013 and the fourth PMSM motor pre-driver 1014 through the fourth bus switch 1028 and the second bus driver 1029 to achieve motor drive. Specifically, when the second microprocessor module 1009 is operating normally, intelligent load balancing is achieved through the bus driver 1029, and the distribution of communication tasks is dynamically adjusted according to the system load; S4): When the first microprocessor module 1008 fails or malfunctions, the output watchdog signal is interrupted, and the first watchdog module 1030 stops working. At this time, the second bus switch 1025 is turned on, and the third microprocessor module 1023 starts to intervene, providing a watchdog signal instead of the first microprocessor module 1008, providing an enabling signal through the second watchdog module 1031 to turn off the first bus switch 1024, and communicating with the first PMSM motor pre-driver 1011 and the second PMSM motor pre-driver 1012 through the first bus driver 1026 to achieve motor drive. Specifically, the third microprocessor module 1023 can integrate an adaptive switching strategy and adaptively select a switching strategy, such as fast switching or progressive switching, according to the severity of the fault and the system state; S5): When the second microprocessor module 1009 fails or malfunctions, the watchdog signal interrupt is output, and the third watchdog module 1033 stops working. At this time, the third bus switch 1027 is turned on, and the third microprocessor module 1023 starts to intervene, replacing the second microprocessor module 1009 to provide the watchdog signal, turning off the fourth bus switch 1028 by providing an enable signal through the fourth watchdog module 1032, and communicating with the third PMSM motor pre-driver 1013 and the fourth PMSM motor pre-driver 1014 through the second bus driver 1029 to achieve motor drive. Specifically, the third microprocessor module 1023 can integrate a fault isolation mechanism. When detecting the failure of the second microprocessor module 1009, the fault isolation mechanism is immediately started to cut off the connection between the faulty module and the system to prevent the spread of the fault.

[0051] The above are only the preferred embodiments of the present invention. It should be noted that for those of ordinary skill in the art, without departing from the principle of the present invention, several improvements can be made, and these improvements should also be regarded as the protection scope of the present invention.

Claims

1. A novel wire-controlled EMB system architecture, characterized in that: Including: A controller PCBA (1100), the controller PCBA (1100) includes a first microprocessor module (1008), a second microprocessor module (1009), a third microprocessor module (1023), a first bus switch (1024), a second bus switch (1025), a third bus switch (1027), a fourth bus switch (1028), a first bus driver (1026) and a second bus driver (1029); The first microprocessor module (1008) is connected to the first bus switch (1024) through bus signal 1; the third microprocessor module (1023) is connected to the second bus switch (1025) through bus signal 2; the second microprocessor module (1009) is connected to the fourth bus switch (1028) through bus signal 3; the third microprocessor module (1023) is connected to the fourth bus switch (1028) through bus signal 4; A first watchdog module (1030) is further provided between the first microprocessor module (1008) and the second bus switch (1025), and the first watchdog module (1030) transmits an enable signal 1 to the second bus switch (1025) to control its opening or closing; A second watchdog module (1031) is further provided between the third microprocessor module (1023) and the first bus switch (1024), and the second watchdog module (1031) transmits an enable signal 2 to the first bus switch (1024) to control its opening or closing; A third watchdog module (1033) is further provided between the second microprocessor module (1009) and the third bus switch (1027), and the third watchdog module (1033) transmits an enable signal 3 to the third bus switch (1027) to control its opening or closing; A fourth watchdog module (1032) is further provided between the third microprocessor module (1023) and the fourth bus switch (1028), and the fourth watchdog module (1032) transmits an enable signal 4 to the fourth bus switch (1028) to control its opening or closing; Both the first bus switch (1024) and the second bus switch (1025) are connected to the first bus driver (1026) to ensure communication; Both the third bus switch (1027) and the fourth bus switch (1028) are connected to the second bus driver (1029) to ensure communication.

2. The novel wire-controlled EMB system architecture according to claim 1, characterized in that: The controller PCBA (1100) further includes a first PMSM motor pre-driver (1011), a second PMSM motor pre-driver (1012), a third PMSM motor pre-driver (1013), a fourth PMSM motor pre-driver (1014), a first MOS three-phase bridge (1015), a second MOS three-phase bridge (1016), a third MOS three-phase bridge (1017) and a fourth MOS three-phase bridge (1018); The first PMSM motor pre-driver (1011) and the second PMSM motor pre-driver (1012) are both connected to the first bus driver (1026); the third PMSM motor pre-driver (1013) and the fourth PMSM motor pre-driver (1014) are both connected to the second bus driver (1029); the first MOS three-phase bridge (1015), the second MOS three-phase bridge (1016), the third MOS three-phase bridge (1017), and the fourth MOS three-phase bridge (1018) are respectively connected to the first PMSM motor pre-driver (1011), the second PMSM motor pre-driver (1012), the third PMSM motor pre-driver (1013), and the fourth PMSM motor pre-driver (1014).

3. The novel wire-controlled EMB system architecture according to claim 2, characterized in that: It further includes a right front brake motor (1019), a left rear brake motor (1020), a left front brake motor (1021), and a right rear brake motor (1022); the right front brake motor (1019), the left rear brake motor (1020), the left front brake motor (1021), and the right rear brake motor (1022) are respectively connected to the first MOS three-phase bridge (1015), the second MOS three-phase bridge (1016), the third MOS three-phase bridge (1017), and the fourth MOS three-phase bridge (1018) through a wire harness; the wire harness includes U, V, and W three-phase drive signals and motor position sensor signals.

4. The novel wire-controlled EMB system architecture according to claim 2, wherein: The controller PCBA (1100) further includes a first CAN transceiver (1002), a second CAN transceiver (1003), a third CAN transceiver (1004), a fourth CAN transceiver (1005), a first power management PMIC and 4-wheel speed signal processing module (1006), a second power management PMIC and 4-wheel speed signal processing module (1007), and a wheel speed current signal 4-to-8 processing module (1001); The first CAN transceiver (1002) and the second CAN transceiver (1003) are both connected to the first microprocessor module (1008); the second CAN transceiver (1003) and the third CAN transceiver (1004) are both connected to the second microprocessor module (1009); the wheel speed current signal 4-to-8 processing module (1001) is respectively connected to the first microprocessor module (1008) and the second microprocessor module (1009) through the first power management PMIC and 4-wheel speed signal processing module (1006) and the second power management PMIC and 4-wheel speed signal processing module (1007).

5. The novel wire-controlled EMB system architecture according to claim 4, wherein: It further includes a connector module (1000); the first CAN transceiver (1002), the second CAN transceiver (1003), the third CAN transceiver (1004), the fourth CAN transceiver (1005), the first microprocessor module (1008), and the second microprocessor module (1009) are all connected to the connector module (1000).

6. The novel wire-controlled EMB system architecture according to claim 5, wherein: The controller PCBA (1100) further includes a power supply switching switch (1010), a first redundant power supply switching logic module (1035), and a second redundant power supply switching logic module (1036); The first redundant power supply switching logic module (1035) and the second redundant power supply switching logic module (1036) are respectively connected to the first microprocessor module (1008) and the second microprocessor module (1009); the power supply switching switch (1010) is connected to the power supply switching switch (1010); the power supply switching switch (1010) is respectively connected to the first MOS three-phase bridge (1015), the second MOS three-phase bridge (1016), the third MOS three-phase bridge (1017), and the fourth MOS three-phase bridge (1018).

7. The novel wire-controlled EMB system architecture according to claim 6, characterized in that: The connector module (1000) further includes power supply 1 and power supply 2; both power supply 1 and power supply 2 are connected to the power supply switching switch (1010).

8. The novel wire-controlled EMB system architecture according to claim 5, characterized in that: The connector module (1000) further includes pedal signal 1 and pedal signal 2; pedal signal 1 and pedal signal 2 are respectively connected to the first microprocessor module (1008) and the second microprocessor module (1009) through heterogeneous pedal signal 1 and heterogeneous pedal signal 2.

9. The novel wire-controlled EMB system architecture according to claim 1, wherein: The first microprocessor module (1008), the second microprocessor module (1009), and the third microprocessor module (1023) are also connected to each other through information interaction channels.

10. A novel method for wire-controlled EMB is used to implement a novel wire-controlled EMB system architecture as claimed in claims 1 to 9, characterized in that: Including: S1): The first bus switch (1024), the second bus switch (1025), the third bus switch (1027), and the fourth bus switch (1028) are in the normally open mode and turn off when an input enable signal is received; S2): When the first microprocessor module (1008) is operating normally, the first microprocessor module (1008) provides an enable signal through the first watchdog module (1030) to turn off the second bus switch (1025), and the third microprocessor module (1023) does not provide a watchdog signal. At this time, the first bus switch (1024) is normally open, and the first microprocessor module (1008) communicates with the first PMSM motor pre-driver (1011) and the second PMSM motor pre-driver (1012) through the first bus switch (1024) and the first bus driver (1026) to achieve motor drive; S3): When the second microprocessor module (1009) is operating normally, the second microprocessor module (1009) provides an enable signal through the third watchdog module (1033) to turn off the third bus switch (1027), and the third microprocessor module (1023) does not provide a watchdog signal. At this time, the fourth bus switch (1028) is normally open, and the second microprocessor module (1009) communicates with the third PMSM motor pre-driver (1013) and the fourth PMSM motor pre-driver (1014) through the fourth bus switch (1028) and the second bus driver (1029) to achieve motor drive; S4): When the first microprocessor module (1008) fails or malfunctions, the watchdog signal is interrupted, and the first watchdog module (1030) stops working. At this time, the second bus switch (1025) is turned on, and the third microprocessor module (1023) starts to intervene, providing the watchdog signal instead of the first microprocessor module (1008). The first bus switch (1024) is turned off by providing an enabling signal through the second watchdog module (1031), and communication is carried out with the first PMSM motor pre-driver (1011) and the second PMSM motor pre-driver (1012) through the first bus driver (1026) to achieve motor drive; S5): When the second microprocessor module (1009) fails or malfunctions, the watchdog signal is interrupted, and the third watchdog module (1033) stops working. At this time, the third bus switch (1027) is turned on, and the third microprocessor module (1023) starts to intervene, providing the watchdog signal instead of the second microprocessor module (1009). The fourth bus switch (1028) is turned off by providing an enabling signal through the fourth watchdog module (1032), and communication is carried out with the third PMSM motor pre-driver (1013) and the fourth PMSM motor pre-driver (1014) through the second bus driver (1029) to achieve motor drive.

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