Strain-type piezoresistive effect sensitive element and manufacturing method thereof

Abstract

The present invention provides a strain-type piezoresistive effect sensitive element and a manufacturing method thereof, wherein the sensitive element includes an SOI wafer, a resistor, a second insulating layer and a second shielding layer, the SOI wafer includes a first shielding layer and a first insulating layer, the resistor is arranged on a side of the first insulating layer away from the first shielding layer, the second insulating layer is arranged on a side of the first insulating layer away from the first shielding layer and covers the resistor, and the second shielding layer covers the outer side of the second insulating layer and is located on a side of the resistor away from the first shielding layer; wherein, at least one of the first shielding layer and the second shielding layer is also surrounded by the circumferential outer side of the resistor, so that the resistor is surrounded by the first shielding layer and the second shielding layer on the upper and lower sides and the circumferential outer side, thereby improving the shielding effect of the strain-type piezoresistive effect sensitive element on the external electromagnetic field, avoiding the influence of the external electromagnetic field, and thus improving the strain accuracy of the detected object and the measurement stability.

Description

Technical Field

[0001] The present invention relates to the field of pressure / force sensors, and in particular to a strain-type piezoresistive effect sensitive element and a manufacturing method thereof. Background Art

[0002] A semiconductor silicon strain gauge, also known as a semiconductor strain gauge, is a sensitive element made using the piezoresistive effect of semiconductor single crystal silicon. The piezoresistive effect is the phenomenon in which the resistivity of a semiconductor crystal changes when a force is applied to it in a specific direction and the material deforms. Semiconductor strain gauges are attached to a specimen to measure its strain or to an elastic sensitive element to indirectly sense the external force being measured. The voltage across the strain gauge is then measured to determine the strain of the object to which it is attached. Semiconductor strain gauges offer advantages such as high sensitivity, minimal mechanical hysteresis, compact size, and low power consumption.

[0003] Existing semiconductor silicon strain gauges are usually not provided with a shielding structure, or a shielding layer is only provided on one side of the resistor. The shielding effect of the gauge against the external electromagnetic field is poor and the gauge is easily affected by the external electromagnetic field, resulting in inaccurate strain of the detected object. Summary of the Invention

[0004] The present invention aims to solve the problem that the existing semiconductor silicon strain gauge is easily affected by the external electromagnetic field, resulting in inaccurate strain of the detected object.

[0005] In order to solve the above technical problems, the present invention provides a strain-type piezoresistive effect sensitive element, which includes an SOI wafer, a resistor, a second insulating layer and a second shielding layer; the SOI wafer includes a first shielding layer and a first insulating layer, and the first insulating layer is arranged on one side of the first shielding layer; the resistor is arranged on the side of the first insulating layer away from the first shielding layer; the second insulating layer is arranged on the side of the first insulating layer away from the first shielding layer, the second insulating layer covers the resistor, and the second insulating layer and the first insulating layer cover the resistor; the second shielding layer covers the side of the second insulating layer away from the first shielding layer; at least one of the first shielding layer and the second shielding layer also surrounds the circumferential outside of the resistor.

[0006] In some schemes of the present application, the second shielding layer includes a shielding body and a shielding edge connected to the circumferential edge of the shielding body, the shielding body is located on the side of the second insulating layer away from the first insulating layer, and the shielding edge protrudes toward the side of the resistor and is located on the circumferential outside of the resistor.

[0007] In some schemes of the present application, the first shielding layer and the first insulating layer are stacked along the thickness direction of the SOI wafer, the resistor protrusion is arranged on the side surface of the first insulating layer away from the first shielding layer, and the shielding edge is connected to the first insulating layer on the side away from the shielding body.

[0008] In some embodiments of the present application, the second insulating layer includes an insulating body and an insulating edge connected to the circumferential edge of the insulating body and protruding to one side, the insulating body is located on the side of the resistor away from the first insulating layer, the insulating edge is located on the circumferential outside of the resistor, and the side of the insulating edge away from the insulating body is connected to the first insulating layer; the shielding body is located on the side of the insulating body away from the resistor, and the shielding edge is located on the circumferential inside of the insulating edge; or, the second insulating layer includes a silicon oxide layer and a silicon nitride layer, the silicon oxide layer covers the outer surface of the resistor, and the silicon nitride layer covers the outer surface of the silicon oxide layer.

[0009] In some solutions of the present application, the sensitive element further includes a third insulating layer, and the third insulating layer covers the outer side of the second shielding layer.

[0010] In some schemes of the present application, the resistor element includes four resistors, two of the four resistors are connected in series to form a first half-bridge; the other two resistors are connected in series to form a second half-bridge; the first half-bridge and the second half-bridge are symmetrically arranged; the first half-bridge and the second half-bridge are connected to an external circuit to form a Wheatstone bridge; each of the resistors includes multiple resistor bars and conductive connectors, the multiple resistor bars have the same length direction and are spaced apart along the width direction of the resistor bars, and the conductive connector connects two adjacent resistor bars so that the multiple resistor bars are connected in series in sequence.

[0011] In some solutions of the present application, the sensitive element is provided with a hollow through hole between at least two adjacent resistors; the hollow through hole is connected to the circumferential edge of the sensitive element; and the sensitive element has a smooth transition at the corner of the edge of the hollow through hole.

[0012] A method for manufacturing a strain-type piezoresistive effect sensitive element, comprising:

[0013] S100: Taking two wafers, at least one of the two wafers having a first shielding layer and at least one of the two wafers having a first insulating layer, bonding the two wafers to form an SOI wafer having the first shielding layer and the first insulating layer built therein;

[0014] S200: forming a resistor on the SOI wafer through photolithography, doping, annealing, diffusion, and etching processes; the resistor protrudes from a surface of the first insulating layer on a side away from the first shielding layer;

[0015] S300: forming a second insulating layer on the sidewalls and front surface of the resistor by oxidation, deposition, and photolithography processes; the second insulating layer protrudes from the surface of the first insulating layer and surrounds the resistor together with the first insulating layer;

[0016] S400: forming a low-impedance shielding layer on a surface of the second insulating layer by physical deposition or evaporation, and photolithographically etching the low-impedance shielding layer to form a second shielding layer; the second shielding layer protrudes from a surface of the first insulating layer on a side facing away from the first shielding layer, and covers an outer side of the second insulating layer;

[0017] S500: forming a third insulating layer on the surface and side surfaces of the second shielding layer by a deposition process;

[0018] S600: etching lead holes penetrating the second insulating layer, the second shielding layer and the third insulating layer by a photolithography process, forming connecting pins connected to the resistor by deposition and photolithography processes, and the connecting pins penetrate the lead holes for connection to an external circuit.

[0019] In some embodiments of the present application, step S100 includes:

[0020] S111: taking a wafer and providing a first conductive layer on the wafer to form a first wafer;

[0021] S112: Take another wafer and provide at least a first insulating layer on the wafer to form a second wafer;

[0022] S113: Bonding a first wafer provided with a first conductive layer to a second wafer provided with a first insulating layer to obtain an SOI wafer having a first conductive layer and a first insulating layer built therein, wherein the first shielding layer includes the first conductive layer.

[0023] In some schemes of the present application, in step S112, a second conductive layer is further provided on the second wafer, and the second conductive layer is stacked with the first insulating layer; the second conductive layer is provided on the outside of the first insulating layer; in step S113, the second conductive layer is bonded to the first conductive layer to form a first shielding layer.

[0024] In some schemes of the present application, S121: take a silicon wafer, and form a first insulating layer and a first shielding layer on the silicon wafer; the first shielding layer and the first insulating layer are stacked, and the first shielding layer is arranged on the outside of the first insulating layer; S122: take another wafer, and bond it to the silicon wafer with the first insulating layer and the first shielding layer formed thereon to obtain an SOI wafer with a first shielding layer and a first insulating layer built in.

[0025] In some embodiments of the present application, step S300 includes: S310: forming a silicon oxide layer on the circumferential outer side of the resistor and on a side away from the first insulating layer through an oxidation or deposition process; S320: forming a silicon nitride layer on the circumferential outer side of the silicon oxide layer and on a side away from the first insulating layer through a deposition and photolithography process; the silicon oxide layer and the silicon nitride layer form the second insulating layer.

[0026] In some solutions of the present application, after step S600, the following steps are further included: S700: forming a hollow through hole on the outside of the resistor by an etching process; S800: etching the wafer to separate it into individual sensitive elements.

[0027] It can be seen from the above technical solution that the beneficial effects of the present invention are:

[0028] The strain-type piezoresistive effect sensitive element of the present application includes an SOI wafer, a resistor, a second insulating layer and a second shielding layer. The SOI wafer includes a first shielding layer and a first insulating layer. The resistor is arranged on the side of the first insulating layer away from the first shielding layer. The second insulating layer is arranged on the side of the first insulating layer away from the first shielding layer and covers the resistor. The second shielding layer covers the outside of the second insulating layer and is located on the side of the resistor away from the first shielding layer. At least one of the first shielding layer and the second shielding layer is also surrounded by the circumferential outside of the resistor, so that the resistor is surrounded by the first shielding layer and the second shielding layer on the upper and lower sides and the circumferential outside, thereby improving the shielding effect of the strain-type piezoresistive effect sensitive element on the external electromagnetic field, avoiding the influence of the external electromagnetic field, and thus improving the strain accuracy of the detected object. The first insulating layer and the second insulating layer completely surround the resistor, thereby isolating the resistor from the first shielding layer and the second shielding layer, avoiding short circuit between the resistor and the first insulating layer and the second insulating layer, and avoiding leakage of the resistor. At the same time, the resistor can be completely wrapped, effectively reducing the impact of the external environment including humidity, dust, ions, etc. on the resistor, and improving the strain accuracy and measurement stability of the strain-type piezoresistive effect sensitive element on the detected object. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 It is a schematic cross-sectional view of a sensitive element in an embodiment when viewed from above.

[0030] Figure 2 yes Figure 1 Schematic cross-sectional view at AA.

[0031] Figure 3 FIG. 1 is a flow chart of a SOI wafer process in one embodiment.

[0032] Figure 4 FIG. 4 is a flow chart of a SOI wafer process in another embodiment.

[0033] Figure 5 This is a SOI wafer process flow chart in yet another embodiment.

[0034] The reference numerals are as follows: 1-SOI wafer; 11-first shielding layer; 12-first insulating layer; 13-base material layer; 2-resistor; 21-resistor; 201-first resistor; 202-second resistor; 203-third resistor; 204-fourth resistor; 205-first half bridge; 206-second half bridge; 211-resistor bar; 212-conductive connecting member; 2111-first resistor bar; 2112-second resistor bar; 2113-third resistor; Three resistor bars; 2114-fourth resistor bar; 3-connecting pin; 31-first connecting piece; 32-second connecting piece; 33-third connecting piece; 4-second insulating layer; 41-insulating body; 411-silicon oxide layer body; 412-silicon nitride layer body; 42-insulating edge; 421-silicon oxide layer edge; 422-silicon nitride layer edge; 5-second shielding layer; 51-shielding body; 52-shielding edge; 6-third insulating layer; 7-hollow through hole. DETAILED DESCRIPTION

[0035] Typical embodiments embodying the features and advantages of the present invention are described in detail in the following description. It should be understood that the present invention is capable of various variations in different embodiments without departing from the scope of the present invention, and that the descriptions and illustrations herein are intended to be illustrative rather than limiting.

[0036] In the description of this application, it should be understood that in the embodiments illustrated in the accompanying drawings, indications of directions or positional relationships (such as up, down, left, right, front, and back) are provided solely for the purpose of facilitating the description of this application and simplifying the description. They are not intended to indicate or imply that the devices or components referred to must have, be constructed, or operate in a specific orientation. These descriptions are appropriate when these components are in the positions shown in the accompanying drawings. If the descriptions of the positions of these components change, these directional indications will also change accordingly.

[0037] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of the technical features being referred to. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the described features. Throughout the description of this application, "plurality" means two or more, unless otherwise specifically defined.

[0038] The strain gauge piezoresistive effect sensitive element of the present application is in the form of a thin sheet. When the sensitive element is used to detect solids, it is attached to the surface of the object to be measured and connected to a circuit board so that the resistors on the sensitive element are connected to form a Wheatstone bridge. When the sensitive element is used to detect the fluid pressure of a fluid, the sensitive element is attached to the pressure seat of a pressure transmitter, the pressure of the fluid is detected by the pressure transmitter, and the sensitive element is connected to the circuit board so that the resistors on the sensitive element are connected to form a Wheatstone bridge. The following description uses the use of a sensitive element to detect the fluid pressure of a fluid as an example.

[0039] See Figure 1 and Figure 2 The sensitive element includes an SOI wafer 1, a resistor 2, a second insulating layer 4, a second shielding layer 5, a third insulating layer 6, and a connecting pin 3. The SOI wafer 1 includes a first shielding layer 11 and a first insulating layer 12. The resistor 2 is arranged on the side of the first insulating layer 12 away from the first shielding layer 11. The second insulating layer 4 is arranged on the side of the first insulating layer 12 away from the first shielding layer 11 and covers the resistor 2. The second shielding layer 5 covers the outside of the second insulating layer 4 and is located on the side of the resistor 2 away from the first shielding layer 11 and the circumferential outside. The third insulating layer 6 covers the outside of the second shielding layer 5. The connecting pin 3 passes through the second insulating layer 4, the second shielding layer 5, and the third insulating layer 6 and is electrically connected to the resistor 2. The end of the connecting pin 3 away from the resistor 2 is connected to an external circuit board and is electrically connected through the circuit on the circuit board to connect the resistor 2 to form a Wheatstone bridge. The circumferential outside refers to the outside of the sensitive element in the horizontal and vertical directions.

[0040] When in use, the side of the sensitive element facing away from the connecting pin 3 is attached to the pressure seat of the pressure transmitter, and the connecting pin 3 is electrically connected to the circuit board through the bonding wire. When the fluid applied to the pressure seat causes the pressure seat to deform, the sensitive element deforms along with the pressure seat, thereby changing the resistance value of the resistor 2 of the sensitive element. The change in the resistance value of the resistor 2 is detected by the circuit on the circuit board, and the pressure of the fluid that causes the pressure seat and the sensitive element to deform is obtained.

[0041] Specifically, the first shielding layer 11 and the first insulating layer 12 on the SOI wafer 1 are stacked along the thickness direction of the SOI wafer 1, and the first insulating layer 12 is located above the first shielding layer 11. A base material layer 13 of the SOI wafer 1 is provided on the side of the first shielding layer 11 facing away from the first insulating layer 12. The base material layer 13 is a silicon material layer or a glass material layer to protect the first shielding layer 11.

[0042] The first shielding layer 11 is a metal conductive layer formed on a wafer by a sputtering process, or a low-resistance conductive layer formed by high doping and annealing diffusion on the surface of a silicon wafer.

[0043] In one embodiment, the first insulating layer 12 is a silicon oxide layer, that is, a silicon oxide layer is provided on a wafer having the first shielding layer 11 formed thereon, thereby obtaining an SOI wafer including the first insulating layer 12 and the first shielding layer 11. In other embodiments, the first insulating layer 12 may also be a silicon nitride layer, or the first insulating layer 12 may include a silicon oxide layer and a silicon nitride layer.

[0044] In other embodiments, the first shielding layer 11 is not only disposed on the side of the first insulating layer 12 facing away from the resistor 2, but is also disposed on the circumferential outer side of the first insulating layer 12. That is, the first shielding layer 11 includes a main body and a surrounding edge, wherein the main body is located on the side of the first insulating layer 12 facing away from the resistor 2, and the surrounding edge is located on the circumferential outer side of the first insulating layer 12.

[0045] For example, a first shielding layer 11 with a certain thickness is first provided on the base material layer 13 of the wafer, and then the first shielding layer 11 is photoetched so that a groove is formed on the first shielding layer 11 (the bottom of the groove also has a certain thickness of the first shielding layer 11 material), and then a first insulating layer 12 is formed in the groove, forming an SOI wafer 1 structure in which the first shielding layer 11 is formed on the side of the first insulating layer 12 facing away from the resistor 2 and on the circumferential outside.

[0046] The resistor 2 is provided in a raised manner on the surface of the first insulating layer 12 facing away from the first shielding layer 11. Preferably, the resistor 2 is entirely provided in a raised manner on the surface of the first insulating layer 12 facing away from the first shielding layer 11. In other embodiments, the resistor 2 may also be provided in a partially raised manner on the surface of the first insulating layer 12 facing away from the first shielding layer 11.

[0047] The resistive element 2 includes four resistors 21. Two of the four resistors 21 are connected in series to form a first half-bridge 205, and the remaining two resistors 21 are connected in series to form a second half-bridge 206. The first half-bridge 205 and the second half-bridge 206 are electrically connected to the circuit board to form a Wheatstone bridge. It should be noted that the two resistors 21 of the first half-bridge 205 can also be connected in series via the circuit board, and the two resistors 21 of the second half-bridge 206 can also be connected in series via the circuit board. The first half-bridge 205 and the second half-bridge 206 are symmetrically arranged, ensuring a balanced overall structure of the sensitive element.

[0048] The first half-bridge 205 is used to detect and measure compressive stress, while the second half-bridge 206 is used to measure tensile stress. Alternatively, the resistors on one side of the first half-bridge 205 and the resistors on one side of the second half-bridge 206 are used to detect and measure compressive stress, while the resistors on the other side of the first half-bridge 205 and the resistors on the other side of the second half-bridge 206 are used to measure tensile stress. Alternatively, the first half-bridge 205 and the second half-bridge 206 can simultaneously measure compressive stress or tensile stress.

[0049] Preferably, the four resistors 21 have the same or nearly the same size and resistance value, and the manufacturing process of the four resistors 21 is the same, making their production more convenient, reducing costs, and having a zero offset voltage close to 0.

[0050] In Figure 1 In the illustrated embodiment, the four resistors 21 are respectively a first resistor 201, a second resistor 202, a third resistor 203, and a fourth resistor 204. The first resistor 201 and the second resistor 202 are symmetrically arranged along the transverse direction of the sensing element, and the third resistor 203 and the fourth resistor 204 are symmetrically arranged along the transverse direction of the sensing element, such that the first resistor 201, the second resistor 202, the third resistor 203, and the fourth resistor 204 are distributed in an approximate "field" shape, thereby making the overall structure of the sensing element more balanced. Among them, the first resistor 201 and the second resistor 202 are connected in series to form a first half-bridge 205, and the third resistor 203 and the fourth resistor 204 are connected in series to form a second half-bridge 206. It should be noted that it can also be that the first resistor 201 distributed along the longitudinal direction of the sensing element and the third resistor 203 are connected in series to form a first half-bridge 205, and the second resistor 202 distributed along the longitudinal direction of the sensing element and the fourth resistor 204 are connected in series to form a second half-bridge 206.

[0051] Each resistor 21 includes a plurality of resistor bars 211 and conductive connectors 212. The length directions of the plurality of resistor bars 211 are the same, and they are arranged at intervals along the width direction of the resistor bar 211 (the longitudinal direction of the sensing element). The conductive connectors 212 connect two adjacent resistor bars 211 to enable the plurality of resistor bars 211 to be connected in series in sequence. With such a setting, when the resistors 21 have the same resistance value, the strength of the sensing element is more uniform everywhere, so that the sensing element is more uniform when undergoing elastic deformation, and further the pressure detected by the sensing element is more accurate.

[0052] In Figure 1 In the illustrated embodiment, each resistor 21 includes 4 resistor bars 211. The 4 resistor bars 211 are successively a first resistor bar 2111, a second resistor bar 2112, a third resistor bar 2113, and a fourth resistor bar 2114. The first resistor bar 2111, the second resistor bar 2112, the third resistor bar 2113, and the fourth resistor bar 2114 are connected in series in sequence, that is, between the first resistor bar 2111 and the second resistor bar 2112, between the second resistor bar 2112 and the third resistor bar 2113, and between the third resistor bar 2113 and the fourth resistor bar 2114, all through the conductive connector 212 to achieve the series connection of the 4 resistor bars 211. It should be noted that the number of resistor bars 211 is not limited to 4, and can also be 2, 3, 5, or more. The distribution pattern of the plurality of resistor bars 211 can also be other shapes.

[0053] The lengths of the first resistor bar 2111, the second resistor bar 2112, the third resistor bar 2113, and the fourth resistor bar 2114 are all arranged transversely of the sensitive element and spaced apart in the longitudinal (width) direction of the sensitive element. The first resistor bar 2111, the second resistor bar 2112, the third resistor bar 2113, and the fourth resistor bar 2114 are flush at one end in the longitudinal direction. The conductive connector 212 is arranged longitudinally, and its ends are electrically connected to the corresponding ends of two adjacent resistors 21, respectively, making the overall structure more balanced. Furthermore, shortening the length of the conductive connector 212 facilitates the arrangement of the resistor element 2 structure on the SOI wafer 1, thereby facilitating production and reducing costs.

[0054] In one embodiment, the end of the resistor bar 211 that is flush with the end surface in the longitudinal direction is referred to as the first end, and the other end is referred to as the second end. Figure 1 As shown, the end of the resistance bar 211 of the first resistor 201 away from the second resistor 202 is the first end of the resistance bar 211 of the first resistor 201, and the end of the resistance bar 211 of the first resistor 201 close to the second resistor 202 is the second end of the resistance bar 211 of the first resistor 201; the end of the resistance bar 211 of the second resistor 202 away from the first resistor 201 is the first end of the resistance bar 211 of the second resistor 202, and the end of the resistance bar 211 of the second resistor 202 close to the first resistor 201 is the second end of the resistance bar 211 of the second resistor 202; the arrangement between the third resistor 203 and the fourth resistor 204 is the same as the arrangement between the first resistor 201 and the second resistor 202.

[0055] The first resistor bar 2111 and the fourth resistor bar 2114 are of equal length, the second resistor bar 2112 and the third resistor bar 2113 are of equal length, and the lengths of the first resistor bar 2111 and the fourth resistor bar 2114 are greater than the lengths of the second resistor bar 2112 and the third resistor bar 2113, so that there is space for arranging the connecting pins 3 between the second end of the first resistor bar 2111 and the second end of the fourth resistor bar 2114 and laterally outside the second end of the second resistor bar 2112 and the second end of the third resistor bar 2113, so that the arrangement of the resistors 21 of the sensitive element is more balanced, there is more space between two adjacent resistors 21 for arranging the connecting pins 3, and the structure is more compact.

[0056] Connecting pins 3 are provided between the first resistor 201 and the second resistor 202, and between the third resistor 203 and the fourth resistor 204. The connecting pins 3 between the first resistor 201 and the second resistor 202 are symmetrically arranged with the connecting pins 3 between the third resistor 203 and the fourth resistor 204, and are independent of each other. The following describes the structure of the connecting pins 3 using the connection structure between the first resistor 201, the second resistor 202, and the connecting pins 3 as an example.

[0057] The connecting pin 3 includes a first connector 31, a second connector 32, and a third connector 33, which are spaced apart. One end of the first connector 31 is electrically connected to the first resistor 201, specifically connected to the end of the first resistor bar 2111 of the first resistor 201, and the other end forms a solder pad. One end of the second connector 32 is electrically connected to the second resistor 202, specifically connected to the end of the first resistor bar 2111 of the second resistor 202, and the other end forms a solder pad. One end of the third connector 33 is electrically connected to the first resistor 201 and the second resistor 202, specifically connected to the end of the fourth resistor bar 2114 of the first resistor 201 and the fourth resistor bar 2114 of the second resistor 202, and the other end forms a solder pad. The third connector 33 realizes the series connection between the first resistor 201 and the second resistor 202, while also reducing the number of connectors. It should be noted that the third connector 33 can also be divided into two parts spaced apart, one part connecting to the end of the first resistor 201 away from the first connector 31 and forming a soldering pad, and the other part connecting to the end of the second resistor 202 away from the second connector 32 and forming a soldering pad. The two parts of the third connector 33 are then electrically connected through the circuit on the circuit board, thereby achieving a series connection between the first resistor 201 and the second resistor 202. The aforementioned soldering pads are both used to electrically connect to the circuit on the circuit board.

[0058] The connection structure between the connecting pin 3 and the third resistor 203 and the fourth resistor 204 is the same as the connection structure between the connecting pin 3 and the first resistor 201 and the second resistor 202 , and will not be repeated here.

[0059] The second insulating layer 4 is disposed on a side of the first insulating layer 12 away from the first shielding layer 11 . The second insulating layer 4 covers the resistor 2 . The second insulating layer 4 and the first insulating layer 12 surround the resistor 2 , thereby improving the physical isolation of the resistor 2 .

[0060] exist Figure 2In the embodiment shown, the second insulating layer 4 includes an insulating body 41 and an insulating edge 42 connected to the circumferential edge of the insulating body 41 and protruding to one side. The insulating body 41 is located on the side of the resistor 2 away from the first insulating layer 12, and the insulating edge 42 is located on the circumferential outside of the resistor 2. The side of the insulating edge 42 away from the insulating body 41 is connected to the first insulating layer 12, so that the second insulating layer 4 and the first insulating layer 12 completely cover the resistor 2, thereby achieving complete isolation of the resistor 2 from the first shielding layer 11, the second shielding layer 5 and the external environment, avoiding short circuit between the resistor 2 and the first insulating layer 12 and the second insulating layer 4, and avoiding leakage of the resistor 2, thereby improving the strain accuracy and stability of the strain-type piezoresistive effect sensitive element for the detected object.

[0061] The second insulating layer 4 includes a silicon oxide layer and a silicon nitride layer. The silicon oxide layer covers the outer surface of the resistor 2, and the silicon nitride layer covers the outer surface of the silicon oxide layer. Specifically, the insulating body 41 includes a silicon oxide layer body 411 and a silicon nitride layer body 412. The silicon oxide layer body 411 and the silicon nitride layer body 412 are stacked, and the silicon oxide layer body 411 is located between the silicon nitride layer body 412 and the top surface of the resistor 2. The insulating perimeter 42 includes a silicon oxide layer perimeter 421 and a silicon nitride layer perimeter 422. The silicon oxide layer perimeter 421 and the silicon nitride layer perimeter 422 are both arranged circumferentially outside the resistor 2, and the silicon oxide layer perimeter 421 is located between the silicon nitride layer perimeter 422 and the side surface of the resistor 2. The silicon oxide layer perimeter 421 is connected to the silicon oxide layer body 411 at one end in the thickness direction of the sensitive element, and the silicon nitride layer perimeter 422 is connected to the silicon nitride layer body 412 at one end in the thickness direction of the sensitive element. It should be noted that the second insulating layer 4 may also be a silicon oxide layer or a silicon nitride layer, that is, the second insulating layer 4 may include only one of the silicon oxide layer and the silicon nitride layer.

[0062] It should be noted that when the circumferential outer side of the resistor 2 and the side close to the first shielding layer 11 are both covered by the first insulating layer 12, the second insulating layer 4 can be arranged only on the side of the resistor 2 away from the first shielding layer 11, and the second insulating layer 4 and the first shielding layer 11 can completely cover the resistor 2.

[0063] The second shielding layer 5 covers the side of the second insulating layer 4 away from the first shielding layer 11, and at least one of the first shielding layer 11 and the second shielding layer 5 also surrounds the circumferential outside of the resistor 2, so that the resistor 2 is surrounded by the first shielding layer 11 and the second shielding layer 5 on both sides in the thickness direction of the sensitive element and on the circumferential outside, thereby improving the shielding effect of the sensitive element against external electromagnetic fields, reducing interference, and thus improving the strain accuracy of the detected object.

[0064] The second shielding layer 5 includes a shielding body 51 and a shielding edge 52 connected to the circumferential edge of the shielding body 51. The shielding body 51 is located on the side of the second insulating layer 4 facing away from the first insulating layer 12, that is, the shielding body 51 is located on the side of the insulating body 41 facing away from the resistor 2. The shielding edge 52 protrudes toward the side of the resistor 2 and is located circumferentially outside the resistor 2, that is, the shielding edge 52 is located circumferentially inside the insulating edge 42. This arrangement ensures that the resistor 2 is surrounded by the first shielding layer 11 and the second shielding layer 5 on both sides of the thickness direction of the sensitive element and on the circumferential outside. In this embodiment, although the shielding edge 52 is separated from the first shielding layer 11 by the first insulating layer 12, the thickness of the first insulating layer 12 is typically between tens of nanometers and hundreds of nanometers, making the impact of the shielding edge 52 and the first shielding layer 11 on the electromagnetic shielding effect of the resistor 2 at the first insulating layer 12 almost negligible.

[0065] In other embodiments, the shielding edge 52 may further extend to the first shielding layer 11 and be connected to the first shielding layer 11 to increase the coverage area of ​​the second shielding layer 5 on the resistor 2 , thereby improving the electromagnetic shielding effect.

[0066] It should be noted that when the first shielding layer 11 includes a main body and a surrounding edge, the main body is located on the side of the first insulating layer 12 away from the resistor 2, and the surrounding edge is located on the circumferential outside of the first insulating layer 12, the second shielding layer 5 can only cover the side of the resistor 2 away from the main body, and the circumferential outside of the resistor 2 is surrounded by the surrounding edge; or the shielding surrounding edge 52 and the surrounding edge form a parallel structure on the circumferential outside of the resistor 2, that is, the circumferential outside of the resistor 2 is surrounded by the shielding surrounding edge 52 and the surrounding edge.

[0067] The sensitive element further includes a third insulating layer 6, which covers the outer side of the second shielding layer 5 to protect the second shielding layer 5 and achieve electrical isolation between the pad of the connecting pin 3 and the second shielding layer 5. Figure 1 In the illustrated embodiment, the side of the shielding body 51 facing away from the resistor 2 and the circumferential outer side of the shielding edge 52 are both surrounded by the third insulating layer 6 .

[0068] See Figure 1 In one embodiment, the sensor element is provided with a hollow through-hole 7 between at least two adjacent resistors 21. The hollow through-hole 7 is arranged along the thickness direction of the sensor element and extends through both sides of the thickness direction of the sensor element. The provision of the hollow through-hole 7 allows the liquid tension to be effectively broken through during bonding and encapsulation with the pressure seat, achieving better filling and bubble removal, thereby improving the post-encapsulation connection strength between the sensor element and the pressure seat. Furthermore, the provision of the hollow through-hole 7 enables a better integration with the pressure seat, allowing the sensor element to follow the elastic deformation of the pressure seat with low loss, thereby making the pressure detected by the sensor more accurate.

[0069] In some embodiments, a hollow through hole 7 is also provided between two adjacent resistor bars 211 of the same resistor 21. For example, Figure 1 As shown, a hollow through hole 7 is also provided between the second resistor bar 2112 and the third resistor bar 2113 of the same resistor 21. It should be noted that a hollow through hole 7 can also be provided between the first resistor bar 2111 and the second resistor bar 2112 or between the third resistor bar 2113 and the fourth resistor bar 2114 of the same resistor 21.

[0070] In some embodiments, the hollow through hole 7 is connected to the circumferential edge of the sensitive element, further facilitating the breakthrough of liquid tension to improve the connection strength between the sensitive element and the pressure seat after packaging.

[0071] In some embodiments, the sensitive element has a smooth transition at the corner of the edge of the hollow through hole 7, which can effectively reduce the internal stress of the structure.

[0072] See Figure 1 , a method for manufacturing a strain-type piezoresistive effect sensitive element, comprising:

[0073] S100: Take two wafers, at least one of which is provided with a first shielding layer 11 and at least one of which is provided with a first insulating layer 12, and bond the two wafers together to form an SOI wafer 1 having the first shielding layer 11 and the first insulating layer 12 embedded therein. The SOI wafer 1 has a base material layer 13 provided on the side of the SOI wafer 1 in the thickness direction close to the first shielding layer 11 to protect the first shielding layer 11; and a silicon material layer provided on the side of the SOI wafer 1 in the thickness direction close to the first insulating layer 12 to facilitate the formation of a groove in the silicon material layer and the formation of the resistor 2 in subsequent processes.

[0074] See Figure 3In one embodiment, step S100 specifically includes: S111: taking a wafer, and setting a first conductive layer on the wafer to form a first wafer. The wafer material of the first wafer located below the first conductive layer forms a base material layer 13. S112: taking another wafer, and setting a first insulating layer 12 and a second conductive layer on the wafer, and the second conductive layer and the first insulating layer 12 are stacked; the second conductive layer is set on the outside of the first insulating layer 12 to form a second wafer. The wafer material under the second wafer forms a silicon material layer. S113: bonding the first wafer provided with the first conductive layer to the second wafer provided with the first insulating layer 12 to obtain an SOI wafer 1 with a first conductive layer and a first insulating layer 12 built in, and the first shielding layer 11 includes a first conductive layer. In this step, the first conductive layer of the first wafer is bonded to the second conductive layer of the second wafer to form a first shielding layer 11, and the base material layer 13 and the silicon material layer are respectively located on both sides of the thickness direction of the SOI wafer 1, and the bonding surface between the first wafer and the second wafer is the same material, which improves the stability after bonding.

[0075] The first conductive layer can be a metal conductive layer formed on the wafer by a sputtering process, or a low-resistance conductive layer formed by high-doping and annealing diffusion on the surface of the silicon wafer. Similarly, the second conductive layer can be a metal conductive layer formed on the wafer by a sputtering process, or a low-resistance conductive layer formed by high-doping and annealing diffusion on the surface of the silicon wafer.

[0076] See Figure 4 In one embodiment, step S112 may also involve only providing the first insulating layer 12 on the wafer to form the second wafer. In step S113, when the first wafer and the second wafer are bonded, the first conductive layer is bonded to the first insulating layer 12. The wafer used to form the first wafer is a silicon wafer or a glass sheet; the wafer used to form the second wafer is a silicon wafer.

[0077] See Figure 5 In one embodiment, step S100 specifically includes: S121: taking a silicon wafer, and forming a first insulating layer 12 and a first shielding layer 11 on the silicon wafer; the first shielding layer 11 and the first insulating layer 12 are stacked, and the first shielding layer 11 is arranged on the outside of the first insulating layer 12. S122: taking another wafer, and bonding it to the silicon wafer formed with the first insulating layer 12 and the first shielding layer 11, to obtain an SOI wafer 1 with the first shielding layer 11 and the first insulating layer 12 built in. Among them, in the SOI wafer 1 of this embodiment, the silicon wafer taken in step S121 forms a silicon material layer, and the wafer taken in step S122 is a silicon wafer or a glass sheet, which forms a basic material layer 13.

[0078] In the above description, the SOI wafer 1 is formed by bonding two wafers, which simplifies the process and makes the production more convenient, thereby reducing the cost of the sensitive components.

[0079] See Figure 1 S200: Resistor 2 is formed on SOI wafer 1 through photolithography, doping, annealing, diffusion, and etching processes. Specifically, a device layer is first formed on the silicon material layer of SOI wafer 1 through doping, annealing, and diffusion processes. Then, the device layer is photolithographically and etched to form resistor 2. Resistor 2 protrudes from the surface of first insulating layer 12 on the side facing away from first shielding layer 11.

[0080] S300: A second insulating layer 4 is formed on the circumferential outer side of the resistor 2 and on a side facing away from the first insulating layer 12 through oxidation, deposition, and photolithography processes. The second insulating layer 4 protrudes from the surface of the first insulating layer 12 and, together with the first insulating layer 12, surrounds the resistor 2. In this step, insulating material is first formed on the top and side surfaces of the structure obtained in step S200 through oxidation or deposition processes. Then, the insulating material located outside the side surfaces and the top surface of the resistor 2 is photolithographically etched, so that only a portion of the insulating material on the side surfaces and the insulating material on the top surface of the resistor 2 remains after photolithography, forming the second insulating layer 4. The insulating material on the side surfaces forms an insulating edge 42, and the insulating material on the top surface of the resistor 2 forms an insulating body 41.

[0081] When the second insulating layer 4 includes a silicon oxide layer and a silicon nitride layer, a silicon oxide material is first formed on the top surface and circumferential side surface of the resistor element 2 through an oxidation process, and then a portion of the silicon oxide material is removed through a photolithography process, leaving only the silicon oxide material located on the top surface and circumferential side surface of the resistor element 2 and having a preset thickness, thereby forming a silicon oxide layer; that is, S310: an oxide layer is formed on the circumferential outer side of the resistor element 2 and on the side facing away from the first insulating layer 12 through an oxidation or deposition process. Then, a silicon nitride layer is formed on the top surface and circumferential outer side of the silicon oxide layer through deposition and photolithography processes, the silicon nitride layer completely covering the silicon oxide layer, and the bottom surface of the silicon oxide layer contacts the top surface of the first insulating layer 12; that is, S320: a silicon nitride layer is formed on the circumferential outer side of the oxide layer and on the side facing away from the first insulating layer 12 through deposition and photolithography processes; the oxide layer and the silicon nitride layer form the second insulating layer 4.

[0082] When the second insulating layer 4 only includes a silicon oxide layer, a silicon oxide material is first formed on the top surface and circumferential side surfaces of the resistor element 2 through an oxidation process, and then part of the silicon oxide material is removed through a photolithography process, leaving only the silicon oxide material located on the top surface and circumferential side surfaces of the resistor element 2 and having a preset thickness, thereby forming a silicon oxide layer.

[0083] When the second insulating layer 4 only includes a silicon nitride layer, a silicon nitride layer is formed on the top surface and circumferential outer side of the silicon oxide layer through deposition and photolithography processes, the silicon nitride layer completely covers the silicon oxide layer, and the bottom surface of the silicon oxide layer contacts the top surface of the first insulating layer 12.

[0084] S400: A low-impedance shielding layer is formed on the surface of the second insulating layer 4 by physical deposition or evaporation, and the low-impedance shielding layer is photoetched to form a second shielding layer 5. Specifically, the low-impedance shielding material on the top surface and sidewalls of the structure obtained in step S300 is first formed by physical deposition or evaporation, and then the low-impedance shielding material is photoetched to form the second shielding layer 5. The low-impedance shielding material located on the sidewalls forms the shielding edge 52 of the second shielding layer 5, and the low-impedance shielding material located on the top surface of the second insulating layer 4 forms the shielding body 51 of the second shielding layer 5. After the second shielding layer 5 is formed, there is space on the outer side of the second shielding layer 5 for forming the third insulating layer 6. In this step, the second shielding layer 5 protrudes from the surface of the first insulating layer 12 facing away from the first shielding layer 11 and covers the outer side of the second insulating layer 4. When the bottom surface of the sidewall used to fill the shielding layer material is located on the top surface of the first shielding layer 11, the second shielding layer 5 protrudes from the surface of the first shielding layer 11 and covers the outer side of the second insulating layer 4.

[0085] S500 : forming a third insulating layer 6 on the surface and side surfaces of the second shielding layer 5 through a deposition process. The third insulating layer 6 covers the top surface and circumferential side surfaces of the second shielding layer 5 to protect the second shielding layer 5 .

[0086] S600: A lead hole is etched through the second insulating layer 4, the second shielding layer 5, and the third insulating layer 6 using a photolithography process. An insulating layer is formed on the sidewalls of the lead hole. Then, a connecting pin 3 for connecting to the resistor 2 is formed using deposition and photolithography processes. The connecting pin 3 extends through the lead hole. One end of the connecting pin 3 is connected to the resistor 2, and the other end forms a pad on the outside of the third insulating layer 6.

[0087] In some embodiments, after step S600, the method further includes: S700: forming a hollow through hole 7 on the circumferential outer side of the resistor 2 by an etching process. In the structure obtained after etching the hollow through hole 7, a second insulating layer 4, a second shielding layer 5, and a third insulating layer 6 of a certain thickness are provided on the circumferential outer side of the resistor 2.

[0088] The process of forming multiple sensitive elements on the same wafer at the same time also includes step S800: etching the wafer to separate it into individual sensitive elements.

[0089] In some embodiments, for thicker structures, wafer thinning is required to achieve the preset thickness requirement of the sensitive element. The wafer thinning process can be performed on the SOI wafer 1 obtained in step S100, or on the structure obtained in step S600 or step S700.

[0090] The strain-type piezoresistive effect sensitive element of the present application includes an SOI wafer, a resistor 2, a second insulating layer 4 and a second shielding layer 5. The SOI wafer includes a first shielding layer 11 and a first insulating layer 12. The resistor 2 is arranged on the side of the first insulating layer 12 away from the first shielding layer 11. The second insulating layer 4 is arranged on the side of the first insulating layer 12 away from the first shielding layer 11 and covers the resistor 2. The second shielding layer 5 covers the outside of the second insulating layer 4 and is located on the side of the resistor 2 away from the first shielding layer 11; wherein, at least one of the first shielding layer 11 and the second shielding layer 5 is also surrounded by the circumferential outside of the resistor 2, so that the resistor 2 is surrounded by the first shielding layer 11 and the second shielding layer 5 on the upper and lower sides and the circumferential outside, thereby improving the strain-type piezoresistive effect sensitive element's shielding effect on the external electromagnetic field, thereby improving the strain accuracy of the detected object. The first insulating layer 12 and the second insulating layer 4 completely surround the resistor 2, thereby isolating the resistor 2 from the first shielding layer 11 and the second shielding layer 5, avoiding a short circuit between the resistor 2 and the first insulating layer 12 and the second insulating layer 4, and avoiding leakage of the resistor 2. At the same time, it also isolates the resistor 2 from external moisture, dust and ions, thereby improving the strain accuracy and measurement stability of the strain-type piezoresistive effect sensitive element for the detected object.

[0091] While the present invention has been described with reference to several exemplary embodiments, it should be understood that the terms used are intended to be illustrative and exemplary rather than restrictive. Since the present invention can be embodied in many forms without departing from the spirit or essence of the invention, it should be understood that the above-described embodiments are not limited to any of the foregoing details, but should be interpreted broadly within the spirit and scope of the appended claims. All changes and modifications that fall within the scope of the claims or their equivalents are intended to be covered by the appended claims.

Claims

1. A method for manufacturing a strain-type piezoresistive effect sensitive element, characterized in that: The strain-type piezoresistive effect sensitive element comprises: An SOI wafer includes a base material layer, a first shielding layer, and a first insulating layer, wherein the first insulating layer is disposed on one side of the first shielding layer, the base material layer is disposed on a side of the first shielding layer facing away from the first insulating layer, and the first insulating layer is one of a silicon oxide layer and a silicon nitride layer, or a combination of the two; a resistor, disposed on a side of the first insulating layer facing away from the first shielding layer; a second insulating layer, disposed on a side of the first insulating layer away from the first shielding layer, the second insulating layer covering the resistor, and the second insulating layer and the first insulating layer covering the resistor; a second shielding layer covering a side of the second insulating layer facing away from the first shielding layer; at least one of the first shielding layer and the second shielding layer also surrounds the circumferential outside of the resistor; The manufacturing method comprises: S100: Taking two wafers, at least one of the two wafers being provided with a first shielding layer and at least one being provided with a first insulating layer, and bonding the two wafers to form an SOI wafer having the first shielding layer and the first insulating layer built therein; and providing a base material layer on a side of the SOI wafer close to the first shielding layer in a thickness direction to protect the first shielding layer; and providing a silicon material layer on a side of the SOI wafer close to the first insulating layer in a thickness direction to facilitate forming a groove in the silicon material layer and forming a resistor in a subsequent process; S200: forming a resistor on the SOI wafer through photolithography, doping, annealing, diffusion, and etching processes; the resistor protrudes from a surface of the first insulating layer on a side facing away from the first shielding layer; S300: forming a second insulating layer on the circumferential outer side of the resistor and on a side facing away from the first insulating layer through oxidation, deposition, and photolithography processes; the second insulating layer protrudes from the surface of the first insulating layer and surrounds the resistor together with the first insulating layer; S400: forming a low-impedance shielding layer on the surface of the second insulating layer by physical deposition or evaporation, and photolithographically etching the low-impedance shielding layer to form a second shielding layer; the second shielding layer protrudes from the surface of the first insulating layer on a side facing away from the first shielding layer, and covers the outer side of the second insulating layer; S500: forming a third insulating layer on the surface and side surfaces of the second shielding layer by a deposition process; S600: etching lead holes penetrating the second insulating layer, the second shielding layer and the third insulating layer by a photolithography process, forming connecting pins connected to the resistor by deposition and photolithography processes, wherein the connecting pins penetrate the lead holes for connection to an external circuit.

2. The method for manufacturing a strain-type piezoresistive effect sensitive element according to claim 1, characterized in that: The second shielding layer includes a shielding body and a shielding edge connected to the circumferential edge of the shielding body. The shielding body is located on the side of the second insulating layer away from the first insulating layer. The shielding edge protrudes toward the side of the resistor and is located on the circumferential outside of the resistor.

3. The method for manufacturing a strain-type piezoresistive effect sensitive element according to claim 2, wherein: The first shielding layer and the first insulating layer are stacked along the thickness direction of the SOI wafer, the resistor protrusion is arranged on the side surface of the first insulating layer away from the first shielding layer, and the side of the shielding edge away from the shielding body is connected to the first insulating layer.

4. The method for manufacturing a strain-type piezoresistive effect sensitive element according to claim 3, wherein: The second insulating layer includes an insulating body and an insulating edge connected to the circumferential edge of the insulating body and protruding to one side, the insulating body is located on the side of the resistor away from the first insulating layer, the insulating edge is located on the circumferential outside of the resistor, and the side of the insulating edge away from the insulating body is connected to the first insulating layer; the shielding body is located on the side of the insulating body away from the resistor, and the shielding edge is located on the circumferential inside of the insulating edge; or, The second insulating layer includes a silicon oxide layer and a silicon nitride layer. The silicon oxide layer covers the outer surface of the resistor, and the silicon nitride layer covers the outer surface of the silicon oxide layer.

5. The method for manufacturing a strain-type piezoresistive effect sensitive element according to claim 1, wherein: The sensitive element further includes a third insulating layer, and the third insulating layer covers the outer side of the second shielding layer.

6. The method for manufacturing a strain-type piezoresistive effect sensitive element according to claim 1, wherein: The resistor element includes four resistors, two of which are connected in series to form a first half-bridge, and the other two are connected in series to form a second half-bridge; the first half-bridge and the second half-bridge are symmetrically arranged; the first half-bridge and the second half-bridge are connected to an external circuit to form a Wheatstone bridge; Each of the resistors includes multiple resistor bars and conductive connectors. The length directions of the multiple resistor bars are consistent and are arranged at intervals along the width direction of the resistor bars. The conductive connector connects two adjacent resistor bars so that the multiple resistor bars are connected in series in sequence.

7. The method for manufacturing a strain-type piezoresistive effect sensor according to claim 6, characterized in that: The sensitive element is provided with a hollow through hole between at least two adjacent resistors; The hollow through hole is connected to the circumferential edge of the sensitive element; The sensitive element has a smooth transition at the corner of the edge of the hollow through hole.

8. The method for manufacturing a strain-type piezoresistive effect sensitive element according to claim 1, wherein: Step S100 includes: S111: taking a wafer and providing a first conductive layer on the wafer to form a first wafer; S112: Take another wafer and provide at least a first insulating layer on the wafer to form a second wafer; S113: Bonding a first wafer provided with a first conductive layer to a second wafer provided with a first insulating layer to obtain an SOI wafer having a first conductive layer and a first insulating layer built therein, wherein the first shielding layer includes the first conductive layer.

9. The method for manufacturing a strain-type piezoresistive effect sensitive element according to claim 8, characterized in that: In step S112, a second conductive layer is further provided on the second wafer, the second conductive layer being stacked on the first insulating layer; the second conductive layer is provided outside the first insulating layer; In step S113 , the second conductive layer is bonded to the first conductive layer to form a first shielding layer.

10. The method for manufacturing a strain-type piezoresistive effect sensitive element according to claim 1, wherein: S121: Take a silicon wafer and form a first insulating layer and a first shielding layer on the silicon wafer; the first shielding layer and the first insulating layer are stacked, and the first shielding layer is arranged on the outside of the first insulating layer; S122: Take another wafer and bond it to the silicon wafer formed with the first insulating layer and the first shielding layer to obtain an SOI wafer with the first shielding layer and the first insulating layer built in.

11. The method for manufacturing a strain-type piezoresistive effect sensitive element according to claim 1, wherein: Step S300 includes: S310: forming a silicon oxide layer on a circumferential outer side of the resistor and on a side facing away from the first insulating layer through an oxidation or deposition process; S320: forming a silicon nitride layer on the circumferential outer side of the silicon oxide layer and on a side facing away from the first insulating layer by deposition and photolithography processes; the silicon oxide layer and the silicon nitride layer form the second insulating layer.

12. The method for manufacturing a strain-type piezoresistive effect sensor according to claim 1, wherein: After step S600, the method further includes: S700: forming a hollow through hole on the outer side of the resistor by an etching process; S800: Wafer etching, separation into individual sensitive components.

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