SPAD macro pixel unit with dark count dynamic regulation and control function and detector

Abstract

The invention discloses an SPAD macro pixel unit with dark count dynamic regulation and control and a detector, and belongs to the field of single photon detection. The SPAD macro pixel unit comprises a signal processing unit, a dynamic bias unit, four groups of quenching circuits and a dark count detection unit, dark count detection is carried out by setting the dark count detection unit, SPAD bias voltage is dynamically adjusted, and the non-uniform phenomenon of SPAD array pixel dark count is solved; the dynamic bias unit is provided with a current steering circuit and adopts a current steering method, so that current does not need to be reestablished during conversion of charging and discharging of a capacitor, only the current is steered, the charging and discharging states are switched more quickly, output resistance is increased through a current source structure, and the power consumption is reduced. Therefore, the current is kept constant when the output voltage changes, the consistency of charging and discharging current is ensured, and the dynamic bias voltage regulation and control are more accurate.

Description

Technical Field

[0001] The present invention relates to a SPAD macro-pixel unit and a detector with dynamic regulation of dark counts, and belongs to the field of single-photon detection. Background Art

[0002] As a new type of photodetector, the single-photon avalanche diode is widely used in weak-light detection fields such as lidar ranging imaging, quantum communication, and fluorescence lifetime imaging due to its high sensitivity. In traditional SPAD detectors, a single SPAD forms a detection pixel, which is easily interfered by dark counts, thus affecting the accuracy of ranging and imaging. Therefore, a scheme in which multiple SPADs form a macro-pixel has emerged. This scheme can detect dark counts, and by setting a threshold, it can distinguish environmental light interference from real signal photons, thereby improving the stability of the pixel and reducing the influence of dark counts.

[0003] Although the macro-pixel scheme can reduce the influence of dark counts to a certain extent, due to process deviations, noise, etc. of the SPAD circuits in each pixel of the SPAD pixel array, the generated dark counts are also different, which leads to non-uniformity of dark counts in the overall SPAD detection array. During the imaging process, the SPAD pixel array needs to synchronously detect and convert the optical signals in the scene. If the dark counts of the pixels are non-uniform, it will cause inconsistent responses of different pixels to the same optical signal, resulting in unevenness in aspects such as brightness and contrast of the generated image, and affecting the overall consistency of the image. For some applications with high requirements for image quality, the consistency of the image is very important. Therefore, ensuring the uniformity of dark counts of the SPAD array pixels is a necessary and urgent requirement.

[0004] As is well known, the dark counts of SPADs are related to factors such as process and bias voltage. In a circuit, the over-bias voltage of SPADs is positively correlated with dark counts. A high over-bias voltage will increase the detection probability of SPADs, but at the same time, it will also increase dark counts. In traditional SPAD arrays, since the over-bias voltage is fixed, when the SPADs in the array are affected by factors such as process and working state, the dark counts of different SPADs will show non-uniformity. Therefore, adopting dynamic bias voltage is an effective solution to the non-uniformity of dark counts of SPAD array pixels. However, in existing dynamic bias voltage adjustment schemes, there are problems such as slow bias voltage adjustment rate and inaccurate dark count detection. Summary of the Invention

[0005] To solve the existing problems, the present invention provides a SPAD macro-pixel unit and a detector with dark count dynamic regulation. This solution designs a dark count detection unit, adopts a dark count detection and dynamic adjustment of the SPAD bias voltage scheme to solve the non-uniformity phenomenon of the dark count of the SPAD array pixels, and adopts a dynamic adjustment bias method to determine the adjustment amount according to the detection result of the real-time dark count. Since the SPAD adopts an anode negative voltage bias, the voltage magnitude required for the bias voltage applied to the SPAD cathode is smaller, the bias voltage range to be adjusted is smaller, and the complexity of the bias circuit is lower. Moreover, the solution of the present application sets up a current steering circuit and adopts a current steering method, so that it is not necessary to re-establish the current, but only to steer the current, making the speed state switching faster, and thus the bias voltage can be adjusted more quickly. In addition, this solution also sets up a compensation voltage circuit, and by providing a reference voltage negatively correlated with temperature, the bias voltage has strong stability at different temperatures.

[0006] The first object of the present invention is to provide a SPAD macro-pixel unit with dark count dynamic regulation. The SPAD macro-pixel unit includes: a signal processing unit, a dynamic bias unit, four groups of quenching circuits, and a dark count detection unit. The signal processing unit is used to determine whether to output an up signal or a down signal according to the relationship between the difference between the COUNT signal and the TRIG signal output by the dark count detection unit and a preset dark count threshold. The dynamic bias unit is used to dynamically adjust the bias voltage of the SPAD according to the up signal or the down signal output by the signal processing unit. The four groups of quenching circuits are used to quench and reset the SPAD and improve the accuracy of detecting real photons through mutual verification. The dark count detection unit is used to obtain a dark count detection result according to the VP voltage signal and the Vinv voltage signal output by the four groups of quenching circuits.

[0007] Optionally, the dynamic bias unit includes a compensation voltage circuit, a reference current circuit, a charge and discharge circuit, and a current steering circuit. Among them, the compensation voltage circuit is used to provide a reference voltage V negatively correlated with temperature for the reference current circuit. ref The charge and discharge circuit is used to realize the charge and discharge of the capacitor. The current steering circuit is used to realize the direction conversion of the current between the charging circuit and the discharging current. Both the reference current circuit and the charge and discharge circuit are formed by an operational amplifier, a resistor, and a MOS transistor to form a current source structure.

[0008] Optionally, the quenching circuit is simultaneously provided with a low-threshold inverter and a high-threshold inverter to ensure that the SPAD cathode voltage can output a high level as long as it is greater than 1 / 4 of the power supply voltage. Among them, the threshold of the low-threshold inverter is greater than or equal to half of the threshold of the high-threshold inverter.

[0009] Optionally, the dark count detection unit is provided with a voltage comparator. By setting the reference voltage Vref2 of the voltage comparator, it is determined whether the number of times the quenching circuit is triggered reaches a threshold, and further whether the photon signal generated by the SPAD is a real photon signal. At the same time, the dark count detection unit is also provided with a four-input OR gate, whose inputs are the Vinv voltage signals of four groups of quenching circuits and the output is the number of times the quenching circuit is triggered. Subtracting the number of real photon signals from the number of times the quenching circuit is triggered gives the dark count.

[0010] Optionally, in the dynamic bias unit, the compensation voltage circuit consists of a first PMOS transistor MP1, a second PMOS transistor MP2, a first NMOS transistor MN1, a low-threshold NMOS transistor MN-LVth, and a high-threshold NMOS transistor MN-HVth; the reference current circuit consists of a first amplifier A1, a second NMOS transistor MN2, a first resistor R1, and a second resistor R2; the charging circuit consists of a second resistor R2, a fourth resistor R4, a third amplifier A3, and a third PMOS transistor MP3; the discharging circuit consists of a first resistor R1, a third resistor R3, a second amplifier A2, and a third NMOS transistor MN3; the current steering circuit consists of a fourth NMOS transistor MN4, a fifth NMOS transistor MN5, a sixth NMOS transistor MN6, a seventh NMOS transistor MN7, a fourth PMOS transistor MP4, a fifth PMOS transistor MP5, and a fourth amplifier A4.

[0011] Optionally, the quenching circuit includes a buffer, a sixth PMOS transistor MP6, a seventh PMOS transistor MP7, an eighth PMOS transistor MP8, an eighth NMOS transistor MN8, a ninth NMOS transistor MN9, a tenth NMOS transistor MN10, an eleventh NMOS transistor MN11, a delay unit, an AND gate, and an inverter; among them, the low-threshold inverter composed of the seventh PMOS transistor MP7 and the tenth NMOS transistor MN10, and the high-threshold inverter composed of the eighth PMOS transistor MP8 and the eleventh NMOS transistor MN11.

[0012] Optionally, the dark count detection unit includes the ninth to twelfth PMOS transistors, a fifth resistor R5, a voltage comparator, and a four-input OR gate. Among them, the gates of the ninth to twelfth PMOS transistors are respectively connected to the VP voltage signal terminals of four groups of quenching circuits, the sources are connected to VDD, the drains are connected to the fifth resistor R5, and are simultaneously connected to the positive input terminal of the voltage comparator. The negative input terminal of the voltage comparator is connected to the reference voltage Vref2.

[0013] Optionally, the signal processing unit is a digital circuit composed of Verilog programming. A dark count threshold is preset to determine whether to output an up signal or a down signal according to the relationship between the difference between the COUNT signal and the TRIG signal output by the dark count detection unit and the preset dark count threshold.

[0014] The second object of the present invention is to provide a photodetector, and the pixel unit of the photodetector has the above-mentioned SPAD macro-pixel unit with dark count dynamic regulation.

[0015] The third object of the present invention is to provide the application of the above-mentioned photodetector in the fields of lidar ranging imaging, quantum communication, and fluorescence lifetime imaging.

[0016] The beneficial effects of the present invention are as follows:

[0017] (1) In the dynamic bias unit, both the reference current circuit and the charge and discharge circuit are composed of operational amplifiers, resistors, and MOS transistors, forming a current source structure. Therefore, the output resistance is increased, so that when the output voltage changes, the current remains constant, ensuring the consistency of the charge and discharge current. Thus, only by strictly controlling the time of the up and down signals can the change of the bias voltage be accurately controlled, and the dynamic bias voltage regulation can be made more precise.

[0018] (2) The dynamic bias unit adopts temperature compensation. By using two NMOS transistors with different turn-on voltages in the subthreshold region to provide a negative temperature coefficient voltage and combining it with a negative temperature coefficient resistor, temperature compensation is achieved, and the stability of the charge and discharge current under large-scale temperature changes is improved.

[0019] (3) The quenching circuit adopts anode negative voltage biasing, so that the bias voltage applied to the cathode only needs to be dynamically biased within a small range, reducing the complexity of the dynamic bias circuit.

[0020] (4) In the dark count detection unit, the threshold voltage of the comparator is provided externally, and different threshold voltages can be selected. The detection threshold can be changed to adapt to photon signals of different intensities. In actual use, only by adjusting the external voltage according to the intensity of the ambient light can the detection of photon signals of different intensities be realized, and it has stronger adaptability.

[0021] (5) By adjusting the over-bias voltage of the SPAD through the dark count, the dark count uniformity of the SPAD array can be guaranteed, and the accuracy of SPAD array imaging and ranging can be improved. Description of the Drawings

[0022] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the following drawings are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0023] Figure 1 It is a schematic diagram of the SPAD macro-pixel circuit structure with dark count dynamic regulation provided in an embodiment of the present invention.

[0024] Figure 2 Schematic diagram of the dynamic bias unit in the SPAD macro-pixel circuit with dark count dynamic regulation provided in an embodiment of the present invention.

[0025] Figure 3 Schematic diagram of the quenching circuit in the SPAD macro-pixel circuit with dark count dynamic regulation provided in an embodiment of the present invention.

[0026] Figure 4 Schematic diagram of the dark count detection unit in the SPAD macro-pixel circuit with dark count dynamic regulation provided in an embodiment of the present invention.

[0027] Figure 5 Simulation result diagram of a SPAD macro-pixel with dark count dynamic regulation in an embodiment of the present invention. Detailed implementation manners

[0028] To make the objectives, technical solutions and advantages of the present invention clearer, the following will further describe the embodiments of the present invention in detail with reference to the accompanying drawings.

[0029] Embodiment 1

[0030] This embodiment provides a SPAD macro-pixel with dark count dynamic regulation. Refer to Figure 1 , which includes a signal processing unit 100, a dynamic bias unit 200, a quenching circuit 300, and a dark count detection unit 400.

[0031] The signal processing unit 100 is a digital circuit composed of Verilog. Its inputs are the output COUNT signal and TRIG signal of the dark count detection unit. Among them, the COUNT signal is the real photon count, and the TRIG signal is the total number of triggers. Then, the number of TRIG signals minus the number of COUNT signals is the dark count:

[0032] When the dark count is greater than the set threshold within the set time, the signal processing unit will generate a down signal and send the down signal to the dynamic bias unit to control the dynamic bias unit to reduce the bias voltage provided for the SPAD, thereby reducing the dark count of the SPAD pixel.

[0033] When the dark count does not reach the threshold within the set time, the signal processing unit will generate an up signal and send the up signal to the dynamic bias unit to control the dynamic bias unit to increase the bias voltage of the SPAD, thereby increasing the detection probability of the SPAD.

[0034] As shown in Figure 2As shown, the dynamic bias unit 200 consists of a compensation voltage circuit, a reference current circuit, a charge and discharge circuit, and a current steering circuit. Among them, the compensation voltage circuit consists of a first PMOS transistor MP1, a second PMOS transistor MP2, a first NMOS transistor MN1, a low-threshold NMOS transistor MN-LVth, and a high-threshold NMOS transistor MN-HVth, and is used to provide a reference voltage V that is negatively correlated with temperature for the reference current circuit ref . The low-threshold NMOS transistor MN-LVth and the high-threshold NMOS transistor MN-HVth operate in the subthreshold region. The second PMOS transistor MP2 and the first PMOS transistor MP1 form a mirror current source, copying the current in the branch where the first PMOS transistor MP1 is located to the branch where the second PMOS transistor MP2 is located, and adjusting the aspect ratio of the first NMOS transistor MN1 so that the branch current can make the low-threshold NMOS transistor MN-LVth and the high-threshold NMOS transistor MN-HVth operate in the subthreshold region. The current of the high-threshold NMOS transistor MN-HVth operating in the subthreshold region is:

[0035]

[0036] The current of the low-threshold NMOS transistor MN-LVth is:

[0037]

[0038] Since their currents are the same, the reference voltage can be solved as:

[0039]

[0040] Where V thH , V thL are the threshold voltages of the high-threshold and low-threshold NMOS transistors, K H , K L are their aspect ratios, η is the subthreshold slope factor, and V T is the thermal voltage. And the relationship between the threshold voltage and temperature is:

[0041] V th =V th0 (1 - βΔT)

[0042] The relationship between the thermal voltage and temperature is:

[0043] V T =V T0 (1 + αΔT)

[0044] Where V th0 , V T0 are the threshold voltage and thermal voltage at room temperature, and α, β are the temperature coefficients. Then the reference voltage can also be expressed as:

[0045] Vref = V ref0 (1 - γΔT)

[0046] And the temperature coefficient can be changed by adjusting the aspect ratio of the high and low turn-on voltage NMOS.

[0047] The reference current circuit is composed of the first amplifier A1, the second NMOS transistor MN2, the first resistor R1, and the second resistor R2; due to the virtual short characteristic of the first amplifier A1, the voltages at the positive and negative input terminals are the same, and the resistance temperature characteristic is:

[0048] R = R0(1 - θΔT)

[0049] Then the current of the current source is:

[0050]

[0051] By changing the aspect ratio of the low-threshold NMOS transistor MN-LVth and the high-threshold NMOS transistor MN-HVth, the temperature coefficient of the reference voltage and the resistance can be made the same, so as to obtain a reference current with zero temperature coefficient.

[0052] The charging circuit is composed of the second resistor R2, the fourth resistor R4, the third amplifier A3, and the third PMOS transistor MP3; due to the virtual short characteristic of the third amplifier A3, the positive and negative input terminals are the same, and the value of the fourth resistor R4 is equal to that of the second resistor R2, then the current I2 = I1.

[0053] The discharging circuit is composed of the first resistor R1, the third resistor R3, the second amplifier A2, and the third NMOS transistor MN3; due to the virtual short characteristic of the second amplifier A2, the positive and negative input terminals are the same, and the value of the third resistor R3 is equal to that of the first resistor R1, then the current I3 = I1. Since negative feedback is utilized by the operational amplifier, the equivalent output resistances from the third NMOS transistor MN3 downward and from the third PMOS transistor MP3 upward are greatly increased, so that the charging and discharging currents remain unchanged under the condition of voltage change.

[0054] The current steering circuit consists of a fourth NMOS transistor MN4, a fifth NMOS transistor MN5, a sixth NMOS transistor MN6, a seventh NMOS transistor MN7, a fourth PMOS transistor MP4, a fifth PMOS transistor MP5, and a fourth amplifier A4. When both the up and down signals generated by the signal processing unit are at a low level, the fourth PMOS transistor MP4 and the fourth NMOS transistor MN4 in the current steering circuit are turned on, and the fifth PMOS transistor MP5 and the fifth NMOS transistor MN5 are turned off. The charging current I2 flows through the fourth PMOS transistor MP4 and the fourth NMOS transistor MN4 and is the same as the discharging current I3. The output voltage Vout on the capacitor C remains constant. When the up signal arrives, the fourth PMOS transistor MP4 is turned off and the fifth PMOS transistor MP5 is turned on. The charging current flowing through the fourth PMOS transistor MP4 is steered to the fifth PMOS transistor MP5 to charge the capacitor. When the down signal arrives, the fourth NMOS transistor MN4 is turned off and the fifth NMOS transistor MN5 is turned on. The discharging current flowing through the fourth NMOS transistor MN4 is steered to flow through the fifth NMOS transistor MN5 to discharge the capacitor C. The change in the output voltage Vout is:

[0055]

[0056] The capacitance value of the capacitor C and the charging and discharging currents are both constant values. Therefore, by only controlling the time of the up and down signals, the change in the bias voltage can be accurately controlled. In the circuit of the present invention, a current steering circuit is added and the current steering method is adopted, so that when switching the charging and discharging of the capacitor, there is no need to re - establish the current, but only to steer the current, thus making the switching of the charging and discharging states faster. And the sixth NMOS transistor MN6 and the seventh NMOS transistor MN7 are used as capacitors to eliminate the spike noise generated during the switch switching, making the change value of the output voltage more accurate.

[0057] In the dynamic bias unit, the source of the first NMOS transistor MN1 is connected to GND, and the gate and drain are connected to the drain of the first PMOS transistor MP1. The gates of the first PMOS transistor MP1 and the second PMOS transistor MP2 are connected to the drain of the first PMOS transistor MP1. The sources of the first PMOS transistor MP1 and the second PMOS transistor MP2 are connected to VDD, and the drain of the second PMOS transistor MP2 is connected to the drain and gate of the low-threshold NMOS transistor MN-LVth and to the gate of the high-threshold NMOS transistor MN-HVth. The drain of the high-threshold NMOS transistor MN-HVth is connected to the source of the low-threshold NMOS transistor MN-LVth and the positive input terminal of the first amplifier A1 in the reference current circuit, and the source is connected to GND. The output of the first amplifier A1 is connected to the gate of the second NMOS transistor MN2, and the negative input terminal is connected to the source of the second NMOS transistor MN2. One end of the second resistor R2 is connected to the drain of the second NMOS transistor MN2 and the positive input terminal of the third amplifier A3, and the other end is connected to VDD. One end of the first resistor R1 is connected to the source of the second NMOS transistor MN2 and the positive input terminal of the second amplifier A2 in the discharge circuit, and the other end is connected to GND. One end of the third resistor R3 is connected to the negative input terminal of the second amplifier A2 and the source of the third NMOS transistor MN3, and the other end is connected to GND. The gate of the third NMOS transistor MN3 is connected to the output terminal of the amplifier A2 and the gate of the sixth NMOS transistor MN6. The source and drain of the sixth NMOS transistor MN6 are connected to each other and to GND. One end of the fourth resistor R4 is connected to the negative input terminal of the third amplifier A3 and the source of the third PMOS transistor MP3, and the other end is connected to VDD. The gate of the third PMOS transistor MP3 is connected to the output terminal of the third amplifier A3 and the gate of the seventh NMOS transistor MN7. The source and drain of the seventh NMOS transistor MN7 are connected to each other and to VDD. The gate of the fourth NMOS transistor MN4 is connected to the inverted signal downn of the down signal, the drain is connected to the drain of the fourth PMOS transistor MP4 and the output terminal of the fourth amplifier A4, and the source is connected to the gate of the sixth NMOS transistor MN6. The gate of the fifth PMOS transistor MP5 is connected to the up signal, and the source is connected to the gate of the seventh NMOS transistor MN7. The gate of the fifth NMOS transistor MN5 is connected to the down signal, the drain is connected to the drain of the fifth PMOS transistor MP5 and the positive input terminal of the fourth amplifier A4, and the source is connected to the gate of the sixth NMOS transistor MN6. The gate of the fifth PMOS transistor MP5 is connected to the inverted signal upn of the up signal, and the source is connected to the gate of the seventh NMOS transistor MN7. The negative input of the fourth amplifier A4 is connected to its output terminal. The upper plate of the capacitor C is connected to the positive input terminal of the fourth amplifier A4, and the lower plate is connected to GND.

[0058] As Figure 3As shown in the figure, the pixel unit in the SPAD macro-pixel with dark count dynamic regulation provided by the present invention includes four identical quenching circuits 300. A 2×2 array is formed by the four quenching circuits, which not only increases the detection area but also enables mutual verification of the results of the four groups, making the detection result of the dark count detection unit more accurate.

[0059] Taking one of the quenching circuits as an example, its specific composition is introduced as follows:

[0060] The quenching circuit 300 includes a buffer, a sixth PMOS transistor MP6, a seventh PMOS transistor MP7, an eighth PMOS transistor MP8, an eighth NMOS transistor MN8, a ninth NMOS transistor MN9, a tenth NMOS transistor MN10, an eleventh NMOS transistor MN11, a delay unit, an AND gate, and an inverter; among them, a low-threshold inverter composed of the seventh PMOS transistor MP7 and the tenth NMOS transistor MN10, and a high-threshold inverter composed of the eighth PMOS transistor MP8 and the eleventh NMOS transistor MN11.

[0061] The input of the buffer is connected to the Vout signal output by the dynamic bias unit. The output of the buffer is connected to the source of the sixth PMOS transistor MP6. The drain of the sixth PMOS transistor MP6 is connected to the SPAD cathode. The SPAD anode is connected to the negative voltage VSS. The drain of the eighth NMOS transistor MN8 is connected to the SPAD cathode, the source is connected to GND, and the gate is controlled by an external enable signal EN. The seventh PMOS transistor MP7 and the tenth NMOS transistor MN10 are low-threshold MOS transistors, and their gates are connected and connected to the SPAD cathode. The source of the seventh PMOS transistor MP7 is connected to the low power supply voltage VDDL, the drain is connected to the drain of the tenth NMOS transistor MN10 and is connected to the gates of the eighth PMOS transistor MP8 and the eleventh NMOS transistor MN11. The source of the tenth NMOS transistor MN10 is connected to GND. The source of the eighth PMOS transistor MP8 is connected to VDD, and the drain is connected to the drain of the eleventh NMOS transistor MN11. The source of the eleventh NMOS transistor MN11 is connected to GND. The drain of the eighth PMOS transistor MP8 and the drain of the eleventh NMOS transistor MN11 output the VP voltage signal and are connected to the input of the inverter and the input of the delay unit. The output Vinv voltage signal of the inverter and the output VR voltage signal of the delay unit are connected to the input of the AND gate. The output of the AND gate is connected to the gate of the ninth NMOS transistor MN9. The drain of the ninth NMOS transistor MN9 is connected to the SPAD cathode, and the source is connected to GND. The VR voltage signal output by the delay unit is connected to the gate of the sixth PMOS transistor MP6.

[0062] The input of the quenching circuit 300 is provided by the output Vout of the dynamic biasing unit 200. Vout is connected to the input terminal of the buffer, and the output VB of the buffer (VB is equal to Vout) provides an over-biasing voltage for the cathode of the SPAD. The anode of the SPAD is connected to the negative voltage VSS, so that only a small dynamic range of VB is required to bias the SPAD.

[0063] In the quenching circuit, the eighth NMOS transistor MN8 is an enabling transistor. When the EN signal is at a high level, the voltage of the SAPD cathode is pulled down to GND, and the SPAD is in a disabled state. At this time, the low-threshold inverter composed of the seventh PMOS transistor MP7 and the tenth NMOS transistor MN10 outputs a high level, and the high-threshold inverter composed of the eighth PMOS transistor MP8 and the eleventh NMOS transistor MN11 outputs a low level, and the VR voltage is at a low level. At this time, although the sixth PMOS transistor MP6 is turned on, the pulling-down ability of the eighth NMOS transistor MN8 is higher than that of the sixth PMOS transistor MP6, and the VC voltage is still GND. The potentials of the other nodes are: the VP voltage is at a low level, the Vinv voltage is at a high level, the VQ voltage is at a low level, and the circuit is in a steady state. When the EN signal is at a low level, the disabled state of the SPAD is released, and the sixth PMOS transistor MP6 starts to pull up the VC voltage to the set VB bias voltage. At this time, the VP voltage is at a high level, the VR voltage is at a high level, the Vinv voltage is at a low level, the VQ voltage is at a low level, the SPAD is in reverse bias, and waits for photons to arrive.

[0064] For the quenching circuit, when a photon arrives, the SPAD detects the photon and undergoes avalanche. Since the sixth PMOS transistor MP6 turns off and acts as a quenching resistor to passively quench the SAPD, the voltage of the SPAD cathode VC drops. When the VC voltage drops below the threshold VDDL / 2 of the low-threshold inverter, the VP voltage becomes low, the Vinv voltage becomes high. Due to the action of the delay unit, the VR voltage is still high, the VQ voltage becomes high, and the quenching transistor, the ninth NMOS transistor MN9, turns on, and actively quenches to pull down the VC voltage to GND. When the delay passes, the VR voltage becomes low, the VQ voltage becomes low, the quenching transistor, the ninth NMOS transistor MN9, turns off, and the reset transistor, the sixth PMOS transistor MP6, turns on, and raises the SPAD cathode voltage to the bias voltage VB again, waiting for the next photon to arrive. From the quenching and reset process, it can be seen that whenever a photon is detected, the VP voltage will generate a low-level square-wave pulse, and the Vinv voltage will generate a high-level square-wave pulse for subsequent dark count detection.

[0065] As Figure 4 shown, the dark count detection unit 400 includes the ninth to twelfth PMOS transistors, the fifth resistor R5, a voltage comparator, and a four-input OR gate.

[0066] The gates of the ninth to twelfth PMOS transistors are respectively connected to the VP voltage signal terminals of four groups of quenching circuits, the sources are connected to VDD, the drains are connected to the fifth resistor R5, and are also connected to the positive input terminal of the voltage comparator. The negative input terminal of the voltage comparator is connected to the reference voltage Vref2.

[0067] When a group of quenching circuits is triggered, a low-level VP voltage signal will be generated, turning on the PMOS to generate a sampling current IM. IM generates a sampling voltage Vr through the fifth resistor R5. The sampling current IM is determined by the PMOS saturation current formula. By setting the reference voltage Vref2 of the voltage comparator, it can be judged whether the number of triggered quenching circuits reaches the threshold. If the threshold is reached, it can be determined as a real photon signal, and the COUNT signal will output a high level. The Vinv voltage signals of the four groups of quenching circuits are connected to a four-input OR gate. The four-input OR gate outputs a TRIG voltage signal, which is the number of times the quenching circuit is triggered. The number of times of the TRIG signal minus the number of times of the COUNT signal is the dark count. The TRIG signal and the COUNT signal will be input to the signal processing unit to perform dynamic biasing on the SPAD to ensure that the dark count is within the control range, thereby realizing the dark count uniformity of the overall SPAD array.

[0068] Figure 3 The simulation timing results of the pixel unit in a SPAD macro-pixel with dynamic dark count regulation according to the present invention are given. It can be seen that the up signal raises the SPAD bias voltage, and the down signal lowers the SPAD bias voltage. When the EN signal becomes low, the SPAD starts to be in the detection state. When the number of times the SPAD is triggered is greater than or equal to three, the COUNT signal generates a high level, and it is judged as a real photon. The present invention realizes the dark count detection and accurate dynamic biasing of the SPAD pixel, enabling it to achieve uniform dark counts in the SPAD array and improving the accuracy of photon imaging and ranging.

[0069] The above are only the preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

Claims

1. A SPAD macro-pixel unit with dark count dynamic regulation, characterized in that The SPAD macro-pixel unit includes: a signal processing unit, a dynamic bias unit, four groups of quenching circuits, and a dark count detection unit. The signal processing unit is used to determine whether to output an up signal or a down signal according to the relationship between the difference between the COUNT signal and the TRIG signal output by the dark count detection unit and a preset dark count threshold. The dynamic bias unit is used to dynamically adjust the bias voltage of the SPAD according to the up signal or the down signal output by the signal processing unit. The four groups of quenching circuits are used to quench and reset the SPAD and improve the accuracy of detecting real photons through mutual verification. The dark count detection unit is used to obtain a dark count detection result according to the VP voltage signal and the Vinv voltage signal output by the four groups of quenching circuits.

2. The SPAD macro pixel unit with dark count dynamic regulation according to claim 1, characterized in that, The dynamic bias unit includes a compensation voltage circuit, a reference current circuit, a charge and discharge circuit, and a current steering circuit. Among them, the compensation voltage circuit is used to provide a reference voltage V that is negatively correlated with temperature for the reference current circuit. ref , the charge and discharge circuit is used to charge and discharge the capacitor, the current steering circuit is used to realize the direction conversion of the current between the charging circuit and the discharging current, and both the reference current circuit and the charge and discharge circuit are formed into a current source structure by operational amplifiers, resistors, and MOS transistors.

3. The SPAD macro-pixel unit with dark count dynamic regulation according to claim 2, wherein, Both a low-threshold inverter and a high-threshold inverter are provided in the quenching circuit to ensure that a high level can be output as long as the cathode voltage of the SPAD is greater than 1 / 4 of the power supply voltage. Among them, the threshold of the low-threshold inverter is greater than or equal to half of the threshold of the high-threshold inverter.

4. The SPAD macro pixel unit with dark count dynamic regulation according to claim 3, characterized in that, The dark count detection unit is provided with a voltage comparator. By setting the reference voltage Vref2 of the voltage comparator, it is judged whether the number of times the quenching circuit is triggered reaches the threshold, and then it is judged whether the photon signal generated by the SPAD is a real photon signal. At the same time, the dark count detection unit is also provided with a four-input OR gate, whose inputs are the Vinv voltage signals of the four groups of quenching circuits and the output is the number of times the quenching circuit is triggered. Subtracting the number of real photon signals from the number of times the quenching circuit is triggered gives the dark count.

5. The SPAD macro-pixel unit with dark count dynamic regulation according to claim 4, characterized in that In the dynamic bias unit, the compensation voltage circuit is composed of a first PMOS transistor MP1, a second PMOS transistor MP2, a first NMOS transistor MN1, a low-threshold NMOS transistor MN-LVth, and a high-threshold NMOS transistor MN-HVth; the reference current circuit is composed of a first amplifier A1, a second NMOS transistor MN2, a first resistor R1, and a second resistor R2; the charging circuit is composed of a second resistor R2, a fourth resistor R4, a third amplifier A3, and a third PMOS transistor MP3; the discharging circuit is composed of a first resistor R1, a third resistor R3, a second amplifier A2, and a third NMOS transistor MN3; the current steering circuit is composed of a fourth NMOS transistor MN4, a fifth NMOS transistor MN5, a sixth NMOS transistor MN6, a seventh NMOS transistor MN7, a fourth PMOS transistor MP4, a fifth PMOS transistor MP5, and a fourth amplifier A4.

6. The SPAD macro-pixel unit with dark count dynamic regulation according to claim 5, wherein, The quenching circuit includes a buffer, a sixth PMOS transistor MP6, a seventh PMOS transistor MP7, an eighth PMOS transistor MP8, an eighth NMOS transistor MN8, a ninth NMOS transistor MN9, a tenth NMOS transistor MN10, an eleventh NMOS transistor MN11, a delay unit, an AND gate, and an inverter; among them, the low-threshold inverter is composed of the seventh PMOS transistor MP7 and the tenth NMOS transistor MN10, and the high-threshold inverter is composed of the eighth PMOS transistor MP8 and the eleventh NMOS transistor MN11.

7. The SPAD macro-pixel unit with dark count dynamic regulation according to claim 6, characterized in that The dark count detection unit includes the ninth to twelfth PMOS transistors, a fifth resistor R5, a voltage comparator, and a four-input OR gate. Among them, the gates of the ninth to twelfth PMOS transistors are respectively connected to the VP voltage signal terminals of four groups of quenching circuits, the sources are connected to VDD, the drains are connected to the fifth resistor R5, and are simultaneously connected to the positive input terminal of the voltage comparator. The negative input terminal of the voltage comparator is connected to the reference voltage Vref2.

8. The SPAD macro-pixel unit with dark count dynamic regulation according to claim 7, characterized in that, The signal processing unit is a digital circuit composed of Verilog programming, and a dark count threshold is preset to determine whether to output an up signal or a down signal according to the relationship between the difference between the COUNT signal and the TRIG signal output by the dark count detection unit and the preset dark count threshold.

9. A photodetector, characterized in that, The pixel unit of the photodetector is the SPAD macro pixel unit with dark count dynamic regulation according to any one of claims 1-8.

10. Application of the photodetector according to claim 9 in the fields of lidar ranging imaging, quantum communication, and fluorescence lifetime imaging.

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