An output current detection method, an electronic device, and a storage medium thereof

Abstract

The embodiment of the application discloses an output current detection method, an electronic device and a storage medium thereof. The method comprises the following steps: acquiring a midpoint current of a switching tube of a switched capacitor converter at a preset time in a switching cycle of the switched capacitor converter; the midpoint current is the sum of the currents of the switching tube; obtaining an output current of the switched capacitor converter based on the midpoint current; the midpoint current is equal to the output current at the preset time; and the preset time is set based on a duty cycle of the switching tube. According to the relationship between the switching tube current and the output current, the output current is obtained by detecting the switching tube current at a specific time, the system loss is reduced, the heat dissipation area is reduced, the power density of the switched capacitor converter is improved, and the possibility that the sampling result is affected by switching noise interference due to the additional sampling resistor in the high-frequency switching loop is avoided.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of switched capacitors, and in particular to an output current detection method, an electronic device and its storage medium. Background Technology

[0002] With the rapid development of artificial intelligence technology, the surge in computing power demand is driving the evolution of hardware systems towards low-voltage, high-current applications. Against this backdrop, DrMOS (Driver-MOSFET integrated module), with its high integration, high efficiency, and optimized thermal management capabilities, has become a core supporting technology for modern power systems. Compared to the high parasitic parameters and slow dynamic response caused by the separation of the driver and MOSFET in traditional discrete solutions, DrMOS integrates both into a single package, significantly reducing the board area (to as much as a quarter of traditional designs), while simultaneously reducing power loss by more than 15% and effectively suppressing high-frequency switching noise.

[0003] DrMOS has achieved a revolutionary breakthrough in current sampling technology. Traditional DCR sampling relies on inductor DC resistors and external RC circuits, which suffer from accuracy issues due to temperature coefficient differences, complex debugging, and the inability to detect inductor saturation in real time. DrMOS, however, employs single-die current mirror technology, directly outputting a mirror current that is strictly proportional to the inductor current through the CS pin, achieving precise cycle-by-cycle monitoring with an error controllable within ±2%. This technology features temperature self-compensation and is independent of on-resistance, duty cycle, and frequency variations, significantly improving the current detection accuracy of each phase. The DrMOS current sensing mechanism can replace the traditional output current sensing network composed of sampling resistors, reducing system losses, minimizing board space, and increasing power density.

[0004] In certain topologies using DrMOS, such as switch-cap converters, directly using the current signal generated by DrMOS cannot directly obtain the actual required output current, causing difficulties in output current detection and protection. Existing switch-cap converters generally employ an output current detection scheme, that is, a sampling resistor R is connected in series in the inductor and output capacitor circuit. CS The signal is then converted by signal processing circuits such as operational amplifiers, and then converted from analog to digital by the controller's ADC to finally obtain the output current. This method requires an additional sampling resistor, which increases system losses and requires a larger heat dissipation area, significantly reducing the power density of the power supply system. Furthermore, because the sampling resistor is located in a high-frequency switching circuit, it is susceptible to switching noise interference, which affects the final sampling result. Summary of the Invention

[0005] The main technical problem solved by the embodiments of the present invention is to provide an output current detection method, an electronic device and its storage medium, which can solve at least some of the defects of existing switched capacitor converters.

[0006] In a first aspect, embodiments of the present invention provide an output current detection method applied to a switched-capacitor converter, comprising: acquiring the midpoint current of the switching transistors of the switched-capacitor converter at a preset time during the switching cycle of the switched-capacitor converter; the midpoint current being the sum of the currents of the switching transistors; acquiring the output current of the switched-capacitor converter based on the midpoint current; the midpoint current being equal to the output current at the preset time; the preset time being set based on the duty cycle of the switching transistors.

[0007] Optionally, the switching transistors include two main switching transistors and two synchronous rectifier switching transistors. The step of acquiring the midpoint current of the switching transistors of the switched capacitor converter at a preset time during the switching cycle of the switched capacitor converter includes: acquiring the currents of the two main switching transistors and the two synchronous rectifier switching transistors at the preset time; summing the currents of the two main switching transistors and the two synchronous rectifier switching transistors to obtain a total switching current; converting the total switching current into a voltage signal; sampling and holding the voltage signal to obtain a digital quantity; and performing data conversion on the digital quantity to obtain the midpoint current.

[0008] Optionally, the switching transistors include two main switching transistors and two synchronous rectifier switching transistors. The step of acquiring the midpoint current of the switching transistors of the switched capacitor converter at a preset time during the switching cycle of the switched capacitor converter includes: acquiring the current of the two synchronous rectifier switching transistors at the preset time; summing the currents of the two synchronous rectifier switching transistors to obtain a total switching current; converting the total switching current into a voltage signal; sampling and holding the voltage signal to obtain a digital quantity; and performing data conversion on the digital quantity to obtain the midpoint current.

[0009] Optionally, when the total switching current is the sum of the currents of the two main switching transistors and the two synchronous rectifier switching transistors, the preset time is 0.5dT. PRD Where d is the duty cycle of the main switch transistor, and T PRD The switching period is denoted as .

[0010] Optionally, when the total switching current is the sum of the currents of the two synchronous rectifier switches, the preset time is (0.5 + 0.5d)T. PRD Where d is the duty cycle of the main switch transistor, and T PRD The switching period is denoted as .

[0011] Optionally, the step of performing data conversion on the digital quantity to obtain the midpoint current includes: multiplying the digital quantity by a conversion coefficient and dividing it by a current sensing coefficient to obtain the midpoint current; the conversion coefficient is the reference voltage of the analog-to-digital conversion unit divided by 2 to the power of n, where n is the number of bits of the analog-to-digital conversion unit; the current sensing coefficient is the resistance value of the sampling resistor, or the product of the sampling resistor and the ratio of the mirror current.

[0012] Optionally, the two main switching transistors include a first main switching transistor and a second main switching transistor; the first main switching transistor and the second main switching transistor are integrated in a first switching transistor driving integrated module, and the current of the first main switching transistor and the current of the second main switching transistor are obtained through the internal current mirror of the first switching transistor driving integrated module.

[0013] Optionally, the two synchronous rectifier switches include a first synchronous rectifier switch and a second synchronous rectifier switch; the first synchronous rectifier switch and the second synchronous rectifier switch are integrated in a second switch driver integrated module, and the current of the first synchronous rectifier switch and the current of the second synchronous rectifier switch are obtained through the internal current mirror of the second switch driver integrated module.

[0014] In a second aspect, embodiments of the present invention provide an electronic device, comprising: at least one processor; at least one network interface communicatively connected to a corresponding processor; and a memory communicatively connected to the at least one processor; wherein the network interface is used to establish a communication connection between the processor and other external devices; the memory stores instructions executable by the at least one processor, the instructions being executed by the at least one processor to enable the at least one processor to perform an output current detection method as described in the first aspect.

[0015] Thirdly, embodiments of the present invention provide a non-volatile computer storage medium storing computer-executable instructions that are executed by one or more processors, causing the one or more processors to perform an output current detection method as described in the first aspect.

[0016] The beneficial effects of the embodiments of the present invention are as follows: Unlike the prior art, the embodiments of the present invention are for switched capacitor converters. Based on the relationship between the switching current and the output current, the output current is obtained by detecting the switching current at a specific time. This avoids the need to add an additional sampling resistor in the output circuit, thereby reducing system losses, reducing the heat dissipation area and increasing the power density of the switched capacitor converter. It also avoids the possibility that adding a sampling resistor in the high-frequency switching circuit will easily affect the sampling results due to switching noise interference. Attached Figure Description

[0017] One or more embodiments are illustrated by way of example with reference to the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Elements having the same reference numerals in the drawings are denoted as similar elements. Unless otherwise stated, the figures in the drawings are not to be limited by scale.

[0018] Figure 1 This is a schematic diagram of the output current detection structure of an existing switched capacitor converter;

[0019] Figure 2 This is the circuit schematic of a switched capacitor converter;

[0020] Figure 3 It is a waveform diagram of the current of each switch when the duty cycle of the main switch is less than or equal to 50%;

[0021] Figure 4 This is a waveform diagram of the current of each switch when the duty cycle of the main switch is greater than 50%.

[0022] Figure 5 It is a current waveform diagram of two synchronous rectifier switches when the duty cycle of the main switch is less than or equal to 50%.

[0023] Figure 6 It is a current waveform diagram of the two synchronous rectifier switches when the duty cycle of the main switch is greater than 50%.

[0024] Figure 7 This is a schematic flowchart of an output current detection method provided by an embodiment of the present invention;

[0025] Figure 8 This is a schematic diagram of the output current detection structure of the first switched capacitor converter provided in the embodiments of the present invention;

[0026] Figure 9 This is a schematic diagram of the output current detection structure of the second switched capacitor converter provided in the embodiments of the present invention;

[0027] Figure 10 This is a schematic diagram of the output current detection structure of the third switched capacitor converter provided in the embodiments of the present invention;

[0028] Figure 11 This is a schematic diagram of the output current detection structure of the fourth switched capacitor converter provided in the embodiments of the present invention;

[0029] Figure 12 This is a schematic diagram of the structure of an electronic device provided by an embodiment of the present invention. Detailed Implementation

[0030] To facilitate understanding of this application, a more detailed description is provided below with reference to the accompanying drawings and specific embodiments. It should be noted that when an element is described as being "fixed to" another element, it can be directly on the other element, or one or more intermediate elements may exist between them. When an element is described as being "connected" to another element, it can be directly connected to the other element, or one or more intermediate elements may exist between them. The terms "upper," "lower," "inner," "outer," "bottom," etc., used in this specification indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application. Furthermore, the terms "first," "second," "third," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0031] Unless otherwise defined, all technical and scientific terms used in this specification have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to limit the scope of this application. The term "and / or" as used in this specification includes any and all combinations of one or more of the associated listed items.

[0032] Furthermore, the technical features involved in the different embodiments of this application described below can be combined with each other as long as they do not conflict with each other.

[0033] The technical solutions in this application will be described below with reference to the accompanying drawings.

[0034] Reference Figure 1 Existing switched-capacitor converters mainly consist of a main circuit section and a control and detection section. The main circuit section includes: a power input terminal V... IN Switching transistors Q1, Q5, Q2, Q6, and leap capacitor C FLY Inductor L1, Inductor L2, Output capacitor C O and load resistance R LOAD The control and detection section includes a sampling resistor R connected in series in the output current path. CS The system includes a signal processing module 10 and a control module 20. The control module 20 contains an analog-to-digital conversion unit 210 and a data conversion unit 220.

[0035] The working principle of the existing switched capacitor converter is as follows: power supply voltage V IN Through the high-frequency switching action of switching transistors Q1, Q5, Q2, and Q6, and via the leap capacitor C... FLYInductors L1 and L2 transfer energy to the output terminal, forming a stable output voltage V. OUT Supply load R LOAD Application. During the operation of the switched capacitor converter, four switching transistors switch according to a specific control strategy to achieve efficient energy transfer.

[0036] For output current detection, the existing technology uses the following method: [The text abruptly shifts to a seemingly unrelated topic about inductors L1 and L2, and output capacitor C]. O A sampling resistor R is connected in series in the circuit. CS When the current I OUT Flow through sampling resistor R CS At this time, a voltage drop proportional to the current will be generated across its terminals. This voltage signal is conditioned and amplified by the signal processing module 10, and then sent to the analog-to-digital conversion unit 210 (such as ADC) inside the control module 20 for analog-to-digital conversion. The converted digital signal is processed by the data conversion unit 220 to finally obtain the output current I. OUT The numerical value.

[0037] The signal processing module 10 in the prior art typically includes signal processing circuits such as operational amplifiers, and mainly performs the following functions: amplification of voltage signals: due to the sampling resistor R CS The resistance value is usually small (milliohm level), and the generated voltage signal is weak, requiring amplification; signal filtering: removes high-frequency switching noise and extracts the real current signal; level conversion: adjusts the signal to the acceptable input range of the ADC of the control module 20; common-mode rejection: reduces common-mode interference through differential structure; the analog-to-digital converter 210 in the control module 20 is responsible for converting the analog voltage signal into a digital signal, while the data conversion unit 220 is responsible for processing the digital signal into the actual output current value according to the preset algorithm.

[0038] Although the above scheme can achieve the detection of output current, it has several technical drawbacks: First, the series sampling resistor R CS This leads to additional power loss, especially in high-current applications. Even with a very small sampling resistor (such as 1mΩ), significant power loss (P=I) can occur under current conditions of tens of amperes. 2 Secondly, the heat generated by the sampling resistor requires additional heat dissipation design, increasing the heat dissipation area requirement; thirdly, additional sampling resistors, signal conditioning circuits, and other components significantly increase the board area occupied, reducing the power density of the power supply system; fourthly, the sampling resistor is located in a high-frequency switching circuit, making it susceptible to switching transients and electromagnetic interference (EMI), reducing sampling accuracy; finally, the temperature coefficient, parasitic inductance, and other parameters of the sampling resistor also affect measurement accuracy, especially in working environments with large temperature variations.

[0039] For modern power systems, especially those powering high-performance computing devices such as AI hardware, power density, efficiency, and accurate current monitoring are becoming increasingly important. With the trend towards low voltage and high current, the shortcomings of traditional sampling resistor solutions are becoming more apparent. For example, in a typical AI accelerator power supply scenario with 12V input and 1V / 100A output, sampling resistor solutions may result in an additional 1-3% efficiency loss, while also increasing the complexity of heat dissipation design by 30-50%.

[0040] Example of power loss calculation introduced by sampling resistor: Assuming a 1mΩ sampling resistor is used, at a current of 100A, the power loss is P = I. 2 R = 100 2 ×0.001 = 10W. The total output power of the power system is P = V × I = 1V × 100A = 100W. Therefore, the loss introduced by the sampling resistor accounts for 10 / 100 = 10%, significantly reducing system efficiency. Furthermore, a heat dissipation scheme needs to be designed for the additional 10W of heat, increasing system size and cost.

[0041] The signal processing flow of existing technical solutions is also relatively complex: first, the current signal must be converted into a voltage signal, then amplified and filtered, then converted into a digital signal by an ADC, and finally processed to obtain the output current value. This multi-stage signal processing not only increases design complexity but may also introduce various errors and delays, affecting the system's dynamic performance and protection response speed.

[0042] Reference Figure 2 The main circuit block diagram of the switched capacitor converter includes: input voltage terminal VIN, first main switch Q1, first synchronous rectifier switch Q5, second main switch Q2, second synchronous rectifier switch Q6, and leap capacitor C. FLY First inductor L1, second inductor L2, output capacitor C O and load resistance R LOAD . Figure 2 The key current paths are also marked, including the first inductor current I1, the second inductor current I2, and the output current I. OUT .

[0043] The switched-capacitor converter operates as follows: the first main switch Q1 and the second main switch Q2 act as the primary control switches, with equal duty cycles within a single switching cycle, and their switching signals are 180 degrees out of phase. The first synchronous rectifier switch Q5 and the first main switch Q1 have complementary conduction states, and the second synchronous rectifier switch Q6 and the second main switch Q2 have complementary conduction states. Through the coordinated operation of these four switches, efficient energy transfer from the input to the output is achieved.

[0044] In a switched-capacitor converter, the leap capacitor CFLY Acting as a charge pump, the switching transistor charges and discharges, forming a specific energy conversion path in conjunction with the two inductors L1 and L2. When the circuit is operating stably, the currents I1 and I2 in the two inductors L1 and L2 are directly related to the output current I. OUT That is, the output current I OUT It is equal to the sum of the currents of the two inductors, I1 and I2.

[0045] The switched-capacitor converter operates as follows: the first main switch Q1 and the second main switch Q2 act as the primary control switches, with equal duty cycles within a single switching cycle, and their switching signals are 180 degrees out of phase. The first synchronous rectifier switch Q5 and the first main switch Q1 have complementary conduction states, and the second synchronous rectifier switch Q6 and the second main switch Q2 have complementary conduction states. Through the coordinated operation of these four switches, efficient energy transfer from the input to the output is achieved.

[0046] In a switched-capacitor converter, the leap capacitor C FLY Acting as a charge pump, the switching transistor charges and discharges, forming a specific energy conversion path in conjunction with the two inductors L1 and L2. When the circuit is operating stably, the currents I1 and I2 in the two inductors L1 and L2 are directly related to the output current I. OUT That is, the output current I OUT It is equal to the sum of the currents of the two inductors, I1 and I2.

[0047] It should be noted that inductors L1 and L2 can be two windings of a coupled inductor, or they can be two independent inductors.

[0048] Depending on the duty cycle of the main switching transistor, the operating state of a switched capacitor converter can be divided into two cases: a duty cycle less than or equal to 50% and a duty cycle greater than 50%. (Refer to...) Figure 3 and Figure 4 The two scenarios will be analyzed in detail below.

[0049] like Figure 3 As shown, when the duty cycle d of main switch Q1 and main switch Q2 is less than or equal to 50%, in one complete switching cycle T PRD The circuit goes through four different operating stages (I, II, III, IV). Figure 3 The control signals (PWM1, PWM5, PWM2, PWM6) of the four switching transistors and the current waveforms of each channel are shown, including the inductor currents i1(t) and i2(t), as well as the current combination i1(t) of the main switching transistor and the synchronous rectifier switching transistor. M1 (t) and i M2 (t).

[0050] When the duty cycle is less than or equal to 50%, a switching cycle can be divided into the following four stages:

[0051] Stage I (0~d): The first main switch Q1 is turned on, and the second synchronous rectifier switch Q6 is turned on;

[0052] Phase II (d~0.5): The first synchronous rectifier switch Q5 is turned on, and the second synchronous rectifier switch Q6 is turned on;

[0053] Phase III (0.5~0.5+d): The first synchronous rectifier switch Q5 is turned on, and the second main switch Q2 is turned on;

[0054] Phase IV (0.5+d~1): The first synchronous rectifier switch Q5 is turned on, and the second synchronous rectifier switch Q6 is turned on.

[0055] The currents flowing through switching transistors Q1, Q2, Q5, and Q6 during each switching stage are shown in the table below:

[0056] Phase I Phase II Phase III Phase IV Duration ratio d 0.5-d d 0.5-d <![CDATA[i Q1 (t)]]> <![CDATA[i1(t)]]> 0 0 0 <![CDATA[i Q2 (t)]]> 0 0 <![CDATA[i2(t)]]> 0 <![CDATA[i Q5 (t)]]> 0 <![CDATA[i1(t)]]> <![CDATA[i1(t)+i2(t)]]> <![CDATA[i1(t)]]> <![CDATA[i Q6 (t)]]> <![CDATA[i2(t)]]> <![CDATA[i2(t)]]> 0 <![CDATA[i2(t)]]> <![CDATA[i M1 (t)=i Q1 (t)+i Q5 (t)]]> <![CDATA[i1(t)]]> <![CDATA[i1(t)]]> <![CDATA[i1(t)+i2(t)]]> <![CDATA[i1(t)]]> <![CDATA[i M2 (t)=i Q2 (t)+i Q6 (t)]]> <![CDATA[i2(t)]]> <![CDATA[i2(t)]]> <![CDATA[i2(t)]]> <![CDATA[i2(t)]]> <![CDATA[i Q_56 (t)=i Q5 (t)+i Q6 (t)]]> <![CDATA[i2(t)]]> <![CDATA[i1(t)+i2(t)]]> <![CDATA[i1(t)+i2(t)]]> <![CDATA[i1(t)+i2(t)]]>

[0057] Table 1

[0058] Analyze the current flowing through each switch in each stage:

[0059] First main switch Q1: conducts only in stage I, with a current of i1(t); Second main switch Q2: conducts only in stage III, with a current of i2(t); First synchronous rectifier switch Q5: conducts in stages II, III and IV, with currents of i1(t), i1(t)+i2(t) and i1(t) respectively; Second synchronous rectifier switch Q6: conducts in stages I, II and IV, with a current of i2(t).

[0060] If i M1 (t) represents the sum of the currents of the first main switch Q1 and the first synchronous rectifier switch Q5, then i M1 (t) is i1(t) throughout the entire period, and only includes the i2(t) part in stage III. If i M2 (t) represents the sum of the currents of the second main switch Q2 and the second synchronous rectifier switch Q6, then i M2 (t) is i2(t) throughout the entire period.

[0061] As shown in Table 1, when the duty cycle d of the main switch is less than or equal to 50%, the sum of the currents i of the first main switch Q1, the second main switch Q2, the first synchronous rectifier switch Q5, and the second synchronous rectifier switch Q6 in stages I, II, and IV is... M1 (t)+i M2(t), which is exactly equal to the inductor current i1(t) + i2(t); in stages II, III, and IV, the sum of the currents of the first synchronous rectifier switch Q5 and the second synchronous rectifier switch Q6 is i Q_56 It is exactly equal to the inductor current i1(t) + i2(t).

[0062] like Figure 4 As shown, when the duty cycle d of the main switching transistors Q1 and Q2 is greater than 50%, the circuit also experiences four different operating stages, but the duration of each stage is different from before:

[0063] Phase I (0~d-0.5): The first main switch Q1 and the second main switch Q2 are turned on simultaneously;

[0064] Phase II (d-0.5~0.5): The first main switch Q1 and the second synchronous rectifier switch Q6 are turned on;

[0065] Stage III (0.5~d): The first main switch Q1 and the second main switch Q2 are turned on;

[0066] Stage IV (d~1): The first synchronous rectifier switch Q5 and the second main switch Q2 are turned on.

[0067] The currents flowing through switching transistors Q1, Q2, Q5, and Q6 during each switching stage are shown in the table below:

[0068] Phase I Phase II Phase III Phase IV Duration ratio d-0.5 1-d d-0.5 1-d <![CDATA[i Q1 (t)]]> <![CDATA[i1(t)+i2(t)]]> <![CDATA[i1(t)]]> <![CDATA[i1(t)+i2(t)]]> 0 <![CDATA[i Q2 (t)]]> <![CDATA[i2(t)]]> 0 <![CDATA[i2(t)]]> <![CDATA[i2(t)]]> <![CDATA[i Q5 (t)]]> 0 0 0 <![CDATA[i1(t)+i2(t)]]> <![CDATA[i Q6 (t)]]> 0 <![CDATA[i2(t)]]> 0 0 <![CDATA[i M1 (t)=i Q1 (t)+i Q5 (t)]]> <![CDATA[i1(t)+i2(t)]]> <![CDATA[i1(t)]]> <![CDATA[i1(t)+i2(t)]]> <![CDATA[i1(t)+i2(t)]]> <![CDATA[i M2 (t)=i Q2 (t)+i Q6 (t)]]> <![CDATA[i2(t)]]> <![CDATA[i2(t)]]> <![CDATA[i2(t)]]> <![CDATA[i2(t)]]> <![CDATA[i Q_56 (t)=i Q5 (t)+i Q6 (t)]]> 0 <![CDATA[i2(t)]]> 0 <![CDATA[i1(t)+i2(t)]]>

[0069] Table 2

[0070] Analyze the current flowing through each switch in each stage:

[0071] The first main switch Q1 is turned on in stages I, II and III, with currents of i1(t)+i2(t), i1(t) and i1(t)+i2(t) respectively.

[0072] The second main switch Q2 is turned on in stages I and III, with currents of i2(t) and i2(t) respectively.

[0073] The first synchronous rectifier switch Q5 is turned on in stage IV, and the current is i1(t) + i2(t);

[0074] The second synchronous rectifier switch Q6 is turned on in stage II, and the current is i2(t).

[0075] As can be seen from Table 2, when the duty cycle d of the main switch is greater than 50%, in stage II, the sum of the currents i of the first main switch Q1, the second main switch Q2, the first synchronous rectifier switch Q5, and the second synchronous rectifier switch Q6 is... M1(t)+i M2 (t), which is exactly equal to the inductor current i1(t) + i2(t); in stage IV, the sum of the currents of the first synchronous rectifier switch Q5 and the second synchronous rectifier switch Q6 is i Q_56 It is exactly equal to the inductor current i1(t) + i2(t).

[0076] See Figure 3 and Figure 4 By selecting a switching cycle time of 0.5dT PRD The sum of the currents of the first main switch Q1, the second main switch Q2, the first synchronous rectifier switch Q5, and the second synchronous rectifier switch Q6 is sampled. At this point, regardless of whether the duty cycle is greater than or less than 50%, there is a stage where the sum of the total currents of the four switches equals the sum of the currents of the two inductors i1(t) and i2(t); and 0.5dT PRD If the time is the middle of this stage, then sampling the total current of the four switches at that time can yield the average value of the output current during the switching cycle.

[0077] Similarly, see Figure 5 and Figure 6 By selecting a switching cycle time (0.5 + 0.5d)T PRD The sum of the currents of the first synchronous rectifier switch Q5 and the second synchronous rectifier switch Q6 is sampled. Regardless of whether the duty cycle is greater than or less than 50%, the following stage occurs: the sum of the total currents of the first synchronous rectifier switch Q5 and the second synchronous rectifier switch Q6 equals the sum of the two inductor currents i1(t) and i2(t); and (0.5+0.5d)T PRD If the time is the middle of this stage, then sampling the total current of the first synchronous rectifier switch Q5 and the second synchronous rectifier switch Q6 at this time can yield the average value of the output current during the switching cycle.

[0078] pass Figure 2 , Figure 3 , Figure 4 , Figure 5 , Figure 6 Analysis reveals that the specific topology and switching timing of the switched-capacitor converter create a deterministic relationship between the switching transistor current and the output current. This embodiment utilizes a method combining switching transistor current information and duty cycle information to achieve accurate measurement of the output current without the need for traditional output current sampling resistors, providing a non-destructive output current detection solution for switched-capacitor converters.

[0079] Reference Figure 7 This application provides a flowchart of an output current detection method, which is applied to... Figure 2The switched capacitor converter shown mainly includes the following two steps:

[0080] Step S100: At a preset time in the switching cycle of the switched capacitor converter, obtain the midpoint current of the switching transistor of the switched capacitor converter.

[0081] In a switched-capacitor converter, the switching transistors operate according to a specific control strategy, and the current switches between different paths. The theoretical analysis above shows that at a specific moment within the switching cycle, the midpoint current of the switching transistors (i.e., the sum of the switching transistor currents) has a deterministic relationship with the output current.

[0082] Determining the preset timing is crucial to this method. By analyzing the operating state of the switched-capacitor converter under different duty cycles, it is determined when the midpoint current of the switching transistor equals the output current. This preset timing is set based on the duty cycle of the switching transistor to ensure that the sampled current value accurately reflects the output current.

[0083] For cases where the duty cycle d is less than or equal to 0.5, the preset time can be 0.5dT. PRD T PRD The switching period is 0.5dT; for cases where the duty cycle d is greater than 0.5, the preset time can also be 0.5dT. PRD Under different duty cycle conditions, there may be multiple preset time points, but this embodiment uses the above-mentioned time point as an example for explanation.

[0084] It is worth noting that the midpoint current is represented as the sum of the currents of the switching transistors. It can be the sum of the currents of all the switching transistors or the sum of the currents of some of the switching transistors, depending on the specific detection scheme.

[0085] Step S200: Obtain the output current of the switched capacitor converter based on the midpoint current.

[0086] Since the midpoint current equals the output current at a preset time, the output current of the switched capacitor converter can be directly obtained based on the midpoint current obtained in step S100 without additional calculation or conversion.

[0087] In practical applications, the acquired midpoint current may need to undergo signal processing before it can be used as the final output current value. Signal processing may include steps such as amplification, filtering, and analog-to-digital conversion to improve signal quality and accuracy.

[0088] In some embodiments of this application, step S100 specifically includes the following steps:

[0089] Step S110: At a preset time, obtain the current of the two main switching transistors and the two synchronous rectifier switching transistors.

[0090] In a switched-capacitor converter, the four key switching transistors include two main switches (Q1, Q2) and two synchronous rectifier switches (Q5, Q6). Determining the preset timing is the core of the entire current detection method, which specifically depends on the duty cycle d of the main switches and the switching period TPRD.

[0091] When the duty cycle d of the main switch is less than or equal to 0.5, the preset time can be 0.5dT. PRD When the duty cycle d is greater than 0.5, the preset time is also 0.5dT. PRD The precise selection of the preset time ensures that the sum of the currents of the four switching transistors at that moment is exactly equal to the output current.

[0092] There are multiple ways to obtain the current of the switching transistor. Figure 8 In the diagram, four switching transistors Q1, Q5, Q2, and Q6 are marked with current detection points IS1, IS5, IS2, and IS6, respectively. These detection points are used to acquire the current signal flowing through each switching transistor during its conduction period.

[0093] There are several possible implementation methods: for example, a trace can be led out from the source or drain terminal of the switching transistor, and the current can be directly measured by a current sensor (such as a Hall sensor, current transformer, etc.) in the signal processing module 10. Alternatively, the signal processing module can integrate a current detection circuit to separately detect the current of the high-side switching transistors (Q1 / Q2) and the low-side switching transistors (Q5 / Q6).

[0094] Step S120: Summarize the currents of the two main switching transistors and the two synchronous rectifier switching transistors to obtain the total switching current.

[0095] Current summing is the process of combining the currents of four switching transistors in a specific way to obtain the total switching current. Summarizing can be implemented in hardware or software, depending on system design requirements and resource constraints. Hardware summarizing is typically achieved through current node connections; according to Kirchhoff's current law, connecting multiple current signals to the same node naturally results in current superposition. Another hardware implementation uses a current adder, building a current summing circuit based on an operational amplifier to achieve precise current addition. Alternatively, multiple current signals can share the same sampling resistor, allowing the currents to naturally superimpose and be converted into corresponding voltage signals.

[0096] The software aggregation first obtains the current values ​​of the four switches separately, and then performs digital addition in the processor. For most implementations, the total switching current can be expressed as the algebraic sum of the currents of the four switches, i.e., I0. Q_all =IQ1 + IQ2 + IQ5 + IQ6. At a carefully selected preset time, this total switching current is exactly equal to the output current of the switched capacitor converter.

[0097] exist Figure 8 In the illustrated embodiment, a hardware aggregation method is used. The current signals of the four switching transistors are introduced into the signal processing module 10, and are directly aggregated into a total current signal through internal circuitry.

[0098] Step S130: Convert the total switching current into a voltage signal.

[0099] from Figure 8 As can be seen, the output of signal processing module 10 is connected to control module 20 through two ports, CS+ and CS-. This indicates that signal processing module 10 converts the summarized current signal into a differential voltage signal for subsequent analog-to-digital conversion processing.

[0100] Current-to-voltage conversion is typically achieved through a precision sampling resistor R. CS Implementation. Unlike traditional solutions, the sampling resistor here is not located in the power loop, but inside the signal processing circuit. Therefore, the power loss on the resistor is minimal and will not significantly affect the system efficiency.

[0101] The conversion circuit may contain the following functional blocks: converting a current signal into a voltage signal, with the conversion ratio determined by the sampling resistor R. CS Decision (V = I × R) CS) The system includes a current-to-voltage converter; a differential amplifier that converts a single-ended voltage signal into a differential signal to improve anti-interference capability; a filter circuit that removes high-frequency noise and extracts the effective components of the current signal; and a level adjustment circuit that ensures the output signal is within the input range of the analog-to-digital converter 210, maximizing the utilization of the dynamic range of the analog-to-digital converter 210 and improving measurement accuracy. It should be noted that the current-to-voltage conversion process introduces a certain gain coefficient, which needs to be compensated for in subsequent data processing to ensure the accuracy of the final calculation result.

[0102] Step S140: Sample and hold the voltage signal to obtain a digital value.

[0103] The analog-to-digital converter (ADC) 210 samples and holds the voltage signal to obtain a digital value. Preferably, a successive approximation analog-to-digital converter (SAR ADC) is used as the ADC 210 because the SAR ADC can sample at precise times and provides sufficient conversion accuracy. Sampling timing control is particularly important; the system needs to precisely control the sampling trigger time to ensure that the sampling occurs at a preset time (0.5dT). PRD The voltage signal is captured. To achieve this, the sampling clock is typically synchronized with the PWM control signal to eliminate sampling timing errors.

[0104] The sample-and-hold circuit inside a SAR ADC consists of a sampling switch, a holding capacitor, and a buffer amplifier. When a sampling command arrives, the sampling switch turns on, transferring the input voltage to the holding capacitor; subsequently, the sampling switch turns off, and the holding capacitor retains the voltage value until the SAR ADC completes the conversion. The buffer amplifier isolates the holding capacitor from subsequent circuitry, preventing charge leakage that could lead to measurement errors. The SAR ADC conversion process is based on a binary search algorithm. The comparator compares the held voltage value with an internal reference voltage, successively approximating the register to control the internal DAC output. After n comparisons, an n-bit digital output is obtained. When selecting a SAR ADC, factors such as its bit depth, conversion rate, and reference voltage accuracy need to be considered. Generally, 8-12 bit resolution SAR ADCs are commonly used in applications to achieve a balance between speed and accuracy.

[0105] It should be noted that the sample-and-hold voltage signal ADC is not limited to SAR ADC; it can also be replaced with other ADC types that can sample the current signal at specific moments during the switching cycle, achieving the same purpose.

[0106] Step S150: Perform data conversion on the digital quantity to obtain the midpoint current.

[0107] Data conversion is the process of converting the digital value output by the analog-to-digital converter (ADC) 210 into an actual current value. The basic conversion formula can be expressed as: Midpoint current = Digital value × Conversion coefficient ÷ Current induction coefficient. Here, the conversion coefficient is equal to the reference voltage divided by 2 raised to the power of n (where n is the number of bits in the ADC 210), and the reference voltage is the full-scale reference voltage of the ADC 210. For example, for a 10-bit ADC, its conversion coefficient is the reference voltage divided by 1024.

[0108] The determination of the current sensing coefficient depends on the current detection method. When using a sampling resistor scheme, the current sensing coefficient equals the sampling resistor value; while when using a current mirror scheme to acquire the switching transistor current, the current sensing coefficient equals the sampling resistor value multiplied by the mirror current ratio. In practical applications, various calibrations and compensations are also required, including temperature compensation, nonlinearity compensation, and offset calibration. Temperature compensation is used to offset measurement deviations caused by the temperature characteristics of components; nonlinearity compensation corrects the nonlinear portion of the ADC conversion characteristic curve; and offset calibration eliminates static errors in the system, improving measurement accuracy.

[0109] It should also be noted that, in conjunction with the integrated switching transistor driver module, step S110 can also be implemented in the following ways, see reference. Figure 9 This application illustrates a specific implementation scheme for detecting the output current of a switched capacitor converter using two half-bridge DrMOS modules. Figure 7The overall system structure is presented in detail, including the DrMOS module with integrated switching transistors, the connection structure, and the control module 20. The following will combine... Figure 9 A detailed explanation of DrMOS's built-in current mirror technology is provided.

[0110] like Figure 9 As shown, the four switching transistors in the switched-capacitor converter are integrated into two half-bridge DrMOS modules: DrMOS1 integrates the first main switch Q1 and the first synchronous rectifier switch Q5; DrMOS2 integrates the second main switch Q2 and the second synchronous rectifier switch Q6. Each DrMOS module contains the following key pins: PWM: used to receive pulse width modulation control signals; IMON: current monitoring output pin, outputting a mirror current proportional to the internal switch current; IREF: current reference setting pin, used to provide a common-mode voltage for IMON, facilitating the generation of negative current signals; other functional pins: such as GND (ground), power input, etc.

[0111] The DrMOS built-in current mirror technology works as follows: Next to each MOSFET, a mirror MOSFET with a very small area ratio (typically 1:500 to 1:2000) is integrated inside the DrMOS chip. This mirror MOSFET shares the same gate drive signal as the main MOSFET, and therefore has exactly the same switching characteristics.

[0112] Because the area of ​​a mirror MOSFET is much smaller than that of the main MOSFET, but both withstand the same gate-source voltage, the current flowing through the mirror MOSFET is strictly proportional to the current in the main MOSFET. This proportion is equal to the ratio of their areas. For example, if the area of ​​the mirror MOSFET is 1 / 1000 of that of the main MOSFET, then the mirror current is 1 / 1000 of the main current.

[0113] DrMOS integrates the main MOSFET and the mirror MOSFET on the same silicon chip, ensuring that they have the exact same temperature coefficient and process parameters, thereby achieving excellent temperature stability and accuracy.

[0114] In a half-bridge configuration, the high-side MOSFET (main switch) and the low-side MOSFET (synchronous rectifier switch) typically conduct in a complementary manner. The internal circuitry of DrMOS can automatically track which MOSFET is currently conducting and output the corresponding mirrored current to the IMON pin.

[0115] like Figure 9 As shown, the IMON pins of the two DrMOS modules are connected together through a shared sampling resistor R. CSThis is converted into a voltage signal. This connection method enables the automatic summarization of the currents of the four switching transistors, forming a comprehensive signal representing the total switching transistor current.

[0116] Specific implementation details include: the mirrored currents output from the IMON pins of the two DrMOS transistors naturally converge and flow through the shared sampling resistor R. CS This generates a voltage signal proportional to the total mirror current. The generated voltage signal is input to the analog-to-digital converter unit 210 of the control module 20 via differential connections (CS+ and CS-). The control module 20 sends control signals to the two DrMOS modules through the PWM1 and PWM2 pins to control the switching states of the four switching transistors. The IREF pin of each DrMOS module is connected to a reference voltage source or resistor network to set the scaling factor of the current mirror, ensuring the accuracy of the measurement results.

[0117] It should also be noted that the switching transistor current detection function can be achieved not only by DrMOS, but also by other discrete circuits with switching transistor current detection function, switching transistor driver chips with integrated switching transistor current detection function, etc.

[0118] In some other embodiments of this application, step S100 specifically includes the following steps:

[0119] Step S160: At a preset time, obtain the current of the two synchronous rectifier switches.

[0120] In switched-capacitor converters, the currents of the synchronous rectifier switches (Q5, Q6) are significantly correlated with the output current at specific times. Unlike sampling all four switches, this embodiment focuses only on the currents of two synchronous rectifier switches, greatly simplifying the detection circuit. In this scheme, the selection of the preset time is particularly crucial. When the duty cycle d of the main switch is less than or equal to 0.5, the preset time is (0.5 + 0.5d)T. PRD When the duty cycle d is greater than 0.5, the preset time is also (0.5 + 0.5d)T. PRD Analysis of the working principle of the switched capacitor converter shows that at the above moment, the sum of the currents of the two synchronous rectifier switches is exactly equal to the output current.

[0121] There are multiple ways to obtain the current of the switching transistor. Figure 10 In the diagram, four switching transistors Q5 and Q6 are marked with current detection points IS5 and IS6, respectively. These detection points are used to acquire the current signal flowing through each switching transistor during conduction.

[0122] There are several possible implementation methods: for example, a trace can be led out from the source or drain terminal of the switching transistor, and the current can be directly measured by a current sensor (such as a Hall sensor, current transformer, etc.) in the signal processing module 10. Alternatively, the signal processing module can integrate a current detection circuit to separately detect the current of the low-side switching transistors (Q5 / Q6).

[0123] Step S170: Summarize the currents of the two synchronous rectifier switches to obtain the total switching current.

[0124] The current summing step combines the currents from the two synchronous rectifier switches Q5 and Q6 to obtain the total switching current. Compared to the four-switch solution, this summing circuit is simpler because it only needs to process two current signals.

[0125] Current aggregation can be implemented in hardware or software, depending on system design requirements and resource constraints. Hardware aggregation is typically achieved through current node connections; according to Kirchhoff's current law, connecting multiple current signals to the same node naturally results in current superposition. Another hardware implementation utilizes a current adder, building a current summing circuit based on an operational amplifier to achieve precise current addition. Furthermore, multiple current signals can share the same sampling resistor, allowing the currents to naturally superimpose and be converted into corresponding voltage signals.

[0126] The software approach involves first acquiring the current values ​​of the two synchronous rectifier switches separately, and then performing digital addition in the processor. For most implementations, the total switching current can be expressed as the algebraic sum of the currents of the two synchronous rectifier switches, i.e., I0. Q_all =IQ5 + IQ6. At a carefully selected preset time, the total switching current is exactly equal to the output current of the switched capacitor converter.

[0127] exist Figure 10 In the illustrated embodiment, a hardware aggregation method is used. The current signals of the two synchronous rectifier switches are introduced into the signal processing module 10, and are directly aggregated into a total current signal through internal circuitry.

[0128] Step S130: Convert the total switching current into a voltage signal.

[0129] from Figure 10 As can be seen, the output of signal processing module 10 is connected to control module 20 through two ports, CS+ and CS-. This indicates that signal processing module 10 converts the summarized current signal into a differential voltage signal for subsequent analog-to-digital conversion processing.

[0130] Current-to-voltage conversion is typically achieved through a precision sampling resistor R. CSImplementation. Unlike traditional solutions, the sampling resistor here is not located in the power loop, but inside the signal processing circuit. Therefore, the power loss on the resistor is minimal and will not significantly affect the system efficiency.

[0131] The conversion circuit may contain the following functional blocks: converting a current signal into a voltage signal, with the conversion ratio determined by the sampling resistor R. CS Decision (V = I × R) CS) The system includes a current-to-voltage converter; a differential amplifier that converts a single-ended voltage signal into a differential signal to improve anti-interference capability; a filter circuit that removes high-frequency noise and extracts the effective components of the current signal; and a level adjustment circuit that ensures the output signal is within the input range of the analog-to-digital converter 210, maximizing the utilization of the dynamic range of the analog-to-digital converter 210 and improving measurement accuracy. It should be noted that the current-to-voltage conversion process introduces a certain gain coefficient, which needs to be compensated for in subsequent data processing to ensure the accuracy of the final calculation result.

[0132] Step S140: Sample and hold the voltage signal to obtain a digital value.

[0133] The analog-to-digital converter (ADC) 210 samples and holds the voltage signal to obtain a digital value. Preferably, a successive approximation analog-to-digital converter (SAR ADC) is used as the ADC 210 because the SAR ADC can sample at precise times and provides sufficient conversion accuracy. Sampling timing control is particularly important; the system needs to precisely control the sampling trigger time to ensure that the sampling occurs at a preset time (0.5dT). PRD The voltage signal is captured. To achieve this, the sampling clock is typically synchronized with the PWM control signal to eliminate sampling timing errors.

[0134] The sample-and-hold circuit inside a SAR ADC consists of a sampling switch, a holding capacitor, and a buffer amplifier. When a sampling command arrives, the sampling switch turns on, transferring the input voltage to the holding capacitor; subsequently, the sampling switch turns off, and the holding capacitor retains the voltage value until the SAR ADC completes the conversion. The buffer amplifier isolates the holding capacitor from subsequent circuitry, preventing charge leakage that could lead to measurement errors. The SAR ADC conversion process is based on a binary search algorithm. The comparator compares the held voltage value with an internal reference voltage, successively approximating the register to control the internal DAC output. After n comparisons, an n-bit digital output is obtained. When selecting a SAR ADC, factors such as its bit depth, conversion rate, and reference voltage accuracy need to be considered. Generally, 8-12 bit resolution SAR ADCs are commonly used in applications to achieve a balance between speed and accuracy.

[0135] Step S150: Perform data conversion on the digital quantity to obtain the midpoint current.

[0136] Data conversion is the process of converting the digital value output by the analog-to-digital converter (ADC) 210 into an actual current value. The basic conversion formula can be expressed as: Midpoint current = Digital value × Conversion coefficient ÷ Current induction coefficient. Here, the conversion coefficient is equal to the reference voltage divided by 2 raised to the power of n (where n is the number of bits in the ADC 210), and the reference voltage is the full-scale reference voltage of the ADC 210. For example, for a 10-bit ADC, its conversion coefficient is the reference voltage divided by 1024.

[0137] The determination of the current sensing coefficient depends on the current detection method. When using a sampling resistor scheme, the current sensing coefficient is equal to the sampling resistor value; while when using a current mirror scheme to collect the switching transistor current, the current sensing coefficient is equal to the sampling resistor value multiplied by the mirror current ratio.

[0138] It should also be noted that, in conjunction with the integrated switching transistor driver module, step S160 can also be implemented in the following ways, see reference. Figure 11 This application illustrates a specific implementation scheme for synchronous rectifier switch current detection using two half-bridge DrMOS modules. Figure 9 The embodiments shown are different. Figure 11 The implementation method focuses on the current sensing of the synchronous rectifier switches (Q5 and Q6), and utilizes DrMOS's built-in low-side current mirror technology to achieve high-precision, lossless current sensing.

[0139] like Figure 11 As shown, the switched-capacitor converter is constructed using two half-bridge DrMOS modules: DrMOS1 integrates the first main switch Q1 and the first synchronous rectifier switch Q5; DrMOS2 integrates the second main switch Q2 and the second synchronous rectifier switch Q6. Key connections and components of the system include: input voltage terminal V... IN Connected to two DrMOS modules, leap capacitor C FLY Connected between the two half-bridges, the first inductor L1 and the second inductor L2 are respectively connected to the output capacitor C. O and load R LOAD The control module 20 sends control signals to the DrMOS module through the PWM1 and PWM2 pins. The IMON pin of the DrMOS outputs a mirrored current, which is connected to the sampling resistor R. CS The CS+ and CS- differential signals are connected to the analog-to-digital conversion unit 210 of the control module 20.

[0140] and Figure 9 The key difference is that, Figure 11The DrMOS in the configuration is set to output only the current information of the synchronous rectifier switch (low-side MOSFET), excluding the current information of the main switch (high-side MOSFET). The first and second synchronous rectifier switches are integrated into a second switch driver module, and current information is obtained through the module's internal current mirror. Figure 11 In one embodiment, this technique is achieved using a low-side current mirror of DrMOS.

[0141] The DrMOS low-side current mirror works as follows: DrMOS integrates a scaled-down mirror MOSFET within the low-side MOSFET (synchronous rectifier switch) chip. This mirror MOSFET shares the same gate drive signal as the main MOSFET and has identical switching characteristics.

[0142] The area of ​​a mirror MOSFET is typically 1 / 500 to 1 / 2000 of that of the main MOSFET, so the current flowing through the mirror MOSFET is precisely proportional to that of the main MOSFET.

[0143] Because the mirror MOSFET and the main MOSFET are integrated on the same silicon chip, they have the exact same temperature coefficient, ensuring a stable proportional relationship when the temperature changes.

[0144] DrMOS typically allows configuration to select the output current information of the low-side MOSFET, high-side MOSFET, or both. Figure 11 In this embodiment, DrMOS is configured to output only the current information of the low-side MOSFET (synchronous rectifier switch).

[0145] exist Figure 11 In the implementation shown, the IMON pins of the two DrMOS modules are connected together, and the mirrored current of the output flows through a shared sampling resistor R. CS The voltage is converted into differential voltage signals (CS+ and CS-) and input to the control module 20.

[0146] Compared to detecting the current of all four switching transistors, detecting only the current of the synchronous rectifier switch has the following significant advantages: Current sensing technology for the low-side MOSFET is more mature and much easier to implement than for the high-side MOSFET. The high-side MOSFET is at a floating potential, making current sensing more complex. Low-side current mirror technology is more reliable and less affected by factors such as temperature and voltage fluctuations. Almost all DrMOS products support low-side current sensing, while some earlier or lower-cost products may not support high-side current sensing. The low-side MOSFET's source is grounded, resulting in lower common-mode noise in the current sensing signal and generally higher signal quality.

[0147] The total switching current must be converted into a voltage signal before it can be acquired and processed by the analog-to-digital converter unit 210. In the synchronous rectifier switch current detection scheme, the current-to-voltage conversion typically uses the sampling resistor method. Since the synchronous rectifier switch current detection circuit is located on the low side, the sampling resistor can be directly connected between the IMON signal path and ground, forming a simple IV conversion. When the mirrored currents of the two synchronous rectifier switches flow through the sampling resistor R... CS At that time, a voltage drop V is generated. OUT = (IQ5 + IQ6) × R CS The selection of the sampling resistor should balance measurement sensitivity and power consumption, and is usually in the range of a few ohms to tens of ohms, depending on the mirror current ratio and the input range of the analog-to-digital converter 210.

[0148] Unlike existing technologies, the embodiments of the present invention are aimed at switched capacitor converters. Based on the relationship between the switching transistor current and the output current, the output current is obtained by detecting the switching transistor current at a specific time. This avoids the need to add an additional sampling resistor in the output circuit, thereby reducing system losses, reducing the heat dissipation area and increasing the power density of the switched capacitor converter. It also avoids the possibility that adding a sampling resistor in a high-frequency switching circuit will easily affect the sampling results due to switching noise interference.

[0149] The present invention also provides an electronic device based on the above-described output current detection method, the schematic diagram of which is shown below. Figure 12 As shown, the electronic device 700 includes:

[0150] One or more processors 701, a network interface 702, and a memory 703, Figure 12 The example consists of a processor 701, a network interface 702, and a memory 703.

[0151] The network interface 702 is communicatively connected to the corresponding processor 701. The processor 701 and the memory 702 can be connected via a bus or other means. Figure 12 Taking the example of a connection between China and Israel via a bus.

[0152] Network interface 702 is used to establish communication connections between processor 701 and other external devices, including the following types: RJ-45 interface, SC fiber optic interface, AUI interface, FDDI interface and Console interface.

[0153] The memory 703, as a non-volatile computer-readable storage medium, can be used to store non-volatile software programs, non-volatile computer-executable programs, and modules. The processor 701 executes various functional applications and data processing of the electronic device by running the non-volatile software programs, instructions, and units stored in the memory 703, thereby implementing the output current detection method of the above-described method embodiment.

[0154] Memory 103 may include a program storage area and a data storage area. The program storage area may store the operating system and applications required for at least one function; the data storage area may store data created based on the use of the electronic device. Furthermore, memory 703 may include high-speed random access memory and may also include non-volatile memory, such as at least one disk storage device, flash memory device, or other non-volatile solid-state storage device. In some embodiments, memory 703 may optionally include memory remotely located relative to processor 701, and these remote memories can be connected to the electronic device via a network. Examples of such networks include, but are not limited to, the Internet, intranets, local area networks, mobile communication networks, and combinations thereof.

[0155] The one or more units are stored in the memory 703. When executed by one or more processors 701, they perform the output current detection method in any of the above method embodiments, for example, the method described above. Figure 7 The method steps S100 to S200.

[0156] The aforementioned electronic device can execute the output current detection method provided in the embodiments of the present invention, and has the corresponding program modules and beneficial effects for executing the method. Technical details not described in detail in the embodiments of the electronic device can be found in the output current detection method provided in the embodiments of the present invention.

[0157] This invention also provides a non-volatile computer-readable storage medium, which may be included in the device described in the above embodiments; or it may exist independently and not assembled into the device. The non-volatile computer-readable storage medium carries one or more programs, which, when executed, implement the output current detection method of this disclosure.

[0158] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and not to limit them; under the concept of this application, the technical features of the above embodiments or different embodiments can also be combined, the steps can be implemented in any order, and there are many other variations of different aspects of this application as described above. For the sake of brevity, they are not provided in detail; although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or make equivalent substitutions for some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. An output current detection method, applied to a switched capacitor converter, characterized in that, The switched-capacitor converter includes an input voltage terminal, a first main switch, a first synchronous rectifier switch, a second main switch, a second synchronous rectifier switch, a flying capacitor, a first inductor, a second inductor, and an output capacitor. The drain of the first main switch is connected to the positive terminal of the input voltage terminal. The source of the first main switch is connected to the first terminal of the flying capacitor and the drain of the second main switch. The source of the second main switch is connected to the drain of the second synchronous rectifier switch and the first terminal of the second inductor. The second terminal of the flying capacitor is connected to the drain of the first synchronous rectifier switch and the first terminal of the first inductor. The second terminal of the first inductor is connected to the second terminal of the second inductor, the first terminal of the output capacitor, and the first terminal of the load. The sources of the first and second synchronous rectifier switches, the second terminal of the output capacitor, and the negative terminal of the input voltage terminal are connected to a reference ground. The method includes: At a preset time during the switching cycle of the switched capacitor converter, the midpoint current of the switching transistors of the switched capacitor converter is obtained; the midpoint current is the sum of the currents of the switching transistors. The output current of the switched capacitor converter is obtained based on the midpoint current; at a preset time, the midpoint current is equal to the output current; the preset time is set based on the duty cycle of the switching transistor. The switched capacitor converter includes two main switching transistors, two synchronous rectifier switching transistors, a flying capacitor, a first inductor, and a second inductor. The output current of the switched capacitor converter is equal to the sum of the current of the first inductor and the current of the second inductor. The preset time is the midpoint of the continuous phase in which the midpoint current is equal to the sum of the current of the first inductor and the current of the second inductor, and the correspondence between the preset time and the duty cycle is the same in the two working states where the duty cycle of the main switch is less than or equal to 50% and greater than 50%. The step of obtaining the midpoint current of the switching transistor of the switched capacitor converter at a preset time during the switching cycle of the switched capacitor converter includes: At the preset time, the currents of the two main switching transistors and the two synchronous rectifier switching transistors are acquired; The currents of the two main switching transistors and the two synchronous rectifier switching transistors are summed to obtain the total switching current; The total current of the switch is converted into a voltage signal; The voltage signal is sampled and held to obtain a digital value; The digital quantity is converted to obtain the midpoint current; Alternatively, obtaining the midpoint current of the switching transistor of the switched capacitor converter at a preset time during the switching cycle of the switched capacitor converter includes: At the preset time, the current of the two synchronous rectifier switches is obtained; The currents of the two synchronous rectifier switches are summed to obtain the total switching current; The total current of the switch is converted into a voltage signal; The voltage signal is sampled and held to obtain a digital value; The digital quantity is converted to obtain the midpoint current; When the total switching current is the sum of the currents of the two main switching transistors and the two synchronous rectifier switching transistors, The preset time is 0.5dT. PRD ; When the total switching current is the sum of the currents of the two synchronous rectifier switches, The preset time is (0.5 + 0.5d)T PRD ; Where d is the duty cycle of the main switch transistor, and T PRD The switching period is denoted as .

2. The method according to claim 1, characterized in that, The step of performing data conversion on the digital quantity to obtain the midpoint current includes: The midpoint current is obtained by multiplying the digital value by the conversion factor and dividing it by the current sensing factor. The conversion factor is the reference voltage of the analog-to-digital converter divided by 2 to the power of n, where n is the number of bits in the analog-to-digital converter; The current sensing coefficient is the resistance value of the sampling resistor, or the product of the sampling resistor and the ratio of the mirror current.

3. The method according to claim 2, characterized in that, The two main switching transistors include a first main switching transistor and a second main switching transistor; The first main switch and the second main switch are integrated in the first switch driver integrated module. The current of the first main switch and the current of the second main switch are obtained through the internal current mirror of the first switch driver integrated module.

4. The method according to claim 2, characterized in that, The two synchronous rectifier switches include a first synchronous rectifier switch and a second synchronous rectifier switch; The first synchronous rectifier switch and the second synchronous rectifier switch are integrated in the second switch driver integrated module. The current of the first synchronous rectifier switch and the current of the second synchronous rectifier switch are obtained through the internal current mirror of the second switch driver integrated module.

5. An electronic device, characterized in that, include: At least one processor; At least one network interface, which is communicatively connected to a corresponding processor; as well as, A memory communicatively connected to the at least one processor; wherein, The network interface is used to establish communication connections between the processor and other external devices; The memory stores instructions that can be executed by the at least one processor to enable the at least one processor to perform an output current detection method as described in any one of claims 1-4.

6. A non-volatile computer storage medium, characterized in that, The computer storage medium stores computer-executable instructions that are executed by one or more processors, causing the one or more processors to perform an output current detection method as described in any one of claims 1-4.

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