Online measurement circuit, siC MOSFET gate oxide layer degradation monitoring method and monitoring system based on drain-source voltage surge characteristics

Abstract

This application provides an online measurement circuit, a method and system for monitoring gate oxide degradation of SiC MOSFETs based on drain-source voltage surge characteristics. The online measurement circuit includes a waveform extraction circuit for extracting the voltage waveform signal between the Kelvin source and power source of the SiC MOSFET under test and performing voltage division output; and an envelope extraction circuit for extracting and outputting the envelope of the voltage waveform signal output by the waveform extraction circuit. The peak value of the envelope is used to characterize the degree of gate oxide degradation of the SiC MOSFET under test. The technical solution of this application, by online measurement of the amplitude change of the surge signal superimposed on the drain-source voltage of the SiC MOSFET, can accurately monitor the degree of gate oxide degradation of the SiC MOSFET during its operation.

Description

Technical Field

[0001] This application belongs to the field of new energy technology, and further relates to the field of power device monitoring technology in new energy equipment, specifically providing an online measurement circuit, a SiC MOSFET gate oxide degradation monitoring method and monitoring system based on drain-source voltage surge characteristics. Background Technology

[0002] SiC MOSFETs are a new type of power device that have been widely used in new energy equipment (such as electric vehicle inverters, photovoltaic inverters, and wind power converters). Because their gate oxide layer is thinner than that of Si MOSFETs, their performance is more susceptible to gate oxide degradation under high voltage and high frequency conditions. Therefore, online monitoring of the gate oxide degradation level of SiC MOSFETs is crucial for ensuring the safe operation of the system.

[0003] However, existing schemes that assess the gate oxide state based on measurements of conventional electrical parameters such as threshold voltage drift or gate leakage current generally have limitations such as high hardware requirements and difficulty in online inverter testing, making it difficult to achieve real-time monitoring of the inverter's operating status.

[0004] Therefore, there is a need for a new solution that simultaneously meets the requirements of low hardware cost and high measurement accuracy, without interrupting device operation, and enables real-time monitoring of the gate oxide degradation level of SiC MOSFETs under inverter operating conditions. Summary of the Invention

[0005] The first aspect of this application provides an online measurement circuit for performing online measurements on a SiC MOSFET under test in a SiC inverter during operation. The online measurement circuit includes:

[0006] The waveform extraction circuit is used to extract the voltage waveform signal between the Kelvin source and the power source of the SiC MOSFET under test and perform voltage division output.

[0007] An envelope extraction circuit is used to extract and output the envelope of the voltage waveform signal output by the waveform extraction circuit. The peak value of the envelope is used to characterize the degree of gate oxide degradation of the SiC MOSFET under test.

[0008] Furthermore, the waveform extraction circuit includes a first resistor and a second resistor connected in series;

[0009] The first end of the first resistor is electrically connected to the Kelvin source of the SiC MOSFET under test, the second end is electrically connected to the first end of the second resistor and serves as the output terminal of the waveform extraction circuit, and the second end of the second resistor is electrically connected to the power source of the SiC MOSFET under test and the ground terminal.

[0010] Preferably, the ratio of the resistance of the first resistor to the resistance of the second resistor is greater than or equal to 2.

[0011] Further, the envelope extraction circuit includes a first operational amplifier, a second operational amplifier, a first switching device, a second switching device, a first capacitor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a seventh resistor, an eighth resistor, a positive power supply, and a negative power supply. The positive input terminal of the first operational amplifier is electrically connected to the output terminal of the waveform extraction circuit through the fourth resistor, the negative input terminal is electrically connected to the negative power supply through the fifth resistor, and the output terminal is electrically connected to the control terminals of the first and second switching devices. The input terminal of the first switching device is electrically connected to the positive power supply through the sixth resistor, and the output terminal is electrically connected to the negative input terminal of the first operational amplifier. The input terminal of the second switching device is electrically connected to the positive power supply through the seventh resistor, and the output terminal is electrically connected to the positive input terminal of the second operational amplifier. The negative input terminal of the second operational amplifier is electrically connected to the ground terminal, and the output terminal is used to output the envelope and is electrically connected to the ground terminal through the eighth resistor. The two ends of the first capacitor and the two ends of the third resistor are both connected between the positive input terminal of the second operational amplifier and the ground terminal.

[0012] Furthermore, both the first and second switching devices are NPN bipolar junction transistors, with the base as the control terminal, the collector as the input terminal, and the emitter as the output terminal.

[0013] Preferably, the resistance value r3 of the third resistor is the same as the capacitance value c of the first capacitor. E Satisfy the following formula:

[0014]

[0015] Among them, f SW Where is the switching frequency of the SiC MOSFET under test, and K is the discharge coefficient.

[0016] Preferably, the maximum operating frequency of both the first operational amplifier and the second operational amplifier is not less than 100MHz, and the slew rate is not less than 3.14V / ns.

[0017] A second aspect of this application provides a method for monitoring gate oxide degradation of SiC MOSFETs based on drain-source voltage surge characteristics, comprising:

[0018] During the operation of the SiC inverter, the V of the tested SiC MOSFET is... S The peak value of the waveform signal envelope is measured online, as is the drain-source current of the SiC MOSFET under test in the turn-on state. V S The voltage between the Kelvin source and the power source of the SiC MOSFET under test;

[0019] The gate oxide degradation level of the SiC MOSFET under test is monitored using a pre-calibrated estimation model and online measurement results of the SiC MOSFET under test.

[0020] Furthermore, the gate oxide layer degradation estimation model includes a non-degraded fitting curve, which is obtained through the following steps:

[0021] Offline measurements were performed on the first calibrated SiC MOSFET to obtain its drain-source current and V under several different operating conditions in the on-state. S The peak value of the waveform signal envelope, wherein the first calibrated SiC MOSFET is a SiC MOSFET of the same type as the SiC MOSFET under test and is not degraded.

[0022] Curve fitting was performed on the offline measurement results of the first calibrated SiC MOSFET to obtain the non-degraded fitting curve.

[0023] Preferably, the gate oxide layer degradation estimation model further includes a degradation tolerance table, which is obtained through the following steps:

[0024] Offline measurements were performed on several different second-calibration SiC MOSFETs to obtain the drain-source current and Vo of each second-calibration SiC MOSFET in the turn-on state under several different operating conditions. S The peak value of the envelope of the waveform signal, wherein several different second-calibrated SiC MOSFETs are SiC MOSFETs of the same model as the SiC MOSFET under test but in different degradation states;

[0025] Based on offline measurement results of several different second-calibrated SiC MOSFETs and undegraded fitting curves, a degradation tolerance table was obtained.

[0026] A third aspect of this application provides a SiC MOSFET gate oxide degradation monitoring system based on drain-source voltage surge characteristics, comprising:

[0027] The aforementioned online measurement circuit is used to measure the Vt of the SiC MOSFET under test during the operation of the SiC inverter. S The peak value of the envelope of the waveform signal is measured online;

[0028] The current measurement module is used to measure the drain-source current of the SiC MOSFET under test in the turn-on state during the operation of the SiC inverter.

[0029] The monitoring module uses a pre-calibrated gate oxide degradation estimation model and online measurement results of the SiC MOSFET under test to monitor the gate oxide degradation level of the SiC MOSFET under test.

[0030] The online measurement circuit provided in the embodiments of this application adopts a non-intrusive online monitoring method. It can monitor the surge voltage signal that reflects the degree of gate oxide degradation by using the self-induced voltage of the inherent parasitic inductance between the Kelvin source and the power source. It does not require external sensors or interrupt device operation, and realizes real-time status monitoring under inverter operating conditions. The hardware requirements and cost of this online measurement circuit are low. Hardware costs are reduced by reusing parasitic inductance and the ADC sampling rate requirement is reduced by using peak hold.

[0031] Furthermore, the parameters acquired by this online measurement circuit are decoupled from temperature, giving it high resistance to temperature interference. Under a specific drive resistor, the output results are minimally affected by temperature, and the output results are sensitive to gate oxide degradation, showing significant changes in the early stages of aging. It has strong versatility and compatibility, and the detection module can be directly integrated into commercial SiC MOSFET systems using 4-pin packages. Attached Figure Description

[0032] Figure 1 This is a circuit diagram of a SiC inverter;

[0033] Figure 2 This is a schematic diagram of an online measurement circuit provided according to an embodiment of this application;

[0034] Figure 3 This is a pinout diagram of a SiC MOSFET in a 4-pin package.

[0035] Figure 4 To Figure 3 The equivalent circuit diagram for driving SiC MOSFETs;

[0036] Figure 5 This is a schematic diagram of the voltage waveform signal and its envelope between the source (S) and source (S') terminals of a SiC MOSFET in a specific embodiment.

[0037] Figure 6This is a schematic diagram of the gate oxide degradation mechanism of a SiC MOSFET.

[0038] Figure 7 The IV characteristics of SiC MOSFET during the turn-off process;

[0039] Figure 8 A schematic diagram of the drain-source voltage waveforms and PWM drive signals of the three SiC MOSFETs on the upper bridge of a SiC inverter;

[0040] Figure 9 for Figure 8 A schematic diagram of the equivalent circuit for the surge voltage A stage generated by Q1;

[0041] Figure 10 for Figure 8 A schematic diagram of the equivalent circuit for the surge voltage C stage generated by Q1;

[0042] Figure 11 A physical diagram of the online measurement circuit provided according to an embodiment of this application;

[0043] Figure 12 This is a flowchart of a SiC MOSFET gate oxide degradation monitoring method based on drain-source surge characteristics provided in an embodiment of this application;

[0044] Figure 13 This is a circuit diagram of the calibration test equipment provided according to an embodiment of this application;

[0045] Figure 14 A physical diagram of the calibration test equipment provided according to the embodiments of this application;

[0046] Figure 15 This is a schematic diagram showing the results of a calibration experiment on a fresh SiC MOSFET.

[0047] Figure 16 V for fresh SiC MOSFET surge_C I D_ON Relationship diagram;

[0048] Figure 17 A schematic diagram of the equipment used for aging a second-calibrated SiC MOSFET;

[0049] Figure 18 This is a schematic diagram showing the state changes of a second-calibrated SiC MOSFET after different aging times.

[0050] Figure 19 V of the second calibrated SiC MOSFET after different aging times surge_C I D_ON Relationship diagram;

[0051] Figure 20 This is a flowchart of a SiC MOSFET gate oxide degradation monitoring method based on drain-source surge characteristics provided in an embodiment of this application;

[0052] Figure 21 This is a schematic diagram of the experimental platform for real SiC inverter operation under actual conditions provided in the embodiments of this application;

[0053] Figure 22 This is a schematic diagram of some experimental data collected in the actual measurement experiment;

[0054] Figure 23 A schematic diagram showing the monitoring results of a healthy SiC MOSFET;

[0055] Figure 24 This is a schematic diagram showing the monitoring results of an aging SiC MOSFET.

[0056] Figure 25 This is a schematic diagram of the architecture of a SiC MOSFET gate oxide degradation monitoring system based on drain-source surge characteristics, according to an embodiment of this application. Detailed Implementation

[0057] The present application will now be further described based on preferred embodiments and with reference to the accompanying drawings.

[0058] In the description of the embodiments of this application, it should be noted that the terms "upper," "lower," "inner," and "outer," etc., indicating orientation or positional relationships based on the orientation or positional relationships shown in the accompanying drawings, or the orientation or positional relationships commonly used when the product of this application is in use, are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation on this application. Furthermore, in the description of this application, the terms "first," "second," etc., are used to distinguish different units, but these are not limited by the manufacturing order, nor should they be construed as indicating or implying relative importance. Their names may differ in the detailed description and claims of this application. In addition, for ease of understanding, various components in the drawings have been enlarged or reduced, but this is not intended to limit the scope of protection of this application.

[0059] The vocabulary used in this specification is for illustrative purposes and is not intended to limit the scope of this application. It should also be noted that, unless otherwise expressly specified and limited, the terms "set," "connected," and "linked" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection, an electrical connection, a direct connection, or an indirect connection via an intermediate medium; or they can refer to the internal communication between two components. Those skilled in the art will understand the specific meaning of these terms in this application.

[0060] Figure 1 This is a circuit diagram of a SiC inverter constructed from SiC MOSFETs (Silicon Carbide Metal-Oxide-Semiconductor Field-Effect Transistors). In this circuit, Q1 to Q6 are six SiC MOSFETs, L1 to L6 are the parasitic inductances of Q1 to Q6, C1 to C6 are the equivalent output capacitances of Q1 to Q6, S1 to S6 are the gate drive signals of Q1 to Q6, and M is the load motor.

[0061] During the operation of the SiC inverter, the gate oxide layer of the SiC MOSFET is relatively thin, making it more prone to gate oxide degradation. This degradation has become one of the key issues affecting the reliability of SiC MOSFETs and has severely restricted their widespread application. Therefore, it is necessary to conveniently, efficiently, and accurately measure and evaluate the gate oxide degradation of each SiC MOSFET in the SiC inverter during its operation.

[0062] Although various methods for estimating the gate oxide degradation level of SiC MOSFETs have been published, some existing methods suffer from limitations such as high hardware requirements and difficulty in online inverter testing. Some methods are dependent on the junction temperature coupling between the measurement results and the power device's junction temperature, leading to high demands on the temperature stability of the measurement environment. Others require additional temperature acquisition modules to decouple the measurement results from the temperature, introducing new parasitic parameters that affect the performance of the drive circuit. Still others require sampling circuits with extremely high sampling rates to meet sampling accuracy requirements, significantly increasing the cost and difficulty of hardware implementation. Therefore, current methods for measuring and estimating the gate oxide degradation level of SiC MOSFETs generally suffer from limitations such as high hardware requirements and difficulty in online inverter testing.

[0063] To solve the above problems, such as Figure 2As shown, this application provides an online measurement circuit 1 through an embodiment, which is used to perform online measurement on the SiC MOSFET under test in the SiC inverter during the operation of the SiC inverter. The measurement results can be used to characterize the degree of gate oxide degradation of the SiC MOSFET under test.

[0064] like Figure 2 As shown, the online measurement circuit 1 can... Figure 1 The SiC inverter shown is in normal operating condition, and the bridge arm circuit 2 connected to the inverter ( Figure 2 The middle bridge arm circuit 2 is composed of SiC MOSFETs Q1 and Q2, and the SiC MOSFET Q1 under test on the bridge arm circuit 2 is measured online. In the embodiments of this application, the SiC MOSFET used for online measurement and obtaining its gate oxide layer aging degree is called the SiC MOSFET under test, for example, Figure 2 Q1 in the diagram represents the SiC MOSFET under test. Clearly, in other embodiments, this in-circuit measurement circuit can also be used to measure... Figure 1 Other SiC MOSFETs Q2 to Q5 were measured online.

[0065] like Figure 2 As shown, the online measurement circuit 1 consists of a waveform extraction circuit 11 and an envelope extraction circuit 12. Specifically, the waveform extraction circuit 11 is used to extract the voltage waveform signal between the Kelvin source S' and the power source S of the SiC MOSFET (i.e., Q1) under test and perform voltage division output; the envelope extraction circuit 12 is used to extract the envelope of the voltage waveform signal output by the waveform extraction circuit 11 and output it. The peak value of the extracted and output envelope is used to characterize the degree of gate oxide degradation of Q1.

[0066] Figure 3 The pinout of a SiC MOSFET in a 4-pin package is shown. Figure 4 The equivalent circuit diagram for driving it is shown. This type of 4-pin packaged SiC MOSFET is currently widely used in applications such as electric motor inverters for new energy vehicles and photovoltaic inverters. As shown in the figure, in addition to the G (gate), D (drain), and S (source) terminals that are the same as those in the 3-pin package, an S' terminal is also brought out. To distinguish it from the S terminal, for the 4-pin packaged SiC MOSFET, the S terminal is called the power source, and the S' terminal is called the Kelvin source.

[0067] The Kelvin source is constructed by separating a portion of the source through a pin during metallization. When driving a SiC MOSFET, the S' terminal is connected to the G terminal, thus separating the gate-source circuit from the drain-source circuit. This prevents the reverse voltage generated by the parasitic inductance on the drain-source circuit due to the rapid flow of a large current when the circuit is turned on from affecting the gate-source circuit.

[0068] Correspondingly, an induced inductance L will be generated between the S and S' poles. S L S The presence of [something] causes a changing voltage waveform during the switching process of the SiC MOSFET. The online measurement circuit provided in this application is used to extract and output the envelope of the voltage waveform between the S and S' poles.

[0069] Figure 5 The diagram illustrates, in one specific embodiment, the voltage waveform signal (after voltage division) between the S and S' terminals and its envelope, the peak value of which is used in the monitoring method described later to monitor the degree of gate oxide degradation of the SiC MOSFET.

[0070] It should be noted that the essence of the Kelvin source is to bring out a separate circuit to the gate on the source of the SiC MOSFET chip. Even for SiC MOSFETs without a separate S' pin, the S' pin can still be brought out independently through adaptive modifications.

[0071] The following section explains the mechanism of the voltage waveform signal envelope between the S and S' terminals by analyzing the relationship between the gate oxide layer degradation of the SiC MOSFET and the corresponding changes in various electrical parameters during the SiC MOSFET turn-off process.

[0072] I. Relationship between the degree of gate oxide degradation of SiC MOSFET and the changes in related electrical parameters

[0073] Figure 6 The degradation mechanism of the gate oxide layer in SiC MOSFETs is shown, based on... Figure 6 The N-channel power SiC MOSFET structure shown in section (a) exhibits increased defects at the SiC / SiO2 interface in the gate oxide layer under prolonged exposure to high junction temperature stress and high electrical field stress. When the SiC MOSFET is turned on, the drain-source current I... D The path is shown by the blue arrow. When the current path is close to the gate oxide interface, such as... Figure 6As shown in section (b), more electrons are deposited at the defects, which increases the cumulative charge density Nt at the SiC / SiO2 interface.

[0074] The gate threshold voltage V of the SiC MOSFET TH Satisfying equation (1), it can be seen from equation (1) that gate oxide degradation will lead to V TH Increase.

[0075]

[0076] Miller plateau voltage V GP Satisfying equation (2):

[0077]

[0078] Among them, L CH W is the length of the channel. CH Where C is the channel width, μ is the carrier migration velocity, and C is the channel width. ox For gate oxide capacitance, I D The stable drain-source current value of the SiC MOSFET before turn-off (its amplitude is I) D_on The relationship between μ and Nt satisfies equation (3):

[0079]

[0080] Differentiating equation (3) yields equation (4):

[0081]

[0082] As can be seen from equation (4), gate oxide degradation will lead to V GP Increase.

[0083] The equivalent circuit of SiC MOSFET is as follows: Figure 6 As shown in section (c), the IV characteristics during its turn-off process are illustrated in... Figure 7 Referring to the above figure, during the Miller plateau phase (t1~t2), the drain-source voltage V DS As the gate-source voltage V gradually increases, GS Maintain at Miller voltage V GP The driving current I remains unchanged. G Due to the gate-drain capacitance C GD Discharge generates, I G Satisfies equation (5), where t off This represents the time variable of the shutdown phase.

[0084] At this time V GP It can be obtained from equation (6):

[0085]

[0086] V GP =V EE +I G R G (6),

[0087] Among them, R G V is the gate drive resistor. EE Given the gate turn-off drive voltage, and combining equations (5) and (6), we can see that the rate of change of the drain-source voltage dV DS / dt satisfies equation (7):

[0088]

[0089] Combining equations (2) and (4), it can be seen that in I D If the gate oxide layer degrades while the current remains constant, V GP An increase will lead to an increase in dV during the turn-off process of the SiC MOSFET. DS / dt increases.

[0090] During the current decline period (t2~t3), the drain-source current I D The load current gradually decreases to 0, and the gate-source voltage V... GS Satisfying equation (8):

[0091]

[0092] Among them, C GS For gate-source capacitance, in the actual operation of SiC MOSFET, the current fall period is extremely short, and time t-t2 can be treated as a constant B.

[0093] transconductance g of SiC MOSFET m Satisfying equation (9):

[0094]

[0095] Combining equation (8), we can see that the rate of change of the drain-source current satisfies equation (10):

[0096]

[0097] Combining equations (3) and (4), it can be seen that in I D If the gate oxide layer degrades while the current remains constant, V GP The change in μ will lead to the change in dI during the turn-off process of SiCMOSFET. D / dt change.

[0098] The above analysis shows that dI during the turn-off process of SiC MOSFET... D / dt can be used as a characterization parameter for the degradation of its gate oxide layer.

[0099] II. Voltage Surge Phenomenon and Mechanism Analysis in SiC MOSFETs

[0100] SiC inverters exhibit various parasitic parameters during actual operation, such as... Figure 1 The SiC inverter shown typically has a heat sink installed to meet heat dissipation requirements, which introduces parasitic capacitance C between the heat sink and each bridge arm. su C sv C sw And the parasitic capacitance C introduced between the heat sink and the busbar. sn C sp Due to the existence of parasitic parameters, dV DS / dt and dI D / dt will cause a surge in the drain-source voltage of the SiC MOSFET.

[0101] The following section uses the upper bridge as an example to illustrate the surge characteristics of the drain-source voltage under the operating conditions of a SiC inverter. Figure 8 The drain-source voltage waveforms and PWM drive signals of the three SiC MOSFETs Q1, Q3, and Q5 on the upper bridge are shown from top to bottom. As shown in the figure, each SiC MOSFET generates three surge voltages, A, B, and C, on its drain-source voltage during the turn-off process of its switching cycle.

[0102] The mechanism of surge voltage A is as follows: the switching state of the SiC MOSFET in the current bridge arm remains unchanged, while the SiC MOSFETs in other bridge arms are turned off. The dV generated by the turn-off of the SiC MOSFETs in other bridge arms... DS / dt generates a surge current through the output capacitor. The surge current flows through the parasitic capacitance path, causing the drain-source voltage of the current bridge arm SiC MOSFET to generate a surge voltage A.

[0103] Taking the surge voltage A of Q1 as an example, derive its amplitude V. surge_A The expression, Figure 9 The equivalent circuit for generating surge voltage A for Q1 is shown by the red arrow in the figure. Since Q1 and Q3 are in the on-state, their on-resistance is R. on At the instant Q5 is turned off, the output capacitor C5 discharges, which yields equation (11), and equations (12) and (13) satisfied by the voltage U1:

[0104]

[0105] Combining equations (11) to (13), we can obtain equation (14), and finally obtain the amplitude expression of the Q1 surge voltage A shown in equation (15):

[0106]

[0107] V surge_A =I surge_A ×R on (15).

[0108] The mechanism of surge voltage B is similar to that of A. It is also caused by the turn-off of SiC MOSFETs in other bridge arms, resulting in a surge on the drain-source voltage of the SiC MOSFET in the current bridge arm. For example, the surge voltage B of Q1 is caused by the turn-off of Q3.

[0109] The generation mechanism of surge voltage C differs from that of surge voltages A and B. Instead, it is due to a change in the switching state of the SiC MOSFET in the current bridge arm, resulting in dI. D / dt is generated across the drain-source voltage of the SiC MOSFET in the current bridge arm through parasitic inductance. Taking Q1 as an example, the equivalent circuit when it generates the surge voltage C is as follows: Figure 10 As shown, during the Q1 shutdown period, I D When the current becomes 0, the expression for the surge voltage C satisfies equation (16):

[0110]

[0111] III. Characteristic Analysis of Surge Voltages A, B, and C

[0112] From equations (14) and (15), it can be seen that for SiC MOSFET Q1, its V surge_A The values ​​of parasitic inductances L1 and L5, and parasitic capacitance C SW C SU On-state resistance R on and V DS Of the variables mentioned above, only R is relevant. on It will be affected by gate oxide degradation, but due to R on It will also change with the junction temperature. Therefore, if you want to achieve this through V... surge_A To determine the degree of gate oxide degradation, additional junction temperature information is required. Based on the same analysis, if we want to determine the degree of degradation through V... surge_B Determining the degree of gate oxide degradation also requires obtaining junction temperature information. However, in SiC inverters, junction temperature and R... on The complex acquisition method will undoubtedly increase the complexity of the measurement circuit.

[0113] Furthermore, when the inverter's operating conditions change, the change in duty cycle will cause V surge_A Superimposed on different gate-source voltage waveforms, for example, in Figure 8 In the embodiment shown, Q1's V surge_A Superimposed on the on-state voltage V on Up, while Q3 and Q5 Vsurge_A Then superimposed on the DC bus voltage V BUS Above, V surge_B It also has the above characteristics, therefore, if V surge_A or V surge_B As a measurement item, it is also necessary to consider the bridge arm where the SiC MOSFET under test is located to ensure that data is collected at different times, or to design a separate measurement circuit for different bridge arms, which will also make the measurement circuit design difficult.

[0114] According to equation (16), for SiC MOSFET Q1, V surge_C The values ​​of parasitic inductance L1 and dI D The parasitic inductance L1 is related to / dt. Under normal circumstances, it does not change with temperature or operating time. Therefore, under SiC inverter operating conditions, by collecting I... D and V surge_C It can reflect the degree of degradation of the gate oxide layer.

[0115] Based on the above analysis, V should be used. surge_C As a parameter characterizing the degree of degradation of SiC MOSFETs, a design capable of acquiring V surge_C (or able to collect data with V) surge_C A measurement circuit for electrical parameters that are linearly proportional and easy to measure.

[0116] IV. Selecting appropriate electrical parameters for measurement

[0117] Based on the foregoing analysis, V surge_C It can characterize the gate oxide degradation of SiC MOSFETs, but V surge_C Signal superimposed on an amplitude equal to V BUS On the gate-source voltage, V BUS The amplitude is large and independent of gate oxide degradation. If the gate-source voltage is used as the measurement term, the sensitivity of the measurement circuit needs to be greatly improved to ensure that high V values ​​can be obtained. BUS The amplitude of the surge is small. Therefore, compared to directly measuring the gate-source voltage and separating the surge voltage C, dI D / dt reflects V surge_C It is a more reasonable choice.

[0118] according to Figure 8 It can be seen that when the switching state of the inverter changes, V surge_A and V surge_B It will also be superimposed on V BUS Above. By Figure 8 It can be observed that V surge_C It has the highest amplitude among the three surge voltages; therefore, extracting the envelope can highlight V. surge_C Excluding V peak valuesurge_A and V surge_B The impact.

[0119] V is obtained using the envelope. surge_C The peak-rate method can also effectively reduce hardware costs because, in actual inverters, the dI of SiC MOSFETs... D / dt is approximately 5A / ns, V surge_C The rate of change of the signal is roughly the same as that of the complete V signal. surge_C The high cost of hardware due to excessive signal intensity can lead to excessively high hardware costs. In contrast, extracting the envelope can reduce the resolution requirements of the ADC while preserving peak information, thereby reducing hardware costs.

[0120] Furthermore, from equation (17), it can be seen that L S Voltage across terminals and dI D The relationship between / dt and the total number of seconds is directly proportional.

[0121]

[0122] Combining equation (16), we can obtain Vs and V surge_C It has a linear proportional relationship as shown in equation (18):

[0123]

[0124] It can be seen that V surge_C You can use V S The online measurement circuit 1 provided in this application measures the change in inductance L between the S and S' poles. S Voltage V across the terminals S To reflect V surge_C Based on the above analysis, the measurement results will be used to estimate the gate oxide degradation of SiC MOSFETs in the gate oxide monitoring method described later. Furthermore, in the following description, V can be used... surge_C Replace V S .

[0125] V. Specific Implementation Methods of Online Measurement Circuits

[0126] In the embodiments of this application, such as Figure 2 As shown, the waveform extraction circuit 11 includes a first resistor R1 and a second resistor R2 connected in series. The first terminal of the first resistor R1 is electrically connected to the Kelvin source S' of the SiC MOSFET under test, and the second terminal is electrically connected to the first terminal of the second resistor R2 and serves as the output terminal of the waveform extraction circuit 11. The second terminal of the second resistor R2 is electrically connected to the power source S of the SiC MOSFET under test and to ground. The waveform extraction circuit 11 achieves V through the first resistor R1 and the second resistor R2.S Extraction and voltage division output of voltage waveform.

[0127] Preferably, the ratio of the resistance value of the first resistor R1 to the resistance value of the second resistor R2 is greater than or equal to 2. For example, in a specific embodiment, R1 is 1kΩ and R2 is 470Ω. By reasonably setting the resistance values ​​of the two resistors R1 and R2, it can be ensured that the output voltage amplitude meets the range requirements of the subsequent processing circuit.

[0128] In the embodiments of this application, such as Figure 2 As shown, the envelope extraction circuit 12 includes a first operational amplifier U1, a second operational amplifier U2, a first switching device q1, a second switching device q2, and a first capacitor C. E The resistors are: R3 (third resistor), R4 (fourth resistor), R5 (fifth resistor), R6 (sixth resistor), R7 (seventh resistor), R8 (eighth resistor), and a positive and a negative power supply. Both the positive and negative power supplies are DC power supplies with voltage values ​​of V. CC and -V CC Its specific value can be determined based on the positive and negative voltage ratings of the operational amplifier, for example, choosing V... CC 5V or 3.3V (correspondingly, -V) CC (Voltage is -5V or -3.3V).

[0129] Furthermore, the positive input terminal of the first operational amplifier U1 is electrically connected to the output terminal of the waveform extraction circuit 11 through the fourth resistor R4, and the negative input terminal is connected to the negative power supply (-V) through the fifth resistor R5. CC The output terminal is electrically connected to both the control terminal of the first switching device q1 and the control terminal of the second switching device q2; the input terminal of the first switching device q1 is connected to the positive power supply (V) through the sixth resistor R6. CC The output terminal is electrically connected to the negative input terminal of the first operational amplifier U1; the input terminal of the second switching device q2 is connected to the positive power supply (V) through the seventh resistor R7. CC The output terminal is electrically connected to the positive input terminal of the second operational amplifier U2; the negative input terminal of the second operational amplifier U2 is electrically connected to the ground terminal, and the output terminal is used to output the envelope (Vout), and is also electrically connected to the ground terminal through the eighth resistor R8; the first capacitor C E One end of the resistor R3 is electrically connected to the positive input terminal of the second operational amplifier U2, and the other end is electrically connected to the ground terminal; similarly, one end of the third resistor R3 is electrically connected to the positive input terminal of the second operational amplifier U2, and the other end is electrically connected to the ground terminal.

[0130] The waveform of the Vout signal output by the envelope extraction circuit 12 is... Figure 5 The envelope in the diagram, and the working principle of the envelope extraction circuit 12 is as follows:

[0131] In Vsurge_C During the rapid ascent phase, Vs after voltage division (equivalent to V) surge_C ) Enters the positive input terminal of the first operational amplifier U1, and interacts with -V CC The output voltage signal, after comparison, will simultaneously control the first switching device q1 and the second switching device q2 to remain continuously on, thereby causing the first capacitor C to... E Charge until V surge_C The peak value, and the V output of the second operational amplifier U2. out Rapidly rise to V surge_C Peak value;

[0132] When V surge_C After its peak point begins to decline, the voltage signal output by the first operational amplifier U1 reverses, and the first switching device q1 and the second switching device q2 remain off. After this, the first capacitor C... E Entering the discharge state, during this process, other surge voltages such as A and B cannot exceed the capacitor C. E The potential, therefore the V output of operational amplifier U2 out The voltage decreases slowly until the surge voltage C of the next cycle triggers the first switching device q1 and the second switching device q2 to turn on again.

[0133] Analog-to-digital conversion (ADC) can be performed using an AD converter that meets the sampling rate, speed, and accuracy requirements, followed by further digital signal processing. It can be observed that by outputting a signal in envelope form, the peak value of the surge voltage C is preserved while effectively filtering voltage fluctuations caused by other surge voltages, thus effectively reducing the accuracy requirements for AD conversion and data processing. In some specific embodiments, an AD9248, for example, can be used as the AD converter, with a range of ±12V and an accuracy higher than 5mV.

[0134] In some preferred embodiments, the first switching device q1 and the second switching device q2 are both NPN bipolar junction transistors, with their base as the control terminal, collector as the input terminal, and emitter as the output terminal. Using NPN bipolar junction transistors to construct switching devices can effectively improve the response speed of the circuit.

[0135] The first operational amplifier U1 and the second operational amplifier U2 can be constructed using operational amplifiers with suitable parameters. Their bandwidth and slew rate have a significant impact on the accuracy of envelope extraction. Specifically, the slew rate and bandwidth of the operational amplifiers are calculated according to equation (19).

[0136]

[0137] Where SR is the slew rate of the operational amplifier, V m f is the maximum output voltage of the operational amplifier.max This is the maximum operating frequency of the circuit. Since the switching speed of a SiC MOSFET is approximately 5A / ns, and the switching duration of a SiC MOSFET under inverter conditions is approximately 30ns, therefore f... max Preferably, the frequency should be no less than 100MHz. To fully utilize the ADC accuracy and without exceeding the ADC range, the frequency should be within V. m Based on a value of 5V, calculations show that SR is at least 3.14V / ns.

[0138] In one specific embodiment, U1 and U2 can use an operational amplifier of model LM7171 with a bandwidth of 200MHz and a slew rate of 4.1V / ns.

[0139] Combination Figure 5 As can be seen from the previous analysis, the formation of the envelope can be divided into a charging phase and a discharging phase. The charging phase is generally shorter, much shorter than the switching process of a SiC MOSFET; the envelope morphology during the discharging phase is similar to that of R3 and C. E The value is related to the two V values. surge_C Between peak values, R3 and C E The value should satisfy equation (20) to maximize C. E The voltage won't drop too much:

[0140]

[0141] Among them, f sw Where is the switching frequency of the SiC MOSFET, and K is the discharge coefficient.

[0142] The ranges of the above parameters can be reasonably set according to the specific operating conditions of the SiC inverter and the requirements for data acquisition accuracy. For example, in a specific embodiment, K=5, the switching frequency of the SiC inverter is 20kHz, R3 is 47kΩ, and C... E The value is 10nF. In other embodiments, the parameter values ​​of the above-mentioned devices can also be reasonably set according to the specific parameters of the SiC MOSFET under test.

[0143] Similarly, although Figure 2 The illustrated embodiment provides optional resistance values ​​for resistors R4 to R8. However, in other embodiments, the resistance values ​​can be flexibly adjusted according to the specifications of the SiC MOSFET under test, and taking into account the range, accuracy, and speed characteristics of the operational amplifier and switching devices.

[0144] Figure 11 The illustrated embodiment shows that, according to Figure 2 The physical diagram of the online measurement circuit 1 manufactured from the circuit schematic is shown.

[0145] VI. Online monitoring of gate oxide degradation in SiC MOSFETs

[0146] Some embodiments of this application provide a method for monitoring the gate oxide degradation of a SiC MOSFET based on drain-source surge characteristics, the method comprising:

[0147] During the operation of the SiC inverter, the V of the tested SiC MOSFET is... S The peak value of the waveform signal envelope is measured online, and the drain-source current I of the tested SiC MOSFET in the turn-on state is measured. D_ON Online measurements are performed, where V S The voltage between the Kelvin source and the power source of the SiC MOSFET under test;

[0148] The gate oxide degradation level of the SiC MOSFET under test is monitored using a pre-calibrated estimation model and online measurement results of the SiC MOSFET under test.

[0149] Figure 12 A specific embodiment of the method is shown, see reference. Figure 12 During the operation of the SiC inverter, after identifying the SiC MOSFET under test, V can be obtained through the aforementioned online measurement circuit. S The envelope of the signal is measured, and the drain-source current in the on-state is measured using devices such as current probes. The measurement results can be converted from analog to digital using a dual-channel AD converter such as the aforementioned AD9248, and the peak information of the envelope is extracted. Then, the peak value of the envelope and I... D_ON The results were compared with a preset gate oxide degradation estimation model to obtain an estimate of the gate oxide degradation level of the tested SiC MOSFET. Furthermore, after monitoring one tested SiC MOSFET, the measured and compared MOSFETs can be replaced, and the above measurement and comparison process can be repeated.

[0150] During the monitoring of the SiC MOSFET under test, it is necessary to acquire V... S Envelope information and I D_ON The reason for conducting the measurement is that, as can be seen from equations (2) and (10), V surge_C Subject to drain-source current I before turn-off D The stable value (i.e., I) D_on The influence represented by ) is due to the fact that the I of the SiC inverter varies depending on its operating conditions. D_on They are not the same; therefore, when comparing measurement results with models of gate oxide degradation, the same I0 should be considered. D_on conduct.

[0151] VII. Establishing an estimation model for the gate oxide layer degradation degree of SiC MOSFETs

[0152] A model for estimating the gate oxide degradation level of SiC MOSFETs is used to reflect the performance of undegraded SiC MOSFETs under various operating conditions (with different Ig values). D_on The drain-source voltage surge C (as analyzed above, can be represented by V) is a factor of the drain-source voltage surge. S Characterized by the peak value of the envelope, generally, V can be used. surge_C_fresh =f(I D The function curve is represented in the form of (), and this function curve can be constructed using... Figure 13 The calibration experimental equipment shown is used for offline measurement. The experimental principle is similar to that of the double-pulse test. Q and DUT are both fresh, non-degraded SiC MOSFETs. V1 is a constant voltage source that provides a small constant voltage (e.g., 4V) to keep Q normally closed. L is the load inductor, and its inductance value can be determined according to the SiC MOSFET specifications (e.g., a 100uH inductor). The data acquisition part includes a measurement circuit and a current probe. The measurement circuit is the aforementioned online measurement circuit for outputting the VS waveform envelope.

[0153] Figure 14 The embodiment shows a physical diagram of the calibration experimental equipment. As shown in the figure, the controller is used to generate the drive signal for the DUT, and the DC Bus Capacitor is used to stabilize the voltage, making V BUS The voltage is maintained at a set value (e.g., 300V), and the driver generates N high-level times for a duration of t. high The low-level time is t low The gate pulse causes each group of I... D The value increases sequentially as shown in equation (21):

[0154]

[0155] N groups of I can be continuously measured using a measuring circuit and a current probe. D and V surge_C .

[0156] Table 1 shows the specific experimental parameters of the calibration equipment in a certain calibration experiment:

[0157] Table 1

[0158]

[0159]

[0160] Since the maximum continuous current of the DUT is 25A, according to equation (21), N is taken as 8, thigh A value of 1.4 µs was obtained. A calibration experiment was performed using a fresh SiC MOSFET, and the drain-source voltage VUT was acquired via an oscilloscope. DS Surge voltage V surge_C and drain-source current I D The waveform is as follows Figure 15 As shown in section (a), with I D The increase of V surge_C Gradually increase, in I D After exceeding 22.4A, due to dI D The absolute value of / dt no longer increases, and the values ​​of R3 and C in the measurement circuit are no longer increasing. E A discharge circuit is formed, making V surge_C The curve shows a downward trend; therefore, the surge voltage C is related to the current, which is consistent with the previous analysis. According to... Figure 15 As can be seen from the curve in part (b), in I D After exceeding 22.4A, dI D The absolute value of / dt remains at 77.1 A / us, therefore V surge_C No further increases are made. Furthermore, at a bus voltage of 300V, with the gate drive parameters remaining constant, V... surge_C with I D Relationship such as Figure 16 As shown, V can be obtained by fitting the measurement results. surge_C with I D The relationship curve, for example, for Figure 16 By fitting the data, we can obtain the undegraded fitting curve shown in equation (22) (that is, the gate oxide degradation estimation model of the DUT-type SiC MOSFET):

[0161]

[0162] After obtaining the above-mentioned non-degraded fitting curves, the Vt of each tested SiC MOSFET can be acquired in real time during its turn-off process while the SiC inverter is operating. S The peak value of the envelope (in this application, the measured value is denoted as V) surge_C_real ) and the corresponding I D_on Then, using this non-degenerate fitted curve, the performance at the same I... D In the case of V surge_C_real With V surge_C_fresh The degree of deviation is used to estimate the degree of degradation of the tested SiC MOSFET.

[0163] In some preferred embodiments, it is also possible to use Figure 13 , Figure 14Using experimental equipment, offline measurements were performed on several SiC MOSFETs with different gate oxide degradation levels. The offline measurement results were combined with the fitting curves of the fresh SiC MOSFETs before degradation to obtain the degradation tolerance table T. ol =TABLE(I D In the embodiments of this application, to clearly distinguish the curve V used to establish the non-degenerate fitting curve... surge_C_fresh =f(I D Fresh SiC MOSFETs and the tolerance table T for generating degradation levels ol =TABLE(I D SiC MOSFETs at different degradation levels are referred to as first-calibrated SiC MOSFETs and second-calibrated SiC MOSFETs.

[0164] Obviously, the second-calibrated SiC MOSFET needs to undergo different degrees of aging beforehand, and its aging degree needs to be monitored. This operation can be achieved through... Figure 17 The device shown is implemented, Figure 17 Part (a) is the circuit schematic, in which SMU1 is used to apply high electrical field stress to the gate of the DUT (i.e., the second calibrated SiC MOSFET). Simultaneously, SMU1 and SMU2 can be used to measure the V0 of the DUT. TH When SMU1 applies a gate-source scan voltage, the drain-source voltage provided by SMU2 remains unchanged. D Exceeding the threshold current I th The gate-source voltage at that time is V. TH As shown in the physical diagram in part (b) of the figure, the temperature chamber is used to provide a high-temperature testing environment. The ambient temperature is set to 150℃, and the V of the DUT is measured periodically. TH The value is used to assess the aging degree of the DUT. The aging strategy for the second-calibrated SiC MOSFET is shown in Table 2.

[0165] Table 2

[0166]

[0167]

[0168] Figure 18 Part (a) shows the second-calibrated SiC MOSFE at the turn-off moment V after different aging times. surge_C The changes indicate that the V of the second-calibrated SiC MOSFET after aging... surge_C The values ​​are all greater than the V of a fresh, first-calibrated SiC MOSFET. surge_C_Fresh , Figure 18Part (b) can be used to explain the above results.

[0169] Figure 18 Part (b) shows I at the moment of shutdown. D The changes that occur with increasing aging duration, within the time interval t1 to t2, when the aging duration is less than 48 hours, dI D The absolute value of / dt increases with increasing duration, V surge_C It also increases accordingly; when the aging duration is greater than 48 hours but less than 72 hours, dI D The absolute value of / dt decreases as the aging duration increases, V surge_C It also decreases accordingly; when the aging duration is greater than 72 hours, dI D The absolute value of / dt increases with increasing V. surge_C It also increases, but remains greater than the V of a fresh SiC MOSFET. surge_C and dI D The absolute value of / dt, which is related to the previous discussion about dI at the moment of turn-off. D This is consistent with the analysis that / dt changes with aging.

[0170] V at turn-off for the second-calibrated SiC MOSFE under different aging durations surge_C with I D Relationship such as Figure 19 As shown, it can be seen that the same I D V below surge_C The value changes with the degree of aging.

[0171] Same I D The V between the aged SiC MOSFET (second-calibrated SiC MOSFET) and the fresh SiC MOSFET (first-calibrated SiC MOSFET) surge_C Peak voltage (ΔV) surge_C Differences in these parameters can be used to characterize gate oxide layer degradation.

[0172] ΔV surge_C =V surge_C_Aged -V surge_C_Fresh (twenty three),

[0173] The V at the beginning of the aging process of a SiC MOSFET can be used to... surge_C Called V surge_C_D V surge_C_D With V surge_C_fresh The difference is the tolerance value T. ol If ΔV surge_CIf the value exceeds the tolerance value, the SiC MOSFET is considered to have gate oxide aging; otherwise, the SiC MOSFET is considered healthy. The smallest ΔV value from the experiments can be taken. surge_C Used as a tolerance value, such as Figure 19 The yellow area indicates the region.

[0174] Table 3 records the information related to each I D The corresponding specific tolerance value T ol Using this degradation tolerance table, T can be... ol with I D Establish the lookup table relationship T ol =TABLE(I D ).

[0175] Table 3

[0176] <![CDATA[I D (A)]]> <![CDATA[T ol (mV)]]> 2.8 202 5.6 118 8.4 75 11.2 113 14 140 16.8 87 19.6 73 22.4 74

[0177] Figure 20 The embodiment illustrates a complete process for monitoring the gate oxide degradation level of individual SiC MOSFETs under test in a SiC inverter under operating conditions, wherein the gate oxide degradation estimation model used is derived from the fitted curve V surge_C_fresh =f(I D ) and the degradation tolerance table T ol =TABLE(I D The implementation of each step in this embodiment has been described in detail above.

[0178] VIII. Experimental Verification

[0179] To verify the effectiveness of the gate oxide layer degradation monitoring method provided in this application, in a specific embodiment, a system as follows was constructed. Figure 21 The three-phase six-bridge power topology shown is used for actual SiC inverter operation test. Parts (a) and (b) are the circuit schematic and physical diagram, respectively. The specific parameter settings of the test platform are shown in Table 4.

[0180] This verification experiment uses an oscilloscope to acquire the V0 of the SiC MOSFET under test. DS Phase current I A I D and V surge_C (by collecting V) S (Information obtained), some experimental data such as Figure 22 As shown, under the target Q-axis current, the phase current is stable, the phase voltage exhibits surge phenomena, the peak envelope extraction value is stable, and V surge_C It increases with the increase of the absolute value of the drain current, which is consistent with the previous analysis and meets expectations.

[0181] Table 4

[0182] Experimental settings parameters value Switching frequency 20kHz Q-axis target current 23A LOAD SIC MOSFET Cree C3M0016120K LOAD L 200uL V mcu 300V V motor 300V NI FPGA PXIe-7822

[0183] Verification experiments were conducted on healthy and aged SiC MOSFETs, respectively, in I D_on The operating point is 19.6A, and V is substituted into the equation. surge_C_fresh =f(I D The obtained V surge_C_fresh and lookup table T ol =TABLE(I D The obtained T ol The data was compared.

[0184] Figure 23 Experimental results for healthy SiC MOSFETs are presented, showing that in I D_on When = 19.6A, the experimentally measured V surge_C_Healthy Value and V surge_C_fresh The difference is 35mV, which is less than the tolerance value T obtained from the table. ol Therefore, it can be assumed that the health status of its gate oxide layer has not changed, and it belongs to a healthy SiC MOSFET.

[0185] Figure 24 Experimental results of aged SiC MOSFETs are presented, showing that in I D_on When = 19.6A, the experimentally measured V surge_C_Aged Value and V surge_C_fresh The difference is 92mV, which exceeds the tolerance value T obtained from the table. ol It can be assumed that the health of its gate oxide layer has changed significantly, and this SiC MOSFET is an aged SiC MOSFET.

[0186] Some embodiments of this application also provide a SiC MOSFET gate oxide degradation monitoring system based on drain-source voltage surge characteristics, such as... Figure 25 As shown, the monitoring system includes:

[0187] The aforementioned online measurement circuit is used to measure the Vt of the SiC MOSFET under test during the operation of the SiC inverter. S The peak value of the envelope of the waveform signal is measured online;

[0188] The current measurement module is used to measure the drain-source current of the SiC MOSFET under test in the turn-on state during the operation of the SiC inverter.

[0189] The monitoring module uses a pre-calibrated gate oxide degradation estimation model and online measurement results of the SiC MOSFET under test to monitor the gate oxide degradation level of the SiC MOSFET under test.

[0190] The specific implementation methods of the online measurement circuit and current measurement module have been described above. In some specific embodiments, the monitoring module can be implemented in a manner known to those skilled in the art. For example, it can use devices including but not limited to digital signal processors (DSPs), microcontroller units (MCUs), field-programmable gate arrays (FPGAs), and embedded systems based on Linux or RTOS. The gate oxide degradation estimation model can be pre-stored in built-in or external storage units, and the aforementioned comparison operation between the measurement data and the degradation estimation model can be performed through a pre-installed executable program. Furthermore, the system can also include a display device and an interactive interface to achieve real-time display of monitoring results, switching of the power device under test, and parameter adjustment functions.

[0191] The specific embodiments of this application have been described in detail above. For those skilled in the art, several improvements and modifications can be made to this application without departing from the principle of this application, and these improvements and modifications also fall within the protection scope of the claims of this application.

Claims

1. An online measurement circuit for performing online measurements on the SiC MOSFET under test in the SiC inverter during the operation of the SiC inverter, characterized in that, include: The waveform extraction circuit is used to extract the voltage waveform signal between the Kelvin source and the power source of the SiC MOSFET under test and perform voltage division output. An envelope extraction circuit is used to extract and output the envelope of the voltage waveform signal output by the waveform extraction circuit. The peak value of the envelope is used to characterize the degree of gate oxide degradation of the SiC MOSFET under test. The envelope extraction circuit includes a first operational amplifier, a second operational amplifier, a first switching device, a second switching device, a first capacitor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a seventh resistor, an eighth resistor, a positive power supply, and a negative power supply. The positive input terminal of the first operational amplifier is electrically connected to the output terminal of the waveform extraction circuit through a fourth resistor, the negative input terminal is electrically connected to the negative power supply through a fifth resistor, and the output terminal is electrically connected to the control terminal of the first switching device and the control terminal of the second switching device. The input terminal of the first switching device is electrically connected to the positive power supply through the sixth resistor, and the output terminal is electrically connected to the negative input terminal of the first operational amplifier. The input terminal of the second switching device is electrically connected to the positive power supply through the seventh resistor, and the output terminal is electrically connected to the positive input terminal of the second operational amplifier. The negative input terminal of the second operational amplifier is electrically connected to the ground terminal, and the output terminal is used to output the envelope and is electrically connected to the ground terminal through the eighth resistor; Both ends of the first capacitor and both ends of the third resistor are connected between the positive input terminal and the ground terminal of the second operational amplifier.

2. The online measurement circuit according to claim 1, characterized in that, The waveform extraction circuit includes a first resistor and a second resistor connected in series; The first end of the first resistor is electrically connected to the Kelvin source of the SiC MOSFET under test, the second end is electrically connected to the first end of the second resistor and serves as the output terminal of the waveform extraction circuit, and the second end of the second resistor is electrically connected to the power source of the SiC MOSFET under test and the ground terminal.

3. The online measurement circuit according to claim 2, characterized in that, The ratio of the resistance of the first resistor to the resistance of the second resistor is greater than or equal to 2.

4. The online measurement circuit according to claim 1, characterized in that, Both the first and second switching devices are NPN bipolar junction transistors, with the base as the control terminal, the collector as the input terminal, and the emitter as the output terminal.

5. The online measurement circuit according to claim 1, characterized in that, The resistance value of the third resistor With the capacitance value of the first capacitor Satisfy the following formula: ， in, The switching frequency of the SiC MOSFET under test is... This represents the discharge coefficient.

6. The online measurement circuit according to claim 1, characterized in that, The maximum operating frequency of both the first operational amplifier and the second operational amplifier is not less than 100MHz, and the slew rate is not less than 3.14V / ns.

7. A method for monitoring gate oxide degradation of SiC MOSFETs based on drain-source voltage surge characteristics, characterized in that, include: During the operation of the SiC inverter, the online measurement circuit described in claim 1 is used to measure the SiC MOSFET under test. The peak value of the waveform signal envelope is measured online, as is the drain-source current of the SiC MOSFET under test in the turn-on state. The voltage between the Kelvin source and the power source of the SiC MOSFET under test; The gate oxide degradation level of the SiC MOSFET under test is monitored using a pre-calibrated estimation model and online measurement results of the SiC MOSFET under test.

8. The SiC MOSFET gate oxide degradation monitoring method based on drain-source voltage surge characteristics according to claim 7, characterized in that, The gate oxide layer degradation estimation model includes a non-degraded fitting curve, which is obtained through the following steps: Offline measurements were performed on the first calibrated SiC MOSFET to obtain its drain-source current in the turn-on state under several different operating conditions. The peak value of the envelope of the waveform signal, wherein the first calibrated SiC MOSFET is a SiC MOSFET of the same type as the SiC MOSFET under test and which has not degraded; Curve fitting was performed on the offline measurement results of the first calibrated SiC MOSFET to obtain the non-degraded fitting curve.

9. The SiC MOSFET gate oxide degradation monitoring method based on drain-source voltage surge characteristics according to claim 8, characterized in that, The gate oxide layer degradation estimation model also includes a degradation tolerance table, which is obtained through the following steps: Offline measurements were performed on several different second-calibration SiC MOSFETs to obtain the drain-source current and output current of each second-calibration SiC MOSFET in the turn-on state under several different operating conditions. The peak value of the envelope of the waveform signal, wherein several different second-calibrated SiC MOSFETs are SiC MOSFETs of the same type as the SiC MOSFET under test but in different degradation states; Based on offline measurement results of several different second-calibrated SiC MOSFETs and undegraded fitting curves, a degradation tolerance table was obtained.

10. A SiC MOSFET gate oxide degradation monitoring system based on drain-source voltage surge characteristics, characterized in that, include: The online measurement circuit as described in claim 1 is used to measure the SiC MOSFET under test during the operation of the SiC inverter. The peak value of the envelope of the waveform signal is measured online; The current measurement module is used to measure the drain-source current of the SiC MOSFET under test in the turn-on state during the operation of the SiC inverter. The monitoring module uses a pre-calibrated gate oxide degradation estimation model and online measurement results of the SiC MOSFET under test to monitor the gate oxide degradation level of the SiC MOSFET under test.

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