Synchronous binary ratio multiplier chip test method, device and equipment and storage medium

Abstract

The invention belongs to the technical field of integrated circuits, and discloses a synchronous binary ratio multiplier chip testing method, device and equipment and a storage medium. The method comprises the following steps: starting an automatic test device and performing self-inspection, and then dynamically configuring test parameters; generating a boundary value and random sampling combination by utilizing a divide-and-conquer algorithm on the basis of the test parameters, executing a rate multiplication function test, a synchronous loading function test and a zero clearing function test in parallel to obtain a function test result, and monitoring phase deviation of a clock signal and an output signal in real time by adopting a time sequence closed-loop feedback circuit to obtain a time sequence parameter measurement result; a programmable load module of the ATE is connected with an output pin of the chip to be tested, load resistance is dynamically scanned, a curve of output voltage changing along with load is recorded, and an electrical characteristic test result is obtained; and generating a test report by integrating a plurality of test results, and realizing efficient function verification by utilizing dynamic configuration input parameters and multi-mode parallel test.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit testing, and particularly to a testing method, device, equipment and storage medium for a synchronous binary ratio multiplier chip. Background Art

[0002] The SN7497 chip is a rate multiplier based on a binary control word, and its function is to generate a pulse output proportional to the input data by inputting a clock signal and a control word. The traditional testing methods have the following problems:

[0003] 1. The cost of traditional high-end testing machines is high, and it is difficult for small and medium-sized manufacturers to bear.

[0004] 2. The testing methods for old-fashioned logic chips such as SN7497 rely on manual operations (such as verifying point by point with an oscilloscope), which are inefficient and error-prone.

[0005] 3. Existing low-cost testing systems lack dedicated testing algorithms and vector generation methods for ratio multiplier chips.

[0006] 4. Low testing coverage: The manually generated test vectors are difficult to cover all combinations of control words and input data.

[0007] 5. Timing complexity: It is necessary to verify the strict synchronization between the output pulse and the clock signal. The traditional method relies on external circuit simulation, which is costly and inefficient.

[0008] 6. Single function mode: The co-testing of the clear and synchronous load functions is not integrated.

[0009] The above content is only used to assist in understanding the technical solution of the present invention, and does not represent an admission that the above content is prior art. Summary of the Invention

[0010] The main purpose of the present invention is to provide a testing method, device, equipment and storage medium for a synchronous binary ratio multiplier chip, aiming to solve the technical problems of high current testing cost, low efficiency and single testing module.

[0011] To achieve the above purpose, the present invention provides a testing method for a synchronous binary ratio multiplier chip, and the testing method for the synchronous binary ratio multiplier chip includes the following steps:

[0012] Start the automatic test ATE device, establish a communication connection with the chip to be tested, and perform an initialization self-check to ensure the normal operation of the ATE device, and dynamically configure test parameters, where the test parameters include a control word, input data and a clock frequency, and the chip to be tested is a synchronous binary ratio multiplier chip;

[0013] Based on the test parameters and using a divide-and-conquer algorithm to generate a combination of boundary values and random sampling, parallelly execute the rate multiplication function test, the synchronous loading function test, and the clearing function test to obtain the functional test results;

[0014] Adopt a timing closed-loop feedback circuit to monitor the phase offset between the clock signal and the output signal in real time to obtain the timing parameter measurement results;

[0015] Connect the output pins of the chip under test through the programmable load module of the ATE device, dynamically scan the load resistance and record the curve of the output voltage changing with the load to obtain the electrical characteristic test results;

[0016] Generate a test report including the timing error rate, the functional matching rate, and the electrical parameters by synthesizing the functional test results, the timing parameter measurement results, and the electrical characteristic test results.

[0017] In some embodiments, start the automatic test ATE device, establish a communication connection with the chip under test, and perform an initialization self-check to ensure the normal operation of the ATE device, and dynamically configure the test parameters, including:

[0018] Start the ATE device, execute the self-check process, and verify the voltage output accuracy of the PMU module of the ATE device;

[0019] Verify the contact reliability between the pins of the chip under test and the test channels of the ATE device through open / short circuit detection;

[0020] Configure the test environment parameters through an external temperature control device, and the environment parameters include the ambient temperature;

[0021] Allocate the digital input channels of the ATE device to the clock signal pin, the data input signal pin, the control signal pin, and the enable signal pin of the chip under test, and allocate the digital output channels of the ATE device to the pulse output pin of the chip under test;

[0022] Initialize the clock signal, set the initial phase of the clock signal to 0 ns, the frequency to 1 MHz, and the duty cycle to 50%.

[0023] In some embodiments, the generating a combination of boundary values and random sampling based on the test parameters and using a divide-and-conquer algorithm, and parallelly executing the rate multiplication function test, the synchronous loading function test, and the clearing function test to obtain the functional test results, includes:

[0024] According to the binary ratio multiplication logic of the chip under test, generate input combinations of all 0s, all 1s, and random ratio values;

[0025] Based on the error rate between the output pulse count and the theoretical value counted by the bit error rate detection module of the ATE device for the said input combination, and combined with the clear function test, determine the correctness of the function;

[0026] Execute the coverage boundary condition test based on the said input combination to verify whether the output duty cycle is 50% when the input data is the intermediate value;

[0027] Based on the said input combination, dynamically switch the enable signal state during the parallel execution rate multiplication function test, synchronous load function test and clear function test, and verify whether the output starts and stops correctly with the enable signal state.

[0028] In some embodiments, the method uses a timing closed-loop feedback circuit to monitor the phase shift between the clock signal and the output signal in real time, and obtain the timing parameter measurement results, including:

[0029] Set the frequency of the clock signal to 2 MHz, and adjust the advance time of the data signal on the data input pin of the chip under test relative to the rising edge of the clock signal in steps of 1 ns;

[0030] Detect whether the output matches the adjusted advance time through the digital comparator of the ATE device. If it matches, determine the minimum setup time through the digital comparator;

[0031] Based on the minimum setup time, after the rising edge of the CLK is triggered, use the timestamp recording function to capture the delay of the output signal jumping from the first level to the second level. After reaching the number of measurements, eliminate the outliers and take the arithmetic mean as the transmission delay.

[0032] In some embodiments, the method connects the output pin of the chip under test through the programmable load module of the ATE device, dynamically scans the load resistance and records the curve of the output voltage changing with the load to obtain the electrical characteristic test results, including:

[0033] Apply the first level and the second level to the input signal pin and the enable signal pin in sequence through the PMU module, and measure the input leakage current respectively to verify the static power consumption characteristics of the input end;

[0034] Connect the programmable load resistance to the output pin, scan the load change and record the output voltage to simulate the driving ability under the actual application scenario;

[0035] Draw the curve of the output level changing with the load current to determine whether it meets the preset requirements.

[0036] In some embodiments, the method further includes:

[0037] Run open circuit or short circuit detection before the test starts to ensure that all pins of the chip under test are connected normally;

[0038] If the first test fails, it will automatically retry based on the set number of times;

[0039] When the PMU voltage drift of the ATE device exceeds a set threshold, a corresponding prompt is output, where the prompt is used to remind the user to recalibrate the ATE device.

[0040] In some embodiments, the method further comprises:

[0041] Setting a decision threshold, wherein the decision threshold is used to provide a quantitative standard for automated decision making;

[0042] Compare the test results with the theoretical values item by item, calculate the error rate and pass rate, and dynamically update the test progress and statistical results;

[0043] Automatically generate a test report containing a test summary, detailed data table, and error list. The test report can be exported in multiple formats and displays test results including timing parameter distribution, drive capability curve, and phase compensation effect through visual charts.

[0044] The test results are stored in a database to create a chip test file, which is used for historical data query, batch comparison and trend analysis.

[0045] In addition, to achieve the above-mentioned object, the present invention further provides a synchronous binary rate multiplier chip testing device, the synchronous binary rate multiplier chip testing device comprising:

[0046] a configuration module for starting an automatic test ATE device, establishing a communication connection with a chip to be tested, performing an initialization self-test to ensure normal operation of the ATE device, and dynamically configuring test parameters, the test parameters including a control word, input data, and clock frequency, wherein the chip to be tested is a synchronous binary rate multiplier chip;

[0047] A testing module is used to generate boundary values and random sampling combinations based on the test parameters and using a divide-and-conquer algorithm, and to execute a rate multiplication function test, a synchronous loading function test, and a clearing function test in parallel to obtain a function test result;

[0048] The test module is used to monitor the phase offset between the clock signal and the output signal in real time using a timing closed-loop feedback circuit to obtain timing parameter measurement results;

[0049] The test module is used to connect the output pin of the chip to be tested through the programmable load module of the ATE equipment, dynamically scan the load resistance and record the curve of the output voltage changing with the load to obtain the electrical characteristics test result;

[0050] A reporting module, configured to generate a test report including a timing error rate, a function matching rate, and electrical parameters by integrating the functional test results, the timing parameter measurement results, and the electrical characteristic test results.

[0051] In addition, to achieve the above object, the present invention further provides a synchronous binary ratio multiplier chip test device, which includes: a memory, a processor, and a synchronous binary ratio multiplier chip test program stored on the memory and executable on the processor. The synchronous binary ratio multiplier chip test program is configured to implement the steps of the synchronous binary ratio multiplier chip test method as described above.

[0052] In addition, to achieve the above object, the present invention further provides a storage medium with a synchronous binary ratio multiplier chip test program stored thereon. When the synchronous binary ratio multiplier chip test program is executed by a processor, it implements the steps of the synchronous binary ratio multiplier chip test method as described above.

[0053] In the present invention, an automatic test ATE device is started, a communication connection with the chip to be tested is established, and an initialization self-check is performed to ensure the normal operation of the ATE device. Test parameters are dynamically configured, and the test parameters include a control word, input data, and a clock frequency. The chip to be tested is a synchronous binary ratio multiplier chip. Based on the test parameters and using a divide-and-conquer algorithm, a combination of boundary values and random sampling is generated, and the rate multiplication function test, the synchronous loading function test, and the clearing function test are executed in parallel to obtain functional test results. A timing closed-loop feedback circuit is used to monitor the phase shift between the clock signal and the output signal in real time to obtain timing parameter measurement results. The output pins of the chip to be tested are connected through the programmable load module of the ATE device, the load resistance is dynamically scanned, and the curve of the output voltage changing with the load is recorded to obtain electrical characteristic test results. A test report including a timing error rate, a function matching rate, and electrical parameters is generated by integrating the functional test results, the timing parameter measurement results, and the electrical characteristic test results. The above method realizes efficient function verification by using dynamically configured input parameters and multi-mode parallel testing. Description of the Drawings

[0054] Figure 1 It is a schematic flowchart of the first embodiment of the synchronous binary ratio multiplier chip test method of the present invention;

[0055] Figure 2 It is a connection diagram of the chip pins and the ATE device channels in the synchronous binary ratio multiplier chip test method of the present invention;

[0056] Figure 3 It is a flowchart of dynamic clock phase compensation in the synchronous binary ratio multiplier chip test method of the present invention;

[0057] Figure 4 This is the logic block diagram of the channel board in the test method of the synchronous binary ratio multiplier chip of the present invention;

[0058] Figure 5 This is the structural block diagram of the first embodiment of the test device for the synchronous binary ratio multiplier chip of the present invention.

[0059] The realization, functional features and advantages of the object of the present invention will be further described in conjunction with the embodiments with reference to the accompanying drawings. Specific embodiments

[0060] It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0061] The embodiment of the present invention provides a test method for a synchronous binary ratio multiplier chip. Refer to Figure 1 , Figure 1 This is the flow schematic diagram of the first embodiment of a test method for a synchronous binary ratio multiplier chip of the present invention.

[0062] In this embodiment, the test method for the synchronous binary ratio multiplier chip includes the following steps:

[0063] Step S10: Start the automatic test ATE device, establish a communication connection with the chip to be tested, perform an initialization self-check to ensure the normal operation of the ATE device, and dynamically configure test parameters.

[0064] In this embodiment, the execution subject of this embodiment is a test device for a synchronous binary ratio multiplier chip. Among them, the test device for the synchronous binary ratio multiplier chip has functions such as data processing, data communication, and program operation. The test device for the synchronous binary ratio multiplier chip can be a computer terminal device or other network devices. Of course, it can also be other devices with similar functions. This embodiment does not limit this.

[0065] In the specific implementation, the overall structure of the test system applied in this embodiment is first described. The test system architecture is divided into a hardware layer, a control layer, and a dynamic clock phase compensation unit. Among them, the hardware layer includes an ATE device, a DIP-16 adapter fixture, and a programmable load module. The control layer is based on an automation script and integrates test vector generation, data acquisition, and result analysis. The dynamic clock phase compensation unit realizes the automatic calibration of the phase offset between the CLK signal and the data signal through the timing programmability of the digital channels of the ATE device. The ratio multiplication output verification algorithm determines the correctness of the function based on the error tolerance between the statistical pulse count and the theoretical value. This dynamic clock phase compensation unit is also the core innovative module of this solution. The overall technical solution includes the following steps: Step 1: Device initialization and channel binding. Configure the PMU module of the ATE device to output a 5V power supply, and allocate digital channels to the CLK, data inputs (A0 - A5), control terminals (STROBE / S0 - S5), and output pins of the SN7497. Set the test environment parameters (such as temperature, sampling rate). Step 2: Function test vector generation. Generate multiple groups of input combinations (such as all 0s, all 1s, random ratio values) according to the binary ratio multiplication logic of the SN7497. Design a synchronous control strategy for the enable signal (STROBE) to verify the output enable / disable state switching. Step 3: Adaptive measurement of timing parameters. Setup / hold time test: By stepwise adjusting the time difference between the CLK rising edge and the data signal, use the bit error rate detection function of the ATE device to determine the critical value. Propagation delay test: Measure the time difference from the CLK rising edge to the output stabilization under a fixed load, and repeat multiple times to take the statistical median. Step 4: Electrical characteristic analysis. Input leakage current measurement: Apply high / low levels to the input pins and record the current values in real time through the PMU. Drive ability verification: Connect a programmable load resistor and test the curve of the output voltage changing with the load. Step 5: Automatic result determination. Automatically generate a test report through preset thresholds (such as timing error ≤ 10%, function matching rate ≥ 99.9%).

[0066] In a specific implementation, after starting the automatic test ATE device in this embodiment, it is necessary to establish a communication connection with the chip to be tested and perform an initialization self-check to ensure the normal operation of the ATE device, and dynamically configure test parameters. The specific process is to start the ATE device, execute the self-check process, and verify the voltage output accuracy of the PMU module of the ATE device; verify the contact reliability between the pins of the chip to be tested and the test channels of the ATE device through open / short detection; configure test environment parameters through an external temperature control device, and the environment parameters include the ambient temperature; allocate the digital input channels of the ATE device to the clock signal pin, data input signal pin, control signal pin, and enable signal pin of the chip to be tested, and allocate the digital output channels of the ATE device to the pulse output pin of the chip to be tested; initialize the clock signal, set the initial phase of the clock signal to 0 ns, the frequency to 1 MHz, and the duty cycle to 50%.

[0067] It should be noted that for device connection, install the chip to be tested, such as the SN7497 chip (DIP-16 package), onto a custom adapter fixture to ensure reliable contact between the pins and the test channels of the ATE device. Provide a power supply of 5V±0.1V to the chip through the PMU module of the ATE device, and set the current limit to 200 mA. Allocate the digital input channels to the clock signal CLK pin (pin 1), data input pins (pins 2-7), control signal pins (pins 9-14), and enable signal STROBE pin (pin 15). The specific pins can be referred to Figure 2 as shown. The logic of the channel board can be referred to Figure 3 as shown, and allocate the digital output channels to the pulse output pins of the chip (such as pins 10-14).

[0068] The voltage output accuracy requirement of the PMU is that the error ≤±1%, and the test environment temperature set by the external temperature control device is 25℃±3℃.

[0069] Step S20: Based on the test parameters, use the divide-and-conquer algorithm to generate a combination of boundary values and random sampling, and concurrently execute the rate multiplication function test, synchronous loading function test, and clear function test to obtain the function test results.

[0070] In a specific implementation, in this embodiment, functional testing needs to be performed first. Specifically, according to the binary ratio multiplication logic of the chip to be tested, input combinations of all 0s, all 1s, and random ratio values are generated; based on the input combinations, the error rate between the output pulse count and the theoretical value is statistically analyzed through the bit error rate detection module of the ATE device, and combined with the clear function test, the functional correctness is determined. Based on the input combinations, the boundary condition test is performed to verify whether the output duty cycle is 50% when the input data is the intermediate value; based on the input combinations, the enable signal state is dynamically switched during the parallel execution rate multiplication function test, synchronous load function test, and clear function test to verify whether the output starts and stops correctly with the enable signal state.

[0071] It should be noted that according to the binary ratio multiplication logic of the chip to be tested, such as SN7497, multiple groups of input combinations are generated to cover the following scenarios. For example, in basic verification, all 0s means 0 / 64, and all 1s means 63 / 64, and the output pulse count and the CLK cycle count × 63 / 64 are verified to verify the functional correctness. Another example is to cover the boundary condition test. The intermediate value is 32 / 64, and when the input is this intermediate value, it is verified whether the output duty cycle is 50%. Finally, enable control can be performed, and the enable signal state is dynamically switched during the test. For example, the enable STROBE signal state is switched from 0 → 1 → 0, and it is verified whether the output starts and stops correctly with the enable signal state through this change.

[0072] Further, in this embodiment, compensation for the dynamic clock phase will also be performed. The parameter settings and compensation can refer to Figure 4 As shown, the specific process includes completing the initialization phase parameters: setting the initial phase of the CLK signal to 0 ns and the frequency to 1 MHz (duty cycle 50%). Phase step adjustment: With a step size of 5 ns, the relative delay between the CLK signal and the data signals (A0 - A5) is gradually adjusted within the range of 0 - 100 ns. Bit error rate detection: The functional test is run at each phase point, and the error rate between the output pulse count and the theoretical value is statistically analyzed. Optimal phase selection: The phase value with the lowest bit error rate (≤0.1%) is selected as the final calibration parameter and saved to the ATE device configuration file.

[0073] Step S30: Use a timing closed-loop feedback circuit to monitor the phase offset between the clock signal and the output signal in real time to obtain the timing parameter measurement result.

[0074] In a specific implementation, for the chip under test, in this embodiment, its timing parameters are measured. The specific process is to set the frequency of the clock signal to 2 MHz, and adjust the advance time of the data signal of the data input pin of the chip under test relative to the rising edge of the clock signal in steps of 1 ns; detect whether the output matches the adjusted advance time through the digital comparator of the ATE device. If it matches, determine the minimum setup time through the digital comparator; after the minimum setup time is triggered at the rising edge of the CLK, use the timestamp recording function to capture the delay of the output signal jumping from the first level to the second level. After reaching the number of measurements, remove the outliers and take the arithmetic mean as the transmission delay.

[0075] It should be noted that the timing parameter measurement includes two processes: setup time measurement and transmission delay measurement. For the rated parameter settings in the setup time, refer to the above parameter settings. In the transmission delay measurement process, the first level is the low level and the second level is the high level. In actual situations, it can be measured 100 times. After removing the outliers, take the arithmetic mean as the final transmission delay.

[0076] Step S40: Connect the output pin of the chip under test through the programmable load module of the ATE device, dynamically scan the load resistance, and record the curve of the output voltage changing with the load to obtain the electrical characteristic test result.

[0077] In a specific implementation, in this embodiment, the chip under test also needs to be subjected to electrical characteristic tests. These electrical characteristic tests are divided into input leakage current tests and output drive ability verification. Specifically, the PMU module is used to apply the first level and the second level to the input signal pin and the enable signal pin in sequence, and measure the input leakage current respectively to verify the static power consumption characteristics of the input end; connect a programmable load resistor to the output pin, scan the load change and record the output voltage to simulate the drive ability under the actual application scenario; draw the curve of the output level changing with the load current to determine whether it meets the preset requirements.

[0078] It should be noted that when performing the input leakage current test, set the PMU to the high level mode, that is, the 5V mode, and apply a 5V voltage to the input signal pin and the enable signal pin in sequence to measure the input current I IH , and then switch the PMU to the low level mode, that is, the 0V mode, and measure the input current I IL . In the output drive ability verification, the range of the programmable load resistor is 50Ω - 1kΩ. Draw the curve of the high level V OH / V OL changing with the load current, and determine whether it meets the requirements of the specification. For example, V OH ≥2.4V, where V OH and V OL represent the voltage value at the output high level and the voltage value at the output low level respectively.

[0079] Step S50: Generate a test report including a timing error rate, a function matching rate, and electrical parameters based on the comprehensive function test results, the timing parameter measurement results, and the electrical characteristic test results.

[0080] In a specific implementation, this embodiment also has a corresponding exception handling mechanism for exception handling. Specifically, open-circuit or short-circuit detection is run before the test starts to ensure that all pins of the chip to be tested are normally connected; if the first test fails, automatic retry is performed based on a set number of times; when the PMU voltage drift of the ATE device exceeds a set threshold, a corresponding prompt is output, and the prompt is used to remind the user to recalibrate the ATE device.

[0081] It should be noted that the set number of times can be 3 times, that is, if the first test fails, it will be automatically retried 3 times to exclude the influence of random interference. The set threshold is ±2%. When the PMU voltage drift exceeds ±2%, the system prompts the user to recalibrate the device. The test time of the above test method is shortened from 120 minutes of the traditional method to 18 minutes, and there is no need for an external pulse counter and a timing analyzer, relying only on the built-in resources of the ATE. At the same time, for fault location, this embodiment supports outputting real-time error records (such as K / N values, CLK cycle numbers) to accelerate defect analysis.

[0082] Furthermore, a determination threshold can also be set in this embodiment, and the determination threshold is used to provide a quantitative standard for automatic determination; the test results are compared item by item with the theoretical values, the error rate and the qualification rate are calculated, and the test progress and statistical results are dynamically updated; a test report including a test summary, a detailed data sheet, and an error list is automatically generated, and the test report supports export in multiple formats, and the test results including the timing parameter distribution, the driving ability curve, and the phase compensation effect are displayed through visual charts; the test results are stored in a database to establish a chip test file, and the test file is used for historical data query, batch comparison, and trend analysis.

[0083] In this embodiment, the automatic test ATE device is started, a communication connection with the chip to be tested is established, and an initialization self-check is performed to ensure the normal operation of the ATE device, and the test parameters are dynamically configured. The test parameters include control words, input data, and clock frequencies. The chip to be tested is a synchronous binary ratio multiplier chip. Based on the test parameters and using the divide-and-conquer algorithm, a combination of boundary values and random sampling is generated, and the rate multiplication function test, synchronous loading function test, and clearing function test are executed in parallel to obtain the function test results. A timing closed-loop feedback circuit is used to monitor the phase shift between the clock signal and the output signal in real time to obtain the timing parameter measurement results. The output pins of the chip to be tested are connected through the programmable load module of the ATE device, and the load resistance is dynamically scanned and the curve of the output voltage changing with the load is recorded to obtain the electrical characteristic test results. A test report including the timing error rate, function matching rate, and electrical parameters is generated by integrating the function test results, the timing parameter measurement results, and the electrical characteristic test results. The above method realizes efficient function verification by using dynamically configured input parameters and multi-mode parallel testing.

[0084] In addition, an embodiment of the present invention also proposes a storage medium, on which a test program for a synchronous binary ratio multiplier chip is stored. When the test program for the synchronous binary ratio multiplier chip is executed by a processor, the steps of the synchronous binary ratio multiplier chip test method described above are implemented.

[0085] Referring to Figure 5 , Figure 5 is the structural block diagram of the first embodiment of the synchronous binary ratio multiplier chip test device of the present invention.

[0086] As Figure 5 shown, the synchronous binary ratio multiplier chip test device proposed by the embodiment of the present invention includes:

[0087] A configuration module 10, which is used to start the automatic test ATE device, establish a communication connection with the chip to be tested, perform an initialization self-check to ensure the normal operation of the ATE device, and dynamically configure test parameters. The test parameters include control words, input data, and clock frequencies. The chip to be tested is a synchronous binary ratio multiplier chip;

[0088] A test module 20, which is used to generate a combination of boundary values and random sampling based on the test parameters and use the divide-and-conquer algorithm to execute the rate multiplication function test, synchronous loading function test, and clearing function test in parallel to obtain the function test results;

[0089] The test module 20 is used to use a timing closed-loop feedback circuit to monitor the phase shift between the clock signal and the output signal in real time to obtain the timing parameter measurement results;

[0090] The test module 20 is configured to connect to the output pins of the chip under test through the programmable load module of the ATE device, dynamically scan the load resistance, and record the curve of the output voltage varying with the load to obtain the electrical characteristic test result;

[0091] The report module 30 is configured to generate a test report including the timing error rate, the function matching rate, and the electrical parameters by synthesizing the function test result, the timing parameter measurement result, and the electrical characteristic test result.

[0092] In this embodiment, the automatic test ATE device is started, a communication connection with the chip under test is established, and an initialization self-check is performed to ensure the normal operation of the ATE device. The test parameters are dynamically configured, and the test parameters include the control word, the input data, and the clock frequency. The chip under test is a synchronous binary ratio multiplier chip. Based on the test parameters, a combination of boundary values and random sampling is generated using the divide-and-conquer algorithm, and the rate multiplication function test, the synchronous loading function test, and the clear function test are executed in parallel to obtain the function test result. A timing closed-loop feedback circuit is used to monitor the phase shift between the clock signal and the output signal in real time to obtain the timing parameter measurement result. The output pins of the chip under test are connected through the programmable load module of the ATE device, the load resistance is dynamically scanned, and the curve of the output voltage varying with the load is recorded to obtain the electrical characteristic test result. A test report including the timing error rate, the function matching rate, and the electrical parameters is generated by synthesizing the function test result, the timing parameter measurement result, and the electrical characteristic test result. The above method realizes efficient function verification by using dynamically configured input parameters and multi-mode parallel testing.

[0093] In some embodiments,

[0094] The embodiment of the present application further provides a synchronous binary ratio multiplier chip test device, including a processor, a communication interface, a memory, and a communication bus. Among them, the processor, the communication interface, and the memory complete communication with each other through the communication bus. The memory is used to store the synchronous binary ratio multiplier chip test program. The processor is used to implement the above synchronous binary ratio multiplier chip test method when executing the program stored on the memory.

[0095] The communication bus mentioned in the above synchronous binary ratio multiplier chip test device may be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus, etc. This communication bus can be divided into an address bus, a data bus, a control bus, etc.

[0096] The communication interface is used for communication between the above-mentioned synchronous binary ratio multiplier chip test device and other devices.

[0097] The memory may include a random access memory (abbreviation: RAM in English: Random Access Memory), or may also include a non-volatile memory (abbreviation: NVM in English: Non-Volatile Memory), such as at least one disk memory. Optionally, the memory may also be at least one storage device located far from the aforementioned processor.

[0098] The aforementioned processor may be a general-purpose processor, including a central processing unit (abbreviation: CPU in English: Central Processing Unit), a network processor (abbreviation: NP in English: Network Processor), etc.; it may also be a digital signal processor (abbreviation: DSP in English: Digital Signal Processing), an application-specific integrated circuit (abbreviation: ASIC in English: Application Specific Integrated Circuit), a field-programmable gate array (abbreviation: FPGA in English: Field-Programmable Gate Array), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components.

[0099] In the above embodiments, it can be implemented in whole or in part by software, hardware, firmware, or any combination thereof. When implemented using software, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the processes or functions described in the embodiments of the present application are generated in whole or in part. The computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices. The computer instructions may be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions may be transmitted from one website, computer, server, or data center to another website, computer, server, or data center in a wired manner (such as coaxial cable, optical fiber, digital subscriber line (DSL)) or a wireless manner (such as infrared, wireless, microwave, etc.). The computer-readable storage medium may be any available medium that can be accessed by a computer, or a data storage device such as a server or data center that includes one or more integrated available media. The available medium may be a magnetic medium (for example, a floppy disk, a hard disk, a magnetic tape), an optical medium (for example, a DVD), or a semiconductor medium (for example, a solid-state disk (SSD)).

[0100] It should be noted that, in this document, relational terms such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprising", "including" or any other variant thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device comprising a series of elements not only includes those elements, but also includes other elements not expressly listed, or also includes elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "comprising one..." does not exclude the existence of additional identical elements in the process, method, article or device comprising the said element.

[0101] Each embodiment in this specification is described in a related manner. The same or similar parts among the embodiments can be referred to each other, and the differences between each embodiment and other embodiments are emphasized. In particular, for the system embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the description of the method embodiment.

[0102] The above embodiments are only used to illustrate the technical solutions of the present invention, not to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements for some of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

[0103] It should be understood that the above is only for illustration and does not constitute any limitation to the technical solutions of the present invention. In specific applications, those skilled in the art can set according to needs, and the present invention does not limit this.

[0104] It should be noted that the above-described work process is only illustrative and does not limit the protection scope of the present invention. In actual applications, those skilled in the art can select some or all of them according to actual needs to achieve the purpose of the embodiment solution, and there is no limitation here.

[0105] In addition, for the technical details not described in detail in this embodiment, reference can be made to the synchronous binary ratio multiplier chip test method provided in any embodiment of the present invention, which will not be elaborated here.

[0106] In addition, it should be noted that in this text, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, such that a process, method, article or system comprising a series of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article or system. Without further limitation, an element defined by the statement "comprising one..." does not exclude the presence of additional identical elements in the process, method, article or system comprising such element.

[0107] The serial numbers of the above embodiments of the present invention are only for description and do not represent the superiority or inferiority of the embodiments.

[0108] Through the description of the above embodiments, those skilled in the art can clearly understand that the above embodiment methods can be implemented by means of software plus a necessary general hardware platform. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on such an understanding, the technical solution of the present invention, in essence or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium (such as Read Only Memory (ROM) / RAM, magnetic disk, optical disc), and includes several instructions to enable a terminal device (which can be a mobile phone, computer, server, or network device, etc.) to execute the methods described in the various embodiments of the present invention.

[0109] The above are only the preferred embodiments of the present invention, and do not limit the patent scope of the present invention accordingly. Any equivalent structural or equivalent process transformation made by using the content of the specification and drawings of the present invention, or directly or indirectly applied in other related technical fields, shall be equally included in the patent protection scope of the present invention.

[0110] It can be understood that the system provided by the embodiments of the present invention corresponds to the method provided by the embodiments of the present invention. The explanations, examples and beneficial effects of the relevant content can refer to the corresponding parts in the above method.

Claims

1. A test method for a synchronous binary ratio multiplier chip, characterized in that, The test method for the synchronous binary ratio multiplier chip includes: Starting the automatic test ATE device, establishing a communication connection with the chip to be tested, and performing an initialization self-check to ensure the normal operation of the ATE device, and dynamically configuring test parameters, where the test parameters include control words, input data, and clock frequency, and the chip to be tested is a synchronous binary ratio multiplier chip; Generating a combination of boundary values and random sampling based on the test parameters and using the divide-and-conquer algorithm, and parallelly executing the rate multiplication function test, synchronous loading function test, and clearing function test to obtain the function test results; Using a timing closed-loop feedback circuit to monitor the phase shift between the clock signal and the output signal in real time to obtain the timing parameter measurement results; Connecting the output pins of the chip to be tested through the programmable load module of the ATE device, dynamically scanning the load resistance and recording the curve of the output voltage changing with the load to obtain the electrical characteristic test results; Generating a test report including the timing error rate, function matching rate, and electrical parameters by synthesizing the function test results, the timing parameter measurement results, and the electrical characteristic test results.

2. The synchronous binary ratio multiplier chip testing method according to claim 1, characterized in that, The starting the automatic test ATE device, establishing a communication connection with the chip to be tested, and performing an initialization self-check to ensure the normal operation of the ATE device, and dynamically configuring test parameters includes: Starting the ATE device, executing the self-check process, and verifying the voltage output accuracy of the PMU module of the ATE device; Verifying the contact reliability between the pins of the chip to be tested and the test channels of the ATE device through open / short circuit detection; Configuring the test environment parameters through an external temperature control device, where the environment parameters include the ambient temperature; Allocating the digital input channels of the ATE device to the clock signal pin, data input signal pin, control signal pin, and enable signal pin of the chip to be tested, and allocating the digital output channels of the ATE device to the pulse output pin of the chip to be tested; Initializing the clock signal, setting the initial phase of the clock signal to 0 ns, the frequency to 1 MHz, and the duty cycle to 50%.

3. The synchronous binary ratio multiplier chip testing method according to claim 1, characterized in that The generating a combination of boundary values and random sampling based on the test parameters and using the divide-and-conquer algorithm, and parallelly executing the rate multiplication function test, synchronous loading function test, and clearing function test to obtain the function test results includes: Generating input combinations of all 0s, all 1s, and random ratio values according to the binary ratio multiplication logic of the chip to be tested; Based on the input combinations, statistically analyzing the error rate between the output pulse number and the theoretical value through the bit error rate detection module of the ATE device, and combining the clearing function test to determine the function correctness; Performing a coverage boundary condition test based on the input combinations to verify whether the output duty cycle is 50% when the input data is the intermediate value; Based on the input combinations, dynamically switching the enable signal state during the parallel execution of the rate multiplication function test, synchronous loading function test, and clearing function test to verify whether the output starts and stops correctly with the enable signal state.

4. The synchronous binary ratio multiplier chip testing method according to claim 1, wherein, The using a timing closed-loop feedback circuit to monitor the phase shift between the clock signal and the output signal in real time to obtain the timing parameter measurement results includes: Set the frequency of the clock signal to 2 MHz and adjust the advance time of the data signal of the data input pin of the chip under test relative to the rising edge of the clock signal in 1 ns steps; Detect whether the output matches the adjusted advance time through the digital comparator of the ATE device. If it matches, determine the minimum setup time through the digital comparator; Based on the minimum setup time, after the rising edge of the CLK is triggered, use the timestamp recording function to capture the delay of the output signal jumping from the first level to the second level. After reaching the number of measurements, remove the outliers and take the arithmetic mean as the transmission delay.

5. The synchronous binary ratio multiplier chip testing method according to claim 1, characterized in that Connect the output pin of the chip under test through the programmable load module of the ATE device, dynamically scan the load resistance and record the curve of the output voltage changing with the load to obtain the electrical characteristic test results, including: Apply the first level and the second level to the input signal pin and the enable signal pin in sequence through the PMU module, and measure the input leakage current respectively to verify the static power consumption characteristics of the input end; Connect the programmable load resistor to the output pin, scan the load change and record the output voltage to simulate the driving ability under the actual application scenario; Draw the curve of the output level changing with the load current to determine whether it meets the preset requirements.

6. The test method for the synchronous binary ratio multiplier chip according to claim 1, wherein The method further includes: Run open-circuit or short-circuit detection before the test starts to ensure that all pins of the chip under test are normally connected; If the first test fails, perform automatic retry based on the set number of times; When the PMU voltage drift of the ATE device exceeds the set threshold, output a corresponding prompt, and the prompt is used to remind the user to recalibrate the ATE device.

7. The synchronous binary ratio multiplier chip testing method according to any one of claims 1 to 6, characterized in that, The method further includes: Set a determination threshold, and the determination threshold is used to provide a quantitative standard for automatic determination; Compare the test results with the theoretical values item by item, calculate the error rate and the qualification rate, and dynamically update the test progress and the statistical results; Automatically generate a test report including a test summary, a detailed data sheet and an error list. The test report supports multiple format exports and displays the test results including the timing parameter distribution, the driving ability curve and the phase compensation effect through visual charts; Store the test results in the database and establish a chip test file, and the test file is used for historical data query, batch comparison and trend analysis.

8. A synchronous binary ratio multiplier chip test device, characterized in that The synchronous binary ratio multiplier chip test device includes: A configuration module for starting the automatic test ATE device, establishing a communication connection with the chip under test, performing an initialization self-check to ensure the normal operation of the ATE device, and dynamically configuring test parameters, where the test parameters include a control word, input data and a clock frequency, and the chip under test is a synchronous binary ratio multiplier chip; A test module for generating a combination of boundary values and random sampling based on the test parameters and using the divide-and-conquer algorithm to perform a rate multiplication function test, a synchronous load function test and a clear function test in parallel to obtain function test results; The test module is used to use a timing closed-loop feedback circuit to monitor the phase shift between the clock signal and the output signal in real time to obtain timing parameter measurement results; The test module is used to connect to the output pins of the chip to be tested through the programmable load module of the ATE device, dynamically scan the load resistance and record the curve of the output voltage varying with the load, so as to obtain the electrical characteristic test result; The reporting module is used to generate a test report including the timing error rate, the function matching rate and the electrical parameters by synthesizing the function test result, the timing parameter measurement result and the electrical characteristic test result.

9. A synchronous binary ratio multiplier chip test device, characterized in that The synchronous binary ratio multiplier chip test device includes: a memory, a processor, and a synchronous binary ratio multiplier chip test program stored on the memory and executable on the processor, and the synchronous binary ratio multiplier chip test program is configured to implement the steps of the synchronous binary ratio multiplier chip test method according to any one of claims 1 to 7.

10. A storage medium, characterized in that, A synchronous binary ratio multiplier chip test program is stored on the storage medium, and when the synchronous binary ratio multiplier chip test program is executed by a processor, the steps of the synchronous binary ratio multiplier chip test method according to any one of claims 1 to 7 are implemented.

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