Bias circuit, semiconductor circuit, and electronic device

Abstract

The invention relates to a bias circuit, a semiconductor circuit and an electronic device. The biasing circuit comprises a first current mirror module, a second current mirror module and a virtual resistor module. A first input end and a second input end of the first current mirror module are connected with a power supply voltage end, a first branch output end of the first current mirror module is respectively connected with a first bias voltage end and a first input end of the second current mirror module, and a second branch output end of the first current mirror module is respectively connected with a second bias voltage end and a second input end of the second current mirror module. The first branch output end of the second current mirror module is connected with the common end, and the second branch output end is connected with the first end of the virtual resistor module; the signal receiving end of the virtual resistor module is connected with the adjusting signal end, the second end is connected with the common end, and the virtual resistor module is configured to change the resistance value between the first end and the second end according to the switching frequency of the signal received by the signal receiving end, so that the resistance value is negatively correlated with the switching frequency. The bias circuit can help to improve the accuracy and stability of bias provided by the bias circuit.

Description

Technical Field

[0001] This application relates to the field of electronic and electrical technologies, and particularly to a bias circuit, a semiconductor circuit, and an electronic device. Background Art

[0002] In the design of analog integrated circuits, a bias circuit is a DC circuit whose main function is to set the static electrical parameters of semiconductor devices to ensure a stable operating state of the semiconductor devices. Reasonably setting the circuit bias point can generate the precise current or voltage required by the circuit, reduce distortion, lower circuit power consumption, increase the switching speed, ensure the normal operation of the operational amplifier, and thus improve the overall circuit performance of the circuit. A complete bias circuit should have the characteristics of stability and precision. A precise reference bias circuit is the guarantee for the normal and efficient operation of the entire circuit.

[0003] In order to introduce non-linear factors into the bias circuit to provide the circuit bias point, a fixed resistor or a constant-value resistor circuit is usually set in the bias circuit to ensure the accuracy and stability of the circuit bias point based on the fixity of the resistor. However, process deviations existing in the current manufacturing process will cause large deviations in the resistance values of resistors or resistor circuits, and the process deviation of a single resistor can even reach 30%, which will seriously affect the accuracy and stability of the bias provided by the bias circuit. Summary of the Invention

[0004] This application provides a bias circuit, a semiconductor circuit, and an electronic device, which can help improve the accuracy and stability of the bias provided by the bias circuit.

[0005] This application provides a bias circuit. The bias circuit has a first bias voltage terminal, a second bias voltage terminal, an adjustment signal terminal, a power supply voltage terminal, and a common terminal. The bias circuit includes a first current mirror module, a second current mirror module, and a virtual resistor module; wherein,

[0006] The first input terminal and the second input terminal of the first current mirror module are both connected to the power supply voltage terminal. The first DC output terminal of the first current mirror module is respectively connected to the first bias voltage terminal and the first input terminal of the second current mirror module. The second DC output terminal of the first current mirror module is respectively connected to the second bias voltage terminal and the second input terminal of the second current mirror module. The first DC output terminal of the second current mirror module is connected to the common terminal. The second DC output terminal of the second current mirror module is connected to the first end of the virtual resistor module;

[0007] The signal receiving end of the virtual resistor module is connected to the adjustment signal end, the second end of the virtual resistor module is connected to the common end, and the virtual resistor module is configured to change the resistance value between the first end and the second end of the virtual resistor module according to the switching frequency of the signal received by the signal receiving end, so that the resistance value is negatively correlated with the switching frequency.

[0008] In some possible implementation manners, the adjustment signal end includes a first clock signal end and a second clock signal end. The on-period of the first clock signal provided by the first clock signal end is staggered from the on-period of the second clock signal provided by the second clock signal end, and the frequencies of the first clock signal and the second clock signal are both equal to the switching frequency; the signal receiving end includes a first receiving end connected to the first clock signal end and a second receiving end connected to the second clock signal end, and the virtual resistor module includes a first switching unit, a second switching unit, and a capacitor unit; wherein,

[0009] The first switching unit is respectively connected to the first end, the first clock signal end, and a first node, and the first switching unit is configured to switch the on-off switching state between the first end and the first node according to the first clock signal;

[0010] The second switching unit is respectively connected to the first node, the second clock signal end, and the second end, and the second switching unit is configured to switch the on-off switching state between the first node and the second end according to the second clock signal;

[0011] Two ends of the capacitor unit are respectively connected to the first node and the common end.

[0012] In some possible implementation manners, the first clock signal end includes a first sub-signal end that provides a positive-phase first clock signal and a second sub-signal end that provides an inverted-phase first clock signal, the second clock signal end includes a third sub-signal end that provides a positive-phase second clock signal and a fourth sub-signal end that provides an inverted-phase second clock signal, the first receiving end includes a first sub-receiving end connected to the first sub-signal end and a second sub-receiving end connected to the second sub-signal end, the second receiving end includes a third sub-receiving end connected to the third sub-signal end and a fourth sub-receiving end connected to the fourth sub-signal end, the first switching unit includes a first N-type transistor and a first P-type transistor, and the second switching unit includes a second N-type transistor and a second P-type transistor; wherein,

[0013] The gate of the first N-type transistor is connected to the first sub-receiving end, the first pole of the first N-type transistor is connected to the first end, and the second pole of the first N-type transistor is connected to the first node;

[0014] The gate of the first P-type transistor is connected to the second sub-receiving end, the first pole of the first P-type transistor is connected to the first end, and the second pole of the first P-type transistor is connected to the first node;

[0015] The gate of the second N-type transistor is connected to the third sub-receiving end, the first pole of the second N-type transistor is connected to the first node, and the second pole of the second N-type transistor is connected to the second end;

[0016] The gate of the second P-type transistor is connected to the fourth sub-receiving end, the first pole of the second P-type transistor is connected to the first node, and the second pole of the second P-type transistor is connected to the second end.

[0017] In some possible implementation manners, the first current mirror module includes a third P-type transistor and a fourth P-type transistor, and the third P-type transistor and the fourth P-type transistor have the same channel width-to-length ratio; wherein,

[0018] The gate of the third P-type transistor is connected to the second bias voltage terminal, the first pole of the third P-type transistor is connected to the first input terminal of the first current mirror module, and the second pole of the third P-type transistor is connected to the first DC output terminal of the first current mirror module;

[0019] The gate of the fourth P-type transistor is connected to the second bias voltage terminal, the first pole of the fourth P-type transistor is connected to the second input terminal of the first current mirror module, and the second pole of the fourth P-type transistor is connected to the second DC output terminal of the first current mirror module.

[0020] In some possible implementation manners, the second current mirror module includes a third N-type transistor and a fourth N-type transistor, and the channel width-to-length ratio of the fourth N-type transistor is K times that of the third N-type transistor, where K is an integer greater than 1; wherein,

[0021] The gate of the third N-type transistor is connected to the first bias voltage terminal, the first pole of the third N-type transistor is connected to the first input terminal of the second current mirror module, and the second pole of the third N-type transistor is connected to the first DC output terminal of the second current mirror module;

[0022] The gate of the fourth N-type transistor is connected to the first bias voltage terminal, the first pole of the fourth N-type transistor is connected to the second input terminal of the second current mirror module, and the second pole of the fourth N-type transistor is connected to the second DC output terminal of the second current mirror module.

[0023] In some possible implementation manners, the transconductance value gm of the bias circuit is configured and implemented by the following formula: gm = C0 × f, where C0 is the capacitance value of the capacitor unit and f is the switching frequency.

[0024] In some possible implementation manners, the output current value I of the bias circuit REF is configured and implemented by the following formula:

[0025]

[0026] where K is the multiple of the channel width-to-length ratio of the fourth N-type transistor relative to the channel width-to-length ratio of the third N-type transistor, b is equal to the channel width-to-length ratio of the third N-type transistor multiplied by the carrier mobility of the third N-type transistor and then multiplied by the gate oxide capacitance of the third N-type transistor, C0 is the capacitance value of the capacitor unit, and f is the switching frequency.

[0027] This application also provides a semiconductor circuit, and the semiconductor circuit includes the bias circuit of any one of the above.

[0028] In some possible implementation manners, the semiconductor circuit includes a semiconductor device, and a working voltage terminal of the semiconductor device is connected to the first bias voltage terminal or the second bias voltage terminal of a bias circuit.

[0029] This application also provides an electronic device, and the electronic device includes the semiconductor circuit of any one of the above.

[0030] In the bias circuit of the embodiments of this application, a virtual resistor module whose resistance value is negatively correlated with the switching frequency of the input signal is adopted to replace the resistor or resistor circuit in the related art to provide the non-linear characteristics in the bias circuit. Therefore, the characteristics of high precision, easy adjustment, and easy compensation of the signal switching frequency can be utilized to help improve the accuracy and stability of the bias provided by the bias circuit, and contribute to improving the working performance of the related semiconductor circuit and electronic device.

[0031] It should be understood that the above general description and the following detailed description are only exemplary and explanatory, and cannot limit this application. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] The accompanying drawings here are incorporated into the specification and constitute a part of this specification, showing the embodiments consistent with this application, and are used together with the specification to explain the principles of this application.

[0033] Figure 1 is a structural block diagram of a bias circuit provided by an embodiment of this application;

[0034] Figure 2 is a schematic circuit diagram of a bias circuit provided by an embodiment of this application;

[0035] Figure 3 It is a waveform schematic diagram of an adjustment signal provided to a bias circuit according to an embodiment of the present application;

[0036] Figure 4 It is a structural block diagram of a semiconductor circuit according to an embodiment of the present application;

[0037] Figure 5 It is a structural block diagram of an electronic device according to an embodiment of the present application. Detailed implementation manners

[0038] To make the objectives, technical solutions and advantages of the present disclosure clearer, the following will further describe the embodiments of the present disclosure in detail with reference to the accompanying drawings.

[0039] The terms used in the embodiments part of the present disclosure are only for explaining the embodiments of the present disclosure, rather than aiming to limit the present disclosure. Unless otherwise defined, the technical terms or scientific terms used herein should be the ordinary meanings understood by those of ordinary skill in the field to which the present disclosure belongs. The "first", "second", "third" and similar terms used in the specification and claims of the present patent application do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, the terms such as "a" or "one" do not indicate a quantity limitation, but indicate that there is at least one. The terms such as "include" or "comprise" mean that the elements or objects appearing before "include" or "comprise" cover the elements or objects listed after "include" or "comprise" and their equivalents, and do not exclude other elements or objects. The terms such as "connect" or "couple" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

[0040] Figure 1 It is a structural block diagram of a bias circuit according to an embodiment of the present application. Refer to Figure 1, the bias circuit has a first bias voltage terminal VBN, a second bias voltage terminal VBP, an adjustment signal terminal ST, a power supply voltage terminal VDD, and a common terminal GND, and includes a first current mirror module 11, a second current mirror module 12, and a virtual resistor module 13, where: The first input terminal A1 and the second input terminal A2 of the first current mirror module 11 are both connected to the power supply voltage terminal VDD. The first branch output terminal B1 of the first current mirror module 11 is respectively connected to the first bias voltage terminal VBN and the first input terminal X1 of the second current mirror module 12. The second branch output terminal B2 of the first current mirror module 11 is respectively connected to the second bias voltage terminal VBP and the second input terminal X2 of the second current mirror module 12. The first branch output terminal Y1 of the second current mirror module 12 is connected to the common terminal GND. The second branch output terminal Y2 of the second current mirror module 12 is connected to the first terminal Z1 of the virtual resistor module 13; The signal receiving terminal Z3 of the virtual resistor module 13 is connected to the adjustment signal terminal ST. The second terminal Z2 of the virtual resistor module 13 is connected to the common terminal GND. The virtual resistor module 13 is configured to change the resistance value between the first terminal Z1 and the second terminal Z2 of the virtual resistor module 13 according to the switching frequency of the signal received by the signal receiving terminal Z3, so that the resistance value is negatively correlated with the above-mentioned switching frequency.

[0041] It should be noted that the current mirror module described in this article, such as the above-mentioned first current mirror module 11 and the second current mirror module 12, can adopt any circuit structure that can provide mirror currents with equal or proportional current values at the first branch output terminal and the second branch output terminal, and can have any circuit structure of a current mirror in the related art. It should also be noted that the virtual resistor module described in this article can adopt any circuit structure that can change the resistance value between the first terminal and the second terminal of the virtual resistor module according to the switching frequency of the signal received by the signal receiving terminal, so that the resistance value is negatively correlated with the above-mentioned switching frequency, such as a circuit structure that uses a capacitor or an inductor to change the equivalent resistance value through the switching frequency. Specific exemplary implementation manners will be given later. It should also be noted that the switching frequency of the signal in this article refers to the number of signal switching cycles (for example, the process of the signal changing from the "on state" to the "off state" and then back to the "on state") experienced per unit time. For example, if a signal experiences 1000 switching cycles in 1 second, the switching frequency of the signal is 1 kHz; if a signal experiences 100 switching cycles in 1 second, the switching frequency of the signal is 100 Hz.

[0042] It should be understood that according to the working principle of the bias circuit, the first current mirror module 11, the second current mirror module 12, and the virtual resistor module 13 can achieve the function of providing constant currents with equal and controllable current values in two current branches (i.e., the function of an adjustable current source). In this way, the bias circuit can output a constant bias current with the required current value through the first branch output terminal Y1 of the second current mirror module 12, the second branch output terminal Y2 of the second current mirror module 12, or the second terminal Z2 of the virtual resistor module 13. It can also provide a constant bias voltage through the first bias voltage terminal VBN and the second bias voltage terminal VBP, so as to realize the function of the bias circuit providing bias to other devices or circuit structures.

[0043] It can be seen that based on the structural characteristics of the above bias circuit, the virtual resistor module whose resistance value is negatively correlated with the input signal switching frequency can be used to replace the resistor or resistor circuit in the related art to provide the non-linear characteristics in the bias circuit. Thus, the characteristics of high precision, easy adjustment, and easy compensation of the signal switching frequency can be utilized to help improve the accuracy and stability of the bias provided by the bias circuit, which is helpful for improving the working performance of related semiconductor circuits and electronic devices.

[0044] Figure 2 It is a schematic circuit diagram of a bias circuit provided by an embodiment of the present application. Refer to Figure 2 , in this bias circuit, the virtual resistor module 13 includes a first N-type transistor N1, a first P-type transistor P1, a second N-type transistor N2, a second P-type transistor P2, and a first capacitor C1. The first current mirror module 11 includes a third P-type transistor P3 and a fourth P-type transistor P4. The second current mirror module 12 includes a third N-type transistor N3 and a fourth N-type transistor N4. Figure 2 In the shown bias circuit, the adjustment signal terminal ST includes a first sub-signal terminal providing a positive-phase first clock signal, a second sub-signal terminal providing an inverted-phase first clock signal, a third sub-signal terminal providing a positive-phase second clock signal, and a fourth sub-signal terminal providing an inverted-phase second clock signal. The signal receiving terminal Z3 of the virtual resistor module 13 includes a first sub-receiving terminal S1 connected to the first sub-signal terminal, a second sub-receiving terminal S2 connected to the second sub-signal terminal, a third sub-receiving terminal S3 connected to the third sub-signal terminal, and a fourth sub-receiving terminal S4 connected to the fourth sub-signal terminal.

[0045] Figure 2In the shown virtual resistor module 13, the gate of the first N-type transistor N1 is connected to the first sub-receiving end S1, the first pole of the first N-type transistor N1 is connected to the first end Z1 of the virtual resistor module 13, and the second pole of the first N-type transistor N1 is connected to the first node Q1. The gate of the first P-type transistor P1 is connected to the second sub-receiving end S2, the first pole of the first P-type transistor P1 is connected to the first end Z1 of the virtual resistor module 13, and the second pole of the first P-type transistor P1 is connected to the first node Q1. The gate of the second N-type transistor N2 is connected to the third sub-receiving end S3, the first pole of the second N-type transistor N2 is connected to the first node Q1, and the second pole of the second N-type transistor N2 is connected to the second end Z2 of the virtual resistor module 13. The gate of the second P-type transistor P2 is connected to the fourth sub-receiving end S4, the first pole of the second P-type transistor P2 is connected to the first node Q1, and the second pole of the second P-type transistor P2 is connected to the second end Z2 of the virtual resistor module 13. Both ends of the first capacitor C1 are respectively connected to the first node Q1 and the common terminal GND.

[0046] It should be noted that the above first pole and second pole refer to the two electrodes of the transistor other than the gate. In one example, the above first pole is the source electrode and the above second pole is the drain electrode; in another example, the above first pole is the drain electrode and the above second pole is the source electrode; in another example, the source part and the drain part of the transistor are symmetrical to each other, and in this case, there is no special distinction between which one of the first pole and the second pole is the source / drain electrode.

[0047] Figure 3 It is a waveform schematic diagram of an adjustment signal provided to a bias circuit according to an embodiment of the present application. Refer to Figure 3 , in one example, the adjustment signal provided to the adjustment signal terminal ST of the bias circuit includes a first clock signal and a second clock signal. The first clock signal includes a positive-phase first clock signal CK1A and an inverted-phase first clock signal CK1B, and the second clock signal includes a positive-phase second clock signal CK2A and an inverted-phase second clock signal CK2B. The opening period of the first clock signal (such as the high-level period of the positive-phase first clock signal CK1A) and the opening period of the second clock signal (such as the high-level period of the positive-phase second clock signal CK2A) are staggered from each other, and the frequencies of both the first clock signal and the second clock signal are equal to the switching frequency of the signal provided to the signal receiving end of the virtual resistor module 13.

[0048] Combined with Figure 2 and Figure 3, within each clock cycle of the first clock signal and the second clock signal, the virtual resistor module 13 undergoes a capacitor charging process and a capacitor discharging process once. During the on period of the first clock signal, the first N-type transistor N1 and the first P-type transistor P1 are turned on, and the second N-type transistor N2 and the second P-type transistor P2 are turned off. As a result, the first capacitor C1 is charged to a charge amount reaching the first charge amount Q1 = C0 * VZ, where C0 is the capacitance value of the first capacitor C1, and VZ1 is the voltage value of the first terminal Z1 of the virtual resistor module 13. During the on period of the second clock signal, the second N-type transistor N2 and the second P-type transistor P2 are turned on, and the first N-type transistor N1 and the first P-type transistor P1 are turned off. As a result, the second capacitor C1 is discharged to the second charge amount Q2 = C0 * VZ2, where VZ2 is the voltage value of the second terminal Z2 of the virtual resistor module 13. Thus, within the clock cycle, it is equivalent to having a current flowing from the first terminal Z1 of the virtual resistor module 13 to the second terminal Z2. The current value I0 of this current is I0 = (Q1 - Q2) / t0 = (Q1 - Q2) * f = C0 * (VZ1 - VZ2) * f, where t0 is the duration of the clock cycle, and f is the frequency of the clock signal (which is the reciprocal of t0). According to Ohm's law, the equivalent resistance value Req of the virtual resistor module 13 is Req = (VZ1 - VZ2) / I0 = 1 / (C0 * f). That is, the equivalent resistance value of the virtual resistor module 13 within this clock cycle is equal to the reciprocal of the product of the capacitance value C0 of the first capacitor C1 and the frequency f of the clock signal. That is to say, as the frequency f of the clock signal (i.e., the above-mentioned switching frequency) changes, the resistance value between the first terminal Z1 and the second terminal Z2 of the virtual resistor module 13 will also change accordingly, and this resistance value is negatively correlated with the switching frequency.

[0049] Figure 2 In the first current mirror module 11 shown, the gate of the third P-type transistor P3 is connected to the second bias voltage terminal VBP. The first pole of the third P-type transistor P3 is connected to the first input terminal A1 of the first current mirror module 11. The second pole of the third P-type transistor P3 is connected to the first DC output terminal B1 of the first current mirror module 11. The gate of the fourth P-type transistor P4 is connected to the second bias voltage terminal VBP. The first pole of the fourth P-type transistor P4 is connected to the second input terminal A2 of the first current mirror module 11. The second pole of the fourth P-type transistor P4 is connected to the second DC output terminal B2 of the first current mirror module 11. Here, the third P-type transistor P3 and the fourth P-type transistor P4 have the same channel width-to-length ratio.

[0050] Figure 2In the second current mirror module 12 shown, the gate of the third N-type transistor N3 is connected to the first bias voltage terminal VBN, the first pole of the third N-type transistor N3 is connected to the first input terminal X1 of the second current mirror module 12, and the second pole of the third N-type transistor N3 is connected to the first DC output terminal Y1 of the second current mirror module 12. The gate of the fourth N-type transistor N4 is connected to the first bias voltage terminal VBN, the first pole of the fourth N-type transistor N4 is connected to the second input terminal X2 of the second current mirror module 12, and the second pole of the fourth N-type transistor N4 is connected to the second DC output terminal Y2 of the second current mirror module 12. Here, the channel width-to-length ratio of the fourth N-type transistor N4 is K times that of the third N-type transistor N3, and K is an integer greater than 1.

[0051] Based on the above circuit structure, ignoring the slight differences in the parameters not mentioned for the above transistors, combining the working principle of the bias circuit, the characteristics of the transistors, and the expression of the equivalent resistance value of the above virtual resistance module 13, the output current value I REF of this bias circuit can be deduced as:

[0052]

[0053] In the above formula, K is the multiple of the channel width-to-length ratio of the fourth N-type transistor relative to that of the third N-type transistor, b is equal to the channel width-to-length ratio of the third N-type transistor multiplied by the carrier mobility of the third N-type transistor and then multiplied by the gate oxide capacitance of the third N-type transistor, C0 is the capacitance value of the capacitance unit (the first capacitor C1), and f is the switching frequency. In addition, the expression of the transconductance value gm of this bias circuit is gm = C0 × f.

[0054] It can be seen from this that the current value of the output current of this bias circuit (for example, the current flowing from the first DC output terminal Y1 of the second current mirror module 12, the second DC output terminal Y2 of the second current mirror module 12, or the second terminal Z2 of the virtual resistance module 13 to the common terminal GND) has nothing to do with the power supply voltage provided by the power supply voltage terminal VDD, and the transconductance value of the bias circuit also has nothing to do with the power supply voltage provided by the power supply voltage terminal VDD. Therefore, the bias provided by this bias circuit will not change with the fluctuation of the power supply voltage provided by the power supply voltage terminal VDD; moreover, since the accuracy of the capacitance value of the first capacitor C1 can be easily guaranteed in the manufacturing process, and when this bias circuit is working, it is very easy to accurately set or adjust the switching frequency of the signal provided to the bias circuit through the adjustment signal terminal ST from the outside. Therefore, it is easy to accurately set the bias provided by the bias circuit to the required level through manual debugging or automatic compensation. It can be seen that this bias circuit can provide a bias with high accuracy and high stability, which helps to improve the working performance of related semiconductor circuits and electronic devices.

[0055] In the related art, for the part corresponding to the above virtual resistance module 13, in order to achieve precise control and compensation of the resistance value, generally, the switch resistance method of "using multiple switches to control whether each small resistor is connected" is adopted to adjust or compensate the resistance value of the fixed resistor within a certain range. However, such a method has many drawbacks. In contrast, for example Figure 2 The bias circuit shown has the following advantages: The above switch resistance method requires a large number of switches and small resistors to cooperate with an equally large number of switch control signals to achieve a large enough adjustment range and accuracy of the resistance value. However, the virtual resistance module of the present application can utilize the characteristics of a large adjustable range and high adjustment accuracy of the signal switching frequency with only one capacitor and several transistors to achieve an effect close to "infinitely adjustable resistance value in a large range". It not only has high adjustment accuracy, a large adjustable range, and a simpler adjustment and compensation method, but also can greatly reduce the required circuit layout space, and can greatly help improve the working performance and reliability of the relevant circuit structure and electronic device to a great extent.

[0056] It should be noted that Figure 2 The circuit structure shown is Figure 1 An exemplary implementation of the bias circuit shown, and it can also be implemented in other ways with reference to the above text Figure 1 The bias circuit shown. In one example, the first capacitor C1 can adopt a structure formed by connecting multiple capacitors in parallel, and can cooperate with a switch to form a capacitor structure with an adjustable capacitance value. In one example, the above first P-type transistor, second P-type transistor, second sub-receiving end S2, and fourth sub-receiving end S4 can be Figure 2 Omitted from the circuit structure shown, so that the circuit structure and its control method of the bias circuit can be simplified.

[0057] In a possible implementation manner, the above signal receiving end includes a first receiving end connected to the first clock signal end and a second receiving end connected to the second clock signal end. The virtual resistance module includes a first switch unit, a second switch unit, and a capacitor unit; wherein, the first switch unit is respectively connected to the first end, the first clock signal end, and the first node, and the first switch unit is configured to switch the on-off switch state between the first end and the first node according to the first clock signal; the second switch unit is respectively connected to the first node, the second clock signal end, and the second end, and the second switch unit is configured to switch the on-off switch state between the first node and the second end according to the second clock signal; both ends of the capacitor unit are respectively connected to the first node and the common end. It should be understood that the implementation manners of the first switch unit, the second switch unit, and the capacitor unit here can all be implemented with reference to Figure 2 The circuit structure shown, and will not be elaborated here one by one.

[0058] It should be noted that the bias circuit can be, for example, a separate component installed in an electronic device or on a circuit board, or can form an integrated circuit board (such as a PCB board) together with other circuits, or can also be a part of a circuit product with certain functions (in this case, the bias circuit can share at least some circuit components with other circuit parts, and there may or may not be a clear area division between it and other circuit parts). The embodiments of the present application do not limit this.

[0059] It should also be noted that any of the above-mentioned transistors can be any type of transistor, such as a CMOS (Complementary Metal Oxide Semiconductor) transistor, a MOSFET (Metal Oxide Semiconductor Field-Effect Transistor), an IGBT (Insulated-Gate Bipolar Transistor), and so on. In order to make the performance of the bias circuit more stable, paired transistors such as the third P-type transistor and the fourth P-type transistor can have equivalent characteristics in other aspects in addition to having equal channel width-to-length ratios; for example, they can be made as mirror-image transistors, or formed by sampling the same process, size, and manufacturing specifications on the same substrate, or by selecting devices of the same model, batch, and device parameters, and so on.

[0060] Figure 4 is a structural block diagram of a semiconductor circuit provided by an embodiment of the present application. The semiconductor circuit can be, for example, any circuit structure including semiconductor devices and their bias circuits, and can have a product form such as an internal circuit module or a circuit board in an electronic product. Refer to Figure 4 , the semiconductor circuit includes a bias circuit 10 and semiconductor devices 20, where the bias circuit 10 can be implemented using any of the above-mentioned bias circuits, and the first bias voltage terminal VBN or the second bias voltage terminal VBP of the bias circuit 10 is connected to the semiconductor devices 20 to provide a suitable bias voltage to the semiconductor devices 20. It should be understood that the number of the bias circuit 10 and the semiconductor devices 20 in the semiconductor circuit and the connection manner between the two can be set according to application requirements, and there is no need to be limited to a single case.

[0061] Figure 5 is a structural block diagram of an electronic device provided by an embodiment of the present application. Refer to Figure 5, the electronic device includes a semiconductor circuit 100 and a controller 200. The semiconductor circuit 100 is any one of the above semiconductor circuits, and the semiconductor circuit 100 is connected to the controller 200. The controller 200 may include, for example, a processor and a memory, where the processor can execute instructions stored in the memory to implement the function of providing a signal to the adjustment signal terminal ST of any one of the above bias circuits.

[0062] It should be noted that the electronic device may be, for example, any signal system device, such as a signal filter, a signal interface, a signal converter, a signal generator, a data transceiver device, etc., or may be any application device including a signal system device, such as an overall machine controller, a battery management system, an electric vehicle, etc. In different implementation manners, the above processor may be implemented in different forms, such as a controller or a single-chip microcomputer that receives digital signals, a main control module of a vehicle controller, etc.

[0063] In one example, the processor may include one or more processing cores, such as a 4-core processor, an 8-core processor, etc. The processor may be implemented in at least one hardware form of DSP (Digital Signal Processing), FPGA (Field-Programmable Gate Array), or PLA (Programmable Logic Array). The processor may also include a main processor and a coprocessor. The main processor is a processor used to process data in the wake state, also known as the CPU (Central Processing Unit); the coprocessor is a low-power processor used to process data in the standby state. In some embodiments, the processor may be integrated with a GPU (Graphics Processing Unit), and the GPU is responsible for rendering and drawing the content required to be displayed on the vehicle display screen. In some embodiments, the processor may further include an AI (Artificial Intelligence) processor, and the AI processor is used to process computing operations related to machine learning. The memory may include one or more computer-readable storage media, and the computer-readable storage media may be non-transitory. The memory may also include high-speed random access memory and non-volatile memory, such as one or more disk storage devices and flash storage devices.

[0064] As another example, in any implementation manner of the embodiments of the present application, the above-mentioned processor may include one or more application-specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field-programmable gate arrays (FPGAs), controllers, microcontrollers, microprocessors, or other electronic components.

[0065] The foregoing are only alternative embodiments of the present application and are not intended to limit the present application. Any modifications, equivalent replacements, improvements, etc. made within the principles of the present application shall be included within the protection scope of the present application.

Claims

1. A bias circuit, characterized in that, The bias circuit has a first bias voltage terminal, a second bias voltage terminal, an adjustment signal terminal, a power supply voltage terminal, and a common terminal. The bias circuit includes a first current mirror module, a second current mirror module, and a virtual resistor module. Among them, The first input terminal and the second input terminal of the first current mirror module are both connected to the power supply voltage terminal. The first DC output terminal of the first current mirror module is respectively connected to the first bias voltage terminal and the first input terminal of the second current mirror module. The second DC output terminal of the first current mirror module is respectively connected to the second bias voltage terminal and the second input terminal of the second current mirror module. The first DC output terminal of the second current mirror module is connected to the common terminal. The second DC output terminal of the second current mirror module is connected to the first end of the virtual resistor module. The signal receiving terminal of the virtual resistor module is connected to the adjustment signal terminal. The second end of the virtual resistor module is connected to the common terminal. The virtual resistor module is configured to change the resistance value between the first end and the second end of the virtual resistor module according to the switching frequency of the signal received by the signal receiving terminal, so that the resistance value is negatively correlated with the switching frequency.

2. The bias circuit according to claim 1, wherein, The adjustment signal terminal includes a first clock signal terminal and a second clock signal terminal. The on period of the first clock signal provided by the first clock signal terminal is staggered from the on period of the second clock signal provided by the second clock signal terminal. And the frequencies of the first clock signal and the second clock signal are both equal to the switching frequency. The signal receiving terminal includes a first receiving terminal connected to the first clock signal terminal and a second receiving terminal connected to the second clock signal terminal. The virtual resistor module includes a first switching unit, a second switching unit, and a capacitor unit. Among them, The first switching unit is respectively connected to the first end, the first clock signal terminal, and a first node. The first switching unit is configured to switch the on-off switching state between the first end and the first node according to the first clock signal. The second switching unit is respectively connected to the first node, the second clock signal terminal, and the second end. The second switching unit is configured to switch the on-off switching state between the first node and the second end according to the second clock signal. Both ends of the capacitor unit are respectively connected to the first node and the common terminal.

3. The offset circuit according to claim 2, characterized in that, The first clock signal terminal includes a first sub-signal terminal providing a positive-phase first clock signal and a second sub-signal terminal providing an inverted-phase first clock signal. The second clock signal terminal includes a third sub-signal terminal providing a positive-phase second clock signal and a fourth sub-signal terminal providing an inverted-phase second clock signal. The first receiving terminal includes a first sub-receiving terminal connected to the first sub-signal terminal and a second sub-receiving terminal connected to the second sub-signal terminal. The second receiving terminal includes a third sub-receiving terminal connected to the third sub-signal terminal and a fourth sub-receiving terminal connected to the fourth sub-signal terminal. The first switching unit includes a first N-type transistor and a first P-type transistor. The second switching unit includes a second N-type transistor and a second P-type transistor. Among them, The gate of the first N-type transistor is connected to the first sub-receiving terminal, the first pole of the first N-type transistor is connected to the first terminal, and the second pole of the first N-type transistor is connected to the first node; The gate of the first P-type transistor is connected to the second sub-receiving terminal, the first pole of the first P-type transistor is connected to the first terminal, and the second pole of the first P-type transistor is connected to the first node; The gate of the second N-type transistor is connected to the third sub-receiving terminal, the first pole of the second N-type transistor is connected to the first node, and the second pole of the second N-type transistor is connected to the second terminal; The gate of the second P-type transistor is connected to the fourth sub-receiving terminal, the first pole of the second P-type transistor is connected to the first node, and the second pole of the second P-type transistor is connected to the second terminal.

4. The bias circuit according to claim 2 or 3, characterized in that, The first current mirror module includes a third P-type transistor and a fourth P-type transistor, and the third P-type transistor and the fourth P-type transistor have the same channel width-to-length ratio; wherein, The gate of the third P-type transistor is connected to the second bias voltage terminal, the first pole of the third P-type transistor is connected to the first input terminal of the first current mirror module, and the second pole of the third P-type transistor is connected to the first DC output terminal of the first current mirror module; The gate of the fourth P-type transistor is connected to the second bias voltage terminal, the first pole of the fourth P-type transistor is connected to the second input terminal of the first current mirror module, and the second pole of the fourth P-type transistor is connected to the second DC output terminal of the first current mirror module.

5. The offset circuit according to claim 4, characterized in that, The second current mirror module includes a third N-type transistor and a fourth N-type transistor, and the channel width-to-length ratio of the fourth N-type transistor is K times that of the third N-type transistor, where K is an integer greater than 1; wherein, The gate of the third N-type transistor is connected to the first bias voltage terminal, the first pole of the third N-type transistor is connected to the first input terminal of the second current mirror module, and the second pole of the third N-type transistor is connected to the first DC output terminal of the second current mirror module; The gate of the fourth N-type transistor is connected to the first bias voltage terminal, the first pole of the fourth N-type transistor is connected to the second input terminal of the second current mirror module, and the second pole of the fourth N-type transistor is connected to the second DC output terminal of the second current mirror module.

6. The offset circuit according to claim 5, characterized in that The transconductance value gm of the bias circuit is configured and implemented by the following formula: gm = C0 × f, where C0 is the capacitance value of the capacitor unit and f is the switching frequency.

7. The bias circuit according to claim 5, characterized in that, The output current value I of the bias circuit REF is configured and implemented by the following formula: Where K is the multiple of the channel width-to-length ratio of the fourth N-type transistor relative to that of the third N-type transistor, b is equal to the channel width-to-length ratio of the third N-type transistor multiplied by the carrier mobility of the third N-type transistor and then multiplied by the gate oxide capacitance of the third N-type transistor, C0 is the capacitance value of the capacitor unit, and f is the switching frequency.

8. A semiconductor circuit, characterized in that, The semiconductor circuit includes at least one bias circuit as described in any one of claims 1 to 7.

9. The semiconductor circuit according to claim 8, wherein, The semiconductor circuit includes semiconductor devices, and a working voltage terminal of the semiconductor devices is connected to the first bias voltage terminal or the second bias voltage terminal of a bias circuit.

10. An electronic device, characterized in that, The electronic device includes the semiconductor circuit as described in claim 8 or 9.

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