LDO (Low Dropout Regulator) frequency compensation circuit based on voltage-controlled current source

Abstract

The invention relates to the technical field of analog integrated circuits, and discloses an LDO (Low Dropout Regulator) frequency compensation circuit based on a voltage-controlled current source, which comprises an input differential amplification module, a power regulation module, a frequency compensation module and a feedback voltage division module, and is characterized in that the output end of the input differential amplification module is electrically connected with the input end of the frequency compensation module; the frequency compensation module comprises a voltage-controlled current source and a compensation capacitor C1, the compensation capacitor C1 is matched with the voltage-controlled current source to adjust the loop frequency response, through a multi-stage current mirror and a Miller compensation network, pole distribution is optimized in a targeted mode, the Miller effect of the compensation capacitor C1 is matched, the dominant pole frequency can be actively lowered, a dominant pole is made to be away from a high-frequency area, and the loop phase margin is guaranteed; the self-excited oscillation is fundamentally suppressed, and the output voltage is stable and free of fluctuation.

Description

Technical Field

[0001] The present invention relates to the technical field of analog integrated circuits, and particularly relates to an LDO frequency compensation circuit based on a voltage-controlled current source. Background Art

[0002] Traditional LDO circuits mainly consist of a differential input stage, a power adjustment module, and a feedback voltage-dividing network. The core follows the closed-loop control logic of voltage feedback - error amplification - power adjustment. The differential input stage is composed of a pair of differential pair transistors, and their gates are respectively connected to the reference voltage Vref and the feedback voltage Vfb. Using the differential amplification principle, the voltage difference between Vref and Vfb is converted into a current difference to initially extract the error signal. The power adjustment module takes a large-size power MOS transistor as the core, and its gate is controlled by the error signal output by the differential input stage. By adjusting the conduction degree of the power transistor, the fluctuation of the output voltage Vout is compensated to maintain a stable output. The feedback voltage-dividing network is composed of resistors R1 and R2 in series, and divides the voltage of Vout to obtain the feedback voltage Vfb, realizing the sampling and feedback of the output voltage, and making the LDO form a negative feedback closed-loop.

[0003] However, there are multiple stages of signal amplification and transmission links inside the LDO circuit, such as the differential input stage, the power transistor drive stage, etc. The parasitic capacitance of transistors and the load capacitance of each stage of the circuit will introduce multiple high-frequency poles. These poles cause the signal phase to lag as the frequency increases. When the frequency rises to a certain critical value, the phase superposition of multiple poles may reach 180°. If the loop gain is still greater than 0 at this time, the LDO circuit will enter the self-oscillation state, and the output voltage will show continuous and irregular fluctuations. Moreover, traditional LDO circuits rely on single-stage differential amplification to extract error signals. Affected by the process, temperature, and bias current of MOS transistors, in actual circuits, there are process deviations in the threshold voltage Vth and mobility μ of current mirror MOS transistors. The overall loop gain is limited, and tiny changes in the output voltage cannot be accurately amplified. The error signal has low recognition, and the adjustment of the power transistor lags, ultimately resulting in poor voltage regulation accuracy.

[0004] Therefore, it is necessary to provide an LDO frequency compensation circuit based on a voltage-controlled current source to solve the above problems. Summary of the Invention

[0005] The purpose of the present invention is to provide a technical solution to solve the problems in the prior art mentioned in the above background art.

[0006] To achieve the above purpose, the present invention adopts the following technical solutions: An LDO frequency compensation circuit based on a voltage-controlled current source includes an input differential amplification module, a power adjustment module, a frequency compensation module, and a feedback voltage-dividing module; The power adjustment module includes an MOS transistor MP. The current signal output by the input differential amplification module controls the gate voltage of the MOS transistor MP to adjust the conduction degree of the MOS transistor MP. The source of the MOS transistor MP is the output voltage Vout. The feedback voltage division module includes a resistor R1 and a resistor R2. The resistor R1 and the resistor R2 are connected in series. The resistor R1 is connected to the output voltage Vout, and the resistor R2 is grounded. The output end of the input differential amplification module is electrically connected to the input end of the frequency compensation module. The frequency compensation module includes a voltage-controlled current source and a compensation capacitor C1. The compensation capacitor C1 cooperates with the voltage-controlled current source to adjust the loop frequency response. The input differential amplification module includes a differential input stage, a first current mirror, a second current mirror, and a bias circuit. The differential input stage is used to compare the reference voltage Vref and the feedback voltage Vfb and convert them into a current difference. The first current mirror cooperates with the differential input stage to preliminarily amplify the signal and provide a suitable current signal for the subsequent stage. The second current mirror and the bias circuit provide a stable bias current for the differential input stage to ensure that the circuit operates at a suitable quiescent operating point.

[0007] Preferably, the differential input stage includes MOS transistors M1 and M2. The MOS transistors M1 and M2 are differential pair transistors. The gate of the MOS transistor M1 is connected to the reference voltage Vref, and the gate of the MOS transistor M2 is connected to the feedback voltage Vfb.

[0008] Preferably, the first current mirror includes MOS transistors M3, M4, M5, and M6. The MOS transistors M3 and M4 form a first group of current mirrors, and the MOS transistors M5 and M6 form a second group of current mirrors. The gates of the MOS transistor M3 and the MOS transistor M4 are commonly connected. The drain of the MOS transistor M3 is connected to its gate, and the drain of the MOS transistor M3 is connected to the source of the MOS transistor M1.

[0009] Preferably, the second current mirror includes MOS transistors M7 and M8. The source of the MOS transistor M7 and the MOS transistor M8 form a third group of current mirrors. The gates of the MOS transistor M7 and the MOS transistor M8 are commonly connected. The sources of the MOS transistor M7 and the MOS transistor M8 are connected to the power supply bus VDD. The drain of the MOS transistor M7 is connected to the drain of the MOS transistor M4, and the drains of the MOS transistor M8 and the MOS transistor M6 are commonly connected.

[0010] Preferably, the bias circuit includes MOS transistor M11 and MOS transistor M12. The source of MOS transistor M12 is connected to the power supply bus VDD. The drain of MOS transistor M12 is connected to the source of MOS transistor M11. The drain of MOS transistor M11 is commonly connected to the source of MOS transistor M1 and the source of MOS transistor M12. The drain of MOS transistor M8, the drain of MOS transistor M6 are connected to the gate of MOS transistor MP.

[0011] Preferably, the voltage-controlled current source includes MOS transistor M9 and MOS transistor M10. The gates of MOS transistor M9 and MOS transistor M10 are commonly connected. The drain of MOS transistor M9 is connected to the source of MOS transistor M14, and the source of transistor M14 is the output voltage Vout2. The gate of MOS transistor M14 is connected to the drain of MOS transistor M8 and the drain of MOS transistor M6. The source of MOS transistor M14 is connected to the power supply bus VDD. The drains of MOS transistor M10 and MOS transistor M13 are commonly connected and are the feedback voltage signal Vfb. The source of MOS transistor M13 is connected to the power supply bus VDD, and the gate of MOS transistor M13 is connected to the bias voltage Vb. One end of the compensation capacitor C1 is connected to the drain of MOS transistor M9, and the other end of the compensation capacitor C1 is connected to the gate of MOS transistor M9.

[0012] Preferably, the voltage-controlled current source includes MOS transistor M9 and MOS transistor M10. The gates of MOS transistor M9 and MOS transistor M10 are commonly connected. The drain of MOS transistor M9 is connected to the source of MOS transistor M14. One end of the compensation capacitor C1 is connected to the drain of MOS transistor M9, and the other end of the compensation capacitor C1 is connected to the gate of MOS transistor M9. The source of MOS transistor M14 is connected to the power supply bus VDD. The drains of MOS transistor M10 and MOS transistor M13 are commonly connected and are the feedback voltage signal Vfb. The source of MOS transistor M13 is connected to the power supply bus VDD, and the gate of MOS transistor M13 is connected to the bias voltage Vb. Wherein, the gate of MOS transistor M14 is connected to the output terminal of the operational amplifier OP. The inverting input terminal of the operational amplifier OP is connected to the output voltage Vout, and the non-inverting input terminal of the operational amplifier OP is connected to the output voltage Vout2.

[0013] Preferably, the voltage-controlled current source includes MOS transistor M9 and MOS transistor M10. The gates of MOS transistor M9 and MOS transistor M10 are commonly connected. The drain of MOS transistor M9 is connected to the drain of MOS transistor M14. The drain and gate of MOS transistor M9 are short-circuited. The source of transistor M14 is the output voltage Vout2. The gate of MOS transistor M14 is connected to the drain of MOS transistor M8 and the drain of MOS transistor M6. The source of MOS transistor M14 is connected to the power supply bus VDD. The drains of MOS transistor M10 and MOS transistor M13 are commonly connected and are the feedback voltage signal Vfb. The source of MOS transistor M13 is connected to the power supply bus VDD. The gate of MOS transistor M13 is connected to the bias voltage Vb. Wherein, one end of the compensation capacitor C1 is connected to the output voltage Vout2, and the other end of the compensation capacitor C1 is grounded.

[0014] Preferably, the voltage-controlled current source includes MOS transistor M21 and MOS transistor M22. The source of MOS transistor M21 is connected to the gate of MOS transistor M25. The drain of MOS transistor M25 is connected to the drain of MOS transistor M23. After the sources of MOS transistor M25 and MOS transistor M26 are commonly connected, they are connected to the drain of MOS transistor M33. The drain of MOS transistor M26 is connected to the gate of MOS transistor M22 and the drain of MOS transistor M24. The drain of MOS transistor M22 is connected to the drain of MOS transistor M30. The source of MOS transistor M30 is connected to the drain of MOS transistor M28. The gate of MOS transistor M30 is connected to the gate of MOS transistor M31. The gates of MOS transistor M28 and MOS transistor M29 are connected. The drain of MOS transistor M31 is connected to the drain of MOS transistor M35. The gate of MOS transistor M35 is connected to the gate of MOS transistor M34. The source of MOS transistor M35 is connected to the drain of MOS transistor M37. The source of MOS transistor M34 is connected to the drain of MOS transistor M36. The gate of MOS transistor M36 is connected to the gate of MOS transistor M37. Wherein, the drain of MOS transistor M34 is respectively connected to the gate of MOS transistor M26 and the source of MOS transistor M22, and a compensation capacitor C1 is connected to the source of MOS transistor M22. The other end of the compensation capacitor C1 is grounded.

[0015] Preferably, the drain of the MOS transistor M21 is connected to the power supply bus VDD, the sources of the MOS transistors M23, M24, M28, and M29 are all connected to the power supply bus VDD, the source of the MOS transistor M21 is further connected to the drain of the MOS transistor M32, and the sources of the MOS transistors M32, M33, M36, and M37 are grounded.

[0016] Technical effects and advantages of the present invention: A voltage-controlled current source-based LDO frequency compensation circuit proposed by the present invention has the following advantages compared with the prior art: 1. Through a multi-stage current mirror and a Miller compensation network, the present invention optimizes the pole distribution specifically. While the multi-stage current mirror converts the differential current into a single-ended signal, it blocks the reverse coupling of the subsequent-stage noise, reduces the additional poles introduced by parasitic capacitance, and with the high output impedance of the multi-stage current mirror, in cooperation with the Miller effect of the compensation capacitor C1, it can actively lower the main pole frequency, move the main pole away from the high-frequency region. The compensation capacitor C1 is connected across the high-impedance node, and uses the equivalent large capacitor generated by the Miller effect to compensate for the phase lag of the multi-stage poles. When the signal frequency increases and the phase superposition approaches 180°, the compensation capacitor C1 provides an additional AC feedback path to ensure the loop phase margin, fundamentally suppressing self-oscillation and making the output voltage stable without fluctuations. 2. Through multi-stage current mirror amplification + operational amplifier OP, the error signal of the differential input stage is amplified step by step, significantly increasing the loop gain. Compared with the traditional single-stage differential amplification, the gain can be increased by several times to 5 times. And through the operational amplifier OP, using its high gain and high input impedance characteristics, it can amplify the small voltage difference between Vout and Vout2 to generate a strong driving error signal, accurately regulating the power transistor. At the same time, the operational amplifier OP can suppress the process deviations of MOS transistors, such as the influence of Vth drift and temperature change on the gain, greatly improving the recognition of the error signal, making the power transistor adjustment more timely, and ultimately enabling the LDO circuit to adapt to the harsh scenarios of high frequency, high precision, and complex loads, such as radio frequency power supplies and high-end analog circuit power supplies, significantly improving the reliability and performance of the circuit. Description of the Drawings

[0017] Figure 1 It is the circuit diagram of Embodiment 1 and Embodiment 2 of the present invention; Figure 2 It is the circuit diagram of Embodiment 1 and Embodiment 3 of the present invention; Figure 3 It is the circuit diagram of Embodiment 1 and Embodiment 4 of the present invention; Figure 4 It is the circuit diagram of Embodiment 1 and Embodiment of the present invention; Detailed Embodiments

[0018] Reference will now be made to example embodiments to discuss the subject matter described herein. It should be understood that discussing these embodiments is only to enable those skilled in the art to better understand and thus implement the subject matter described herein. Without departing from the scope of protection of the content of this specification, changes can be made to the functions and arrangements of the elements discussed. Each example can omit, substitute, or add various processes or components as needed. Additionally, the features described in some examples can also be combined in other examples.

[0019] Please refer to Figures 1 to 4 , the embodiments provided by the present invention: Embodiment 1

[0020] As Figures 1 - 4 shown, an LDO frequency compensation circuit based on a voltage-controlled current source includes an input differential amplification module, a power regulation module, and a feedback voltage division module; The power regulation module includes an MOS transistor MP. The current signal output by the input differential amplification module controls the gate voltage of the MOS transistor MP, thereby adjusting the conduction degree of the MOS transistor MP. The source of the MOS transistor MP is the output voltage Vout. The input differential amplification module includes a differential input stage, a first current mirror, a second current mirror, and a bias circuit. The differential input stage is used to convert the voltage difference between the reference voltage Vref and the feedback voltage Vfb into a current difference after comparison. The first current mirror cooperates with the differential input stage to preliminarily amplify the signal and provide a suitable current signal for the subsequent stage. The second current mirror and the bias circuit provide a stable bias current for the differential input stage to ensure that the circuit operates at a suitable quiescent operating point; Specifically, the differential input stage includes an MOS transistor M1 and an MOS transistor M2. The MOS transistor M1 and the MOS transistor M2 are differential pair transistors, forming the differential input stage of an operational amplifier. The gate of the MOS transistor M1 is connected to the reference voltage Vref, and the gate of the MOS transistor M2 is connected to the feedback voltage Vfb. The voltage difference is converted into a current difference through differential amplification. When Vout changes, Vfb changes accordingly, generating a voltage difference ΔV = Vref - Vfb with Vref. The voltage difference causes a differential current ΔI to appear in the drain currents of the MOS transistor M1 and the MOS transistor M2; The first current mirror includes an MOS transistor M3, an MOS transistor M4, an MOS transistor M5, and an MOS transistor M6. The MOS transistor M3 and the MOS transistor M4 form the first group of current mirrors, and the MOS transistor M5 and the MOS transistor M6 form the second group of current mirrors. The gate of the MOS transistor M3 is commonly connected to the gate of the MOS transistor M4. The drain of the MOS transistor M3 is connected to its gate. The drain of the MOS transistor M3 is connected to the source of the MOS transistor M1. The MOS transistor M3, the MOS transistor M4, the MOS transistor M5, and the MOS transistor M6 convert the differential current difference ΔI into a single-ended voltage signal.

[0021] The second current mirror includes MOS transistors M7 and M8. The source of MOS transistor M7 and MOS transistor M8 form a third group of current mirrors. The gates of MOS transistor M7 and MOS transistor M8 are commonly connected. The sources of MOS transistor M7 and MOS transistor M8 are connected to the power supply bus VDD. The drain of MOS transistor M7 is connected to the drain of MOS transistor M4. The drains of MOS transistor M8 and MOS transistor M6 are commonly connected; The bias circuit includes MOS transistors M11 and M12. The source of MOS transistor M12 is connected to the power supply bus VDD. The drain of MOS transistor M12 is connected to the source of MOS transistor M11. The drain of MOS transistor M11 is commonly connected to the source of MOS transistor M1 and MOS transistor M12 respectively. The drains of MOS transistor M8 and MOS transistor M6 are connected to the gate of MOS transistor MP.

[0022] MOS transistors M7, M8, M11 and M12 form a multi-stage current mirror, jointly constituting a high-gain amplification stage to further amplify the error signal of the differential input stage, thereby improving the overall gain of the operational amplifier.

[0023] The feedback voltage division module includes resistors R1 and R2. Resistors R1 and R2 are connected in series. Resistor R1 is connected to the output voltage Vout. Resistor R2 is grounded. After the output voltage Vout is divided by resistors R1 and R2, the feedback voltage Vfb connected to the gate of MOS transistor M2 is obtained. Thus, by comparing the reference voltage Vref with the obtained feedback voltage Vfb, if the output voltage Vout changes, such as increasing due to load variation, then Vfb changes accordingly, thereby adjusting the conduction degree of MOS transistor MP.

[0024] The output end of the input differential amplification module is electrically connected to the input end of the frequency compensation module. The frequency compensation module includes a voltage-controlled current source and a compensation capacitor C1. The compensation capacitor C1 cooperates with the voltage-controlled current source to adjust the loop frequency response; Embodiment 2

[0025] As Figure 1 shown, on the basis of Embodiment 1, since the differential input stage and the intermediate amplification stage in the input differential amplification module will introduce multiple poles, it is easy to cause insufficient phase margin and self-excited oscillation; Therefore, the voltage-controlled current source includes MOS transistor M9 and MOS transistor M10. The gates of MOS transistor M9 and MOS transistor M10 are commonly connected. The drain of MOS transistor M9 is connected to the source of MOS transistor M14. The source of MOS transistor M14 is the output voltage Vout2. The gate of MOS transistor M14 is connected to the drain of MOS transistor M8 and the drain of MOS transistor M6. The source of MOS transistor M14 is connected to the power supply bus VDD. The drains of MOS transistor M10 and MOS transistor M13 are commonly connected and are the feedback voltage signal Vfb. The source of MOS transistor M13 is connected to the power supply bus VDD. The gate of MOS transistor M13 is connected to the bias voltage Vb. One end of the compensation capacitor C1 is connected to the drain of MOS transistor M9 and is also connected to the drain of MOS transistor M14. The other end of the compensation capacitor C1 is connected to the gate of MOS transistor M9.

[0026] The compensation capacitor C1 is connected across the drain of MOS transistor M14 and the gate of MOS transistor M9. Through the Miller effect, a very small capacitor can be equivalent to a large capacitor of C1×(1 + ) ( is the voltage gain of the MOS transistor M9 - MOS transistor M14 stage), which makes the main pole closer to the low frequency and improves the phase margin at the same time. When the signal frequency in the circuit increases and the phase changes, the compensation capacitor C1 provides an additional AC feedback path to ensure that the phase margin is sufficient.

[0027] MOS transistors M9 and M10 are in a cascode structure, which improves the output impedance, enhances the effect of Miller compensation, allows the compensation capacitor C1 to adjust the poles more efficiently, and isolates the influence of the subsequent load on the compensation network to ensure the stability of the pole position. The gate of M13 is connected to the bias voltage Vb, which can accurately set its own conduction state, provide a stable static current for the frequency compensation network, ensure the stability of the DC operating point of the frequency compensation module under different working conditions, and make the compensation function operate reliably. Embodiment 3

[0028] As Figure 2 shown, on the basis of Embodiment 1, in order to solve the problems of poor circuit accuracy, weak anti-interference ability, and slow dynamic response, the voltage-controlled current source includes MOS transistor M9 and MOS transistor M10. The gates of MOS transistor M9 and MOS transistor M10 are commonly connected. The drain of MOS transistor M9 is connected to the source of MOS transistor M14. One end of the compensation capacitor C1 is connected to the drain of MOS transistor M9, and the other end of the compensation capacitor C1 is connected to the gate of MOS transistor M9; The source of MOS transistor M14 is connected to the power supply bus VDD. The drains of MOS transistor M10 and MOS transistor M13 are commonly connected and are the feedback voltage signal Vfb. The source of MOS transistor M13 is connected to the power supply bus VDD. The gate of MOS transistor M13 is connected to the bias voltage Vb; Among them, the gate of MOS transistor M14 is connected to the output terminal of operational amplifier OP. The inverting input terminal of operational amplifier OP is connected to output voltage Vout, and the non-inverting input terminal of operational amplifier OP is connected to output voltage Vout2, and the voltage difference between the two is compared in real time: If Vout is not equal to Vout2, an error signal ΔV is generated at the output terminal of operational amplifier OP, driving the gate of MOS transistor M14, adjusting the conduction degree of M14, and then changing the current and voltage of the subsequent circuit to make Vout and Vout2 tend to be consistent. Due to the high gain of operational amplifier OP itself, a small voltage difference can be amplified, making the error correction more sensitive and improving the voltage regulation accuracy of the entire loop.

[0029] Among them, according to Embodiment 1, Vout is divided by resistors R1 and R2 to generate Vfb. At the same time, Vout and Vout2 are input to operational amplifier OP for comparison. If Vout drifts due to load changes, the output of operational amplifier OP drives MOS transistor M14 to adjust the current, which is transmitted to the Vfb node through current mirror MOS transistors M9, M10, and M13 of the frequency compensation module, and then corrects Vout back to the target value. At this time, compensation capacitor C1 is approximately open-circuited, which does not affect the DC bias, and the high gain of operational amplifier OP ensures the voltage regulation accuracy.

[0030] When the load changes rapidly or there is high-frequency noise, Vout shows high-frequency fluctuations. Operational amplifier OP responds quickly, outputs a high-frequency error signal to drive MOS transistor M14, and the drain current of MOS transistor M14 changes at high frequency, forming Miller compensation with compensation capacitor C1, depressing the main pole frequency and compensating for phase lag to avoid self-oscillation of the loop due to high-frequency phase superposition. Embodiment 4

[0031] As Figure 3 shown, on the basis of Embodiment 1, in order to be suitable for fast response and noise suppression, the voltage-controlled current source includes MOS transistors M9 and M10. The gates of MOS transistor M9 and MOS transistor M10 are commonly connected. The drain of MOS transistor M9 is connected to the drain of MOS transistor M14, and the source of MOS transistor M14 is output voltage Vout2; The gate of MOS transistor M14 is connected to the drain of MOS transistor M8 and the drain of MOS transistor M6. The source of MOS transistor M14 is connected to power supply bus VDD. The drains of MOS transistor M10 and MOS transistor M13 are commonly connected and are the feedback voltage signal Vfb. The source of MOS transistor M13 is connected to power supply bus VDD, and the gate of MOS transistor M13 is connected to bias voltage Vb; Among them, the difference from Embodiment 2 is that the drain and gate of MOS transistor M9 are short-circuited. One end of compensation capacitor C1 is connected to output voltage Vout2, and the other end of compensation capacitor C1 is grounded. The short-circuiting of the gate and drain of MOS transistor M9 makes Vgs9 equal to Vds9 when operating in the saturation region, which is equivalent to a MOS transistor connected as a diode. The short-circuiting of the gate and drain of MOS transistor M9 makes the Vgs of MOS transistor M9 change dynamically with Vout2. One end of compensation capacitor C1 is connected to Vout2, and the other end is grounded, becoming the load capacitor of the Vout2 node. For high-frequency signals, compensation capacitor C1 provides a low-impedance path, directly pulling down the high-frequency pole frequency of the Vout2 node and suppressing high-frequency noise and phase mutations. Embodiment 5

[0032] As Figure 4 shown, on the basis of Embodiment 1, in order to improve the anti-interference ability of the circuit and enhance the output stability, the voltage-controlled current source includes MOS transistors M21 and M22. The source of MOS transistor M21 is connected to the gate of MOS transistor M25. The drain of MOS transistor M25 is connected to the drain of MOS transistor M23. After the sources of MOS transistors M25 and M26 are commonly connected, they are connected to the drain of MOS transistor M33. The drain of MOS transistor M26 is connected to the gate of MOS transistor M22 and the drain of MOS transistor M24. The drain of MOS transistor M22 is connected to the drain of MOS transistor M30. The source of MOS transistor M30 is connected to the drain of MOS transistor M28. The gate of MOS transistor M30 is connected to the gate of MOS transistor M31. The gates of MOS transistors M28 and M29 are connected. The drain of MOS transistor M31 is connected to the drain of MOS transistor M35. The gate of MOS transistor M35 is connected to the gate of MOS transistor M34. The source of MOS transistor M35 is connected to the drain of MOS transistor M37. The source of MOS transistor M34 is connected to the drain of MOS transistor M36. The gate of MOS transistor M36 is connected to the gate of MOS transistor M37; Among them, the drain of MOS transistor M34 is respectively connected to the gate of MOS transistor M26 and the source of MOS transistor M22, and a compensation capacitor C1 is connected to the source of MOS transistor M22, and the other end of compensation capacitor C1 is grounded.

[0033] The drain of MOS transistor M21 is connected to power supply bus VDD. The sources of MOS transistors M23, M24, M28, and M29 are all connected to power supply bus VDD. The source of MOS transistor M21 is also connected to the drain of MOS transistor M32. The sources of MOS transistors M32, M33, M36, and M37 are grounded.

[0034] MOS transistor M21 is the input-stage MOS transistor. The error signal of the differential amplification module is input to the gate of MOS transistor M21. If the output voltage Vout increases, it causes the gate voltage of MOS transistor M21 to change, and further causes the source current of MOS transistor M21 to change, thereby triggering the current change of the first-stage current mirror composed of MOS transistors M25, M26, M23, and M24 in the subsequent stage; The source current change of MOS transistor M25 is mirrored to MOS transistor M26, driving the gate of MOS transistor M22. Since the drain of MOS transistor M22 is connected to the drain of MOS transistor M30, and MOS transistors M30, M31, M28, and M29 form a second-stage current mirror, the mirrored currents of MOS transistors M30 and M31 are transmitted to the last-stage current mirror of MOS transistors M34, M35, M36, and M37. The function of each stage of the current mirror is to copy and amplify the current, so that the small current change of MOS transistor M21 generates a significant current in the subsequent stage.

[0035] If the output voltage Vout increases, through the subsequent-stage current regulation of MOS transistor M21, the first-stage current mirror, MOS transistor M22, the second-stage current mirror, and the last-stage current mirror, the current at the Vfb node is pulled down, so that the differential amplification module detects the change of Vfb and corrects the output voltage Vout back to the stable value.

[0036] One end of the compensation capacitor C1 is connected to the source of MOS transistor M22, and the other end is grounded. Using the Miller effect, the source of MOS transistor M22 is a high-impedance node. Since MOS transistor M22 is an amplifying transistor, the drain is connected to the current mirror and the equivalent impedance of the source is high, making the compensation capacitor C1 equivalent to a "multiplied capacitor", Ceq≈C1×(1 + ), is the voltage gain of MOS transistor M22, which can greatly reduce the main pole frequency, make the main pole closer to the low frequency, suppress the phase superposition of high-frequency signals, compensate for the high-frequency pole phase lag of the multi-stage amplifying circuit, and improve the loop phase margin.

[0037] When there is high-frequency noise or rapid load change in the circuit, the compensation capacitor C1 provides a grounding path for the high-frequency current, reduces the high-frequency impedance of the source of MOS transistor M22, suppresses the interference of high-frequency noise on the Vfb node, ensures the purity of the feedback signal Vfb, and enables the front-stage differential amplification module to accurately correct the output voltage Vout.

[0038] The embodiments of the present invention have been described above, but the present invention is not limited to the above specific implementation manners. The above specific implementation manners are merely illustrative rather than restrictive. Under the inspiration of the present invention, those of ordinary skill in the art can also make many forms, all of which fall within the protection scope of the present invention.

Claims

1. An LDO frequency compensation circuit based on a voltage-controlled current source, characterized in that It includes an input differential amplification module, a power regulation module, a frequency compensation module, and a feedback voltage division module; The power regulation module includes an MOS transistor MP. The current signal output by the input differential amplification module controls the gate voltage of the MOS transistor MP, thereby adjusting the conduction degree of the MOS transistor MP. The source of the MOS transistor MP is the output voltage Vout. The feedback voltage division module includes a resistor R1 and a resistor R2. The resistor R1 and the resistor R2 are connected in series. The resistor R1 is connected to the output voltage Vout, and the resistor R2 is grounded; The output end of the input differential amplification module is electrically connected to the input end of the frequency compensation module. The frequency compensation module includes a voltage-controlled current source and a compensation capacitor C1. The compensation capacitor C1 cooperates with the voltage-controlled current source to adjust the loop frequency response; The input differential amplification module includes a differential input stage, a first current mirror, a second current mirror, and a bias circuit. The differential input stage is used to compare the reference voltage Vref and the feedback voltage Vfb and convert them into a current difference. The first current mirror cooperates with the differential input stage to preliminarily amplify the signal and provide a suitable current signal for the subsequent stage. The second current mirror and the bias circuit provide a stable bias current for the differential input stage to ensure that the circuit operates at a suitable quiescent operating point.

2. The LDO frequency compensation circuit based on a voltage-controlled current source according to claim 1, wherein The differential input stage includes MOS transistors M1 and M2. The MOS transistors M1 and M2 are differential pair transistors. The gate of the MOS transistor M1 is connected to the reference voltage Vref, and the gate of the MOS transistor M2 is connected to the feedback voltage Vfb.

3. The LDO frequency compensation circuit based on a voltage-controlled current source according to claim 2, wherein The first current mirror includes MOS transistors M3, M4, M5, and M6. The MOS transistors M3 and M4 form a first group of current mirrors, and the MOS transistors M5 and M6 form a second group of current mirrors. The gates of the MOS transistor M3 and the MOS transistor M4 are commonly connected. The drain of the MOS transistor M3 is connected to its gate. The drain of the MOS transistor M3 is connected to the source of the MOS transistor M1.

4. The LDO frequency compensation circuit based on a voltage-controlled current source according to claim 3, characterized in that, The second current mirror includes MOS transistors M7 and M8. The source of the MOS transistor M7 and the MOS transistor M8 form a third group of current mirrors. The gates of the MOS transistor M7 and the MOS transistor M8 are commonly connected. The sources of the MOS transistor M7 and the MOS transistor M8 are connected to the power supply bus VDD. The drain of the MOS transistor M7 is connected to the drain of the MOS transistor M4, and the drains of the MOS transistor M8 and the MOS transistor M6 are commonly connected.

5. The LDO frequency compensation circuit based on a voltage-controlled current source according to claim 4, wherein The bias circuit includes MOS transistors M11 and M12. The source of the MOS transistor M12 is connected to the power supply bus VDD. The drain of the MOS transistor M12 is connected to the source of the MOS transistor M11. The drain of the MOS transistor M11 is commonly connected to the sources of the MOS transistor M1 and the MOS transistor M12; The drains of the MOS transistor M8 and the MOS transistor M6 are connected to the gate of the MOS transistor MP.

6. The LDO frequency compensation circuit based on a voltage-controlled current source according to claim 5, wherein The voltage-controlled current source includes MOS transistor M9 and MOS transistor M10. The gates of MOS transistor M9 and MOS transistor M10 are commonly connected. The drain of MOS transistor M9 is connected to the source of MOS transistor M14, and the source of MOS transistor M14 is the output voltage Vout2. The gate of MOS transistor M14 is connected to the drains of MOS transistor M8 and MOS transistor M6. The source of MOS transistor M14 is connected to the power supply bus VDD. The drains of MOS transistor M10 and MOS transistor M13 are commonly connected and are the feedback voltage signal Vfb. The source of MOS transistor M13 is connected to the power supply bus VDD, and the gate of MOS transistor M13 is connected to the bias voltage Vb. One end of the compensation capacitor C1 is connected to the drain of MOS transistor M9, and the other end of the compensation capacitor C1 is connected to the gate of MOS transistor M9.

7. The LDO frequency compensation circuit based on a voltage-controlled current source according to claim 5, wherein The voltage-controlled current source includes MOS transistor M9 and MOS transistor M10. The gates of MOS transistor M9 and MOS transistor M10 are commonly connected. The drain of MOS transistor M9 is connected to the source of MOS transistor M14. One end of the compensation capacitor C1 is connected to the drain of MOS transistor M9, and the other end of the compensation capacitor C1 is connected to the gate of MOS transistor M9. The source of MOS transistor M14 is connected to the power supply bus VDD. The drains of MOS transistor M10 and MOS transistor M13 are commonly connected and are the feedback voltage signal Vfb. The source of MOS transistor M13 is connected to the power supply bus VDD, and the gate of MOS transistor M13 is connected to the bias voltage Vb. Wherein, the gate of MOS transistor M14 is connected to the output terminal of the operational amplifier OP. The inverting input terminal of the operational amplifier OP is connected to the output voltage Vout, and the non-inverting input terminal of the operational amplifier OP is connected to the output voltage Vout2.

8. The LDO frequency compensation circuit based on a voltage-controlled current source according to claim 5, wherein The voltage-controlled current source includes MOS transistor M9 and MOS transistor M10. The gates of MOS transistor M9 and MOS transistor M10 are commonly connected. The drain of MOS transistor M9 is connected to the drain of MOS transistor M14, and the drain and gate of MOS transistor M9 are short-circuited. The source of MOS transistor M14 is the output voltage Vout2. The gate of MOS transistor M14 is connected to the drains of MOS transistor M8 and MOS transistor M6. The source of MOS transistor M14 is connected to the power supply bus VDD. The drains of MOS transistor M10 and MOS transistor M13 are commonly connected and are the feedback voltage signal Vfb. The source of MOS transistor M13 is connected to the power supply bus VDD, and the gate of MOS transistor M13 is connected to the bias voltage Vb. Wherein, one end of the compensation capacitor C1 is connected to the output voltage Vout2, and the other end of the compensation capacitor C1 is grounded.

9. The LDO frequency compensation circuit based on a voltage-controlled current source according to claim 5, wherein, The voltage-controlled current source includes MOS transistor M21 and MOS transistor M22. The source of MOS transistor M21 is connected to the gate of MOS transistor M25. The drain of MOS transistor M25 is connected to the drain of MOS transistor M23. After the sources of MOS transistor M25 and MOS transistor M26 are commonly connected, they are connected to the drain of MOS transistor M33. The drain of MOS transistor M26 is connected to the gate of MOS transistor M22 and the drain of MOS transistor M24. The drain of MOS transistor M22 is connected to the drain of MOS transistor M30. The source of MOS transistor M30 is connected to the drain of MOS transistor M28. The gate of MOS transistor M30 is connected to the gate of MOS transistor M31. The gates of MOS transistor M28 and MOS transistor M29 are connected. The drain of MOS transistor M31 is connected to the drain of MOS transistor M35. The gate of MOS transistor M35 is connected to the gate of MOS transistor M34. The source of MOS transistor M35 is connected to the drain of MOS transistor M37. The source of MOS transistor M34 is connected to the drain of MOS transistor M36. The gate of MOS transistor M36 is connected to the gate of MOS transistor M37; Wherein, the drain of MOS transistor M34 is respectively connected to the gate of MOS transistor M26 and the source of MOS transistor M22, and a compensation capacitor C1 is connected to the source of MOS transistor M22, and the other end of the compensation capacitor C1 is grounded.

10. The LDO frequency compensation circuit based on a voltage-controlled current source according to claim 9, characterized in that, The drain of MOS transistor M21 is connected to the power supply bus VDD. The sources of MOS transistors M23, M24, M28, and M29 are all connected to the power supply bus VDD. The source of MOS transistor M21 is further connected to the drain of MOS transistor M32. The sources of MOS transistors M32, M33, M36, and M37 are grounded.

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