Clock processing system, method, device, medium and program product

Abstract

The invention discloses a clock processing system, method and device, a medium and a program product in the technical field of computers. A first clock module is arranged in a processor in each mainboard, and under the condition that a first clock signal is provided, downstream switching equipment of the mainboards and at least two pieces of target equipment connected with the switching equipment take a second clock signal provided by a second clock module in the switching equipment as reference; therefore, homologous synchronization of the clock signals of the downstream switching device and the at least two target devices connected with the switching device is realized. And moreover, the first clock signal provided by each upstream mainboard is not influenced, so that the problem of clock asynchronization of downstream equipment in a scene that multiple mainboards provide clock signals is solved.

Description

Technical Field

[0001] This application relates to the field of computer technologies, and particularly to a clock processing system, method, device, medium, and program product. Background Art

[0002] In a multi-mainboard scenario, if the processors on different mainboards all have built-in clock circuits and output clock signals, then multiple downstream devices connected to these mainboards can only use the clock signal output by a single certain mainboard, resulting in the clocks of these downstream devices being out of sync.

[0003] Therefore, how to solve the problem of out-of-sync clocks of downstream devices in the scenario where multiple mainboards all provide clock signals is a problem that needs to be solved by those skilled in the art. Summary of the Invention

[0004] In view of this, the purpose of this application is to provide a clock processing system, method, device, medium, and program product to solve the problem of out-of-sync clocks of downstream devices in the scenario where multiple mainboards all provide clock signals.

[0005] In a first aspect, this application provides a clock processing system, including: at least two mainboards, a switching device, and at least two target devices; wherein, the processors in each mainboard have built-in first clock modules; the first clock modules are used to provide first clock signals for the corresponding mainboards; the switching device includes: a second clock module, a switching module, and signal processing components respectively corresponding to and connected to each mainboard; the second clock module is respectively connected to the switching module, any signal processing component, and any two target devices; the second clock module is used to provide second clock signals for any signal processing component, the switching module, and any two target devices; the switching module is respectively connected to any signal processing component and any target device; the switching module is used to connect the data path between any signal processing component and any target device.

[0006] Second aspect, the present application provides a clock processing method, which is applied to any signal processing device in a clock processing system. The clock processing system includes: at least two main boards, a switching device, and at least two target devices; wherein, a first clock module is built in the processor of each main board; the first clock module is used to provide a first clock signal for the corresponding main board; the switching device includes: a second clock module, a switching module, and signal processing devices respectively corresponding to and connected to each main board; the second clock module is respectively connected to the switching module, any signal processing device, and any two target devices; the second clock module is used to provide a second clock signal for any signal processing device, the switching module, and any two target devices; the switching module is respectively connected to any signal processing device and any target device; the switching module is used to connect the data path between any signal processing device and any target device; the clock processing method includes: referring to the second clock signal currently generated by the second clock module, performing clock recovery on the upstream data signal sent by the main board corresponding to the signal processing device to obtain a recovered clock signal; referring to the recovered clock signal, transmitting the current upstream data signal to the target device corresponding to the current upstream data signal; and / or, referring to the recovered clock signal, transmitting the received downstream data signal to the destination main board corresponding to the current downstream data signal.

[0007] Third aspect, the present application provides an electronic device, including: a memory for storing a computer program; a processor for executing the computer program to implement the foregoing disclosed clock processing method.

[0008] Fourth aspect, the present application provides a non-volatile storage medium for storing a computer program, wherein the computer program, when executed by a processor, implements the foregoing disclosed clock processing method.

[0009] Fifth aspect, the present application provides a computer program product, including a computer program / instructions, which, when executed by a processor, implement the steps of the foregoing disclosed clock processing method.

[0010] As can be seen from the above solutions, the present application provides a clock processing system, including: at least two main boards, a switching device, and at least two target devices; wherein, a first clock module is built in the processor of each main board; the first clock module is used to provide a first clock signal for the corresponding main board; the switching device includes: a second clock module, a switching module, and signal processing devices respectively corresponding to and connected to each main board; the second clock module is respectively connected to the switching module, any signal processing device, and any two target devices; the second clock module is used to provide a second clock signal for any signal processing device, the switching module, and any two target devices; the switching module is respectively connected to any signal processing device and any target device; the switching module is used to connect the data path between any signal processing device and any target device.

[0011] It can be seen that the beneficial effects of the present application are as follows: when the processors in each main board are all built-in with a first clock module to provide a first clock signal, the downstream switching devices of these main boards and at least two target devices connected to the switching device all refer to the second clock signal provided by the second clock module in the switching device, so as to realize the homologous synchronization of the clock signals of the downstream switching devices and at least two target devices connected to the switching device. Moreover, it does not affect the first clock signals provided by the upstream main boards, and solves the problem of clock asynchronization of downstream devices in the scenario where multiple main boards all provide clock signals.

[0012] Correspondingly, a clock processing method, device, medium and program product provided by the present application also have the above technical effects. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings required to be used in the description of the embodiments or the prior art. Obviously, the drawings in the following description are only the embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained according to the provided drawings without creative efforts.

[0014] Figure 1 Schematic diagram of a clock processing system disclosed in the present application; Figure 2 Schematic diagram of a second clock processing system disclosed in the present application; Figure 3 Schematic diagram of a main board structure disclosed in the present application; Figure 4 Schematic diagram of an FPGA acceleration card structure disclosed in the present application; Figure 5 Schematic diagram of data processing inside an FPGA acceleration card disclosed in the present application; Figure 6 Schematic diagram of a clock recovery process disclosed in the present application; Figure 7 Schematic diagram of a server structure provided by the present application; Figure 8 Schematic diagram of a terminal structure provided by the present application. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0015] The following will clearly and completely describe the technical solutions in the embodiments of the present application with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments of the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the protection scope of the present application.

[0016] It should be noted that in the description of this application, the terms "include", "comprise" or any other variant thereof are intended to cover non-exclusive inclusion, such that a process, method, article or device including a series of elements not only includes those elements but also includes other elements not expressly listed, or elements inherent to such process, method, article or device. The terms "first", "second", etc. in this application are used to distinguish similar objects and not to describe a specific order or sequence.

[0017] To enable those skilled in the art of this technology to better understand the solution of this application, the following further detailed description of this application will be given in conjunction with the accompanying drawings and specific embodiments.

[0018] Currently, in a multi-mainboard scenario, if the processors on different mainboards all have built-in clock circuits and output clock signals, then multiple downstream devices connected to these mainboards can only use the clock signal output by a single certain mainboard, resulting in the clocks of these downstream devices being out of sync. For this reason, this application provides a clock processing solution that can achieve the homologous synchronization of the clock signals of the downstream switching devices of each mainboard and at least two target devices connected to the switching device, and solve the problem of out-of-sync clocks of downstream devices in the scenario where multiple mainboards all provide clock signals.

[0019] See Figure 1 As shown, an embodiment of this application discloses a clock processing system, including: at least two mainboards, a switching device, and at least two target devices; wherein, a first clock module is built into the processor in each mainboard; the first clock module is used to provide a first clock signal for the corresponding mainboard; wherein, the second clock module includes: a clock generator and a clock buffer; the clock generator is used to generate a second clock signal; the clock buffer is used to cache the second clock signal.

[0020] The switching device includes: a second clock module, a switching module, and signal processing components respectively corresponding to and connected to each mainboard; the second clock module is respectively connected to the switching module, any signal processing component, and any two target devices; the second clock module is used to provide a second clock signal for any signal processing component, the switching module, and any two target devices; the switching module is respectively connected to any signal processing component and any target device; the switching module is used to connect the data path between any signal processing component and any target device.

[0021] In this embodiment, the target device can be a memory device or an acceleration card.

[0022] Please see Figure 1 , Figure 1 The thickened lines in are clock lines, and the unthickened lines are data lines. The specific transmission directions of these two types of lines can be seen in Figure 2The arrow shown. In one embodiment, clock lines are connected between the second clock module and the switching module, any signal processing device, and any target device respectively. Specifically, between the second clock module and any signal processing device, the connection of the clock line is achieved through a slot supporting the Peripheral Component Interconnect Express (PCIe) standard; between the second clock module and any target device, the connection of the clock line is achieved through a slot supporting the PCIe standard. In one embodiment, data lines are connected between the switching module and any signal processing device, and any two target devices respectively. Specifically, between the switching module and any signal processing device, the connection of the data line is achieved through a slot supporting the PCIe standard; between the switching module and any target device, the connection of the data line is achieved through a slot supporting the PCIe standard.

[0023] Among them, the signal processing device is used to: refer to the second clock signal currently generated by the second clock module, perform clock recovery on the upstream data signal sent by the motherboard corresponding to the signal processing device to obtain a recovered clock signal, and refer to the recovered clock signal to transmit the current upstream data signal to the target device corresponding to the current upstream data signal, such as: it can be a certain acceleration card; and / or, refer to the recovered clock signal to transmit the received downstream data signal to the destination motherboard corresponding to the current downstream data signal.

[0024] To enable the signal processing device to have the clock recovery function, a clock recovery module is set inside it. This clock recovery module is the CDR (Clock and Data Recovery) module. The specific structure may include: a sampler, a detector, a filter, and an oscillator; the sampler is used to: sample the received data signal; the detector is used to: detect the rising edge or falling edge of the sampled data signal, and compare the phase difference with the second clock signal currently generated by the second clock module, and output a phase error; the filter is used to: perform low-pass filtering on the phase error; the oscillator is used to: adjust the frequency and phase of the clock signal obtained by low-pass filtering to obtain a clock recovery signal, and use the clock recovery signal to sample the received data signal.

[0025] It should be noted that the second clock module and multiple signal processing devices are built into the switching device, and multiple signal processing devices correspond to each motherboard one by one. And, the switching device includes a switching module. Then, the data transmission path from the motherboard to the downstream acceleration card is: motherboard → signal processing device → switching module → acceleration card; correspondingly, the data transmission path from the downstream acceleration card to the motherboard is: acceleration card → switching module → signal processing device → motherboard.

[0026] The data transmission from the motherboard to the downstream acceleration card will be introduced below in combination with each functional module in the signal processing device. In one implementation, the signal processing device includes: an upstream communication module, a clock recovery module, and a downstream communication module; the upstream communication module is configured to: receive the upstream data signal sent by any motherboard; send the currently received downstream data signal to the destination motherboard corresponding to the current downstream data signal; the clock recovery module is configured to: perform clock recovery on the upstream data signal sent by the motherboard corresponding to the signal processing device with reference to the second clock signal currently generated by the second clock module to obtain a recovered clock signal; the downstream communication module is configured to: receive the downstream data signal sent by any acceleration card; send the received upstream data signal to the destination acceleration card corresponding to the current upstream data signal. Among them, the upstream communication module is connected to the upstream connector, and the upstream connector is connected to the motherboard; the downstream communication module is connected to the gold finger, and the gold finger is connected to the switching module (PCIe Switch or CXL Switch) in the switching device through PCIe Slots, and many acceleration cards are connected to the downstream of the switching module through many PCIe Slots.

[0027] More specifically, the signal processing device can also perform many processes such as decoding, frame parsing, and / or demultiplexing on the data signal. In one implementation, the signal processing device further includes: a top-down first parsing unit, a top-down caching unit, and a top-down second parsing unit; the top-down first parsing unit is configured to: perform decoding, frame parsing, and / or demultiplexing on the upstream data signal sent by the upstream communication module with reference to the recovered clock signal; the top-down caching unit is configured to: cache the upstream data signal after decoding, frame parsing, and / or demultiplexing with reference to the recovered clock signal; the top-down second parsing unit is configured to: read the upstream data signal from the top-down caching unit; perform multiplexing, frame parsing, and / or encoding on the read upstream data signal with reference to the second clock signal currently generated by the second clock module, and send the upstream data signal after multiplexing, frame parsing, and / or encoding to the downstream communication module.

[0028] It should also be noted that the data signal is a parallel signal inside the signal processing device and a serial signal outside the signal processing device. Therefore, in one implementation, the signal processing device further includes: a first serial-to-parallel conversion unit and a first parallel-to-serial conversion unit; the first serial-to-parallel conversion unit is configured to: perform serial-to-parallel conversion on the upstream data signal sent by the upstream communication module, and transmit the upstream data signal after serial-to-parallel conversion to the top-down first parsing unit and the clock recovery module; the first parallel-to-serial conversion unit is configured to: perform parallel-to-serial conversion on the upstream data signal after multiplexing, frame parsing, and / or encoding, and transmit the upstream data signal after parallel-to-serial conversion to the downstream communication module.

[0029] Among them, the top-down buffer unit includes: a top-down random access memory area and a top-down double data rate synchronous dynamic random access memory area; since the space of the top-down random access memory area is too small and limited, the data coming out of the top-down random access memory area enters the top-down double data rate synchronous dynamic random access memory area for caching. Specifically, the top-down random access memory area is used for: caching the received upstream data signal with reference to the recovery clock signal; outputting the upstream data signal with reference to the second clock signal currently generated by the second clock module; the top-down double data rate synchronous dynamic random access memory area is used for: caching the upstream data signal output by the random access memory area.

[0030] More specifically, the signal processing device can also encrypt or compress the data signal. In one embodiment, the signal processing device further includes: a top-down signal processing unit; the top-down signal processing unit is used for: performing compression processing and / or encryption processing on the upstream data signal output by the top-down first parsing unit.

[0031] Next, in combination with each functional module in the signal processing device, the data transmission from the downstream acceleration card to the motherboard is introduced. In one embodiment, the signal processing device further includes: a bottom-up first parsing unit, a bottom-up buffer unit, and a bottom-up second parsing unit; the bottom-up first parsing unit is used for: decoding, frame parsing, and / or demultiplexing the downstream data signal sent by the downstream communication module with reference to the second clock signal currently generated by the second clock module; the bottom-up buffer unit is used for: caching the downstream data signal after decoding, frame parsing, and / or demultiplexing with reference to the second clock signal currently generated by the second clock module; the bottom-up second parsing unit is used for: reading the downstream data signal from the bottom-up buffer unit, performing multiplexing, frame parsing, and / or encoding on the read downstream data signal, and sending the multiplexed, frame-parsed, and / or encoded downstream data signal to the upstream communication module.

[0032] Since the data signal is a parallel signal inside the signal processing device and a serial signal outside the signal processing device. Therefore, in one embodiment, the signal processing device further includes: a second serial-to-parallel conversion unit and a second parallel-to-serial conversion unit; the second serial-to-parallel conversion unit is used for: performing serial-to-parallel conversion on the downstream data signal sent by the downstream communication module, and transmitting the serially-to-parallel converted downstream data signal to the bottom-up first parsing unit; the second parallel-to-serial conversion unit is used for: performing parallel-to-serial conversion on the multiplexed, frame-parsed, and / or encoded downstream data signal, and transmitting the parallel-to-serial converted downstream data signal to the upstream communication module.

[0033] Since the space of the random access memory is too small and limited, the data coming out of the random access memory enters the double data rate synchronous dynamic random access memory for caching. Specifically, in one implementation, the cache unit from bottom to top includes: a random access memory from bottom to top and a double data rate synchronous dynamic random access memory from bottom to top; the random access memory from bottom to top is used for: caching the received downstream data signal with reference to the second clock signal currently generated by the second clock module; outputting the downstream data signal with reference to the recovered clock signal; the double data rate synchronous dynamic random access memory from bottom to top is used for: caching the downstream data signal output by the random access memory.

[0034] Since the signal processing device can also encrypt or compress the data signal, in one implementation, the signal processing device further includes: a signal processing unit from bottom to top; the signal processing unit from bottom to top is used for: performing compression processing and / or encryption processing on the downstream data signal output by the first parsing unit from bottom to top.

[0035] It should also be noted that different models of motherboards are allowed in this embodiment. In one implementation, any motherboard includes: at least two processors; at least two processors both have a first clock module built-in; at least two processors are used to generate corresponding upstream data signals by using the first clock signal provided by their built-in first clock modules. That is, different processors that output different clock signals can be included in the same motherboard. For the convenience of interconnecting the motherboard with other devices, the motherboard can be in the form of a card that supports the Peripheral Component Interconnect Express (PCIe) standard. And, the signal processing device can be an FPGA acceleration card. Correspondingly, the FPGA acceleration card includes: an upstream connector and a gold finger; the upstream connector is connected to the corresponding motherboard; the gold finger is connected to the corresponding acceleration card through the switching module in the switching device.

[0036] It can be seen that in this embodiment, when each motherboard provides a clock signal, the downstream switching devices of these motherboards and at least two target devices connected to the switching device all refer to the second clock signal provided by the second clock module in the switching device, so as to achieve the homologous synchronization of the clock signals of the downstream switching devices and at least two target devices connected to the switching device. And it does not affect the clock signals provided by each upstream motherboard, solving the problem of clock asynchronization of downstream devices in the scenario where multiple motherboards all provide clock signals.

[0037] In one example, the system architecture in the dual-motherboard scenario can be as Figure 2 shown. In Figure 2Among them, a main board includes: a processor, a clock buffer, and an MCIO connector (MiniCool Edge I / O, a high-speed I / O connector). These two main boards are respectively connected to two FPGA acceleration cards (i.e., signal processing devices) in the switching device; the switching device also includes: a clock generator, a clock buffer, a switching module, and multiple PCIe Slots (i.e., slots supporting the high-speed serial computer expansion bus standard) required for connection. The three PCIe Slots at the most downstream are respectively connected to three acceleration cards.

[0038] Specifically, the MCIO connector of the main board is connected to the MCIO connector of the FPGA acceleration card through a cable, and then the gold finger of the FPGA acceleration card is connected to the Switch chip (switching module) of the Switch board (switching device). And since the FPGA acceleration card uses the local clock of the Switch board (i.e., the second clock signal provided by the second clock module) and does not use the clock output by the main board CPU, the FPGA acceleration card needs to perform clock recovery on the data signal of the main board CPU received, then use the local clock of the Switch board, and then input the data signal into the Switch chip. The Switch chip transmits it to the acceleration card, so that the downstream acceleration card also uses the clock source of the Switch board card. Thus, the main board and the Switch board use asynchronous clocks. In addition, the FPGA acceleration card is also a Switch device for the main board CPU, that is, the CPU data signal enters the downstream acceleration card after passing through two levels of Switch.

[0039] Please refer to Figure 3, the internal components of the main board may include a CPU, a BMC (Baseboard Management Controller), a CPLD (Complex Programmable Logic Device), a Flash memory, a memory, a hard disk, a clock, and a VRM (Voltage Regulator Module) power module, etc. Among them, the CPU is mainly responsible for resource allocation and computing; the BMC is mainly responsible for device information management, server status monitoring and management, server remote control management, and VGA (Video Graphics Array) display, etc.; the CPLD is mainly responsible for controlling the power supply timing and GPIO (General-Purpose Input / Output) communication, etc.; the VRM is different power modules that output different voltage values for the components on the board; DDR_CH1~DDR_CH4 represent RDIMM memory slots; the MCIO X8 connector is respectively connected to QSFP28, PCIe GEN4, and PCIe GEN5 signals. Among them, QSFP28 can perform optical communication with other devices, and PCIe GEN4 and PCIe GEN5 can be connected to NVME SSDs or other PCIe devices; XDP, UART, etc. are the standard debugging interfaces of the CPU, the VGA is connected to the monitor, and the USB is connected to the mouse and keyboard. This main board can be a pluggable micro main board in the PCIe form.

[0040] Please refer to Figure 4 , the FPGA acceleration card in the Switch board may include an FPGA, a CPLD, a Flash memory, and a VRM power module, etc. Among them, the FPGA is the main control chip, responsible for acceleration computing and communication, etc.; the CPLD is responsible for controlling the power supply timing and GPIO communication, etc.; the VRM is different power modules that output different voltage values for the components on the board; DDR5_1~DDR5_4 represent four-channel memory module slots, and 4 memory modules can be configured; QSFP28_1 and QSFP28_2 are the optical port connectors of the FPGA, which can communicate with other computing units or acceleration units; the two MCIO X8 are high-speed connectors, and they both support PCIe Gen5.0 and CXL protocol communication.

[0041] It should be noted that the CPU data of the CPU board enters the FPGA chip inside the FPGA acceleration card. Since the clock of this data uses the clock output by the CPU itself, and the FPGA acceleration card uses the local clock of the Switch board, both of these clocks are 100MHz, but their phases are generally different, that is, they belong to asynchronous clocks.

[0042] Please refer to Figure 5, inside the FPGA acceleration card, there are upstream ports and downstream ports, which can be understood as the upstream port and downstream port of the FPGA acceleration card acting as a Switch chip. The data signal of the motherboard CPU enters the physical high-speed transceiver IO (upstream communication module) of the FPGA acceleration card through the MCIO connector. After that, the data signal undergoes serial-to-parallel data conversion and then clock recovery. The clock recovery uses the CDR module inside the FPGA acceleration card, taking the local clock as the reference clock for clock data recovery. Then, the recovered clock is used to perform subsequent processing on the data signal, such as: decoding, data frame parsing, demultiplexer, and then outputting the processed layer data packet. At this time, the data packet can also perform some operations inside the FPGA acceleration card, such as compression, encryption, etc. Further, the data packet is asynchronously cached through the RAM inside the FPGA acceleration card. The so-called asynchronous cache means that the input RAM uses the recovered clock mentioned above, and the RAM output uses the local clock. However, due to the small RAM space, the data coming out of the RAM enters the DDR ( Figure 5 memory) for caching. For the DDR, the local clock is adopted to read out the data signal, and then a series of operations such as processed layer data packet packing, multiplexing, data frame parsing, encoding, parallel-to-serial conversion, etc. are performed on the data signal. The data packet is output through the physical high-speed transceiver IO of the downstream port and then enters the corresponding PCIe Slot through the Goldfinger.

[0043] On the transmission path from downstream to upstream, the data signal of the acceleration card enters the physical high-speed transceiver IO of the FPGA acceleration card through the Goldfinger, and then the local clock is used to perform a series of operations on the data signal, such as serial-to-parallel conversion, decoding, data frame parsing, demultiplexing, processed layer data packet, etc. At this time, the processed layer data packet can also perform some operations inside the FPGA acceleration card, such as compression, encryption, etc. Then, it is asynchronously cached through the RAM inside the FPGA acceleration card. The so-called asynchronous cache means that the input RAM uses the local clock, and the RAM output uses the recovered clock mentioned above. However, due to the small RAM space, the data coming out of the RAM enters the DDR for caching. After that, for the DDR, the local clock is adopted to read out the data signal, and then a series of operations such as processed layer data packet packing, multiplexing, data frame parsing, encoding, serial-to-parallel conversion, etc. are performed on the data signal. The obtained data signal is output through the physical high-speed transceiver IO of the upstream port and then enters the motherboard CPU through the MCIO connector.

[0044] Please refer to Figure 6, the data signal processing process of the CDR module in the FPGA acceleration card includes: performing equalization preprocessing on the received serial data, then performing multi-level sampling, and then passing through a phase detector to detect the phase difference between the rising edge / falling edge of the data and the local clock using edge triggering, outputting the phase error, then passing through a digital loop filter to perform low-pass filtering on the phase error signal, and finally passing through a numerically controlled oscillator to adjust the frequency and phase of the output clock, thereby restoring the original clock of the CPU. Then, the input data is sampled using the restored clock to restore the original data and output it to the DDR cache. It can be seen that the core principle of CDR is to extract clock information from high-speed serial data through digital signal processing technology and generate a clock signal synchronized with the data.

[0045] It should be noted that a phase detector, a digital loop filter, a numerically controlled oscillator, etc. can also be customized inside the FPGA acceleration card to implement the CDR function, thereby enabling self-adjustment of parameters such as filtering, making the solution more flexible.

[0046] In this embodiment, the FPGA acceleration card in the Switch board is used to implement asynchronous clock communication between the main board CPU and the Switch and its downstream acceleration cards. Here, the FPGA acceleration card not only implements the PCIe Switch function but also implements the clock recovery function for high-speed serial data.

[0047] Next, a clock processing method provided by an embodiment of the present application will be introduced. The following-described clock processing method can be referred to mutually with other embodiments described herein.

[0048] An embodiment of the present application discloses a clock processing method, which is applied to any signal processing device in a clock processing system. The clock processing system includes: at least two main boards, a switching device, and at least two target devices; wherein, a first clock module is built in the processor of each main board; the first clock module is used to provide a first clock signal for the corresponding main board; the switching device includes: a second clock module, a switching module, and signal processing devices respectively corresponding to and connected to each main board; the second clock module is respectively connected to the switching module, any signal processing device, and any two target devices; the second clock module is used to provide a second clock signal for any signal processing device, the switching module, and any two target devices; the switching module is respectively connected to any signal processing device and any target device; the switching module is used to connect the data path between any signal processing device and any target device.

[0049] The clock processing method provided by this embodiment includes: referring to the second clock signal currently generated by the second clock module, performing clock recovery on the upstream data signal sent by the main board corresponding to the signal processing device to obtain a recovered clock signal; referring to the recovered clock signal, transmitting the current upstream data signal to the target device corresponding to the current upstream data signal; and / or, referring to the recovered clock signal, transmitting the received downstream data signal to the destination main board corresponding to the current downstream data signal.

[0050] To enable the signal processing device to have the clock recovery function, a clock recovery module is provided therein. This clock recovery module is a CDR (Clock and Data Recovery) module, and its specific structure may include: a sampler, a detector, a filter, and an oscillator; the sampler is used for: sampling the received data signal; the detector is used for: detecting the rising edge or falling edge of the sampled data signal, comparing the phase difference with the second clock signal currently generated by the second clock module, and outputting a phase error; the filter is used for: performing low-pass filtering on the phase error; the oscillator is used for: adjusting the frequency and phase of the clock signal obtained by low-pass filtering to obtain a clock recovery signal, and using the clock recovery signal to sample the received data signal.

[0051] In one implementation, the signal processing device includes: an upstream communication module, a clock recovery module, and a downstream communication module; the upstream communication module is used for: receiving the upstream data signal sent by any main board; sending the currently received downstream data signal to the destination main board corresponding to the current downstream data signal; the clock recovery module is used for: referring to the second clock signal currently generated by the second clock module, performing clock recovery on the upstream data signal sent by the main board corresponding to the signal processing device to obtain a recovered clock signal; the downstream communication module is used for: receiving the downstream data signal sent by any acceleration card; sending the received upstream data signal to the destination acceleration card corresponding to the current upstream data signal.

[0052] In one implementation, the signal processing device further includes: a top-down first parsing unit, a top-down caching unit, and a top-down second parsing unit; the top-down first parsing unit is used for: referring to the recovered clock signal, decoding, frame parsing, and / or demultiplexing the upstream data signal sent by the upstream communication module; the top-down caching unit is used for: referring to the recovered clock signal, caching the upstream data signal after decoding, frame parsing, and / or demultiplexing; the top-down second parsing unit is used for: reading the upstream data signal from the top-down caching unit; referring to the second clock signal currently generated by the second clock module, performing multiplexing, frame parsing, and / or encoding on the read upstream data signal, and sending the multiplexed, frame-parsed, and / or encoded upstream data signal to the downstream communication module.

[0053] In one embodiment, the signal processing device further includes: a first serial-to-parallel conversion unit and a first parallel-to-serial conversion unit; the first serial-to-parallel conversion unit is configured to: perform serial-to-parallel conversion on the upstream data signal sent by the upstream communication module, and transmit the serially-converted upstream data signal to the first parsing unit and the clock recovery module from top to bottom; the first parallel-to-serial conversion unit is configured to: perform parallel-to-serial conversion on the multiplexed, frame-parsed, and / or encoded upstream data signal, and transmit the parallel-to-serial converted upstream data signal to the downstream communication module.

[0054] In one embodiment, the cache unit from top to bottom includes: a random access storage area from top to bottom and a double data rate synchronous dynamic random access storage area from top to bottom; the random access storage area from top to bottom is configured to: cache the received upstream data signal with reference to the recovered clock signal; output the upstream data signal with reference to the second clock signal currently generated by the second clock module; the double data rate synchronous dynamic random access storage area from top to bottom is configured to: cache the upstream data signal output by the random access storage area.

[0055] In one embodiment, the signal processing device further includes: a signal processing unit from top to bottom; the signal processing unit from top to bottom is configured to: perform compression processing and / or encryption processing on the upstream data signal output by the first parsing unit from top to bottom.

[0056] In one embodiment, the signal processing device further includes: a first parsing unit from bottom to top, a cache unit from bottom to top, and a second parsing unit from bottom to top; the first parsing unit from bottom to top is configured to: decode, frame-parse, and / or demultiplex the downstream data signal sent by the downstream communication module with reference to the second clock signal currently generated by the second clock module; the cache unit from bottom to top is configured to: cache the decoded, frame-parsed, and / or demultiplexed downstream data signal with reference to the second clock signal currently generated by the second clock module; the second parsing unit from bottom to top is configured to: read the downstream data signal from the cache unit from bottom to top, perform multiplexing, frame-parsing, and / or encoding on the read downstream data signal, and transmit the multiplexed, frame-parsed, and / or encoded downstream data signal to the upstream communication module.

[0057] In one embodiment, the signal processing device further includes: a second serial-to-parallel conversion unit and a second parallel-to-serial conversion unit; the second serial-to-parallel conversion unit is configured to: perform serial-to-parallel conversion on the downstream data signal sent by the downstream communication module, and transmit the serially-converted downstream data signal to the first parsing unit from bottom to top; the second parallel-to-serial conversion unit is configured to: perform parallel-to-serial conversion on the multiplexed, frame-parsed, and / or encoded downstream data signal, and transmit the parallel-to-serial converted downstream data signal to the upstream communication module.

[0058] In one embodiment, the bottom-up cache unit includes: a bottom-up random access storage area and a bottom-up double data rate synchronous dynamic random access storage area; the bottom-up random access storage area is configured to: cache the received downstream data signal with reference to the second clock signal currently generated by the second clock module; output the downstream data signal with reference to the recovered clock signal; the bottom-up double data rate synchronous dynamic random access storage area is configured to: cache the downstream data signal output by the random access storage area.

[0059] In one embodiment, the signal processing device further includes: a bottom-up signal processing unit; the bottom-up signal processing unit is configured to: perform compression processing and / or encryption processing on the downstream data signal output by the bottom-up first parsing unit.

[0060] In one embodiment, the models of different motherboards are different.

[0061] In one embodiment, the signal processing device is an FPGA acceleration card.

[0062] In one embodiment, the FPGA acceleration card includes: an upstream connector and a gold finger; the upstream connector is connected to the corresponding motherboard; the gold finger is connected to the corresponding acceleration card through the switching module in the switching device.

[0063] In one embodiment, any motherboard includes: at least two processors; at least two processors are both built-in with a first clock module; at least two processors are configured to generate corresponding upstream data signals by using the first clock signal provided by the first clock module built in themselves.

[0064] In one embodiment, any motherboard is in the form of a card that supports the Peripheral Component Interconnect Express (PCIe) standard.

[0065] Wherein, for the more specific working processes of each module and unit in this embodiment, reference can be made to the corresponding content disclosed in the foregoing embodiments, and details will not be elaborated herein.

[0066] In this embodiment, when each motherboard provides a clock signal, the downstream switching device of these motherboards and at least two target devices connected to the switching device all refer to the second clock signal provided by the second clock module in the switching device, so as to achieve the homologous synchronization of the clock signals of the downstream switching device and at least two target devices connected to the switching device. And it does not affect the clock signals provided by each upstream motherboard, solving the problem of asynchronous clocks of downstream devices in the scenario where multiple motherboards provide clock signals.

[0067] The following introduces an electronic device provided by an embodiment of the present application. The electronic device described below can be cross-referred to other embodiments described in this article. The electronic device in this embodiment can be any device or functional module described in other embodiments, such as: main board, switching device, acceleration card, first clock module, switching device, second clock module, and signal processing device, etc.

[0068] An embodiment of the present application discloses an electronic device, including: a memory for storing a computer program; a processor for executing the computer program to implement the method disclosed in any of the above embodiments.

[0069] In this embodiment, when the processor executes the computer program stored in the memory, the following steps can be specifically implemented: providing a first clock signal for the corresponding main board.

[0070] In this embodiment, when the processor executes the computer program stored in the memory, the following steps can be specifically implemented: generating a second clock signal.

[0071] In this embodiment, when the processor executes the computer program stored in the memory, the following steps can be specifically implemented: referring to the second clock signal currently generated by the second clock module, performing clock recovery on the upstream data signal sent by the main board corresponding to the signal processing device to obtain a recovered clock signal, and referring to the recovered clock signal, transmitting the current upstream data signal to the destination acceleration card corresponding to the current upstream data signal; and / or, referring to the recovered clock signal, transmitting the received downstream data signal to the destination main board corresponding to the current downstream data signal.

[0072] In this embodiment, when the processor executes the computer program stored in the memory, the following steps can be specifically implemented: sampling the received data signal.

[0073] In this embodiment, when the processor executes the computer program stored in the memory, the following steps can be specifically implemented: detecting the rising edge or falling edge of the sampled data signal, comparing the phase difference with the second clock signal currently generated by the second clock module, and outputting a phase error.

[0074] In this embodiment, when the processor executes the computer program stored in the memory, the following steps can be specifically implemented: performing low-pass filtering on the phase error

[0075] In this embodiment, when the processor executes the computer program stored in the memory, the following steps can be specifically implemented: adjusting the frequency and phase of the clock signal obtained by low-pass filtering to obtain a clock recovery signal, and sampling the received data signal using the clock recovery signal.

[0076] In this embodiment, when the processor executes the computer program stored in the memory, the following steps may be specifically implemented: receiving an upstream data signal sent by any main board; sending the currently received downstream data signal to the destination main board corresponding to the current downstream data signal.

[0077] In this embodiment, when the processor executes the computer program stored in the memory, the following steps may be specifically implemented: referring to the second clock signal currently generated by the second clock module, performing clock recovery on the upstream data signal sent by the main board corresponding to the signal processing device to obtain a recovered clock signal.

[0078] In this embodiment, when the processor executes the computer program stored in the memory, the following steps may be specifically implemented: receiving a downstream data signal sent by any acceleration card; sending the received upstream data signal to the destination acceleration card corresponding to the current upstream data signal.

[0079] In this embodiment, when the processor executes the computer program stored in the memory, the following steps may be specifically implemented: referring to the recovered clock signal, decoding, frame parsing, and / or demultiplexing the upstream data signal sent by the upstream communication module.

[0080] In this embodiment, when the processor executes the computer program stored in the memory, the following steps may be specifically implemented: referring to the recovered clock signal, caching the upstream data signal after decoding, frame parsing, and / or demultiplexing.

[0081] In this embodiment, when the processor executes the computer program stored in the memory, the following steps may be specifically implemented: reading the upstream data signal from the top-down cache unit; referring to the second clock signal currently generated by the second clock module, performing multiplexing, frame parsing, and / or encoding on the read upstream data signal, and sending the multiplexed, frame-parsed, and / or encoded upstream data signal to the downstream communication module.

[0082] In this embodiment, when the processor executes the computer program stored in the memory, the following steps may be specifically implemented: performing serial-to-parallel conversion on the upstream data signal sent by the upstream communication module, and transmitting the serially-to-parallel converted upstream data signal to the top-down first parsing unit and the clock recovery module.

[0083] In this embodiment, when the processor executes the computer program stored in the memory, the following steps may be specifically implemented: performing parallel-to-serial conversion on the upstream data signal after multiplexing, frame parsing, and / or encoding, and transmitting the parallel-to-serial converted upstream data signal to the downstream communication module.

[0084] In this embodiment, when the processor executes the computer program stored in the memory, the following steps can be specifically implemented: caching the received upstream data signal with reference to the recovery clock signal; outputting the upstream data signal with reference to the second clock signal currently generated by the second clock module.

[0085] In this embodiment, when the processor executes the computer program stored in the memory, the following steps can be specifically implemented: caching the upstream data signal output by the random access storage area.

[0086] In this embodiment, when the processor executes the computer program stored in the memory, the following steps can be specifically implemented: performing compression processing and / or encryption processing on the upstream data signal output by the first parsing unit from top to bottom.

[0087] In this embodiment, when the processor executes the computer program stored in the memory, the following steps can be specifically implemented: decoding, frame parsing, and / or demultiplexing the downstream data signal sent by the downstream communication module with reference to the second clock signal currently generated by the second clock module.

[0088] In this embodiment, when the processor executes the computer program stored in the memory, the following steps can be specifically implemented: caching the downstream data signal after decoding, frame parsing, and / or demultiplexing with reference to the second clock signal currently generated by the second clock module.

[0089] In this embodiment, when the processor executes the computer program stored in the memory, the following steps can be specifically implemented: reading the downstream data signal from the bottom-up cache unit, performing multiplexing, frame parsing, and / or encoding on the read downstream data signal, and sending the multiplexed, frame-parsed, and / or encoded downstream data signal to the upstream communication module.

[0090] In this embodiment, when the processor executes the computer program stored in the memory, the following steps can be specifically implemented: performing serial-to-parallel conversion on the downstream data signal sent by the downstream communication module, and transmitting the serially-to-parallel converted downstream data signal to the first parsing unit from bottom to top.

[0091] In this embodiment, when the processor executes the computer program stored in the memory, the following steps can be specifically implemented: performing parallel-to-serial conversion on the multiplexed, frame-parsed, and / or encoded downstream data signal, and transmitting the parallel-to-serial converted downstream data signal to the upstream communication module.

[0092] In this embodiment, when the processor executes the computer program stored in the memory, the following steps may be specifically implemented: caching the received downstream data signal with reference to the second clock signal currently generated by the second clock module; and outputting the downstream data signal with reference to the recovery clock signal.

[0093] In this embodiment, when the processor executes the computer program stored in the memory, the following steps may be specifically implemented: caching the downstream data signal output by the random access storage area.

[0094] In this embodiment, when the processor executes the computer program stored in the memory, the following steps may be specifically implemented: performing compression processing and / or encryption processing on the downstream data signal output by the first parsing unit from bottom to top.

[0095] In this embodiment, when the processor executes the computer program stored in the memory, the following steps may be specifically implemented: generating a corresponding upstream data signal by using the first clock signal provided by the first clock module built in the processor.

[0096] Furthermore, an embodiment of the present application further provides an electronic device. Among them, the above-mentioned electronic device may be, for example, Figure 7 the server shown in Figure 8 or the terminal shown in Figure 7 And Figure 8 are both structural diagrams of electronic devices shown according to an exemplary embodiment, and the content in the figure cannot be considered as any limitation to the scope of use of the present application.

[0097] Figure 7 This is a schematic structural diagram of a server provided by an embodiment of the present application. The server may specifically include: at least one processor, at least one memory, a power supply, a communication interface, an input / output interface, and a communication bus. Among them, the memory is used to store a computer program, and the computer program is loaded and executed by the processor to implement the relevant steps in the clock processing disclosed in any of the foregoing embodiments.

[0098] In this embodiment, the power supply is used to provide working voltage for each hardware device on the server; the communication interface can create a data transmission channel between the server and external devices, and the communication protocol it follows is any communication protocol applicable to the technical solution of the present application, and no specific limitation is imposed on it here; the input / output interface is used to obtain external input data or output data to the outside, and the specific interface type can be selected according to specific application needs, and no specific limitation is made here.

[0099] In addition, as a carrier for resource storage, the memory can be a read-only memory, a random access memory, a magnetic disk, an optical disc, etc. The resources stored thereon include an operating system, computer programs, data, etc. The storage method can be temporary storage or permanent storage.

[0100] Among them, the operating system is used to manage and control each hardware device and computer program on the server to enable the processor to perform operations and processing on the data in the memory. It can be Windows Server, Netware, Unix, Linux, etc. In addition to the computer program that can be used to complete the clock processing method disclosed in any of the foregoing embodiments, the computer program can further include computer programs that can be used to complete other specific tasks. In addition to data such as update information of the application program, the data can also include data such as developer information of the application program.

[0101] Figure 8 The figure is a schematic structural diagram of a terminal provided by an embodiment of the present application. The terminal may specifically include, but is not limited to, a smart phone, a tablet computer, a notebook computer, a desktop computer, etc.

[0102] Generally, the terminal in this embodiment includes: a processor and a memory.

[0103] Among them, the processor may include one or more processing cores, such as a 4-core processor, an 8-core processor, etc. The processor can be implemented in at least one hardware form of DSP (Digital Signal Processing), FPGA (Field-Programmable Gate Array), and PLA (Programmable Logic Array). The processor can also include a main processor and a coprocessor. The main processor is a processor used to process data in the wake state, also known as the CPU (Central Processing Unit); the coprocessor is a low-power processor used to process data in the standby state. In some embodiments, the processor can be integrated with a GPU (Graphics Processing Unit), and the GPU is responsible for rendering and drawing the content to be displayed on the display screen. In some embodiments, the processor can further include an AI (Artificial Intelligence) processor, and the AI processor is used to process computing operations related to machine learning.

[0104] The memory may include one or more computer non-volatile storage media, which may be non-transitory. The memory may also include high-speed random access memory, as well as non-volatile memory, such as one or more disk storage devices and flash storage devices. In this embodiment, the memory is at least used to store the following computer programs. After the computer programs are loaded and executed by the processor, the relevant steps in the clock processing method executed by the terminal side disclosed in any of the foregoing embodiments can be implemented. In addition, the resources stored in the memory may also include an operating system and data, etc., and the storage method may be transient storage or permanent storage. Among them, the operating system may include Windows, Unix, Linux, etc. The data may include, but is not limited to, update information of application programs.

[0105] In some embodiments, the terminal may further include a display screen, an input / output interface, a communication interface, sensors, a power supply, and a communication bus.

[0106] Those skilled in the art can understand that Figure 8 the structure shown in does not constitute a limitation on the terminal, and it may include more or fewer components than shown in the figure.

[0107] Next, a non-volatile storage medium provided by an embodiment of the present application will be introduced. The non-volatile storage medium described below can be referred to each other with other embodiments described in this article.

[0108] A non-volatile storage medium is used to store a computer program. When the computer program is executed by a processor, the clock processing method disclosed in the foregoing embodiment is implemented. Among them, the non-volatile storage medium is a computer-readable non-volatile storage medium. As a carrier for storing resources, it may be a read-only memory, a random access memory, a disk, or an optical disc, etc. The resources stored thereon include an operating system, a computer program, and data, etc., and the storage method may be transient storage or permanent storage.

[0109] In this embodiment, when the processor executes the computer program stored in the non-volatile storage medium, the following steps can be specifically implemented: providing a first clock signal for the corresponding motherboard.

[0110] In this embodiment, when the processor executes the computer program stored in the non-volatile storage medium, the following steps can be specifically implemented: generating a second clock signal.

[0111] In this embodiment, when the processor executes the computer program stored in the non-volatile storage medium, the following steps may be specifically implemented: With reference to the second clock signal currently generated by the second clock module, perform clock recovery on the upstream data signal sent by the main board corresponding to the signal processing device to obtain a recovered clock signal, and with reference to the recovered clock signal, transmit the current upstream data signal to the destination acceleration card corresponding to the current upstream data signal; and / or, with reference to the recovered clock signal, transmit the received downstream data signal to the destination main board corresponding to the current downstream data signal.

[0112] In this embodiment, when the processor executes the computer program stored in the non-volatile storage medium, the following steps may be specifically implemented: Sample the received data signal.

[0113] In this embodiment, when the processor executes the computer program stored in the non-volatile storage medium, the following steps may be specifically implemented: Detect the rising edge or falling edge of the sampled data signal, compare the phase difference with the second clock signal currently generated by the second clock module, and output a phase error.

[0114] In this embodiment, when the processor executes the computer program stored in the non-volatile storage medium, the following steps may be specifically implemented: Perform low-pass filtering on the phase error.

[0115] In this embodiment, when the processor executes the computer program stored in the non-volatile storage medium, the following steps may be specifically implemented: Adjust the frequency and phase of the clock signal obtained by low-pass filtering to obtain a clock recovery signal, and use the clock recovery signal to sample the received data signal.

[0116] In this embodiment, when the processor executes the computer program stored in the non-volatile storage medium, the following steps may be specifically implemented: Receive the upstream data signal sent by any main board; Send the currently received downstream data signal to the destination main board corresponding to the current downstream data signal.

[0117] In this embodiment, when the processor executes the computer program stored in the non-volatile storage medium, the following steps may be specifically implemented: With reference to the second clock signal currently generated by the second clock module, perform clock recovery on the upstream data signal sent by the main board corresponding to the signal processing device to obtain a recovered clock signal.

[0118] In this embodiment, when the processor executes the computer program stored in the non-volatile storage medium, the following steps may be specifically implemented: Receive the downstream data signal sent by any acceleration card; Send the received upstream data signal to the destination acceleration card corresponding to the current upstream data signal.

[0119] In this embodiment, when the processor executes the computer program stored in the non-volatile storage medium, the following steps can be specifically implemented: With reference to the recovered clock signal, decode, frame parse, and / or demultiplex the upstream data signal sent by the upstream communication module.

[0120] In this embodiment, when the processor executes the computer program stored in the non-volatile storage medium, the following steps can be specifically implemented: With reference to the recovered clock signal, cache the upstream data signal after decoding, frame parsing, and / or demultiplexing.

[0121] In this embodiment, when the processor executes the computer program stored in the non-volatile storage medium, the following steps can be specifically implemented: Read the upstream data signal from the top-down cache unit; with reference to the second clock signal currently generated by the second clock module, multiplex, frame parse, and / or encode the read upstream data signal, and send the multiplexed, frame-parsed, and / or encoded upstream data signal to the downstream communication module.

[0122] In this embodiment, when the processor executes the computer program stored in the non-volatile storage medium, the following steps can be specifically implemented: Perform serial-to-parallel conversion on the upstream data signal sent by the upstream communication module, and transmit the serially-to-parallel converted upstream data signal to the top-down first parsing unit and the clock recovery module.

[0123] In this embodiment, when the processor executes the computer program stored in the non-volatile storage medium, the following steps can be specifically implemented: Perform parallel-to-serial conversion on the upstream data signal after multiplexing, frame parsing, and / or encoding, and transmit the parallel-to-serial converted upstream data signal to the downstream communication module.

[0124] In this embodiment, when the processor executes the computer program stored in the non-volatile storage medium, the following steps can be specifically implemented: With reference to the recovered clock signal, cache the received upstream data signal; with reference to the second clock signal currently generated by the second clock module, output the upstream data signal.

[0125] In this embodiment, when the processor executes the computer program stored in the non-volatile storage medium, the following steps can be specifically implemented: Cache the upstream data signal output by the random access storage area.

[0126] In this embodiment, when the processor executes the computer program stored in the non-volatile storage medium, the following steps can be specifically implemented: Perform compression processing and / or encryption processing on the upstream data signal output by the top-down first parsing unit.

[0127] In this embodiment, when the processor executes the computer program stored in the non-volatile storage medium, the following steps may be specifically implemented: With reference to the second clock signal currently generated by the second clock module, decode, frame parse, and / or demultiplex the downstream data signal sent by the downstream communication module.

[0128] In this embodiment, when the processor executes the computer program stored in the non-volatile storage medium, the following steps may be specifically implemented: With reference to the second clock signal currently generated by the second clock module, cache the downstream data signal after decoding, frame parsing, and / or demultiplexing.

[0129] In this embodiment, when the processor executes the computer program stored in the non-volatile storage medium, the following steps may be specifically implemented: Read the downstream data signal from the bottom-up cache unit, perform multiplexing, frame parsing, and / or encoding on the read downstream data signal, and send the multiplexed, frame-parsed, and / or encoded downstream data signal to the upstream communication module.

[0130] In this embodiment, when the processor executes the computer program stored in the non-volatile storage medium, the following steps may be specifically implemented: Perform serial-to-parallel conversion on the downstream data signal sent by the downstream communication module, and transmit the serially-to-parallel converted downstream data signal to the bottom-up first parsing unit.

[0131] In this embodiment, when the processor executes the computer program stored in the non-volatile storage medium, the following steps may be specifically implemented: Perform parallel-to-serial conversion on the downstream data signal after multiplexing, frame parsing, and / or encoding, and transmit the parallel-to-serial converted downstream data signal to the upstream communication module.

[0132] In this embodiment, when the processor executes the computer program stored in the non-volatile storage medium, the following steps may be specifically implemented: With reference to the second clock signal currently generated by the second clock module, cache the received downstream data signal; with reference to the recovered clock signal, output the downstream data signal.

[0133] In this embodiment, when the processor executes the computer program stored in the non-volatile storage medium, the following steps may be specifically implemented: Cache the downstream data signal output by the random access storage area.

[0134] In this embodiment, when the processor executes the computer program stored in the non-volatile storage medium, the following steps may be specifically implemented: Perform compression processing and / or encryption processing on the downstream data signal output by the bottom-up first parsing unit.

[0135] In this embodiment, when the processor executes the computer program stored in the non-volatile storage medium, the following steps may be specifically implemented: generating a corresponding upstream data signal by using the first clock signal provided by the first clock module built in the processor.

[0136] Next, a computer program product provided by an embodiment of the present application will be introduced. The computer program product described below may be referred to each other with other embodiments described herein.

[0137] A computer program product includes a computer program / instructions. When the computer program / instructions are executed by a processor, the steps of the clock processing method disclosed above are implemented.

[0138] Another embodiment of the present application further provides a computer program product, including a non-volatile computer-readable storage medium for storing a computer program. When the computer program is executed by a processor, the steps in any of the above embodiments are implemented.

[0139] The embodiments in this specification are described in a progressive manner. Each embodiment focuses on the differences from other embodiments. The same or similar parts among the embodiments may be referred to each other.

[0140] The steps of the method or algorithm described in combination with the embodiments disclosed in this article may be directly implemented by hardware, a software module executed by a processor, or a combination of both. The software module may be placed in a random access memory (RAM), memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, register, hard disk, removable disk, CD-ROM, or any other form of non-volatile storage medium well known in the technical field.

[0141] Specific examples are used in this article to elaborate on the principles and implementation manners of the present application. The descriptions of the above embodiments are only used to help understand the method and its core idea of the present application; at the same time, for those of ordinary skill in the art, according to the idea of the present application, there will be changes in the specific implementation manners and application scopes. In summary, the content of this specification should not be construed as a limitation to the present application.

Claims

1. A clock processing system, characterized in that, Including: At least two main boards, a switching device, and at least two target devices; Among them, a processor in each main board is built-in with a first clock module; the first clock module is used to provide a first clock signal for the corresponding main board; The switching device includes: a second clock module, a switching module, and signal processing devices respectively corresponding to and connected to each main board; The second clock module is respectively connected to the switching module, any signal processing device, and any two target devices; the second clock module is used to provide a second clock signal for any signal processing device, the switching module, and any two target devices; The switching module is respectively connected to any signal processing device and any target device; the switching module is used to connect the data path between any signal processing device and any target device.

2. The clock processing system according to claim 1, wherein Clock lines are connected between the second clock module and the switching module, any signal processing device, and any target device respectively.

3. The clock processing system according to claim 2, characterized in that, Between the second clock module and any signal processing device, the connection of the clock line is realized through a slot supporting the Peripheral Component Interconnect Express (PCIe) standard; between the second clock module and any target device, the connection of the clock line is realized through a slot supporting the Peripheral Component Interconnect Express (PCIe) standard.

4. The clock processing system according to claim 1, characterized in that Data lines are connected between the switching module and any signal processing device, and any two target devices respectively.

5. The clock processing system according to claim 4, wherein Between the switching module and any signal processing device, the connection of the data line is realized through a slot supporting the Peripheral Component Interconnect Express (PCIe) standard; between the switching module and any target device, the connection of the data line is realized through a slot supporting the Peripheral Component Interconnect Express (PCIe) standard.

6. The clock processing system according to claim 1, wherein The second clock module includes: a clock generator and a clock buffer; the clock generator is used to generate the second clock signal; the clock buffer is used to cache the second clock signal.

7. The clock processing system according to claim 1, wherein The signal processing device is used to: refer to the second clock signal currently generated by the second clock module, perform clock recovery on the upstream data signal sent by the main board corresponding to the signal processing device to obtain a recovered clock signal, and refer to the recovered clock signal to transmit the current upstream data signal to the target device corresponding to the current upstream data signal; and / or, refer to the recovered clock signal to transmit the received downstream data signal to the destination main board corresponding to the current downstream data signal.

8. The clock processing system according to claim 1, characterized in that Any main board includes: at least two processors; the at least two processors are all built-in with the first clock module.

9. The clock processing system according to claim 1, wherein Any main board is in the form of a card supporting the Peripheral Component Interconnect Express (PCIe) standard.

10. The clock processing system according to claim 1, wherein The signal processing device includes: an upstream communication module, a clock recovery module, and a downstream communication module; The upstream communication module is used to: receive the upstream data signal sent by any main board; send the currently received downstream data signal to the destination main board corresponding to the current downstream data signal; The clock recovery module is used to: refer to the second clock signal currently generated by the second clock module, perform clock recovery on the upstream data signal sent by the main board corresponding to the signal processing device to obtain a recovered clock signal; The downstream communication module is configured to: receive a downstream data signal sent by any target device; send the received upstream data signal to the target device corresponding to the current upstream data signal.

11. The clock processing system according to claim 10, wherein The signal processing device further includes: a top-down first parsing unit, a top-down caching unit, and a top-down second parsing unit; The top-down first parsing unit is configured to: decode, frame parse, and / or demultiplex the upstream data signal sent by the upstream communication module with reference to the recovered clock signal; The top-down caching unit is configured to: cache the upstream data signal after decoding, frame parsing, and / or demultiplexing with reference to the recovered clock signal; The top-down second parsing unit is configured to: read the upstream data signal from the top-down caching unit; multiplex, frame parse, and / or encode the read upstream data signal with reference to the second clock signal currently generated by the second clock module, and send the multiplexed, frame-parsed, and / or encoded upstream data signal to the downstream communication module; Correspondingly, the signal processing device further includes: a first serial-to-parallel conversion unit and a first parallel-to-serial conversion unit; The first serial-to-parallel conversion unit is configured to: perform serial-to-parallel conversion on the upstream data signal sent by the upstream communication module, and transmit the serially-to-parallel converted upstream data signal to the top-down first parsing unit and the clock recovery module; The first parallel-to-serial conversion unit is configured to: perform parallel-to-serial conversion on the multiplexed, frame-parsed, and / or encoded upstream data signal, and transmit the parallel-to-serial converted upstream data signal to the downstream communication module; Correspondingly, the top-down caching unit includes: a top-down random access storage area and a top-down double data rate synchronous dynamic random access storage area; The top-down random access storage area is configured to: cache the received upstream data signal with reference to the recovered clock signal; output the upstream data signal with reference to the second clock signal currently generated by the second clock module; The top-down double data rate synchronous dynamic random access storage area is configured to: cache the upstream data signal output by the random access storage area.

12. The clock processing system according to claim 11, wherein The signal processing device further includes: a top-down signal processing unit; The top-down signal processing unit is configured to: perform compression processing and / or encryption processing on the upstream data signal output by the top-down first parsing unit.

13. The clock processing system according to claim 10, wherein: The signal processing device further includes: a bottom-up first parsing unit, a bottom-up caching unit, and a bottom-up second parsing unit; The bottom-up first parsing unit is configured to: decode, frame parse, and / or demultiplex the downstream data signal sent by the downstream communication module with reference to the second clock signal currently generated by the second clock module; The bottom-up caching unit is configured to: cache the downstream data signal after decoding, frame parsing, and / or demultiplexing with reference to the second clock signal currently generated by the second clock module; The bottom-to-top second parsing unit is configured to: read the downstream data signal from the bottom-to-top buffer unit, multiplex, frame parse and / or encode the read downstream data signal, and send the multiplexed, frame parsed and / or encoded downstream data signal to the upstream communication module; Accordingly, the signal processing device further includes: a second serial-to-parallel conversion unit and a second parallel-to-serial conversion unit; The second serial-to-parallel conversion unit is used to perform serial-to-parallel conversion on the downstream data signal sent by the downstream communication module, and transmit the serial-to-parallel converted downstream data signal to the first bottom-to-top parsing unit; The second parallel-to-serial conversion unit is used to perform parallel-to-serial conversion on the downstream data signal after multiplexing, frame parsing and / or encoding, and transmit the downstream data signal after parallel-to-serial conversion to the upstream communication module; Accordingly, the bottom-to-top cache unit includes: a bottom-to-top random access memory area and a bottom-to-top double rate synchronous dynamic random access memory area; The bottom-to-top random access memory area is used to: buffer the received downstream data signal with reference to the second clock signal currently generated by the second clock module; and output the downstream data signal with reference to the recovered clock signal; The bottom-to-top double rate synchronous dynamic random access memory area is used to buffer the downstream data signal output by the random access memory area.

14. The clock processing system according to claim 13, wherein: The signal processing device further includes: a bottom-up signal processing unit; The bottom-to-top signal processing unit is used to perform compression processing and / or encryption processing on the downstream data signal output by the bottom-to-top first parsing unit.

15. The clock processing system according to any one of claims 10 to 14, characterized in that: The clock recovery module includes: a sampler, a detector, a filter and an oscillator; The sampler is used to: sample the received data signal; The detector is used to: detect the rising edge or falling edge of the sampled data signal, compare the phase difference with the second clock signal currently generated by the second clock module, and output a phase error; The filter is used to: perform low-pass filtering on the phase error; The oscillator is used to adjust the frequency and phase of the clock signal obtained by low-pass filtering to obtain the clock recovery signal, and use the clock recovery signal to sample the received data signal.

16. The clock processing system according to any one of claims 1 to 14, characterized in that, The signal processing device is an FPGA acceleration card, which includes: an upstream connector and a gold finger; the upstream connector is connected to the corresponding mainboard; the gold finger is connected to the corresponding target device through the switching module in the switching device.

17. A clock processing method, characterized in that: Applied to any signal processing device in a clock processing system, the clock processing system comprising: at least two main boards, a switching device, and at least two target devices; wherein, a first clock module is built in the processor of each main board; the first clock module is used to provide a first clock signal for the corresponding main board; the switching device comprises: a second clock module, a switching module, and signal processing devices respectively corresponding to and connected to each main board; the second clock module is respectively connected to the switching module, any signal processing device, and any two target devices; the second clock module is used to provide a second clock signal for any signal processing device, the switching module, and any two target devices; the switching module is respectively connected to any signal processing device and any target device; the switching module is used to connect the data path between any signal processing device and any target device; The clock processing method comprises: Referring to the second clock signal currently generated by the second clock module, performing clock recovery on the upstream data signal sent by the main board corresponding to the signal processing device to obtain a recovered clock signal; referring to the recovered clock signal, transmitting the current upstream data signal to the target device corresponding to the current upstream data signal; And / or, referring to the recovered clock signal, transmitting the received downstream data signal to the destination main board corresponding to the current downstream data signal.

18. An electronic device, characterized in that: Comprises: A memory for storing a computer program; A processor for executing the computer program to implement the method according to claim 17.

19. A non-volatile storage medium, characterized in that, For saving a computer program, wherein the computer program, when executed by a processor, implements the method according to claim 17.

20. A computer program product comprising a computer program / instructions, characterized in that, The computer program / instructions, when executed by a processor, implement the method according to claim 17.

Images