Servers and server systems

Abstract

The present application discloses a server and a server system, which relate to the field of communication technology. The server includes at least one first board, a switching group including a plurality of switching boards, a second board group including a plurality of second boards, and a mid-backplane. The switching board and any second board are orthogonal to each other and are pluggable. At least one first board is connected to at least part of the second board through the mid-backplane. In the related art, any two of the first board, the switching board, and the second board are connected through a backplane, and the wiring is very complicated. The orthogonal architecture of the switching board and the second board is used to achieve direct interconnection between the two, which increases the maximum allowable wiring length and solves the problem of complex wiring through the backplane connection in the related art. The wiring complexity of the first board and the second board through the mid-backplane is controllable. The connection through the mid-backplane can minimize the volume of the chassis in terms of space, thereby reducing the wiring complexity while also compressing the volume of the server chassis to the greatest extent.

Description

Technical Field

[0001] The present application relates to the field of communication technology, and in particular to a server and a server system. Background Art

[0002] With the continuous development of electronic technology, signal speeds continue to increase. In high-speed network equipment (such as data center switches and routers), the interconnection design of the switch boards is the core foundation for achieving high-bandwidth, low-latency communications.

[0003] In current switch board system designs, the interconnection between the switch board, the secondary board, and the primary board is typically achieved through a midplane. High-speed signals fan out from the switch board, pass through connectors, and connect to the vertical midplane. They then run through printed circuit board traces within the backplane and connect to the connector on the secondary board, ultimately interconnecting with the secondary board. The switch board and primary board are also interconnected through the midplane traces.

[0004] This type of interconnection has more backplane routing and more complex interconnection relationships, which increases the probability of problems. Once a functional problem occurs, it is very difficult to locate and maintain the problem later. In addition, since the switch board, the second board card and the first board card are all connected through the mid-backplane, the overall size of the server will be larger and the space occupancy rate will be larger. Summary of the Invention

[0005] The present application provides a server and a server system to at least solve the problem in the related art that the switch board, the second board and the first board are all connected through a mid-backplane, the wiring is complex and prone to errors, and the overall size of the server is large.

[0006] The present application provides a server, comprising: at least one first board; a switch board group, comprising multiple switch boards; a second board group, comprising multiple second boards; and a mid-backplane; wherein the switch board and any of the second boards are orthogonal to each other and are pluggable, and at least one of the first boards is connected to at least some of the second boards via the mid-backplane.

[0007] The present application also provides a server system, comprising: a server as described in any one of the preceding claims.

[0008] Through this application, the orthogonal architecture of the switch board and the second board enables direct interconnection between the two. The connection between the switch board and the second board no longer requires routing through the midplane, solving the problem of complex routing through the midplane in related technologies. Furthermore, this orthogonal interconnection method increases the maximum allowable routing length between the switch board and the second board. The routing complexity of the first board and the second board through the midplane is controllable, and connecting through the midplane can reduce the chassis volume in terms of space. Therefore, this solution not only reduces routing complexity but also compresses the size of the server chassis. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] In order to more clearly illustrate the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0010] Figure 1 A schematic diagram of the structure of a server provided in an embodiment of the present application;

[0011] Figure 2 A schematic diagram of a second board connected to a first board via a midplane provided in an embodiment of the present application;

[0012] Figure 3 A schematic diagram of the position of the connector of the second board and the first board on the midplane provided in an embodiment of the present application;

[0013] Figure 4 A schematic diagram of another embodiment of the present application providing a second board connected to a first board via a midplane;

[0014] Figure 5 A schematic diagram of a structure in which a first housing includes a plurality of second boards provided in an embodiment of the present application;

[0015] Figure 6 A schematic structural diagram of two second boards included in a first housing provided in an embodiment of the present application;

[0016] Figure 7 A schematic diagram of another structure provided by an embodiment of the present application, wherein a first housing includes a plurality of second boards;

[0017] Figure 8 A schematic diagram of a structure in which a second housing includes multiple exchange plates according to an embodiment of the present application;

[0018] Figure 9 A schematic diagram of another structure provided by an embodiment of the present application, wherein a second housing includes multiple exchange plates;

[0019] Figure 10 A cross-sectional view of a plane where a connector and a printed circuit board are in contact with each other, provided in an embodiment of the present application;

[0020] Figure 11 A schematic diagram of the layout design of a switch board device for an onboard solution provided in an embodiment of the present application;

[0021] Figure 12 A schematic diagram of wiring connections for a switch board provided in an embodiment of the present application;

[0022] Figure 13 A high-speed signal link diagram using only routing lines, built using simulation software provided in an embodiment of the present application;

[0023] Figure 14 The embodiment of this application provides Figure 13 Schematic diagram of simulation results;

[0024] Figure 15 A schematic diagram of the structure of a switch board provided in an embodiment of the present application;

[0025] Figure 16 A schematic diagram of a flying wire connection of a switch board provided in an embodiment of the present application;

[0026] Figure 17 A high-speed signal link diagram using flying wires and routing wires built using simulation software provided in an embodiment of the present application;

[0027] Figure 18 The embodiment of this application provides Figure 17 Schematic diagram of simulation results;

[0028] Figure 19 A fan-out diagram of a flying wire connector provided in an embodiment of the present application;

[0029] Figure 20 A schematic diagram of the layout of a switching board device for a flying lead connector solution provided in an embodiment of the present application;

[0030] Figure 21 A schematic diagram of the pin correspondence between a second board and a connector of a switch board provided in an embodiment of the present application;

[0031] Figure 22 A schematic diagram of the pin correspondence between another second board and a connector of a switch board provided in an embodiment of the present application;

[0032] Figure 23 A schematic diagram of a normal interconnection relationship between a switch board and a second board provided in an embodiment of the present application;

[0033] Figure 24A schematic diagram of the structure of another server chassis provided in an embodiment of the present application.

[0034] 10. Switch board; 11. Switch chip; 12. First connector; 13. First relay chip; 14. First flying lead connector; 20. Second board; 21. Processor; 22. Second connector; 30. First board; 40. Midplane; 50. Bus bar; 60. First liquid cooling plate; 70. Second liquid cooling plate. DETAILED DESCRIPTION

[0035] The following will be combined with the accompanying drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0036] It should be noted that, in the description of this application, the terms "comprises," "includes," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. The terms "first," "second," etc., in this application are used to distinguish similar objects, and are not used to describe a particular order or sequence.

[0037] In order to enable those skilled in the art to better understand the present application, the present application is further described in detail below with reference to the accompanying drawings and specific implementation methods.

[0038] The embodiment of the present application provides a server, such as Figure 1 As shown, it includes: at least one first board card; a switch board group, including multiple switch boards 10; a second board card group, including multiple second boards 20; a mid-backplane; wherein the switch board 10 and any second board card 20 are orthogonal to each other and pluggable, and at least one first board card is connected to at least some of the second board cards 20 through the mid-backplane.

[0039] The server described above can be used in various types of communication equipment, such as optical communication equipment, routers, and switches. Of course, the server can also be used in other types of communication equipment, without limitation. The first board is a control board that includes a controller (e.g., a CPU), and the second board is a device board that includes a processor (e.g., a GPU).

[0040] A switch board is a core component in network devices (such as switches and routers), responsible for routing and forwarding data packets. It typically contains one or more switch chips, which identify, process, and redirect data packets to their destination. The switch board also includes necessary peripheral circuits, such as connectors, buffers, and clock generators, to transmit signals from input ports to the switch chips, which then output the signals to the correct destination ports.

[0041] In the field of network equipment or servers, a secondary card typically refers to a card that carries terminal devices or loads. This includes, but is not limited to, storage devices, processor boards, and I / O interface boards. Secondary cards connect to the switch board through an orthogonal, pluggable connector. The switch board's Ethernet network enables a fully interconnected topology for all devices, enabling data or command exchange between secondary cards.

[0042] A primary board (PBC) is a device's mainboard used to monitor and control other hardware components. It typically includes a microprocessor, digital signal processor (DSP), memory, and other control circuitry. The PBC's role is to execute system management programs, monitor device status, and coordinate communications and operations between various components. For example, the central processing unit (CPU) is a common PBC in servers, providing remote management capabilities and health monitoring.

[0043] The midplane is a key component in large-scale network equipment (such as high-end routers and switches) or server systems, connecting multiple functional boards (such as the secondary and primary boards). It provides signal and power paths between boards, and its complex structure requires supporting a large number of high-speed signal lines. The midplane's design significantly impacts signal integrity and system performance, as it carries and routes a large number of high-speed, high-density signals. It also requires consideration of electromagnetic compatibility (EMC) and thermal management.

[0044] In the related art, the wiring between any two of the first board, switch board, and second board is complicated by the mid-backplane. However, the above-described server achieves direct interconnection between the switch board and the second board through an orthogonal architecture. The connection between the switch board and the second board no longer requires routing through the mid-backplane, thus resolving the problem of complex routing through the mid-backplane in the related art. Furthermore, this orthogonal interconnection method increases the maximum allowable routing length between the switch board and the second board. The routing complexity between the first board and the second board through the mid-backplane is manageable, and connecting through the mid-backplane can reduce the chassis volume. Therefore, this solution not only reduces routing complexity but also compresses the server chassis.

[0045] Through the orthogonal architecture of the switch board and the second board, the 112G high-speed link of the two nodes is directly interconnected, the design of the middle backplane is eliminated, the maximum allowable routing length of the printed circuit board of the switch board and the second board is increased, and the high-speed link design is simplified. The above-mentioned cross-interconnection architecture can eliminate the optical backplane in the related technology, reduce the interconnection space between the switch board and the second board, which is conducive to making full use of the space in the sub-rack and realizing the minimized design of the interconnection depth, increasing the available space between the switch board and the second board, so that the switch board and the second board can integrate more functions. In addition, since the insertion loss of the optical cross-interconnection architecture is related to the number of nodes, the optical cross-interconnection architecture in the embodiment of the present application eliminates the optical backplane, and the switch board and the second board can be directly connected, thereby reducing the number of nodes and reducing the insertion loss of the optical cross-interconnection architecture in the embodiment of the present application. For example, the insertion loss can be reduced to about 1dB.

[0046] The second board includes a processor, the first board includes a controller, the switching board includes a switching chip, the processor on the second board and the controller on at least one first board are connected via an interface communication protocol, the switching chip on the switching board and the processor on at least one second board are connected via an Ethernet protocol, and any two processors are connected via an Ethernet protocol.

[0047] That is, the processor on the second board communicates with the controller on the connected first board through the Peripheral Component Interconnect Express protocol, and the switching chip on the switch board communicates with the processor on the connected second board through the Ethernet protocol to form a fully interconnected topology. The fully interconnected topology is that any two processors communicate through the Ethernet protocol.

[0048] The controller may be a central processing unit (CPU), and the processor may be a graphics processing unit (GPU). In the above embodiment, the first board and the second board are connected via a backplane, so that the CPU on the first board and the GPU on the second board are communicated via the Peripheral Component Interconnect Express (PCIe) protocol, and the switching chip on the switching board is connected to the OAM module in the second board via the Ethernet protocol, so that the GPUs form a fully interconnected topology, realizing interconnected networking between all GPUs.

[0049] The fully interconnected topology design ensures the shortest communication path between any two processors, thereby reducing data transmission latency. In a fully interconnected architecture, there is no single bottleneck path, which means that data can be transmitted in multiple directions simultaneously, providing higher overall throughput. This is particularly important for GPU clusters that require large amounts of data exchange, as it can accelerate data processing and improve the performance of parallel computing. Since any two GPUs can communicate directly, resource scheduling becomes more flexible. In some deep learning scenarios, GPU resources can be dynamically allocated according to the needs of the algorithm, improving resource utilization efficiency. Direct communication between all GPUs allows parallel processing units to share data and perform collaborative tasks more efficiently, which is particularly beneficial for distributed computing and large-scale parallel computing tasks.

[0050] Alternatively, if the switch board and secondary line cards are fully interconnected in hardware design, software can be used to control the switch board to connect only to a subset of secondary line cards, while disconnecting the remaining subset. This software is controlled by the Basic Input / Output System (BIOS). Each switch board has a Baseboard Management (BMC) module responsible for control, which determines which secondary line cards are interconnected.

[0051] In some embodiments, such as Figure 2 , the first board 30 is parallel to the extension direction of the second board group, at least one first board 30 is parallel to the second board group along the first direction ( Figure 2 The first board 30 and the second board 20 are arranged in sequence in the direction a in the middle, and are located on the same side of the switch board group.

[0052] Placing the first and second boards on the same side of the switch board assembly further saves space and simplifies the wiring on the midplane. If the first and second boards were on different sides of the switch board assembly, not only would they occupy more space, but since the first and second boards would need to be connected via the midplane, the size of the midplane would also increase accordingly, and the wiring on the midplane would also be longer, not only occupying chassis space but also affecting the integrity of signal transmission. Therefore, the above embodiment places the first and second boards on the same side of the switch board assembly, which not only saves chassis space but also reduces the length of the wiring on the midplane, resulting in higher signal integrity.

[0053] And, as Figure 2 As shown, the orthographic projections of the mid-back plate 40 and the switch plate 10 on the preset plane partially overlap, and the preset plane is the extension direction of the switch plate (such as Figure 2 A plane parallel to the a direction in the middle.

[0054] Placing the midplane and switch board on the same side of the second card allows for more efficient use of space, further saving space. This structure eliminates the need for additional space, allowing the midplane to be placed directly within the original cubic structure without increasing the overall size of the chassis.

[0055] Further, such as Figure 2 As shown, the server further includes a bus bar 50, which is connected to the cooling device (not shown) on each second board 20. The mid-backplane 40 is located between the bus bar 50 and the switch board 10. The orthographic projections of the mid-backplane 40, the bus bar 50, and the switch board 10 on the preset plane partially overlap. The preset plane is parallel to the extension direction of the switch board (e.g., Figure 2 A plane parallel to the a direction in the middle.

[0056] The cooling device is a device on the second card that cools heat-generating components (such as GPUs). This device lowers the temperature of the heat-generating components through the flow of coolant. The busbar, on the other hand, collects the coolant from multiple second cards, allowing the coolant to flow through the busbar, cooling the coolant and circulating it around the heat-generating components on the second cards. Furthermore, placing the midplane in the gap between the busbar and the switch board optimizes space utilization without increasing the overall size of the chassis.

[0057] In some embodiments, such as Figure 2 As shown, all the first boards 30 are located on the first side or the second side of the second board group; or, a portion of the first boards 30 are located on the first side of the second board group, and another portion of the first boards 30 are located on the second side of the second board group, and the first side and the second side are opposite sides.

[0058] Among them, such as Figure 2 As shown, the server further includes a plurality of first shells ( Figure 2 (not shown), a first housing includes at least one second board 20.

[0059] Since the second boards need to be orthogonal to the switch board via connectors, arranging all the second boards closely together (i.e., forming a second board group) allows for a more compact arrangement of the connectors on the second boards, thus saving space for the connectors on the second boards. If a first board is installed between multiple second boards and is not connected to the switch board, the area on the switch board where the first board resides will need to be left empty. This will increase the spacing between the two connectors, making the second boards longer, which will take up unnecessary space and reduce space utilization. Therefore, the above embodiment, placing the second boards in the center and the first boards to the side, is the most space-efficient arrangement.

[0060] In some embodiments, such as Figure 2As shown, the number of first boards 30 located on the first side of the second board group is equal to the number of first boards 30 located on the second side of the second board group.

[0061] If there are multiple first boards, splitting the board into two parts and placing them on either side of the second board is the most space-efficient and cabling-efficient arrangement. Splitting the first board into two parts and placing them on either side of the second board allows the first boards on either side to be connected to their more adjacent second boards. This significantly reduces the length of the wiring on the midplane, simplifies the wiring on the midplane, and reduces interference between the wiring.

[0062] For example, if the first board has four cards and the second board has eight cards, the positions of the connectors of the second board and the first board on the midplane are as follows: Figure 3 As shown, the first first board is connected to the first second board and the second second board; the second first board is connected to the third second board and the fourth second board; the third first board is connected to the fifth second board and the sixth second board; and the fourth first board is connected to the seventh second board and the eighth second board. This arrangement of first boards on both sides, with the first boards controlling the closer second boards, allows for tighter and more organized wiring on the midplane, increasing wiring density, reducing wiring complexity, and minimizing errors. Furthermore, the wiring lengths on the midplane are more balanced, eliminating the situation where some wiring is very short and some is very long. Each first board is connected to two second boards. Evenly placing the first boards on both sides ensures symmetrical wiring distribution on the midplane's PCB (printed circuit board) and allows the second boards to be clustered together for orthogonal insertion into the switch board.

[0063] Figure 3 In the embodiment shown in FIG, each first board has a connector interconnected with the midplane. The connector can be divided into two pin sections through the wiring on the midplane, namely, one section connecting to a second board and the other section connecting to another second board. In some embodiments, the first board can also be provided with two connectors, with each first board having two connectors interconnected with the midplane, and each second board having one connector interconnected with the midplane.

[0064] In addition to the structure of the above embodiment, there is another positional relationship between the second board and the first board, such as Figure 4 As shown, the switch board 10 is located on a first side of the second board 20 , and the first board 30 is located on a second side of the second board 20 , where the first side and the second side are opposite sides.

[0065] like Figure 4 As shown, a first housing ( Figure 4The first board 30 in the first housing is connected to all the second boards 20 in the first housing through the mid-backboard 40.

[0066] In the above embodiment, the first board and the second board controlled by the first board are integrated into a first housing, and then the first housing as a whole is plugged into the switch board.

[0067] A first housing can contain one first board and one or more second boards, or multiple first boards and multiple second boards—that is, one first board can be connected to multiple second boards, or one first board can be connected to only one second board. The CPU in the first board coordinates and allocates tasks to the GPUs in the second boards within the same first housing. The number of first and second boards in a first housing depends on their respective performance. The CPU communicates with the GPUs via the PCI Express (PCIe) bus. Therefore, the number of PCIe slots on the motherboard directly determines the number of GPUs the CPU can directly control. However, in some high-end servers or workstations, bridge chips or PCIe switches can be used to increase the number of GPU connections. CPU performance (such as the number of cores, cache size, and bus bandwidth) also affects the number of GPUs it can effectively control. A more powerful CPU can manage more concurrent tasks, thus supporting the simultaneous processing of more GPUs. For example, if two second boards are installed in a first housing, and the CPU has good performance, only one first board is needed to control both second boards. However, if the CPU has poor performance, two first boards are needed in the first housing to control each second board. Connecting one first board to multiple second boards via a backplane allows for more flexible cabling.

[0068] Within the same primary housing, communication between the CPU and GPU can be achieved over shorter distances, significantly reducing data transmission latency and improving system response time and processing speed. The CPU and GPU integrated into a single primary housing can communicate directly via high-speed connections (such as PCIe Gen4 or Gen5), providing higher data bandwidth. Integrating the CPU and GPU into a single primary housing simplifies system architecture and wiring, reducing the number of cables and connectors required, thereby reducing system complexity and improving reliability and ease of maintenance.

[0069] In some embodiments, as Figure 5 As shown, the plurality of second boards 20 are located in the same first housing, and the plurality of second boards 20 in the same first housing are arranged along the first direction (eg Figure 2There is a first liquid cooling plate ( Figure 5 (not shown), the first direction is the same as the arrangement direction of the connectors of one switching board.

[0070] Placing multiple second boards in a single first housing can increase the overall system's device density and reduce space usage. While placing multiple second boards in separate first housings would take up more space, placing multiple second boards in a single first housing reduces the number of first housings, lowering costs while further conserving space and increasing device density.

[0071] Figure 5 This is an example diagram of a first housing including two second boards, such as Figure 5 As shown, the same first housing includes two second boards 20, the processor of one second board 20 is a first processor, the processor of the other second board 20 is a second processor, and the first liquid cooling plate is located between the first processor and the second processor.

[0072] Because two second boards 20 are housed in a single first housing, their proximity within the housing results in poor heat dissipation. Therefore, a first liquid cooling plate is added between the two second boards 20 to dissipate heat simultaneously. Furthermore, the two second boards 20 are positioned opposite each other within the same first housing, with the GPUs mounted on each board on one side in contact with the first liquid cooling plate, effectively cooling the heat-generating GPU.

[0073] Figure 6 is a cross-sectional view of two second boards clamped in a first housing, as shown in FIG. Figure 6 As shown, a first second board and a second second board in a first shell are arranged relative to each other, and a first liquid cooling plate 60 is arranged in the middle. In the figure, J1, J2, J3, J4, J5, and J6 are connectors on the second board, which are used to connect orthogonally with the switch board. The first liquid cooling plate 60 is arranged between the two second boards to dissipate heat for the GPU, power module, logic management control chip heat source, etc. on the second board. There are 6 orthogonal high-density connectors on each second board from left to right. As can be seen from the figure, the two second boards are placed oppositely and oppositely. Since the second board needs to be connected orthogonally with the switch board, the connectors of the two second boards need to be on the same side, and in order to achieve better heat dissipation, the sides of the two second boards with GPUs installed need to face the liquid cooling plate, so the following design is used. Figure 6 If there are multiple second boards in a first housing, a liquid cooling plate is installed between two adjacent second boards.

[0074] If a first housing includes multiple second boards, there may be other installation positions, such as Figure 7 As shown, the plurality of second boards 20 are located in the same first housing, and the plurality of second boards 20 in the same first housing are arranged along the second direction ( Figure 7 The second direction is the same as the arrangement direction of the connectors of a second board.

[0075] This can be applied to some scenarios where the second board does not need to be connected to all switch boards. In large systems, if each GPU is interconnected with all switch boards, the communication network will become extremely complex, resulting in increased difficulty in management and maintenance, as well as increased communication delays and potential bit error rates. The installation method of the second board can reduce the interconnection range, simplify the architecture of the communication network, reduce the complexity of the communication link, thereby reducing latency and improving communication reliability. The fully interconnected architecture requires a large number of high-speed connectors, cables, and complex backplane designs, which will increase the hardware cost of the equipment. In the case of meeting application requirements, adopt Figure 7 In this structure, part of the second board is only interconnected with part of the switch board, which can significantly reduce the required high-speed interconnect components and reduce hardware costs. Figure 7 The installation structure and limiting the interconnection range of the GPU can avoid unnecessary data transmission and reduce communication overhead, thereby improving the overall efficiency and performance of the system.

[0076] Based on the structure of the second board in the first housing in the above embodiment, the switch board can also be installed in a variety of ways, such as Figure 8 As shown, the server includes a plurality of second shells, one second shell includes a plurality of switch boards 10, and the plurality of switch boards 10 are arranged along the second direction ( Figure 8 The second liquid cooling plate 70 is provided between two adjacent exchange plates 10, and the arrangement order of the connectors of the two adjacent exchange plates 10 is opposite.

[0077] Figure 8This diagram illustrates an example of a second housing containing two exchange boards 10. Since two exchange boards 10 are located in the same second housing, their proximity to each other can lead to poor heat dissipation. Therefore, a second liquid cooling plate 70 is added between the two exchange boards 10 to dissipate heat for both switches simultaneously. Furthermore, the two exchange boards 10 within the same second housing are positioned relative to each other, with the sides of the exchange chips mounted on each exchange board 10 in contact with the second liquid cooling plate 70. This improves cooling of the heat-generating exchange chips. Furthermore, placing the two exchange boards 10 within a single second housing increases the overall system component density and reduces space usage. If the two exchange boards 10 were placed in two separate second housings, each would need to be located in each second housing, taking up more space. However, placing the two exchange boards 10 within a single second housing saves space in one second housing, further saving space and increasing component density.

[0078] If a second housing includes multiple exchange boards 10, other installation positions are possible, such as Figure 9 As shown, a second housing includes a plurality of exchange plates 10, and the plurality of exchange plates 10 are arranged along a first direction ( Figure 9 a direction) are set parallel to each other.

[0079] This can be applied to some scenarios where the switch board does not need to be connected to all second boards. In a large system, if each GPU is interconnected with all switch boards, the communication network will become extremely complex, resulting in increased difficulty in management and maintenance, as well as increased communication delays and potential bit error rates. The installation method of the switch board can reduce the interconnection range, simplify the architecture of the communication network, reduce the complexity of the communication link, thereby reducing delays and improving communication reliability. The fully interconnected architecture requires a large number of high-speed connectors, cables and complex backplane designs, which will increase the hardware cost of the equipment. In the case of meeting application requirements, adopt Figure 9 In this structure, a part of the switch board is only connected to a part of the second board, which can significantly reduce the required high-speed interconnect components and reduce hardware costs. Figure 9 The installation structure avoids unnecessary data transmission and reduces communication overhead, thereby improving the overall efficiency and performance of the system.

[0080] In some embodiments, the switch board has a first connector, and the number of rows of pins of the first connector is greater than the number of layers of wiring in the switch board.

[0081] Generally, one pin of the first connector leads to a pair of differential signals. If the first connector has M rows, then one column of pins of the first connector leads to M pairs of differential signals, and each pair of differential signals is distributed on a different layer of the switch board.

[0082] In the above embodiment, the number of rows of pins of the first connector is greater than the number of layers of wiring in the switch board, which greatly reduces the number of layers of wiring in the switch board, reduces the thickness of the switch board, further saves space, and reduces the size of the chassis.

[0083] The number of pin rows on the first connector exceeds the number of routing layers on the switch board, meaning more signal fanout can be achieved on fewer PCB layers. This increases signal transmission density, enabling the switch board to handle larger data flows within a limited physical space, which is crucial for high-bandwidth communications. When the number of pin rows on the first connector exceeds the number of routing layers, signals can be more efficiently distributed across fewer layers, reducing signal routing between layers, thereby reducing signal insertion loss and improving signal quality.

[0084] In some embodiments, the number of rows of pins of the first connector is an integer multiple of the number of layers of wiring in the switch board.

[0085] Setting the number of pin rows on the first connector to an integer multiple of the number of routing layers ensures even signal distribution across each layer, helping to optimize signal layout, reduce mutual interference between signal lines, and improve signal integrity. This integer multiple of pin rows enables efficient signal fan-out, meeting the needs of high-density signal transmission even within the limited area of ​​the switch board, thereby improving overall communication bandwidth and data processing capabilities. This design allows for more organized and simplified signal routing on the PCB, reducing complex corners and cross-layer routing, helping to reduce signal latency and loss, and improving signal quality.

[0086] Specifically, the switching board has a first connector, and there is a gap between any two adjacent rows of solder points on the switching board that are soldered to the first connector. There is a trace in at least one gap, one end of the trace is connected to the pin of the first connector, and the other end of the trace is connected to the switching chip on the switching board.

[0087] The second board further has a second connector, and the first connector and the second connector are the same connector. Figure 10 is a top view of a printed circuit board, namely Figure 10 The cross-section of the plane where the connector and the printed circuit board are in contact is shown in FIG. Figure 10 As shown, the switch board and the second board are connected via a connector. Figure 10 A is the solder joint of the first connector on the switch board, and B1, B2, B3, and B4 are the traces on the switch board. For the second board, Figure 10 A is a soldering point on the second board connected to the second connector, and B1, B2, B3, and B4 are traces on the second board.

[0088] The connector is an orthogonal high-density connector. For the signal fan-out routing at the orthogonal high-density connector, 16 pairs of differential signals are output per layer, requiring a total of four signal layers, with two rows of signals distributed on each layer. Compared to traditional high-density connectors that can only output one pair of differential lines per column per layer, the pins of this high-density connector are distributed in two parts, with the empty area in the middle allowing two pairs of differential lines per column per layer. This reduces the routing layer occupied by the connector output by half, which can greatly improve the wiring density. Figure 10 Signal lines of the same color are on one layer, and signal lines of different colors are represented by different grayscales.

[0089] For example, if the second board is Figure 6 In the structure (i.e. one first housing includes two second boards), if two second boards are to be installed in one first housing, the second boards need to be designed to be as thin as possible. Figure 10 The pin layout and solder joint layout of the orthogonal high-density connector shown in the figure will reduce the number of wiring layers on the circuit board, thereby reducing the thickness of the circuit board, that is, reducing the thickness of the second board. Figure 8 When the structure in (i.e. one second shell includes two exchange plates), it can also be used Figure 10 The pin layout of the orthogonal high-density connector shown is used to reduce the thickness of the switch board.

[0090] Preferably, the switch board has N rows of solder joints, with traces running between the N / 2th row and the N / 2+1th row. That is, the two sections of solder joints on the switch board are evenly distributed. The pins of the first connector are arranged identically to the solder joints on the switch board. Alternatively, the solder joints of the second card and the pins of the second connector can also be as shown above.

[0091] This evenly spaced solder point distribution on the board, with a clear center area, allows for two pairs of differential traces per layer, rather than the traditional single pair. This directly reduces the number of PCB layers required, thereby reducing board complexity and cost. Furthermore, fewer trace layers reduces potential routing errors and improves production yield. A pin layout with evenly spaced pins and a clear center area can mitigate electromagnetic interference and improve the system's electromagnetic compatibility by properly arranging the signal and ground lines.

[0092] Differential signaling is a commonly used signal transmission method, particularly in high-speed data transmission and precision electronic communications. A differential signal pair consists of two traces (or pins), transmitting positive and negative signals, respectively. This signal transmission method effectively reduces electromagnetic interference (EMI) and improves signal integrity and noise immunity. Equal pin spacing helps ensure symmetry within the differential pair. In connector design, the trace lengths, characteristic impedances, and routing paths of the differential pairs should be as consistent as possible to ensure signal integrity and minimize signal distortion. A differential signal pair requires close proximity to maintain differential signal characteristics, but this also makes it susceptible to interference from adjacent signal traces. A pin layout with equal spacing between the upper and lower pairs effectively isolates adjacent differential pairs by creating a free space between them, reducing crosstalk and improving signal quality.

[0093] Furthermore, evenly distributed pinouts double the number of differential pair routing without increasing the number of connector layers. This not only reduces the number of required PCB layers but also optimizes routing paths, improving routing density and board space utilization.

[0094] In some embodiments, the connector of the switch board is a first connector, the connector of the second board is a second connector, the switch board also includes a switch chip, the second board also includes a processor, the switch chip is electrically connected to the first connector through routing, or the switch chip is first connected to the first flying wire connector through routing and then electrically connected to the first connector through flying wire, the processor is electrically connected to the second connector through routing, or the processor is first connected to the second flying wire connector through routing and then electrically connected to the second connector through flying wire, wherein the channel operation margin of the high-speed signal transmitted from the switch chip to the processor is greater than the preset margin, and the preset margin is the minimum margin when the integrity of the high-speed signal transmitted from the switch chip to the processor is greater than or equal to the preset integrity.

[0095] The first connector (or second connector) can be any type of connector, such as an MT fiber optic connector, a multi-core multi-channel pluggable (MPO) fiber optic connector, or an LC fiber optic connector. In practical applications, the first connector (or second connector) can be fastened to a printed circuit board (PCB) or optical assembly of the switch board (or second card) using screws. Alternatively, other methods can be used to secure the first connector or second connector, which are not limited herein.

[0096] Channel Operating Margin (COM) is a metric used to evaluate signal link performance in high-speed digital signal transmission. It reflects the reliability and stability of signal transmission within the link, particularly in terms of signal integrity. The definition of COM is based on the transmission characteristics of the signal link, which typically include factors such as signal attenuation, reflections, crosstalk, and noise. It represents the difference between the actual signal performance within the link and the minimum performance requirement, or the margin of error allowed while maintaining signal integrity. A higher COM value indicates more reliable signal link performance, greater signal transmission stability, and greater tolerance to various environmental variations and signal interference. When designing high-speed signal links, engineers typically set a minimum COM value to ensure that the link can meet performance requirements under the most challenging conditions. When the COM value falls below this threshold, the link's performance may become unreliable, or even transmission errors may occur.

[0097] By controlling the trace lengths between the switch board and the secondary card, signal consumption can be reduced, ensuring that the channel operating margin of high-speed signals exceeds the preset margin, and thus guaranteeing signal integrity. If the trace length cannot guarantee that the channel operating margin of the signal exceeds the preset margin, consider adding flying lead connectors and using flying leads to transmit the signal.

[0098] By controlling signal path length, using flying lead connectors, and optimizing routing design, signal attenuation and distortion can be reduced, thereby improving signal integrity. Improved signal integrity means fewer bit errors and higher data transmission quality, which is crucial for high-speed data transmission applications. Using flying lead connectors can reduce signal trace length on the PCB, thereby reducing signal transmission latency. In scenarios such as high-performance computing and network communications, reducing latency can significantly improve system response speed and processing efficiency. Optimizing signal transmission paths helps reduce energy loss during signal transmission, thereby reducing overall system power consumption. This is particularly important in scenarios such as data centers and cloud computing that require high performance and low power consumption. Ensuring that the channel operating margin for high-speed signal transmission exceeds the preset margin means that the system has greater fault tolerance in the face of various interference and noise, improving system stability and reliability. By using first and second flying lead connectors, system designers can flexibly select signal transmission paths based on actual needs, allowing for either direct connection or flying lead connections, increasing the flexibility and scalability of system architecture. Reducing trace lengths and optimizing signal paths helps simplify board design, reduce PCB layer complexity, and reduce potential routing conflicts, making the design process more efficient while reducing production costs.

[0099] Figure 11The schematic diagram of the layout design of the onboard solution switching board components is as follows: Figure 11 As shown, the switch board 10 includes a first connector 12, a switch chip 11, a power access connector, a Serial Gigabit Media Independent Interface network management signal input connector (Serial Gigabit Media Independent Interface, referred to as SGMII network management signal input connector), a chip power supply and a baseboard management controller (Baseboard Management Controller, referred to as BMC management module) and a complex programmable logic device (Complex Programmable Logic Device, referred to as CPLD). The orthogonal high-density connectors (first connectors) of the switch board all adopt an onboard solution. One switch chip corresponds to 8 orthogonal high-density connectors, each of which can transmit 2 groups of X16 Lane 112G high-speed signals. The signal connection between the switch chip and the orthogonal high-density connector is achieved through PCB copper traces. The signal path is shown in the attached figure. Figure 11 Indicated by the middle line.

[0100] The SGMII signal input connector interconnects with the network management board within the integrated device, providing out-of-band management network signals. The power input connector provides 12V power to the entire board. The CPLD is used for hardware control, management, and coordination of the SW chip, monitoring the status of the switch chip and controlling its power-on and power-off sequencing. The BMC management module provides intra-node management signals and status detection, primarily for remote access management and maintenance, and records system logs for analysis by engineering personnel.

[0101] In some embodiments, such as Figure 12 As shown, the switching board 10 has a switching chip 11 and a first connector 12, the second board 20 includes a processor 21 and a second connector 22, the switching chip 11 is connected to the first connector 12 through a first line, the processor 21 is connected to the second connector 22 through a second line, the sum of the length of the first line and the length of the second line is less than or equal to a first preset length, the first preset length is the minimum line length that makes the channel operation margin of the high-speed signal transmitted from the switching chip 11 to the processor 21 greater than the preset margin, wherein the preset margin is the minimum margin when the integrity of the high-speed signal transmitted from the switching chip 11 to the processor 21 is greater than or equal to the preset integrity.

[0102] By controlling the length of the first trace between the switch chip and the first connector, and the length of the second trace between the processor and the second connector, the combined length of these two traces is ensured to be less than or equal to a preset maximum length (the first preset length). Limiting the combined length of these traces reduces signal attenuation and distortion during transmission, thereby ensuring signal integrity. Longer traces increase signal insertion loss, resulting in a smaller eye diagram, which affects signal intelligibility and signal-to-noise ratio. By controlling trace length, signal margin at the receiver is maintained, ensuring signal stability and reliability. Channel operating margin (COM) is a key metric for measuring signal link performance, reflecting the margin required to maintain a minimum receive level. By ensuring that the combined length of the traces does not exceed the first preset length, the COM of high-speed signals transmitted from the switch chip to the processor is greater than the preset margin. This ensures stable signal link operation under various operating conditions and meets design and specification requirements. Trace length directly affects signal transmission latency. Shorter trace lengths help reduce signal transmission time, which is crucial for applications requiring low latency, such as high-performance computing and real-time data processing. Signal transmission along traces involves a certain amount of energy loss, and longer traces increase power consumption. Controlling trace length can reduce energy loss during signal transmission, helping to lower overall system power consumption. Limiting trace length helps simplify PCB routing design, reduces the complexity of inter-layer routing, and improves design efficiency and manufacturability. Reducing trace length can reduce signal link failure rates and improve overall system reliability. Shorter traces are less susceptible to external interference and crosstalk within the PCB, ensuring stable signal transmission. Shorter traces also help reduce electromagnetic radiation and lower internal and external electromagnetic interference, which is crucial for complying with electromagnetic compatibility standards and reducing interference between systems.

[0103] For 112G high-speed signals, the interconnection scheme design of the signal link is as shown in the attached Figure 12 As shown, the signal is sent from the switch chip 11. It travels along a 10-inch PCB trace on the switch board 10 and enters the pins of the first connector 12 located on the edge of the switch board. It then passes through two high-density connectors (first connector 12 and second connector 22) that are orthogonally connected and then enter a 19-inch PCB trace on the second board 20, ultimately reaching the processor 21.

[0104] For the above 112G high-speed signal, a link is built in the simulation software to perform COM simulation. The simulation link is as shown in the attached figure. Figure 13 The simulation results are shown in the attached Figure 14The simulation results show that when the trace length on the switch board is 10 inches and the trace length on the second card is 19 inches, the channel operating margin is 3.388 dB, which is close to the critical value of 3 dB. Therefore, the simulation experiment shows that a trace length of 10 inches on the switch board and a trace length of 19 inches on the second card are the maximum trace lengths. Therefore, the first preset length can be set to 29 inches, with a preset margin of 3 dB.

[0105] In some embodiments, such as Figure 15 As shown, the switching board 10 has a switching chip 11, a first connector 12 and a first relay chip 13. The switching chip 11 is connected to the first relay chip 13 through a first sub-route, and the first relay chip 13 is connected to the first connector 12 through a second sub-route. The first relay chip 13 is used to enhance the signal strength of the high-speed signal, wherein the sum of the length of the first sub-route and the length of the second sub-route is greater than the second preset length, and the first preset length is greater than the second preset length.

[0106] When the high-speed signal is transmitted from the switching chip to the connector, if the total routing length of the signal link exceeds a certain limit (the first preset length), so that the channel operating margin (COM) of the signal cannot meet the preset margin requirements, it is particularly important to introduce the first relay chip as a signal enhancement link. When the high-speed signal is transmitted from the switching chip to the connector, if the total routing length of the signal link exceeds a certain limit (the first preset length), so that the channel operating margin (COM) of the signal cannot meet the preset margin requirements, it is particularly important to introduce the first relay chip as a signal enhancement link. By using the relay chip, signal distortion and eye closure can be reduced, and the control accuracy of the signal rise time and fall time can be improved, thereby improving signal integrity and ensuring high-quality transmission of the signal under high-speed transmission conditions. The use of the relay chip overcomes the signal attenuation problem caused by the routing length limit (the second preset length), allowing the signal to maintain good performance over a longer distance, providing greater flexibility and a wider range of applications for system design. Figure 15 In the illustrated embodiment, the sum of the lengths of the first and second sub-routes is greater than a second preset length. This means that even if the total route length exceeds the limit when a repeater chip is not used, the signal can still maintain the required COM. This is because the repeater chip compensates for signal attenuation, allowing the link to meet signal integrity requirements over longer distances. The repeater chip can retime the signal, reduce delay fluctuations, and ensure signal transmission stability under different temperature and voltage conditions, which is particularly important for applications that require precise timing control. Through signal enhancement and delay adjustment, the repeater chip improves the robustness of the system, reduces the impact of the signal link's sensitivity to environmental conditions, and maintains stable performance even in harsh operating environments.

[0107] Simulation results show that when the PCB trace on the switch board exceeds 10 inches, or when the PCB trace on the second card exceeds 19 inches, the channel's operating margin is insufficient, leading to the risk of link signal transmission errors. In this case, a first relay chip is required between the switch chip and the first connector to ensure high-speed signal integrity. Therefore, the second preset length is 10 inches.

[0108] In some embodiments, the second board also includes a second relay chip, the processor is connected to the second relay chip through a third sub-route, the second relay chip is connected to the second connector through a fourth sub-route, and the second relay chip is used to enhance the signal strength of the high-speed signal, wherein the sum of the length of the third sub-route and the length of the fourth sub-route is greater than the third preset length, and the first preset length is greater than the third preset length.

[0109] In the above embodiment, the second card incorporates a second relay chip, which connects to the processor via a third sub-trace and then to the second connector via a fourth sub-trace. This design adds signal amplification and processing to the signal transmission path. This is especially true when the combined lengths of the third and fourth sub-trace exceed the third predetermined length, while the first predetermined length is greater than the third predetermined length. This means that the direct path from the switch chip to the first connector (the first predetermined length) can be longer. However, on the second card, the signal requires additional signal processing after traveling the longer distance (the third predetermined length).

[0110] The primary function of the second repeater chip is to enhance signal strength. In high-speed signal transmission, signals gradually attenuate over increasing transmission distance. The repeater chip compensates for this attenuation, ensuring that the signal reaches the processor with sufficient strength to meet receiver sensitivity requirements. The repeater chip not only enhances the signal but also improves signal integrity. It retimes the signal, reducing delay and delay variation caused by trace length, and minimizes signal distortion such as eye closure and reflections, thereby improving signal quality. When the combined length of the third and fourth sub-traces exceeds the third preset length, the signal transmission distance within the second card is longer, which is particularly important in systems with physical constraints. The use of the repeater chip ensures that the signal meets specified performance standards even over long transmission distances. The presence of the repeater chip allows designers greater flexibility in routing design, especially when PCB layout constraints allow for the use of longer traces without compromising signal quality. The repeater chip reduces electromagnetic interference (EMI) impact, especially in long traces and noisy environments. By shaping and retiming the signal, signal radiation and interference with adjacent signals can be reduced. The enhancement of signal strength and improvement of signal integrity directly improve the reliability of the system under high-speed data transmission, reduce the bit error rate, and ensure the accurate transmission of data.

[0111] Simulation results indicate that when the PCB trace on the switch board exceeds 10 inches, or when the PCB trace on the second card exceeds 19 inches, the channel's operating margin is insufficient, leading to the risk of link signal transmission errors. In this case, a second relay chip should be added between the processor chip and the second connector to ensure high-speed signal integrity. Therefore, the third preset length can be set to 19 inches.

[0112] Similarly, in addition to adding a first relay chip between the switch chip and the first connector to ensure the integrity of the high-speed signal, a second relay chip can also be added between the second board and the second connector to ensure the integrity of the high-speed signal. In some embodiments, if the wiring is too long, making it easy for the signal to be transmitted incorrectly, it is possible to consider adding both the first relay chip between the switch chip and the first connector and the second relay chip between the second board and the second connector to ensure the integrity of the high-speed signal. Alternatively, it is possible to add multiple first relay chips between the switch chip and the first connector and multiple second relay chips between the second board and the second connector. All of these are configurable options.

[0113] Furthermore, using only onboard orthogonal high-density connectors on the switch board can lead to long PCB traces, excessive link loss, and a reduced eye diagram. Adding a relay chip requires additional space, so another solution is to use intra-board flying leads. Placing flying lead connectors around the switch chip keeps the PCB traces within 3 inches. These flying lead connectors interconnect with the orthogonal high-density connectors (primary connectors) on the board edge components via cables. This ensures that the overall link loss meets regulatory requirements, eliminating the need for additional relay chips.

[0114] In some embodiments, such as Figure 16 As shown, the switch board 10 has a switch chip 11, a first flying lead connector 14 and a first connector 12. The switch chip 11 is connected to the first flying lead connector 14 via a third wire, and the first flying lead connector 14 is connected to the first connector 12 via a first cable.

[0115] The switch board 10 incorporates a first flying lead connector 14, which connects to the switch chip 11 via a third trace and then to the first connector 12 via a first cable. Using the flying lead connector and cable allows the signal path to bypass the long PCB traces on the switch chip and reach the connector directly. This reduces the signal trace length on the PCB, helping to reduce insertion loss and reflections, thereby improving signal integrity. Cables typically have lower insertion loss than PCB traces, especially in high-speed signal transmission. Therefore, replacing some PCB traces with cables can reduce signal attenuation and ensure sufficient signal strength over long transmission distances. The use of flying lead connectors reduces signal propagation between complex PCB layers, thereby reducing latency and improving signal transmission efficiency, which is crucial for real-time and high-bandwidth applications. The introduction of flying lead connectors simplifies PCB wiring design, reduces the complexity of inter-layer routing, lowers design difficulty and production costs, and improves PCB yield and reliability. The use of cables provides additional flexibility in signal routing, allowing designers to connect different components through cables and achieve more optimized layouts even when physical space is limited. Reducing PCB trace lengths helps reduce heat sources around signal lines, improves thermal management of the switch board, and reduces the need for complex cooling systems. Flying leads and cables typically offer better shielding, reducing electromagnetic radiation during signal transmission, lowering EMI and improving signal purity within the system.

[0116] 112G high-speed signal link design is as attached Figure 16As shown. The signal is sent from the switch chip 11. It passes through a 2.5-inch PCB trace on the switch board 10, enters the first flying lead connector 14 located around the switch chip 11, and then passes through a 0.54m long, 32AWG first cable from the first flying lead connector 14 to the first connector 12 on the node chassis structure at the edge of the switch board 10. The first connector 12 and the second connector 22 are orthogonally connected and connected, then enter the 19-inch PCB trace on the second board 20, and finally enter the processor 21.

[0117] Build a link in the simulation software and simulate and evaluate the 112G high-speed signal link. Figure 17 The COM simulation results are shown in the attached Figure 18 The simulation results show that when the PCB trace length on the switch board is 2.5 inches, the length of the first cable of the first flying lead connector is 0.54 meters, and the PCB trace length on the second card is 19 inches, the channel operating margin of the link is 3.024 dB, which meets the design requirements.

[0118] The fan-out example of the flying wire connector is shown in the attached figure. Figure 19 As shown. Each layer of the flying lead connector has 4 pairs of differential lines, requiring a total of 4 signal layers. Among them, RX is the receive signal and TX is the transmit signal. That is, RX1, RX2, RX3, RX4, RX5, RX6, RX7, and RX8 are the first receive signal, the second receive signal, the third receive signal, the fourth receive signal, the fifth receive signal, the sixth receive signal, the seventh receive signal, and the eighth receive signal respectively; TX1, TX2, TX3, TX4, TX5, TX6, TX7, and TX8 are the first transmit signal, the second transmit signal, the third transmit signal, the fourth transmit signal, the fifth transmit signal, the sixth transmit signal, the seventh transmit signal, and the eighth transmit signal respectively.

[0119] The schematic diagram of the flying lead connector layout scheme on the switch board is shown in the attached figure. Figure 20 As shown in the figure, 16 orthogonal high-density connectors are fixed on the structural member on the left side of the switch board. There are 32 flying wire connectors around each switch chip in the board, that is, the cables of 4 flying wire connectors are connected to 1 orthogonal high-density connector (the first connector). Figure 20 As shown, the switch board has 16 orthogonal high-density connectors (first connectors), a chip power supply and motherboard management controller (BMC management module for short), a central processing unit and memory stick control module (CPU+memory stick control module for short), a power supply module for the switch chip, a power conversion module, and 32 flying wire connectors around each switch chip.

[0120] In some embodiments, one switch chip is connected to a first number of first flying lead connectors, and one first connector is connected to a second number of first flying lead connectors, where the first number is greater than the second number.

[0121] This configuration allows the switch chip to fan out high-speed signals in multiple directions simultaneously, increasing the signal transmission path and capacity, while the first connector acts as a centralized signal convergence point, receiving signals from multiple flying lead connectors. This design facilitates efficient signal distribution and collection and is particularly suitable for applications requiring high-density signal transmission. Because a switch chip is connected to multiple flying lead connectors, even if one flying lead connector or line fails, the other lines can continue to transmit signals, improving the overall redundancy and reliability of the signal link. By connecting the first connector to a smaller number of flying lead connectors, the time difference in signals reaching the first connector can be reduced, ensuring signal synchronization, which is particularly important for communication systems requiring precise clock synchronization. The wiring length between each flying lead connector and the switch chip can be shortened, helping to reduce signal reflections and insertion loss, thereby improving signal integrity. At the same time, the connection of a smaller number of first connectors to flying lead connectors can reduce crosstalk in the signal path, further optimizing signal quality.

[0122] The bandwidth and rate requirements of high-speed signals necessitate signal fan-out and aggregation. At data rates of 112 Gbps and higher, to maintain signal integrity and reduce crosstalk and reflections within the link, multiple flying lead connectors may be required to disperse signal paths while reducing the number of signals handled by each primary connector, resulting in more efficient and reliable signal transmission. Physical space constraints on the circuit board and the system as a whole influence the number of connectors configured. In tight spaces, more flying lead connectors may be required to enable flexible signal routing, maximizing signal transmission density within a limited area. To improve system reliability and fault tolerance, redundant connections may be implemented along the signal path. For example, multiple flying lead connectors may be connected from a switch chip to the primary connector. This allows signals to be transmitted via alternative paths even if a path fails. This typically means having more flying lead connectors on the switch side than on the primary connector side. The system's design architecture and topology also influence the number of these components. For example, if the switch chip communicates directly with multiple devices, more flying lead connectors may be required to achieve this goal. However, if the primary connector acts as a hub, fewer flying lead connectors may be connected to it. The more complex the signal chain, the more connection points may be needed to optimize signal transmission, reduce signal loss and improve signal quality. This may require multiple flying lead connectors to be set between the switch chip and the first connector to ensure effective signal transmission.

[0123] In some embodiments, the second board further includes a second flying lead connector, the processor is connected to the second flying lead connector via a fourth trace, and the second flying lead connector is connected to the second connector via a second cable.

[0124] Flying lead connectors and cables shorten the signal path between the processor and the connector, reducing signal trace length on the circuit board. This reduces signal insertion loss and reflections, optimizing signal integrity. The introduction of a second flying lead connector provides greater flexibility in physical layout. Unconstrained by the planar geometry of the circuit board, they allow for more freedom in connecting distant components, facilitating dense component layout and thermal management. By reducing trace length near the processor, potential heat sources are reduced, improving thermal management of the second board and reducing the need for complex cooling solutions. Flying lead connectors and cables typically offer enhanced shielding, reducing electromagnetic radiation and the impact of electromagnetic interference on other signal paths, enhancing signal purity and ensuring stable system operation. Flying lead connectors occupy less space on the circuit board, enabling designers to place more components within a limited board area and achieve higher integration densities. The use of cables and flying lead connectors reduces the link's dependence on circuit board manufacturing tolerances, improving signal link robustness and reducing the risk of functional failure due to PCB manufacturing defects.

[0125] Similarly, in addition to adding a first flying lead connector between the switch chip and the first connector to increase the routing length, a second flying lead connector can also be added between the second board and the second connector to increase the routing length and ensure the integrity of the high-speed signal. In some embodiments, if the routing length is too long, resulting in signal transmission errors, it is possible to consider adding both the first flying lead connector between the switch chip and the first connector and the second flying lead connector between the second board and the second connector to increase the routing length and ensure the integrity of the high-speed signal.

[0126] Among them, the materials of the routing and flying wires are both copper.

[0127] In some embodiments, the switch board has a first connector, the second board has a second connector, the first surface of the first connector includes a plurality of first pins arranged in a matrix, each first pin corresponds to each element in the first pin matrix, the first surface of the second connector includes a plurality of second pins arranged in a matrix, each second pin corresponds to each element in the second pin matrix, the first pin matrix and the second pin matrix are transposed matrices, the first surface of the first connector is the surface connected to the corresponding second connector, and the first surface of the second connector is the surface connected to the corresponding first connector.

[0128] When two connectors are mated in a transposed matrix configuration, signal alignment becomes intuitive and easy to manage. The matrix's transposition feature ensures seamless signal transition from one connector to the corresponding pin on the other, eliminating the need for complex cross-wiring. The transposed matrix design reduces the possibility of signal errors and signal dropouts. With clear pin assignments, signal confusion caused by wiring errors can be avoided during signal transmission from the first connector to the second, improving overall system reliability and stability. With the transposed matrix, designers can more efficiently utilize space and simplify internal wiring. This design allows signals to travel between the two connectors along the shortest, most direct path, reducing signal routing complexity, helping to reduce signal latency, and improving signal integrity. The transposed matrix design ensures signal alignment between the two connectors, helping to reduce crosstalk and improve signal clarity and quality. Especially in high-speed signal transmission, optimizing signal integrity is crucial for ensuring accurate and efficient data transmission.

[0129] like Figure 21 As shown, for the pin correspondence between the switch board and the orthogonal high-density connector on the second board, due to the orthogonal relationship between the two boards, the differential signal in the row of pin A1 on the switch board corresponds to the differential signal in the column of pin A8 on the second board. If the order correspondence of the differential pairs is represented by a matrix, with the pin order on the switch board defined as matrix T02 and the pin order on the second board defined as matrix T05, then matrices T02 and T05 form a transposed matrix relationship. T01 shows a top view of the switch board, showing the pin distribution of the first connector on the PCB. T02 shows the pin distribution of the orthogonal high-density connector at the interconnection end (i.e., the pin distribution on the side where the first and second connectors connect), on the orthogonal plane between the two nodes, as shown in P02. T03 shows a top view of the second connector on the second board, showing the pin distribution of the second connector on the PCB. T04 shows the pinout of the orthogonal high-density connector (i.e., the pinout on the side where the second connector connects to the first connector), as shown in P04, on the orthogonal plane between the two nodes. T05 shows the pinout of T04, but with the board and connector rotated 90 degrees counterclockwise to achieve an orthogonal relationship. The pinout is shown in P05, along the orthogonal plane between the two nodes. The orthogonal architecture in this solution, namely, the board shown in P02 and P05, exhibits an orthogonal relationship.

[0130] In some embodiments, a first shell includes two second boards, namely a first second board and a second second board, a first surface of the first connector includes a plurality of first pins arranged in a matrix, each first pin corresponds to each element in the first pin matrix, a first surface of the second connector of the first second board includes a plurality of second pins arranged in a matrix, each second pin corresponds to each element in the second pin matrix, a first surface of the second connector of the second second board includes a plurality of third pins arranged in a matrix, each third pin corresponds to each element in the third pin matrix, the first pin matrix and the second pin matrix are transposed matrices, the position of each second pin is centrally symmetrical with the position of each third pin, the first surface of the first connector is a surface connected to the corresponding second connector, and the first surface of the second connector of the first second board and the first surface of the second connector of the second second board are both surfaces connected to the corresponding first connector.

[0131] Because the first and second pin matrices form a transposed matrix, the signal mapping between the second connector and the first connector on the first and second boards is intuitive and clear, eliminating the need for complex signal routing and ensuring accurate signal connection and transmission. The centrally symmetrical third pin matrix design ensures accurate signal mapping even when the second connector on the second board is mated with the first connector, enhancing the overall stability and reliability of the signal link. This precise pin matrix pairing helps reduce crosstalk and reflections, optimizing signal integrity and maintaining signal quality and clarity even at high-speed signal rates, such as 112Gbps. The transposed matrix and centrally symmetrical pin design significantly simplify circuit board layout, reduce routing complexity, minimize signal latency, and improve signal transmission efficiency. During equipment maintenance and troubleshooting, this matrix pairing design enables technicians to quickly locate issues, streamline maintenance processes, and improve system maintainability.

[0132] The line sequence relationship of the orthogonal high-density connector is as follows: Figure 22 As shown. For the pin correspondence sequence of the switch board and the second card orthogonal high-density connector, in addition to the above embodiment (i.e. Figure 21 ), since one first housing includes two second boards, namely the first second board and the second second board, the pin distribution of the orthogonal high-density connector corresponding to the first second board and the second second board is centrosymmetrical, that is, they can overlap after rotating 180 degrees, that is, the pin sequence shown in T051 and T052 is centrosymmetrical. The parts shown in T01~T04 are the same as Figure 21The two boards are identical. T051 shows the pinout of T04, with the board and connector rotated 90 degrees counterclockwise to achieve an orthogonal relationship. On the orthogonal planes between the two nodes, the pinout and position are shown in P051. T052 shows the pinout of T04, with the board and connector rotated 90 degrees clockwise to achieve an orthogonal relationship. On the orthogonal planes between the two nodes, the pinout and position are shown in P052. The orthogonal architecture in the solution, P02, exhibits an orthogonal relationship with the boards shown in P051 and P052. The orthogonal relationship between the two boards is such that the differential signal in the row of pin A1 on the high-density connector on the switch board corresponds to the differential signal in the column of pin A8 on the high-density connector on the first and second boards of the second board, representing the corresponding relationship between T02 and T051. The differential signal in the row where pin A1 of the high-density connector on the switch board is located corresponds to the differential signal in the column where pin A1 of the high-density connector on the second board is located, i.e., the correspondence between T02 and T052. This requires that when the signal in the column where pin A1 of the high-density connector on the device is connected to the transmit signal, the signal in the column where pin A8 is located must also be connected to the transmit signal. If the signal in the column where pin A1 is located is connected to the receive signal, the signal in the column where pin A8 is located must also be connected to the receive signal. Similarly, the signal in the column where pin A2 of the high-density connector on the device must be the same as the signal in the column where pin A7 is located, the signal in the column where pin A3 is located must be the same as the signal in the column where pin A6 is located, and the signal in the column where pin A4 is located must be the same as the signal in the column where pin A5 is located.

[0133] Similarly, for high-density connectors on the switch board, the signal in the row where the A1 pin is located must be the same as the signal in the row where the A8 pin is located, the signal in the row where the A2 pin is located must be the same as the signal in the row where the A7 pin is located, the signal in the row where the A3 pin is located must be the same as the signal in the row where the A6 pin is located, and the signal in the row where the A4 pin is located must be the same as the signal in the row where the A5 pin is located.

[0134] In some embodiments, a first shell includes a second board card, a second shell includes a third number of switch boards, the third number of switch boards are arranged in parallel along the first direction in the second shell, a switch board includes a fourth number of first connectors, the number of second boards is the product of the third number and the fourth number, and the number of second connectors on a second board card is the number of the second shell.

[0135] In some embodiments, a first shell includes a second board card, a second shell includes a fifth number of switch boards, the fifth number of switch boards are stacked along the second direction in the second shell, a switch board includes a sixth number of first connectors, the number of second boards is the sixth number, and the number of second connectors on a second board card is the sum of the number of all switch boards.

[0136] In some embodiments, a second shell includes a switch board, a first shell includes a seventh number of second board cards, the seventh number of second board cards are stacked along the first direction in the first shell, a second board card includes an eighth number of second connectors, and the number of first connectors on a switch board is the sum of the number of all second board cards.

[0137] In some embodiments, a second shell includes a ninth number of switch boards, and the ninth number of switch boards are stacked and arranged in the second direction in the second shell, a first shell includes a tenth number of second board cards, and the tenth number of second board cards are stacked and arranged in the first direction in the first shell, a second board card includes an eleventh number of second connectors, the number of first connectors on a switch board is the sum of the number of all second board cards, and the eleventh number is the number of all switch boards.

[0138] In some embodiments, a second shell includes a twelfth number of switch boards, and the twelfth number of switch boards are arranged in parallel along the first direction in the second shell, a first shell includes a thirteenth number of second boards, and the thirteenth number of second boards are arranged in a stacked manner along the first direction in the first shell, a second board includes a fourteenth number of second connectors, the number of first connectors on a switch board is half the number of all second boards, and the fourteenth number is the number of the second shell.

[0139] Figure 23 A schematic diagram of a positive interconnection relationship between a switch board and a second board provided in an embodiment of the present application is shown in FIG. Figure 23 As shown, 8 first shells are vertically inserted into the server chassis, and 12 second shells are horizontally inserted into the server chassis, and the first shells and the second shells are orthogonally plugged in.

[0140] Figure 24 A structural diagram of another server chassis provided in an embodiment of the present application is shown as follows: Figure 24 As shown, the first shell is inserted horizontally into the server chassis, and the second shell is inserted vertically into the server chassis, and the first shell and the second shell are orthogonally plugged in.

[0141] This embodiment also provides a server system, including any one of the above-mentioned servers.

[0142] Through the description of the above implementation methods, those skilled in the art can clearly understand that the method according to the above embodiment can be implemented by means of software plus the necessary general hardware platform, and of course it can also be implemented by hardware, but in many cases the former is a better implementation method.

[0143] Professionals may further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the above description has generally described the components and steps of each example according to their functions. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0144] The above is a detailed introduction to a server and server system provided by the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only intended to help understand the method and core ideas of the present application. It should be noted that, for those skilled in the art, without departing from the principles of the present application, several improvements and modifications may be made to the present application, and such improvements and modifications also fall within the scope of protection of the claims of the present application.

Claims

1. A server, characterized in that: include: at least one first board; A switch board group, including multiple switch boards; A second board group, comprising a plurality of second boards; Mid-back panel; The switch board and any second board are orthogonal to each other and are pluggable, and at least one first board is connected to at least some of the second boards via the midplane, and the first board is connected to the switch board via the second board, the second board includes a processor, and the first board includes a controller; The switch board has a first connector, the number of rows of pins of the first connector is greater than the number of layers of wiring in the switch board; The switch board is located on a first side of the second board, and the first board is located on a second side of the second board. The first side and the second side are opposite to each other, and the same first housing includes one first board and two second boards. The processor of one second board is a first processor, and the processor of the other second board is a second processor. There is a gap between any two adjacent rows of solder joints on the switch board that are soldered to the first connector. A trace is located in at least one of the gaps. One end of the trace is connected to a pin of the first connector, and the other end of the trace is connected to a switch chip on the switch board. There are N rows of solder joints on the switch board, and the trace is located in a gap between the solder joints in the N / 2th row and the solder joints in the N / 2+1th row.

2. The server according to claim 1, wherein: Multiple second board cards are located in the same first shell, and the multiple second board cards in the same first shell are arranged along a first direction. There is a first liquid cooling plate between two second board cards in the same first shell, and the first direction is the same as the arrangement direction of the connector of one of the exchange boards.

3. The server according to claim 2, wherein: The first liquid cooling plate is located between the first processor and the second processor.

4. The server according to claim 1, wherein: The plurality of second boards are located in the same first housing. The plurality of second boards in the same first housing are arranged in parallel along a second direction, which is the same as the arrangement direction of the connectors of one second board.

5. The server according to claim 1, wherein: The number of rows of pins of the first connector is an integer multiple of the number of layers of wiring in the switch board.

6. The server according to claim 1, wherein: The second board includes a processor, the first board includes a controller, and the switching board includes a switching chip. The processor on the second board and the controller on at least one of the first boards are communicatively connected via an interface communication protocol. The switching chip on the switching board and the processor on at least one of the second boards are communicatively connected via an Ethernet protocol. Any two of the processors are communicatively connected via the Ethernet protocol.

7. The server according to claim 1, wherein: The switching board has a switching chip and a first connector, the second board includes a processor and a second connector, the switching chip is connected to the first connector via a first line, the processor is connected to the second connector via a second line, the sum of the length of the first line and the length of the second line is less than or equal to a first preset length, the first preset length is the minimum line length that makes the channel operation margin of the high-speed signal transmitted from the switching chip to the processor greater than the preset margin, wherein the preset margin is the minimum margin when the integrity of the high-speed signal transmitted from the switching chip to the processor is greater than or equal to the preset integrity.

8. The server according to claim 1, wherein: The switching board includes a switching chip, a first connector, and a first relay chip. The switching chip is connected to the first relay chip via a first sub-route, and the first relay chip is connected to the first connector via a second sub-route. The first relay chip is used to enhance the signal strength of high-speed signals. The sum of the length of the first sub-route and the length of the second sub-route is greater than a second preset length, and the first preset length is greater than the second preset length.

9. The server according to claim 1, wherein: The switching board includes a switching chip, a first flying lead connector, and a first connector. The switching chip is connected to the first flying lead connector via a third wire, and the first flying lead connector is connected to the first connector via a first cable.

10. The server according to claim 1, wherein: The exchange board has a first connector, and the second board has a second connector. The first surface of the first connector includes a plurality of first pins arranged in a matrix, and each first pin corresponds to each element in the first pin matrix. The first surface of the second connector includes a plurality of second pins arranged in a matrix, and each second pin corresponds to each element in the second pin matrix. The first pin matrix and the second pin matrix are transposed matrices. The first surface of the first connector is the surface connected to the corresponding second connector, and the first surface of the second connector is the surface connected to the corresponding first connector.

11. A server system, characterized in that: The server comprises the server according to any one of claims 1 to 10.

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