Power consumption controller, power consumption control method and microprocessor architecture

Abstract

The invention provides a power consumption controller, a power consumption control method and a microprocessor architecture, the power consumption controller is applied to the microprocessor architecture, and the microprocessor architecture comprises a master device module, a slave device module and the power consumption controller which are connected through a bus; the power consumption controller comprises a state monitoring module and a door control switch; a bus interface of the master device module is connected with a first bus interface of the state monitoring module, and a second bus interface of the state monitoring module is connected with a bus interface of the slave device module; the gating switch is connected to an input channel of a clock signal of the slave equipment module; the state monitoring module determines the working state of the slave equipment module by monitoring a bus signal; and when it is determined that the working state of the slave device module is switched from the non-idle state to the idle state, the state monitoring module sends a first signal to the gate control switch to control the gate control switch to close the clock signal of the slave device module. When the power consumption controller is applied to the microprocessor architecture, the power consumption of the microprocessor architecture can be reduced.

Description

Technical Field

[0001] This application relates to the field of computer technologies, and in particular, to a power consumption controller, a power consumption control method, and a microprocessor architecture. Background Art

[0002] With the progress of technologies, the continuous improvement of chip integration has posed more challenges to the design of microprocessor architectures. Especially in the context of multiple functional modules and high-density integration, power consumption management is particularly crucial.

[0003] In a microprocessor architecture, a master device module and a slave device module are connected through a bus to form a bus architecture. For example, the master device module and the slave device module can be connected through an AXI4 (Advanced eXtensible Interface 4) bus to form a bus architecture capable of achieving high-speed data transmission. Currently, bus architectures similar to the above have relatively high power consumption, thus resulting in relatively high power consumption of the microprocessor architecture. Summary of the Invention

[0004] Based on the above technical problems, this application proposes a power consumption controller, a power consumption control method, and a microprocessor architecture, which can reduce the power consumption of the microprocessor architecture.

[0005] In a first aspect of this application, a power consumption controller is proposed, which is applied to a microprocessor architecture. The microprocessor architecture includes a master device module, a slave device module, and the power consumption controller connected through a bus; the power consumption controller includes a status monitoring module and a gating switch; a bus interface of the master device module is connected to a first bus interface of the status monitoring module, and a second bus interface of the status monitoring module is connected to a bus interface of the slave device module; the gating switch is connected to an input path of a clock signal of the slave device module; the status monitoring module determines the working status of the slave device module by monitoring bus signals; in the case where it is determined that the working status of the slave device module switches from a non-idle state to an idle state, the status monitoring module sends a first signal to the gating switch; the first signal is used to control the gating switch to turn off the clock signal of the slave device module.

[0006] A second aspect of the present application proposes a power consumption control method, which is applied to a microprocessor architecture. The microprocessor architecture includes a master device module, a slave device module, and a power consumption controller connected by a bus. The power consumption controller includes a status monitoring module and a gating switch. The bus interface of the master device module is connected to the first bus interface of the status monitoring module, and the second bus interface of the status monitoring module is connected to the bus interface of the slave device module. The gating switch is connected to the input path of the clock signal of the slave device module. The method includes: the status monitoring module determines the working state of the slave device module by monitoring the bus signal; when it is determined that the working state of the slave device module changes from a non-idle state to an idle state, the status monitoring module sends a first signal to the gating switch; the first signal is used to control the gating switch to turn off the clock signal of the slave device module.

[0007] A third aspect of the present application proposes a microprocessor architecture, including a master device module, a slave device module, and the above-mentioned power consumption controller connected by a bus.

[0008] The power consumption controller proposed in the present application is connected to the bus link between the master device module and the slave device module of the microprocessor architecture. A status monitoring module and a gating switch are provided in the power consumption controller. The bus interface of the master device module is connected to the first bus interface of the status monitoring module, and the second bus interface of the status monitoring module is connected to the bus interface of the slave device module. The gating switch is connected to the input path of the clock signal of the slave device module. The status monitoring module determines the working state of the slave device module by monitoring the bus signal. When it is determined that the working state of the slave device module changes from a non-idle state to an idle state, the status monitoring module sends a first signal to the gating switch to control the gating switch to turn off the clock signal of the slave device module. The above-mentioned power consumption controller can turn off the clock signal of the slave device module when the slave device module of the microprocessor architecture is idle, thereby reducing the power consumption of the microprocessor architecture.

[0009] In addition, the above-mentioned power consumption controller, as a separate hardware power consumption control device, can be assembled in the bus path between the master device module and the slave device module of any microprocessor architecture in the above-mentioned manner. Furthermore, the power consumption control of the slave device module can be achieved through this power consumption controller. The implementation of the entire power consumption control process does not require modification of the working logic of the master device module or the slave device module, does not affect the functions of the master device module and the slave device module, does not increase the working burden of the master device module and the slave device module, and the structure of this power consumption controller is simple and the assembly is convenient. It is more convenient and efficient to achieve processor power consumption control through the above-mentioned power consumption controller, and its application scope is wider.

[0010] In some implementations, the gated switch includes a first contact, a second contact, and a control terminal; the status monitoring module includes a signal output terminal for outputting the first signal; the first contact of the gated switch is connected to the clock signal source of the slave device module, the second contact of the gated switch is connected to the clock signal input terminal of the slave device module, and the control terminal is connected to the signal output terminal of the status monitoring module; when the status monitoring module sends the first signal to the gated switch, the gated switch controls the circuit between the first contact and the second contact to be disconnected to turn off the clock signal of the slave device module.

[0011] Based on this implementation, the internal structure of the power consumption controller is simple, and the on / off control of the clock signal of the slave device module can be achieved through an indirect gated switch structure, and its control logic implementation is more concise and efficient.

[0012] In some implementations, the status monitoring module includes: a transaction statistics module and a control finite state machine; the transaction statistics module determines the communication transaction status between the master device module and the slave device module by monitoring the bus signal and sends the communication transaction status between the master device module and the slave device module to the control finite state machine; the control finite state machine determines the working state of the slave device module according to the communication transaction status between the master device module and the slave device module, and when it determines that the working state of the slave device module changes from a non-idle state to an idle state, it sends the first signal to the gated switch.

[0013] Based on this implementation, different modules are used to perform transaction statistics and working state judgment respectively, and different processing contents are assigned to different modules for execution, improving the execution accuracy and efficiency.

[0014] In some implementations, the transaction statistics module includes a transaction counter and a ready signal control module; wherein, the transaction counter counts the communication transactions between the master device module and the slave device module according to the request signal sent by the master device module, the ready signal sent by the ready signal control module, and the last data identification signal, and sends the transaction count result to the control finite state machine; the ready signal control module sends the ready signal to the transaction counter and the control finite state machine according to the request response signal sent by the slave device module and the transaction count result sent by the control finite state machine; the control finite state machine sends the transaction count result to the ready signal control module, and determines the communication transaction status between the master device module and the slave device module according to the transaction count result and the ready signal, and determines the working state of the slave device module according to the communication transaction status.

[0015] Based on this implementation method, by using a transaction counter and a ready signal control module to record the requests sent by the master device module and the responses feedback by the slave device module respectively, the accuracy and efficiency of transaction statistics can be improved.

[0016] In some implementation methods, the transaction counter includes a read transaction counter, a write address counter, and a write data counter; wherein, the read transaction counter counts the read transactions between the master device module and the slave device module according to the read request signal sent by the master device module, the read ready signal sent by the ready signal control module, and the last data identification signal, and sends the read transaction count result to the control finite state machine; the write address counter counts the write address transactions between the master device module and the slave device module according to the write address request signal sent by the master device module and the write address ready signal sent by the ready signal control module, and sends the write address transaction count result to the control finite state machine; the write data counter counts the write data transactions between the master device module and the slave device module according to the write data request signal sent by the master device module, the write data ready signal sent by the ready signal control module, and the last data identification signal, and sends the write data transaction count result to the control finite state machine.

[0017] Based on this implementation method, by setting counters for each type of transaction respectively for transaction statistics, the accuracy and efficiency of transaction counting can be improved.

[0018] In some implementation methods, the status monitoring module further includes a waiting counter; when the control finite state machine determines to clear according to the communication transaction between the master device module and the slave device module, it sends a counting trigger signal to the waiting counter; the waiting counter starts counting when receiving the counting trigger signal and sends the counting result to the control finite state machine; the control finite state machine determines the working state of the slave device module according to the communication transaction state between the master device module and the slave device module, including: when the control finite state machine determines to clear according to the communication transaction between the master device module and the slave device module, and the counting result sent by the waiting counter is equal to the set count value, it determines that the working state of the slave device module switches from a non-idle state to an idle state.

[0019] Based on this implementation method, waiting until a certain count value is reached after the slave device module becomes idle before turning off the clock of the slave device module can avoid frequent start and stop of the slave device module, and ensure that the slave device module can respond to continuous communication transactions in a timely manner.

[0020] In some implementations, the working states of the slave device module include an idle state, a ready state, a transaction processing state, and a waiting state; wherein, the idle state includes a state where there is no current communication transaction or waiting for a new transaction request, the ready state includes a state of monitoring whether the transaction handshake is completed after receiving a transaction request, the transaction processing state includes a state of executing a communication transaction, and the waiting state includes a state where the communication transaction is processed and ready to switch to the idle state; when the state monitoring module determines that the working state of the slave device module is any one of the ready state, the transaction processing state, and the waiting state, it sends a second signal to the gating switch; the second signal is used to control the gating switch to turn on the clock signal of the slave device module.

[0021] Based on this implementation, dividing the working states of the slave device module more finely can improve the fineness of clock control of the slave device module.

[0022] In some implementations, when the state monitoring module determines that the working state of the slave device module switches from the idle state to a non-idle state, it sends a second signal to the gating switch; the second signal is used to control the gating switch to turn on the clock signal of the slave device module.

[0023] Based on this implementation, when the slave device module needs to work, the clock signal of the slave device module can be turned on in time to ensure normal communication inside the microprocessor architecture. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the drawings in the following description are only the embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained according to the provided drawings without creative efforts.

[0025] Figures 1 - 3 They are respectively schematic structural diagrams of some different microprocessor architectures provided by the embodiments of the present application.

[0026] Figure 4 It is a schematic diagram of the state transition of the working state of the slave device module provided by the embodiment of the present application.

[0027] Figures 5 - 7 They are respectively schematic structural diagrams of some other different microprocessor architectures provided by the embodiments of the present application.

[0028] Figure 8 It is a schematic flowchart of a power consumption control method provided by the embodiment of the present application. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0029] The technical solution of the embodiment of the present application is applicable to the application scenario of power consumption control of the microprocessor architecture. Adopting the technical solution of the embodiment of the present application can reduce the power consumption of the microprocessor architecture.

[0030] A microprocessor architecture, also known as a System on Chip (SoC), refers to integrating multiple modules, such as various processors, memories, functional modules, interface control modules, buses, etc., on a single chip to form a complete system.

[0031] With the progress of technology, the continuous improvement of chip integration has brought more challenges to SoC design. Especially in the context of multiple functional modules and high-density integration, power management is particularly crucial.

[0032] Generally, the power consumption of a chip can be divided into static power consumption and dynamic power consumption. Static power consumption mainly comes from the leakage current of the chip, while dynamic power consumption is mainly related to factors such as the switching frequency of signals, the number of signal flips, and voltage in the circuit. In modern SoC design, dynamic power consumption occupies the main part of the power consumption. Therefore, how to effectively control and optimize dynamic power consumption has become one of the core research directions.

[0033] Each module within the system on chip can be connected through a bus. The bus is a transmission channel for control signals and data signals. The application of the bus can greatly simplify the system structure, increase the compatibility, openness, reliability, and maintainability of the system, thereby significantly reducing the system cost. For example, in a microprocessor architecture, the master device module and the slave device module are connected through a bus to form a bus architecture, realizing high-speed data transmission between the master device module and the slave device module.

[0034] The bus in the above bus architecture can adopt any bus protocol. For example, AXI4 (Advanced eXtensible Interface 4, the fourth-generation high-performance extensible interface) is a widely used bus protocol. It provides efficient high-speed data transmission capabilities and can support high-bandwidth communication between different components. However, due to the high-speed and high-frequency characteristics of the bus protocol, the dynamic power consumption problem brought by the bus architecture has also become a difficult point in chip design.

[0035] In response to this, the embodiment of the present application proposes a power consumption control scheme for the above bus architecture in the microprocessor architecture. Applying this scheme to the microprocessor architecture can reduce the power consumption of the bus architecture in the microprocessor architecture, thereby reducing the power consumption of the microprocessor architecture.

[0036] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present application.

[0037] The technical solutions in the embodiments of the present application can be applied to a microprocessor architecture. Refer to Figure 1 As shown, in the microprocessor architecture 100, it includes a master device module 101 and a slave device module 102 connected by a bus.

[0038] As Figure 1 shown, the microprocessor architecture 100 may include at least one master device module 101 and at least one slave device module 102. The master device module 101 and the slave device module 102 are communicatively connected through a bus. For example, the master device module 101 communicates with the bus through the master device interface of the bus, and the slave device module 102 communicates with the bus through the slave device interface of the bus.

[0039] The master device module 101 is generally a device that initiates and implements control. For example, the master device module 101 may be a Central Processing Unit (CPU), a Digital Signal Processor (DSP), a Graphics Processing Unit (GPU), a Neuralnetwork Processing Unit (NPU), a Direct Memory Access (DMA) controller, etc.

[0040] The slave device module 102 is generally a device that responds to the control of the master device module 101 and cooperates to perform corresponding operations. For example, memory devices such as a Static Random Access Memory (SRAM), a Flash Memory controller, a Synchronous Dynamic Random Access Memory (SDRAM) controller, a Double Data Rate SDRAM (DDR) controller, etc.

[0041] In some embodiments, the slave device module 102 may further include external devices, such as a Universal Asynchronous Receiver / Transmitter (UART), a Universal Serial Bus (USB), a DDR controller, etc.

[0042] In addition, in the above microprocessor architecture 100, some devices may be both master device modules and slave device modules. In the above Figure 1 only a simple architecture form is used to represent the connection relationship between the master device module, the slave device module, and the bus in the microprocessor architecture, and the roles of each device module in the actual microprocessor architecture are not strictly limited.

[0043] In addition, in Figure 1 the microprocessor architecture shown, a clock signal source 104 is also configured for the slave device module 102 to provide a clock signal for the slave device module 102 to support the clock requirements of the slave device module 102.

[0044] Under normal circumstances, Figure 1 the clock signal source 104 shown in continuously provides a clock signal for the slave device module 102, so that the slave device module 102 continuously remains in a working state to timely respond to the communication operations of the master device module 101.

[0045] However, keeping the slave device module 102 continuously in a working state results in a relatively high power consumption of the bus architecture, which does not meet the power consumption control requirements for the microprocessor architecture.

[0046] To be able to reduce the power consumption of the microprocessor architecture, an embodiment of the present application proposes a power consumption controller, which can be applied to Figure 1 the microprocessor architecture 100 shown to reduce the power consumption of the microprocessor architecture.

[0047] Specifically, the power consumption controller 103 proposed in the embodiment of the present application can be installed on the bus path between the master device module 101 and the slave device module 102 of the microprocessor architecture 100, thus constituting a microprocessor architecture including the master device module 101, the slave device module 102, and the power consumption controller 103 connected by a bus as shown in Figure 2 In this microprocessor architecture, a clock signal source 104 is also included to provide a clock signal for the slave device module 102.

[0048] In this embodiment, the bus used to connect each module and the power consumption controller in the above microprocessor architecture can be any type of bus. For example, it can be an AXI4 bus, an APB bus, etc. This embodiment does not make strict limitations. In subsequent embodiments, the AXI4 bus will be used as an example of the bus in the microprocessor architecture to introduce the solutions provided by each embodiment of the present application. When other types of buses are applied in the microprocessor architecture, the implementation of each embodiment solution can also be realized with reference to the introduction of each embodiment.

[0049] Continue to refer to Figure 2 , in the microprocessor architecture 100 provided in this embodiment, the power consumption controller 103 includes a status monitoring module 1031 and a gating switch 1032.

[0050] Among them, a first bus interface and a second bus interface are provided on the status monitoring module 1031. The two bus interfaces are respectively used to connect to the master device module 101 and the slave device module 102 through the bus. Moreover, the first bus interface and the second bus interface are communicatively connected through the internal path of the status monitoring module 1031. The bus interface of the master device module 101 is connected to the first bus interface of the status monitoring module 1031 through the bus. At the same time, the second bus interface of the status monitoring module is connected to the bus interface of the slave device module 102 through the bus, so that the master device module 101, the status monitoring module 1031, and the slave device module 102 are sequentially connected in series through the bus.

[0051] Based on the above connection method, the status monitoring module 1031 serves as an intermediate medium during the communication between the master device module 101 and the slave device module 102. The status monitoring module 1031 can obtain all the bus signals during the communication between the master device module 101 and the slave device module 102, and thus can further perform subsequent processing based on the obtained bus signals.

[0052] The gating switch 1032 is an electronic component used to control the on / off of a circuit. When in use, the gating switch is installed in the circuit line. It can receive an external control signal and control the on / off of the circuit according to the control signal. For example, when receiving a high-level signal, the gating switch 1032 controls the circuit where it is located to conduct. When receiving a low-level signal, the gating switch 1032 controls the circuit where it is located to disconnect.

[0053] Such as Figure 2As shown, the above-mentioned status monitoring module 1031 is communicatively connected to the gating switch 1032, so that the status monitoring module 1031 can send signals to the gating switch 1032 to control the closing and conduction of the gating switch 1032. The gating switch 1032 is connected to the input path of the clock signal of the slave device module 102, that is, the gating switch 1032 is connected in series on the path between the clock signal source 104 and the slave device module 102. Based on this connection method, the status monitoring module 1031 controls the switch of the gating switch 1032 by sending signals to the gating switch 1032, and thus can realize the switch control of the clock signal of the slave device module 102.

[0054] In some embodiments, a first contact and a second contact are provided on the gating switch 1032, and the circuit between the two contacts can be conducted or disconnected under the control of the gating switch 1032. In Figure 2 In the shown microprocessor architecture, the first contact of the gating switch 1032 is connected to the clock signal source 104 of the slave device module 102, and the second contact of the gating switch 1032 is connected to the clock signal input terminal of the slave device module 102, so as to realize the series connection of the gating switch 1032 between the clock signal source 104 and the clock signal input terminal of the slave device module 102, so that the gating switch 1032 can control the conduction or disconnection of the circuit between the first contact and the second contact, and thus can control the on-off of the circuit between the clock signal source 104 and the clock signal input terminal of the slave device module 102, that is, can control the switch of the clock signal of the slave device module 102.

[0055] At the same time, a signal output terminal is provided on the status monitoring module 1031, and a control terminal is provided on the gating switch 1032. The signal output terminal of the status monitoring module 1031 is connected to the control terminal of the gating switch 1032, so that the status monitoring module 1031 can input control signals to the gating switch 1032 to realize the switch control of the gating switch 1032.

[0056] Based on the above-mentioned microprocessor architecture, the status monitoring module 1031 in the power consumption controller determines the working state of the slave device module 102 by monitoring the bus signal.

[0057] That is, the status monitoring module 1031 collects the bus signals between the master device module 101 and the slave device module 102 in real time, and analyzes the collected bus signals to determine the working state of the slave device module.

[0058] The above-mentioned bus signal refers to the bus protocol signal when the master device module 101 and the slave device module 102 communicate through the bus.

[0059] For example, the AXI4 bus provides five independent channels: read address, read data, write address, write data, and write response. Each channel has its own signal lines for transmitting corresponding signals. In addition, there may also be global signals such as clock and reset.

[0060] Among them, the signals transmitted by the read address channel include two handshake signals, AR_VALID (read address valid) and AR_READY (ready for read address), which are used to implement the handshake of the read address transaction.

[0061] The signals transmitted by the read data channel include R_VALID (read data valid) and R_READY (ready for read data). R_VALID indicates a request to read data, and R_READY indicates a feedback signal for the completion of data reading.

[0062] The signals transmitted by the write address channel include two handshake signals, AW_VALID (write address valid) and AW_READY (ready for write address), which are used to implement the handshake of the write address transaction.

[0063] The signals transmitted by the write data channel include two handshake signals, W_VALID (write data valid) and W_READY (ready for write data), which are used to implement the handshake of the write data transaction.

[0064] The signals transmitted by the write response channel include B_VALID (write response valid) and B_READY (ready for write response). B_VALID indicates a request to write data, and B_READY indicates a feedback signal for the completion of data writing.

[0065] In addition, in the read data and write data channels, in addition to transmitting the data to be read or written, the last data identification signal (last) also needs to be transmitted. This last data identification signal is used to indicate that the last data packet has been transmitted.

[0066] Generally, in each of the above channels, the device at the first end of the channel sends a VALID signal to the device at the second end of the channel, and the device at the second end of the channel feeds back a READY signal to the device at the first end of the channel. Usually, the master device module 101 sends a VALID signal to the slave device module 102, and the slave device module 102 feeds back a READY signal to the master device module 101.

[0067] Based on the above handshake signals, when the master device module 101 successfully shakes hands with the slave device module 102 (after the master device module 101 issues the VALID signal, the slave device module 102 outputs the corresponding READY signal), it can be regarded that a communication transaction (read data, write address, write data) is established between the master device module and the slave device module. Based on the above R_VALID (read data valid), R_READY (ready to read data), B_VALID (write response valid), and B_READY (ready to write response) signals, it can be determined that the read operation and the write operation between the master device module 101 and the slave device module 102 are completed, and at this time, it indicates that the corresponding communication transaction ends.

[0068] Therefore, by monitoring the bus signals between the master device module 101 and the slave device module 102, the status monitoring module 1031 can determine whether a communication transaction is established between the master device module 101 and the slave device module 102, whether there is a communication transaction waiting for a handshake, and whether the communication transaction is completed, so as to determine whether a communication transaction is being executed or about to be established between the two, and whether all communication transactions are completed. According to the communication transaction status between the master device module 101 and the slave device module 102, the working state of the slave device module 102 can be determined.

[0069] In this embodiment, the working state of the slave device module can be divided into an idle state and a non-idle state. Among them, when all communication transactions between the slave device module 102 and the master device module 101 are completed and there is no established or waiting-for-handshake communication transaction, it is considered that the slave device module 102 is in the idle state, otherwise it is considered that the slave device module is in the non-idle state.

[0070] Therefore, by analyzing the bus signals between the master device module 101 and the slave device module 102, the status monitoring module 1031 can determine the working status of the slave device module. For example, based on the handshake signals such as AR_VALID (read address valid), AR_READY (ready for read address), AW_VALID (write address valid), AW_READY (ready for write address), W_VALID (write data valid), and W_READY (ready for write data) between the master device module 101 and the slave device module 102, the status monitoring module 1031 can determine whether a communication transaction is established between the two (successful handshake indicates successful establishment of a communication transaction) and whether there is a communication transaction waiting to be established (waiting for a successful handshake indicates that the communication transaction is waiting to be established). According to the signals of R_VALID (read data valid), R_READY (ready for read data), B_VALID (write response valid), and B_READY (ready for write response) between the master device module 101 and the slave device module 102, it can be determined whether the communication transaction between the two is completed, and further, the communication transaction status between the master device module 101 and the slave device module 102 and the working status of the slave device module 102 can be determined.

[0071] When the status monitoring module 1031 determines that the working status of the slave device module 102 switches from a non-idle state to an idle state, the status monitoring module 1031 sends a first signal to the gating switch 1032 to control the gating switch to turn off the clock signal of the slave device module 102, that is, to put the slave device module 102 into a power-down state, thereby reducing the power consumption of the slave device module.

[0072] For example, when the status monitoring module 1031 determines that the working status of the slave device module 102 switches from a non-idle state to an idle state, the status monitoring module 1031 sends a first signal to the gating switch 1032 through the signal output terminal. When the gating switch 1032 receives this first signal, it controls the circuit between the first contact connected to the clock signal source 104 and the second contact connected to the clock signal input terminal of the slave device module 102 to be disconnected, thereby cutting off the circuit between the clock signal source 104 and the clock signal input terminal of the slave device module 102, achieving the purpose of turning off the clock signal of the slave device module 102.

[0073] Among them, the above-mentioned first signal can be any signal used to represent turning off the clock signal of the slave device module. For example, it can be a low-level signal.

[0074] As can be seen from the above introduction, the power consumption controller proposed in the embodiment of the present application is connected to the bus link between the master device module and the slave device module of the microprocessor architecture. A status monitoring module and a gating switch are provided in the power consumption controller. The bus interface of the master device module is connected to the first bus interface of the status monitoring module, and the second bus interface of the status monitoring module is connected to the bus interface of the slave device module; the gating switch is connected to the input path of the clock signal of the slave device module. The status monitoring module determines the working state of the slave device module by monitoring the bus signal; when it is determined that the working state of the slave device module switches from the non-idle state to the idle state, the status monitoring module sends a first signal to the gating switch to control the gating switch to turn off the clock signal of the slave device module.

[0075] The above power consumption controller can turn off the clock signal of the slave device module when the slave device module of the microprocessor architecture is idle, thereby reducing the power consumption of the microprocessor architecture.

[0076] In addition, the above power consumption controller, as a separate hardware power consumption control device, can be assembled in the bus path between the master device module and the slave device module of any microprocessor architecture in the above manner. Furthermore, the power consumption control of the slave device module can be achieved through this power consumption controller. The implementation of the entire power consumption control process does not require modification of the working logic of the master device module or the slave device module, does not affect the functions of the master device module and the slave device module, does not increase the working burden of the master device module and the slave device module, and the structure of this power consumption controller is simple and convenient to assemble. Implementing processor power consumption control through the above power consumption controller is more convenient, more efficient, and has a wider scope of application.

[0077] In another embodiment, as shown in Figure 3 the status monitoring module 1031 in the power consumption controller includes a transaction statistics module 1033 and a control finite state machine 1034.

[0078] Among them, the transaction statistics module 1033 is provided with a first bus interface and a second bus interface. The two bus interfaces are respectively used to connect to the master device module 101 and the slave device module 102 through the bus. Moreover, the first bus interface and the second bus interface are communicatively connected through the internal path of the transaction statistics module 1033. The bus interface of the master device module 101 is connected to the first bus interface of the transaction statistics module 1033 through the bus. At the same time, the second bus interface of the transaction statistics module 1033 is connected to the bus interface of the slave device module 102 through the bus, so that the master device module 101, the transaction statistics module 1033, and the slave device module 102 are sequentially connected in series through the bus.

[0079] At the same time, the transaction statistics module 1033 is communicatively connected to the control finite state machine 1034.

[0080] Based on the above connection method, the transaction statistics module 1033 serves as an intermediate medium during the communication between the master device module 101 and the slave device module 102. The transaction statistics module 1033 can obtain all bus signals during the communication between the master device module 101 and the slave device module 102, and thus can further perform subsequent processing based on the obtained bus signals.

[0081] Specifically, the transaction statistics module 1033 determines the communication transaction status between the master device module 101 and the slave device module 102 by monitoring the bus signals during the communication between the master device module 101 and the slave device module 102, and sends the communication transaction status between the master device module 101 and the slave device module 102 to the control finite state machine 1034.

[0082] As described in the above embodiment, the transaction statistics module 1033 can determine the communication transaction status between the master device module 101 and the slave device module 102 by parsing the bus signals between the master device module 101 and the slave device module 102. For example, the transaction statistics module 1033 determines whether a communication transaction is established between the two (a successful handshake indicates a successful establishment of a communication transaction) and whether there is a communication transaction waiting to be established (waiting for a successful handshake indicates that a communication transaction is waiting to be established) based on the handshake signals such as AR_VALID (read address valid), AR_READY (ready for read address), AW_VALID (write address valid), AW_READY (ready for write address), W_VALID (write data valid), and W_READY (ready for write data) between the master device module 101 and the slave device module 102. According to the signals of R_VALID (read data valid), R_READY (ready for read data), B_VALID (write response valid), and B_READY (ready for write response) between the master device module 101 and the slave device module 102, it can be determined whether the communication transaction between the two is completed, and further the communication transaction status between the master device module 101 and the slave device module 102 can be determined.

[0083] After receiving the communication transaction status between the master device module 101 and the slave device module 102, the control finite state machine 1034 determines the working state of the slave device module 102 according to the communication transaction status between the master device module 101 and the slave device module 102. For example, the control finite state machine 1034 can divide the working state of the slave device module into an idle state and a non-idle state. Among them, when all communication transactions between the slave device module 102 and the master device module 101 are completed and there are no established or waiting-to-handshake communication transactions, the slave device module 102 is considered to be in the idle state; otherwise, the slave device module 102 is considered to be in the non-idle state.

[0084] In another embodiment, the working states of the slave device module 102 specifically include the idle state Idle, the ready state Wait_ready, the transaction processing state Wait_com, and the waiting state Cnt.

[0085] Among them, the idle state Idle indicates that there is no current communication transaction or waiting to receive a new transaction request; the ready state Wait_ready indicates monitoring whether the transaction handshake is completed after receiving a transaction request, that is, the state when a transaction request is received but the corresponding ready signal has not been received yet; the transaction processing state Wait_com indicates that a communication transaction is being executed and waiting for the transaction processing to complete; the waiting state Cnt indicates that the communication transaction processing is completed and ready to switch to the idle state.

[0086] Figure 4 The jumps between the various states are shown:

[0087] In the Idle state, when a new transaction request (AW_VALID, W_VALID, AR_VALID) is received, if the backpressure handshake signal (AW_READY, W_READY, AR_READY) is received, indicating that the handshake is completed, it jumps to the Wait_com state. If the backpressure handshake signal is not received, it jumps to the Wait_ready state and waits for the handshake to complete.

[0088] In the Wait_ready state, when the backpressure handshake signal (AW_READY, W_READY, AR_READY) is received, it indicates that the handshake is completed and jumps to the Wait_com state.

[0089] In the Wait_com state, if the transaction is completed, it jumps to the Cnt state.

[0090] In the Cnt state, the counter starts counting, and there are 4 situations during the counting process:

[0091] 1. There is no new request, and the value of the counter has not reached the set waiting count value. At this time, continue counting, and the state remains in the Cnt state.

[0092] 2. There is no new request, and the value of the counter reaches the set waiting count value. At this time, reset the count value of the counter and return to the Idle state.

[0093] 3. A new request is received, and the value of the counter has not reached the set waiting count value. At this time, the count value of the counter is reset, and it jumps to Wait_ready or Wait_com.

[0094] 4. A new request is received and the value of the counter reaches the set waiting count value. At this time, the count value of the counter is reset and the next state jumps to Wait_ready or Wait_com.

[0095] Based on the above state settings and state transition logic, after the transaction statistics module 1033 sends the communication transaction state between the master device module 101 and the slave device module 102 to the control finite state machine 1034 in real time, the control finite state machine 1034 can, according to the communication transaction state between the master device module 101 and the slave device module 102, Figure 4 determine the working state of the slave device module according to the state transition logic shown.

[0096] Among them, when the control finite state machine 1034 determines that the working state of the slave device module 102 is any one of the above-mentioned ready state Wait_ready, transaction processing state Wait_com, and waiting state Cnt, it is regarded that the slave device module 102 is in a non-idle state. At this time, the control finite state machine 1034 sends a second signal to the gating switch 1032 to control the gating switch 1032 to turn on the clock signal of the slave device module 102, that is, to control the gating switch 1032 to close the circuit between its first contact and the second contact to turn on the clock signal of the slave device module 102.

[0097] When the control finite state machine 1034 determines that the working state of the slave device module 102 is the above-mentioned idle state Idle, it is regarded that the slave device module 102 is in an idle state. At this time, the control finite state machine 1034 sends a first signal to the gating switch 1032 to control the gating switch 1032 to turn off the clock signal of the slave device module 102

[0098] In another embodiment, as shown in Figure 5 the transaction statistics module 1033 in the power consumption controller includes a transaction counter 1035 and a ready signal control module 1036.

[0099] Among them, both the transaction counter 1035 and the ready signal control module 1036 are used to receive the bus signals between the master device module 101 and the slave device module 102. Specifically, one bus interface of the transaction counter 1035 is connected to the master device module 101 through a bus, another bus interface of the transaction counter 1035 is connected to one bus interface of the ready signal control module 1036 through a bus, and another bus interface of the ready signal control module 1036 is connected to the slave device module 102 through a bus.

[0100] In addition, the transaction counter 1035 is connected to the control finite state machine 1034 and is used to send the transaction count result to the control finite state machine 1034. Among them, the transaction counter 1035 counts the communication transactions between the master device module 101 and the slave device module 102 according to the request signals (AW_VALID, W_VALID, AR_VALID, R_VALID, B_VALID) sent by the master device module 101, the ready signals (AW_READY, W_READY, AR_READY, R_READY, B_READY) sent by the ready signal control module, and the last data identification signal (last), and sends the transaction count result to the control finite state machine 1034.

[0101] Among them, the transaction counter 1035 determines the communication transaction status between the master device module 101 and the slave device module 102 according to the request signals (AW_VALID, W_VALID, AR_VALID, R_VALID, B_VALID) sent by the master device module 101, the ready signals (AW_READY, W_READY, AR_READY, R_READY, B_READY) sent by the ready signal control module, and the last data identification signal (last). The specific process can refer to the description in the above embodiments. After determining the communication transaction status between the master device module 101 and the slave device module 102, count the uncompleted communication transactions, that is, obtain the transaction count result.

[0102] The ready signal control module 1036 is connected to the control finite state machine 1034 and is used to receive the transaction count result sent by the control finite state machine and send the ready signal to the transaction counter 1035 and the control finite state machine 1034.

[0103] Specifically, the ready signal control module 1036 receives the request response signals (AW_READY, W_READY, AR_READY, R_READY, B_READY) sent by the slave device module 102, and after receiving the request response signals, sends the ready signal to the transaction counter 1035 and the control finite state machine 1034. In addition, the control finite state machine 1034 also sends the transaction count result sent by the transaction counter 1035 to the ready signal control module 1036. The ready signal control module 1036 combines the transaction count result after receiving the request response signal from the slave device module 102 and judges whether to send the ready signal to the transaction counter 1035 and the control finite state machine 1034. When it is judged that the ready signal can be sent, the ready signal is sent to the transaction counter 1035 and the control finite state machine 1034.

[0104] In this power consumption controller architecture, the control finite state machine 1034 determines the communication transaction state between the master device module and the slave device module according to the transaction count result sent by the transaction counter 1035 and the ready signal sent by the ready signal control module 1036, and determines the working state of the slave device module according to the communication transaction state.

[0105] For example, if each communication transaction corresponding to the transaction count result receives the corresponding ready signal and has been processed, or the transaction count result is zero and no signal is received, it can be regarded that all communication transactions between the master device module and the slave device module are completed, and then it can be determined that the slave device module 102 is in the idle state; or, if the communication transaction corresponding to the transaction count result has not received the corresponding ready signal, or the transaction count result is not zero, it can be determined that all communication transactions between the master device module and the slave device module have not been completed, and at this time it can be determined that the slave device module 102 is in the non-idle state.

[0106] In another embodiment, the above-mentioned transaction counter 1035 may specifically include a read transaction counter, a write address counter, and a write data counter, which are respectively used to count the read transactions, write address transactions, and write data transactions between the master device module 101 and the slave device module 102.

[0107] Among them, the read transaction counter counts the read transactions (including read address transactions and read data transactions) between the master device module 101 and the slave device module 102 according to the read request signal (including the read address signal AR_VALID and the read data signal R_VALID) sent by the master device module 101, the read ready signal (including the read address ready signal AR_READY and the read data ready signal R_READY) sent by the ready signal control module 1036, and the last data identification signal (last), and sends the read transaction count result to the control finite state machine 1034. For the specific implementation method of read transaction counting, refer to the transaction counting method described in the above embodiment.

[0108] The write address counter counts the write address transactions between the master device module 101 and the slave device module 102 according to the write address request signal (AW_VALID) sent by the master device module 101 and the write address ready signal (AW_READY) sent by the ready signal control module 1036, and sends the write address transaction count result to the control finite state machine 1034. For the specific implementation method of write address transaction counting, refer to the transaction counting method described in the above embodiment.

[0109] The write data counter counts the write data transactions between the master device module 101 and the slave device module 102 according to the write data request signals (including W_VALID and B_VALID) sent by the master device module 101, the write data ready signals (W_READY and B_READY) sent by the ready signal control module 1036, and the last data identification signal (last), and sends the counting result of the write data transactions to the control finite state machine 1034. For the specific implementation method of the write data transaction counting, refer to the transaction counting method introduced in the above embodiments.

[0110] In another embodiment, refer to Figure 6 As shown, in the status monitoring module 1031 of the power consumption controller 103, there is also a waiting counter 1037, which is connected to the control finite state machine 1034.

[0111] When the control finite state machine 1034 determines to clear the communication transactions between the master device module 101 and the slave device module 102, it sends a counting trigger signal to the waiting counter 1037, causing the waiting counter 1037 to start counting from 0.

[0112] The waiting counter 1037 starts counting when it receives the counting trigger signal sent by the control finite state machine 1034 and sends the counting result to the control finite state machine 1034.

[0113] The control finite state machine 1034 determines the working state of the slave device module 102 according to the communication transaction status between the master device module 101 and the slave device module 102, including:

[0114] When the control finite state machine 1034 determines to clear the communication transactions between the master device module 101 and the slave device module 102 and the counting result sent by the waiting counter 1037 is equal to the set count value, it determines that the working state of the slave device module 102 switches from the non-idle state to the idle state.

[0115] Specifically, combined with Figure 4 As shown in the state transition logic, when the control finite state machine 1034 determines that the slave device module 102 enters the waiting state Cnt, that is, it determines to clear the communication transactions between the master device module 101 and the slave device module 102. At this time, the control finite state machine 1034 sends a counting trigger signal to the waiting counter 1037 to make the waiting counter 1037 start counting. At the same time, the control finite state machine 1034 obtains the counting result fed back by the waiting counter 1037 in real time.

[0116] Before the count result fed back by the wait counter 1037 reaches the set count value, if no new request has been received from the slave device module 102, the wait counter 1037 continues to count, and the slave device module 102 remains in the Cnt state; if a new request is received from the slave device module 102, the wait counter 1037 is reset, its count result is cleared, and the state of the slave device module 102 jumps to Wait_ready or Wait_com.

[0117] If the count result fed back by the wait counter 1037 reaches the set count value, the control finite state machine 1034 can determine that the communication transaction between the master device module 101 and the slave device module 102 is cleared at this time, and the slave device module 102 has waited for a period of time without receiving a new transaction request. At this time, the control finite state machine 1034 determines that the state of the slave device module 102 jumps from the Cnt state to the Idle state, that is, from the non-idle state to the idle state.

[0118] In some other embodiments, after the state monitoring module 1031 determines that the working state of the slave device module 102 has switched from the non-idle state to the idle state and sends a first signal to the gating switch 1032 to control the gating switch 1032 to turn off the clock signal of the slave device module 102, when the state monitoring module 1031 determines that the working state of the slave device module 102 has switched from the idle state to the non-idle state, the state monitoring module 1031 sends a second signal to the gating switch 1032 to control the gating switch 1032 to turn on the clock signal of the slave device module.

[0119] Among them, the above second signal can be any signal used to represent turning on the clock signal of the slave device module. For example, it can be a high-level signal.

[0120] As a more specific example, Figure 7 shows the system architecture diagram after connecting the state monitoring module 1031 in the power consumption controller proposed in this application to the master device module 101 and the slave device module 102, and the interaction schematic diagram between the specific structures inside the state monitoring module 1031.

[0121] Among them, as an example, the signals between the state monitoring module 1031 and the master device module 101 and the slave device module 102 are all AXI4 bus protocol signals.

[0122] Among them, aw_valid_i represents the write address request signal sent by the master device module 101 to the status monitoring module 1031, and aw_valid_o represents the status monitoring module 1031 sending this write address request signal to the slave device module 102. aw_ready_i represents the write address response signal (write address ready signal) sent by the slave device module 102 to the status monitoring module 1031, and aw_ready_o represents the status monitoring module 1031 sending this write address response signal to the master device module 101.

[0123] w_valid_i represents the write data request signal sent by the master device module 101 to the status monitoring module 1031, and w_valid_o represents the status monitoring module 1031 sending this write data request signal to the slave device module 102. w_ready_i represents the write data response signal (write data ready signal) sent by the slave device module 102 to the status monitoring module 1031, and w_ready_o represents the status monitoring module 1031 sending this write data response signal to the master device module 101.

[0124] ar_valid_i represents the read address request signal sent by the master device module 101 to the status monitoring module 1031, and ar_valid_o represents the status monitoring module 1031 sending this read address request signal to the slave device module 102. ar_ready_i represents the read address response signal (read address ready signal) sent by the slave device module 102 to the status monitoring module 1031, and ar_ready_o represents the status monitoring module 1031 sending this read address response signal to the master device module 101.

[0125] b_valid_i represents the write response request signal sent by the master device module 101 to the status monitoring module 1031, and b_valid_o represents the status monitoring module 1031 sending this write response request signal to the slave device module 102. b_ready_i represents the write response signal (write response ready signal) sent by the slave device module 102 to the status monitoring module 1031, and b_ready_o represents the status monitoring module 1031 sending this write response signal to the master device module 101.

[0126] r_valid_i represents the read data request signal sent by the master device module 101 to the status monitoring module 1031, and r_valid_o represents the status monitoring module 1031 sending this read data request signal to the slave device module 102. r_ready_i represents the read data response signal (read data ready signal) sent by the slave device module 102 to the status monitoring module 1031, and r_ready_o represents the status monitoring module 1031 sending this read data response signal to the master device module 101.

[0127] last represents the last data identification signal.

[0128] enable_i is an enable signal used to enable the function of the status monitoring module 1031, that is, to enable the power consumption control function of the slave device module. When enable_i is valid, for example, when enable_i is at a high level, the power consumption control function of the slave device module is enabled. At this time, the status monitoring module 1031 monitors the working status of the slave device module and controls the clock switch of the slave device module by outputting the busy_o signal. When enable_i is invalid, for example, when enable_i is at a low level, the power consumption control function of the slave device module is not started. At this time, the busy_o signal output by the status monitoring module 1031 keeps the clock signal of the slave device module in an always-on state through the gating switch 1032.

[0129] The wait_cnt signal is used to set the set count value of the wait counter, which is used to control the delay of turning off the clock signal of the slave device module 102.

[0130] The ready_delay_i signal is used to adjust the response delay time of the ready signal.

[0131] The busy_o signal represents the control signal output by the status monitoring module 1031 to the gating switch 1032, that is, it is used to output the first signal or the second signal.

[0132] Inside the status monitoring module 1031, the transaction counter 1035 sends the read transaction count result Rd_cnt, the write address transaction count result Aw_cnt, and the write data transaction count result W_cnt to the control finite state machine 1034.

[0133] The ready signal control module 1036 sends a ready signal to the control finite state machine, and the wait counter 1037 sends a count result cnt to the control finite state machine.

[0134] The control finite state machine 1034 sends a count trigger signal cnt_en and a reset signal cnt_rst to the wait counter 1037, and also sends a communication transaction count result busy_q to the ready signal control module 1036.

[0135] Another embodiment of the present application also proposes a power consumption control method, which is applied to a microprocessor architecture. The microprocessor architecture includes a master device module, a slave device module, and a power consumption controller connected by a bus. The specific structure of the microprocessor architecture can be seen in the above embodiment Figure 2 shown microprocessor architecture.

[0136] Specifically, as Figure 2As shown, in the power consumption controller of this microprocessor architecture, it includes a status monitoring module and a gating switch; the bus interface of the master device module is connected to the first bus interface of the status monitoring module, and the second bus interface of the status monitoring module is connected to the bus interface of the slave device module; the gating switch is connected to the input path of the clock signal of the slave device module;

[0137] See Figure 8 As shown, the method includes:

[0138] S101. The status monitoring module determines the working status of the slave device module by monitoring the bus signal.

[0139] S102. When it is determined that the working status of the slave device module switches from a non-idle state to an idle state, the status monitoring module sends a first signal to the gating switch; the first signal is used to control the gating switch to turn off the clock signal of the slave device module.

[0140] In some implementation manners, the gating switch includes a first contact, a second contact, and a control end; the status monitoring module includes a signal output end for outputting the first signal;

[0141] The first contact of the gating switch is connected to the clock signal source of the slave device module, the second contact of the gating switch is connected to the clock signal input end of the slave device module, and the control end is connected to the signal output end of the status monitoring module;

[0142] The method further includes:

[0143] When the status monitoring module sends the first signal to the gating switch, the gating switch controls the circuit between the first contact and the second contact to be disconnected to turn off the clock signal of the slave device module.

[0144] In some implementation manners, the status monitoring module includes:

[0145] A transaction statistics module and a control finite state machine;

[0146] The transaction statistics module determines the communication transaction status between the master device module and the slave device module by monitoring the bus signal, and sends the communication transaction status between the master device module and the slave device module to the control finite state machine;

[0147] The control finite state machine determines the working status of the slave device module according to the communication transaction status between the master device module and the slave device module, and sends the first signal to the gating switch when it is determined that the working status of the slave device module switches from a non-idle state to an idle state.

[0148] In some implementations, the transaction statistics module includes a transaction counter and a ready signal control module;

[0149] Wherein, the transaction counter counts the communication transactions between the master device module and the slave device module according to the request signal sent by the master device module, the ready signal sent by the ready signal control module, and the last data identification signal, and sends the transaction count result to the control finite state machine;

[0150] The ready signal control module sends a ready signal to the transaction counter and the control finite state machine according to the request response signal sent by the slave device module and the transaction count result sent by the control finite state machine;

[0151] The control finite state machine sends the transaction count result to the ready signal control module, determines the communication transaction state between the master device module and the slave device module according to the transaction count result and the ready signal, and determines the working state of the slave device module according to the communication transaction state.

[0152] In some implementations, the transaction counter includes a read transaction counter, a write address counter, and a write data counter;

[0153] Wherein, the read transaction counter counts the read transactions between the master device module and the slave device module according to the read request signal sent by the master device module, the read ready signal sent by the ready signal control module, and the last data identification signal, and sends the read transaction count result to the control finite state machine;

[0154] The write address counter counts the write address transactions between the master device module and the slave device module according to the write address request signal sent by the master device module and the write address ready signal sent by the ready signal control module, and sends the write address transaction count result to the control finite state machine;

[0155] The write data counter counts the write data transactions between the master device module and the slave device module according to the write data request signal sent by the master device module, the write data ready signal sent by the ready signal control module, and the last data identification signal, and sends the write data transaction count result to the control finite state machine.

[0156] In some implementations, the state monitoring module further includes a wait counter;

[0157] The method further includes:

[0158] When the control finite state machine determines that the communication transaction between the master device module and the slave device module is cleared, it sends a counting trigger signal to the waiting counter;

[0159] When the waiting counter receives the counting trigger signal, it starts counting and sends a counting result to the control finite state machine;

[0160] The control finite state machine determines the working state of the slave device module according to the communication transaction state between the master device module and the slave device module, including:

[0161] When the control finite state machine determines that the communication transaction between the master device module and the slave device module is cleared and the counting result sent by the waiting counter is equal to the set count value, it determines that the working state of the slave device module switches from a non-idle state to an idle state.

[0162] In some implementation manners, the working state of the slave device module includes an idle state, a ready state, a transaction processing state, and a waiting state;

[0163] Among them, the idle state includes a state where there is no current communication transaction or waiting for a new transaction request, the ready state includes a state of monitoring whether the transaction handshake is completed after receiving a transaction request, the transaction processing state includes a state of executing a communication transaction, and the waiting state includes a state where the communication transaction is processed and ready to switch to the idle state;

[0164] The method further includes:

[0165] When the state monitoring module determines that the working state of the slave device module is any one of the ready state, the transaction processing state, and the waiting state, it sends a second signal to the gating switch; the second signal is used to control the gating switch to turn on the clock signal of the slave device module.

[0166] In some implementation manners, the method further includes: when the state monitoring module determines that the working state of the slave device module switches from the idle state to the non-idle state, it sends a second signal to the gating switch; the second signal is used to control the gating switch to turn on the clock signal of the slave device module.

[0167] The power consumption control method provided in this embodiment belongs to the same inventive concept as the power consumption controller provided in the above embodiments of the present application. The power consumption controller described in the above embodiments can execute the power consumption control method provided in the embodiments of the present application and has corresponding functional modules for executing this power consumption control method. The power consumption control method provided in this embodiment has the same beneficial effects as the power consumption controller provided in the above embodiments. For technical details not described in detail in this embodiment, reference can be made to the specific introduction of the power consumption controller provided in the above embodiments of the present application, which will not be elaborated here.

[0168] Another embodiment of the present application also proposes a microprocessor architecture, in which a master device module, a slave device module, and the power consumption controller described in any of the above embodiments are connected through a bus.

[0169] Among them, for the specific structure of the power consumption controller in this microprocessor architecture and the connection relationship between this power consumption controller and the master device module and the slave device module, reference can be made to the microprocessor architecture provided in the above embodiments. The microprocessor architecture provided in this embodiment belongs to the same inventive concept as the power consumption controller, the power consumption control method provided in the above embodiments, or the power consumption controller provided in the above embodiments, and has the same beneficial effects. The specific introductions can all refer to the above embodiments, and will not be repeated here.

[0170] For the foregoing method embodiments, for the sake of simple description, they are all expressed as a series of action combinations. However, those skilled in the art should know that the present application is not limited by the described action sequence, because according to the present application, certain steps can be performed in other sequences or simultaneously. Secondly, those skilled in the art should also know that the embodiments described in the specification are all preferred embodiments, and the actions and modules involved are not necessarily essential to the present application.

[0171] It should be noted that the embodiments in this specification are all described in a progressive manner. Each embodiment focuses on the differences from other embodiments. The same or similar parts among the embodiments can be referred to each other. For device embodiments, since they are basically similar to the method embodiments, the description is relatively simple, and the relevant parts can refer to the partial description of the method embodiments.

[0172] The steps in the methods of the various embodiments of the present application can be adjusted, combined, and deleted according to actual needs. The technical features recorded in each embodiment can be replaced or combined.

[0173] The modules and sub-modules in the devices and terminals in the various embodiments of the present application can be combined, divided, and deleted according to actual needs.

[0174] In several embodiments provided by this application, it should be understood that the disclosed terminals, devices, and methods can be implemented in other ways. For example, the terminal embodiments described above are merely illustrative. For example, the division of modules or sub-modules is only a logical function division. In actual implementation, there may be other division methods. For example, multiple sub-modules or modules can be combined or integrated into another module, or some features can be ignored or not executed. Another point is that the displayed or discussed coupling, direct coupling, or communication connection to each other can be through some interfaces. The indirect coupling or communication connection of devices or modules can be in electrical, mechanical, or other forms.

[0175] The modules or sub-modules described as separate components may or may not be physically separated. The components as modules or sub-modules may or may not be physical modules or sub-modules, that is, they can be located in one place, or they can be distributed to multiple network modules or sub-modules. Some or all of the modules or sub-modules can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0176] In addition, in each embodiment of this application, the various functional modules or sub-modules can be integrated in a processing module, or each module or sub-module can exist physically alone, or two or more modules or sub-modules can be integrated in one module. The above-mentioned integrated modules or sub-modules can be implemented in the form of hardware or in the form of software functional modules or sub-modules.

[0177] Those skilled in the art can further realize that the units and algorithm steps of each example described in combination with the embodiments disclosed in this article can be implemented by electronic hardware, computer software, or a combination of the two. To clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described according to functions in the above description. Whether these functions are executed in a hardware or software manner depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods for each specific application to implement the described functions, but such implementation should not be considered to exceed the scope of this application.

[0178] The steps of the methods or algorithms described in combination with the embodiments disclosed in this article can be directly implemented by hardware, software units executed by a processor, or a combination of the two. The software units can be placed in a random access memory (RAM), internal memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, removable disk, CD-ROM, or any other form of storage medium well-known in the technical field.

[0179] Finally, it should also be noted that in this text, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device comprising a series of elements not only includes those elements, but also includes other elements not expressly listed, or further includes elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "comprising an..." does not exclude the presence of additional identical elements in the process, method, article or device comprising the said element.

[0180] The foregoing description of the disclosed embodiments enables those skilled in the art to implement or use the present application. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein can be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application will not be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A power consumption controller, characterized in that, Applied to a microprocessor architecture, the microprocessor architecture includes a master device module, a slave device module, and the power consumption controller connected by a bus; The power consumption controller includes a status monitoring module and a gating switch; the bus interface of the master device module is connected to the first bus interface of the status monitoring module, and the second bus interface of the status monitoring module is connected to the bus interface of the slave device module; the gating switch is connected to the input path of the clock signal of the slave device module; The status monitoring module determines the working status of the slave device module by monitoring the bus signal; When it is determined that the working status of the slave device module changes from a non-idle state to an idle state, the status monitoring module sends a first signal to the gating switch; the first signal is used to control the gating switch to turn off the clock signal of the slave device module.

2. The power consumption controller according to claim 1, wherein The gating switch includes a first contact, a second contact, and a control end; the status monitoring module includes a signal output end for outputting the first signal; The first contact of the gating switch is connected to the clock signal source of the slave device module, the second contact of the gating switch is connected to the clock signal input end of the slave device module, and the control end is connected to the signal output end of the status monitoring module; When the status monitoring module sends the first signal to the gating switch, the gating switch controls the circuit between the first contact and the second contact to be disconnected to turn off the clock signal of the slave device module.

3. The power consumption controller according to claim 1, characterized in that The status monitoring module includes: A transaction statistics module and a control finite state machine; The transaction statistics module determines the communication transaction status between the master device module and the slave device module by monitoring the bus signal, and sends the communication transaction status between the master device module and the slave device module to the control finite state machine; The control finite state machine determines the working status of the slave device module according to the communication transaction status between the master device module and the slave device module, and sends the first signal to the gating switch when it is determined that the working status of the slave device module changes from a non-idle state to an idle state.

4. The power consumption controller according to claim 3, characterized in that, The transaction statistics module includes a transaction counter and a ready signal control module; Wherein, the transaction counter counts the communication transactions between the master device module and the slave device module according to the request signal sent by the master device module, the ready signal sent by the ready signal control module, and the last data identification signal, and sends the transaction count result to the control finite state machine; The ready signal control module sends a ready signal to the transaction counter and the control finite state machine according to the request response signal sent by the slave device module and the transaction count result sent by the control finite state machine; The control finite state machine sends the transaction count result to the ready signal control module, determines the communication transaction status between the master device module and the slave device module according to the transaction count result and the ready signal, and determines the working status of the slave device module according to the communication transaction status.

5. The power consumption controller according to claim 4, wherein The transaction counter includes a read transaction counter, a write address counter, and a write data counter; Among them, the read transaction counter counts the read transactions between the master device module and the slave device module according to the read request signal sent by the master device module, the read preparation signal sent by the preparation signal control module, and the last data identification signal, and sends the read transaction count result to the control finite state machine; The write address counter counts the write address transactions between the master device module and the slave device module according to the write address request signal sent by the master device module and the write address preparation signal sent by the preparation signal control module, and sends the write address transaction count result to the control finite state machine; The write data counter counts the write data transactions between the master device module and the slave device module according to the write data request signal sent by the master device module, the write data preparation signal sent by the preparation signal control module, and the last data identification signal, and sends the write data transaction count result to the control finite state machine.

6. The power consumption controller according to any one of claims 3 to 5, characterized in that, The state monitoring module further includes a wait counter; When the control finite state machine determines to clear according to the communication transaction between the master device module and the slave device module, it sends a count trigger signal to the wait counter; The wait counter starts counting when it receives the count trigger signal and sends the count result to the control finite state machine; The control finite state machine determines the working state of the slave device module according to the communication transaction state between the master device module and the slave device module, including: When the control finite state machine determines to clear according to the communication transaction between the master device module and the slave device module and the count result sent by the wait counter is equal to the set count value, it determines that the working state of the slave device module switches from the non-idle state to the idle state.

7. The power consumption controller according to claim 1, characterized in that, The working state of the slave device module includes an idle state, a preparation state, a transaction processing state, and a wait state; Among them, the idle state includes the state where there is no current communication transaction or waiting for a new transaction request, the preparation state includes the state of monitoring whether the transaction handshake is completed after receiving the transaction request, the transaction processing state includes the state of executing the communication transaction, and the wait state includes the state of preparing to switch to the idle state after the communication transaction is processed; When the state monitoring module determines that the working state of the slave device module is any one of the preparation state, the transaction processing state, and the wait state, it sends a second signal to the gating switch; the second signal is used to control the gating switch to turn on the clock signal of the slave device module.

8. The power consumption controller according to any one of claims 1 to 5, characterized in that, When the state monitoring module determines that the working state of the slave device module switches from the idle state to the non-idle state, it sends a second signal to the gating switch; the second signal is used to control the gating switch to turn on the clock signal of the slave device module.

9. A power consumption control method, characterized in that, Applied to a microprocessor architecture, the microprocessor architecture includes a master device module, a slave device module, and a power consumption controller connected by a bus; The power consumption controller includes a status monitoring module and a gating switch; a bus interface of the master device module is connected to a first bus interface of the status monitoring module, and a second bus interface of the status monitoring module is connected to a bus interface of the slave device module; the gating switch is connected to an input path of a clock signal of the slave device module; The method includes: The status monitoring module determines the working status of the slave device module by monitoring bus signals; When it is determined that the working status of the slave device module changes from a non-idle state to an idle state, the status monitoring module sends a first signal to the gating switch; the first signal is used to control the gating switch to turn off the clock signal of the slave device module.

10. A microprocessor architecture, characterized in that, It includes a master device module, a slave device module and the power consumption controller according to any one of claims 1 to 7 connected by a bus.

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