Method and device for error detection, in particular error correction, in memory computing

Abstract

A method and apparatus for error detection, in particular error correction, in memory computations with a set of memory cells (102) for determining results of linear operations, characterized in that respective memory cells of the set of memory cells (102) comprise respective resistances, wherein the apparatus comprises the group of memory cells (102) and a memory cell for determining a checksum comprising a resistance that is the same or substantially the same as the sum of the respective resistances.

Description

Technical Field

[0001] The present invention relates to a method and apparatus for error detection, particularly error correction, in in-memory computing. Background Art

[0002] In memory, computing involves performing computations directly on data within the memory itself. Error detection mechanisms for in-memory computing (such as hardware lockstep) replace the replication of all computing resources. Summary of the Invention

[0003] An apparatus and method for error detection, particularly for error correction, in in-memory computing according to the independent claims provide a checksum mechanism that performs runtime error detection for linear operations (such as multiply-accumulate (MAC) arithmetic operations) by exploiting the linearity of, for example, MAC arithmetic operations. This mechanism scales well with limited overhead.

[0004] The apparatus is adapted to perform error detection, particularly error correction, in in-memory computing that utilizes a set of memory cells for determining the result of a linear operation, wherein a corresponding memory cell in the set of memory cells includes a corresponding resistor, and the apparatus includes the set of memory cells and at least one memory cell, particularly at least two memory cells, for determining a checksum, which includes a resistor that is the same as or substantially the same as the sum of the corresponding resistors. Thus, the output of the memory cells for determining the checksum corresponds to the sum of the outputs of the set of memory cells.

[0005] According to one example, the apparatus includes a processing element, wherein the processing element includes the set of memory cells and at least one memory cell for determining a checksum. This means that the checksum for the linear operation (such as MAC arithmetic operation) of the processing element is also determined within the processing element.

[0006] According to one example, the resistors of the memory cells in the set of memory cells and at least one memory cell for determining a checksum are connected to a common input line on one side of the corresponding resistors, and the other side of the corresponding resistors is connected to different output lines. This means that error detection for the linear operation (such as MAC arithmetic operation) of the set of memory cells connected to the common input line can be determined, particularly when an input is provided to the input line, the sum of the outputs of the set of memory cells is determined, and the sum is compared with the output of the memory cells connected to the same input line.

[0007] According to an example, the device includes a set of processing elements, where at least one memory cell for determining a checksum is arranged in a processing element different from the set of memory cells in the set of processing elements. This means that the checksum of the linear operations (such as MAC arithmetic operations) of the processing elements is determined in a separate processing element.

[0008] According to an example, the resistors of the memory cells in the set of memory cells are connected to a common output line on one side of the respective resistor and to different input lines on the other side of the respective resistor. This means that by providing respective inputs to different input lines of the set of memory cells and providing the sum of the respective inputs to at least one memory cell for determining the checksum connected to the same output line at different times, error detection of the linear operations (such as MAC arithmetic operations) of the set of memory cells connected to the common output line can be determined.

[0009] According to an example, the resistors of the memory cells in the set of memory cells are connected to a common output line on one side of the respective resistor and to a common input line on the other side of the respective resistor.

[0010] According to an example, the device includes a controller configured to compare the output of the set of memory cells with a checksum and detect an error when the output and the checksum are different, where the device is configured to provide the output and the checksum to the controller.

[0011] For error correction, the device includes a controller configured to add the difference between the output and the checksum to the output when an error is detected. This means that the output of the set of memory cells is corrected with the difference.

[0012] According to an example, the device includes a processing element having a first part of a crossbar including memory cells and a processing element having a second part of a crossbar including memory cells, where a first memory cell of the set of memory cells is arranged in the first part of the crossbar, where a second memory cell of the set of memory cells is arranged in the second part of the crossbar, where the device includes an output adder configured to add the outputs of the first memory cell and the second memory cell to the output of the set of memory cells. In the case where the memory cells of the set of memory cells for linear operations (such as MAC arithmetic operations) are distributed in different processing elements, the output adder generates an output that can be verified against the checksum in error detection.

[0013] According to one example, the device includes a processing element having a portion of a first crossbar including memory cells, and a processing element having a portion of a second crossbar including memory cells, wherein a first memory cell of the set of memory cells is arranged in the portion of the first crossbar, wherein a second memory cell of the set of memory cells is arranged in the portion of the second crossbar, and wherein the device includes an input adder configured to add an input of the crossbar to an input of a memory cell for determining a checksum and provide the input to the memory cell for determining the checksum. The input adder produces an output that results in a checksum, which can be used for error detection in the case where the memory cells of the set of memory cells for linear operations (such as MAC arithmetic operations) are distributed across different crossbars of different processing elements.

[0014] According to one example, the set of memory cells and at least one memory cell for determining a checksum are arranged in a memory cell arrangement that includes a processing element containing the set of memory cells and at least one memory cell for determining a checksum, a set of processing elements, and another set of memory cells, and at least one additional memory cell for determining a checksum of the other set of memory cells, wherein the at least one additional memory cell is arranged in a processing element of the set of processing elements different from the other set of memory cells. This means that another memory cell for determining a checksum is in a different processing element from the other set of memory cells for error correction. The different processing elements can be the same processing element including memory cells for error correction of the set of memory cells, or another processing element.

[0015] For error detection and correction, the device can include memory cells for determining two redundant checksums, and memory cells for parity checking of the two redundant checksums, wherein the memory cells for determining parity checking include a resistance that is the same as the sum of the resistances of the memory cells providing the least significant bits of the two redundant checksums.

[0016] A method for error detection, particularly error correction, in in-memory computing using a set of memory cells for determining the result of a linear operation, wherein respective memory cells in the set of memory cells include respective resistances, the method including providing at least one memory cell, particularly at least two memory cells, for determining a checksum, which includes a resistance that is the same as or substantially the same as the sum of the respective resistances; determining an output of the set of memory cells and providing an input to the memory cell for determining the checksum; comparing the output with the checksum; and detecting an error in the case where the output and the checksum are different.

[0017] The following examples relate to aspects of providing an output of at least one memory cell for determining a checksum and determining a sum of outputs of the set of memory cells for error detection.

[0018] According to one example, the method includes determining corresponding outputs of corresponding memory cells of the set of memory cells and a checksum, the checksum being generated by providing the same input to a memory cell of the set of memory cells and at least one memory cell for determining the checksum; and adding the corresponding outputs of the corresponding memory cells of the set of memory cells to the output.

[0019] According to one example, the method includes providing corresponding voltages to memory cells of the set of memory cells for determining corresponding outputs of the corresponding memory cells of the set of memory cells; adding the corresponding outputs to the output; adding the corresponding input to an input of at least one memory cell for determining the checksum; and providing the input to the memory cell for determining the checksum.

[0020] For error correction, the method includes adding a difference between the checksum and the output to the output when an error is detected.

[0021] According to one example, a first memory cell of the set of memory cells is associated with a first horizontal and vertical part in a first processing element, wherein a second memory cell of the set of memory cells is associated with a second horizontal and vertical part in a second processing element, wherein outputs of the first memory cell and the second memory cell are added to the output of the set of memory cells.

[0022] According to one example, a first memory cell of the set of memory cells is associated with a first horizontal and vertical part in a first processing element, wherein a second memory cell of the set of memory cells is associated with a second horizontal and vertical part in a second processing element, wherein the horizontal and vertical inputs are added to an input of at least one memory cell for determining the checksum.

[0023] For error detection and correction, the method may include checking the parity of memory cells for determining two redundant checksums, wherein the memory cells are for parity checking of the two redundant checksums, wherein the memory cells for determining the parity check include a resistance that is the same as the sum of the resistances of the memory cells providing the least significant bits of the two redundant checksums; recalculating (1004) the checksum in the case of a parity check failure; and otherwise correcting (1016) the error indicated by the two redundant checksums. Description of the Drawings

[0024] Further advantageous embodiments can be derived from the following description and the drawings. In the drawings, Figure 1 a device for in-memory computing is schematically depicted, Figure 2 Schematically depicts a processing element having a channel checksum adder unit Figure 3 Depicts a flowchart depicting steps of a first exemplary method for error detection Figure 4 Schematically depicts a processing element having additional rows of processing elements Figure 5 Depicts a flowchart depicting steps of a first version of a second exemplary method for error detection Figure 6 Schematically depicts a processing element having additional columns of processing elements Figure 7 Depicts a flowchart depicting steps of a second version of a second exemplary method for error detection Figure 8 Depicts a flowchart depicting steps of a method for error correction Figure 9 Schematically depicts a processing element having a cross - checksum and a processing element having parity columns Figure 10 Depicts a flowchart depicting steps of a method for error detection and correction Detailed Description

[0025] In - memory computing (IMC) includes performing data calculations directly within a memory

[0026] The following description relates to hardware security mechanisms that contribute to providing reliable execution of IMC

[0027] According to some examples, errors occurring during a calculation are detected. According to some examples, detected errors are also corrected

[0028] IMC can be used to determine the result of a linear operation. An example of a linear operation is a multiply - add (MAC) arithmetic operation

[0029] According to one example, a memory includes a regular grid of memory cells that store a linear operation or multiple linear operations, such as parameters of a MAC arithmetic operation performed as respective resistance values

[0030] For example, IMC of MAC is used to determine a prediction of a neural network that includes MAC arithmetic operations to map input data of the neural network to a prediction according to parameters of the neural network. The MAC arithmetic operations of the neural network can be implemented in a hardware accelerator, where the parameters of the MAC arithmetic operation define resistance values in a grid

[0031] Neural networks are used, for example, in deep learning algorithms. They are also used, for example, in the automotive field. They are configured, for example, to output a classification representing an object from a set of detectable objects. They are configured, for example, to output a classification based on input data representing a digital image.

[0032] Figure 1 An apparatus 100 for IMC is schematically depicted.

[0033] Device 100 includes a grid of memory cells 102. Memory cells 102 within the same column and row of the grid share vertical and horizontal conductive lines, respectively.

[0034] Figure 1 An example of N=4 rows and M=4 columns is depicted. The grid is not limited to 4 rows and 4 columns. The grid may include more than 4 rows and more than 4 columns.

[0035] This means that the device comprises part of a horizontal and vertical scheme, wherein the horizontal and vertical comprise memory cells 102 connected by the same conductive line in the same row. The memory cells 102 comprise resistors. According to an example, the respective resistors G are programmed according to respective parameters of a linear operation (e.g., a MAC arithmetic operation). c .

[0036] IMC is summarized in the following way: The digital-to-analog converter DAC 104 is used to convert the digital input into a signal in the analog domain, that is, the input voltage V i In this example, a DAC 104 provides a corresponding input voltage V to one of the horizontal and vertical i，n The digital input represents, for example, an input operand of a linear operation (eg, a MAC arithmetic operation).

[0037] An analog signal is applied and propagates to each row within the grid containing memory cells 102 to be programmed.

[0038] Using Ohm's law, determine the output current I of the corresponding memory cell 102 c , that is, a multiplication is performed between the analog input and the resistance value stored in the corresponding programmed memory cell 102. I c =V i G c

[0039] Using Kirchhoff's law, the output current I c The sum of the output currents I c The output current I o，mConvert back to the digital domain. In this example, corresponding sample-and-hold devices 108 are provided for the respective columns. The sample-and-hold devices 108 are configured to sample and hold the output current I of the respective columns o，m . In this example, the ADC 106 is configured to process the output current I available in the sample-and-hold devices 108 o，m .

[0040] The device 100 includes a computing device 110, which is configured to determine a digital result of a linear operation (such as a MAC arithmetic operation) based on the digital output of the ADC 106. In this example, the computing device 110 is configured to shift the digital output of the ADC 106

[0041] According to one example, the DAC 102 is controllable to output a corresponding input voltage V to the respective rows, and the sample-and-hold devices 108 are controllable to sample and hold the output current I of the respective columns coordinated by the controller 112 i，n . The controller 112 is configured, for example, to trigger the DAC 102 to provide the input voltage V to the respective rows o，m . And trigger the sample-and-hold devices 108 to sample and hold the corresponding output current I according to the linear operation (such as a MAC arithmetic operation) implemented by the device 100 i，n . o，m .

[0042] A linear operation, such as a MAC arithmetic operation, can be a sub-part of a calculation

[0043] Logically, a sub-array of the grid can be regarded as a separate processing element PE. Each row of the PE includes a part of the vertical and horizontal, that is, a part of the memory cells 102 of that row. The PE is configured, for example, to perform, in particular, to perform sub-parts of the calculation in parallel

[0044] The resistor can have a resistance value corresponding to a parameter value. These parameters can represent the weights of the neural network

[0045] The input voltage V i，n can have a value corresponding to the activation value of the neural network

[0046] Then, the device 100 can be used to accelerate linear operations, such as MAC arithmetic operations, especially in the neurons of the neural network

[0047] For error detection, the checksum mechanism is implemented at least partially in hardware

[0048] First example: According to the first example, the checksum mechanism includes a channel checksum adder unit O ccadd . According to the second example, the checksum mechanism includes a batch checksum adder unit Obcadd .

[0049] In the following equation, the variable x corresponds to the input, the variable w corresponds to the stored weights, n is the PE index, c is the index of the column of each grid within each PE, and k is the index of the row of each grid within each PE.

[0050] According to the first example, the checksum of the PE block is implemented inside the PE block. According to the first example, the PE block includes an additional column O Wadd , and the additional column includes a resistor whose value corresponds to the sum of the resistors representing the parameters of the rows in the horizontal and vertical parts of the PE.

[0051] Figure 2 Four exemplary PEs are schematically depicted, the first PE n1 , the second PE n2 , the third PE n3 and the fourth PE n4 . Each includes a corresponding channel checksum adder unit 202. In this example, the channel checksum adder unit 202 includes the corresponding last columns of the four exemplary PEs.

[0052] The PEs each include k rows having corresponding input terminals x1, x2, x3,..., x k . The PEs each include c / 2 columns for linear operations, such as MAC arithmetic operations, and one column for partial checksum. In this example, the resistance value of the memory cell in the column of the checksum value of the corresponding PE, i.e., the weight, is the sum of the resistance values of the other memory cells of the corresponding PE in the same row as the memory cell in the column of the checksum, i.e., the weights.

[0053] According to one example, the weights of the first PE n1 are w 1，1 , w 1，2 , w 1，3 ,..., w k，c / 2 . According to one example, the weights of the second PE n2 are w 1，c / 2+1 , w 1，2 , w 1，3 ,..., w k，c . According to one example, the weights of the third PE n3 are w 1，1 , w 1，2 , w 1，3 ,..., w k，c / 2 . According to one example, the weights of the fourth PE n4 are w 1，c / 2+1 , w 1，2 , w 1，3 ,..., w k，c .

[0054] Program the weight values according to a linear operation, such as a MAC arithmetic operation, in particular the weights of the neural network part represented by the corresponding PE.

[0055] According to a first example, the input buffer 204 is configured to provide a first input to the first PE n1 Provide a first input Provide a second input to the second PE n2 Provide a second input Provide a third input to the third PE n3 Provide a third input Provide a fourth input to the fourth PE n4 Provide a fourth input The first input The second input The third input And the fourth input The values of are determined by the operands of the corresponding linear operation, such as a MAC arithmetic operation, in particular the input of the neural network part represented by the corresponding PE.

[0056] The output of a column corresponds to the result of a single linear operation, such as a single MAC arithmetic operation, in particular within a neuron in a single PE.

[0057] Checksum The results from the same input are fed to an additional linear operation in the last row of the corresponding PE.

[0058] Figure 3 Describes a first example of an error detection method.

[0059] The method according to the first example includes step 302.

[0060] Step 302 includes determining the sum of the column outputs of the PE in response to providing the corresponding input to the corresponding PE.

[0061] Step 302 includes determining a checksum for the corresponding column n in response to providing the corresponding input to the corresponding PE

[0062] The method according to the first example includes step 304.

[0063] Step 304 includes comparing the sum of the column n outputs of the PE with the checksum of column n for at least one column n Make a comparison. If the sum of the outputs of column n of the PE matches the checksum Match, then the calculation is correctly executed, otherwise a fault occurs in the sum of that column (i.e., the vertical and horizontal) or in the checksum of column n There is a fault.

[0064] This error detection is based on the following: Second example: The second example is described by examples of a first version and a second version, where the difference between the first version and the second version lies in the way of reusing the parameters of linear operations (such as MAC arithmetic operations).

[0065] According to the checksum mechanism of the first version, resistors, i.e., weights, are reused in the same column of the corresponding PEs. The checksum mechanism includes additional PE rows that contain the sum of the resistors stored within the corresponding PE columns, i.e., the sum of the weight values.

[0066] Figure 4 A part of the corresponding PEs of a set of four PEs including a first PE n1 , a second PE n2 , a third PE n3 and a fourth PE n4 is schematically described, where the additional rows include a first additional PE BCADD，1 and a second additional PE BCADD，2 . The first PE n1 , the third PE n3 and the first additional PE BCADD，1 are arranged in the same column. The second PE n2 , the fourth PE n4 and the second additional PE BCADD，2 are arranged in the same column.

[0067] The first version of the checksum mechanism according to the second example is not limited to four PEs and two additional PEs. According to the first version, more than two columns and more than two rows of PEs can be provided.

[0068] According to the first version, the checksum mechanism includes corresponding accumulator adders 402 in the first column and the second column.

[0069] The corresponding accumulator adders 402 are configured to add the outputs of each horizontal and vertical from different PEs within the same column, maintaining the same index. The accumulator adders 402 respectively obtain vectors of values corresponding to the accumulation results for each column from different horizontals and verticals. According to the example with c columns of memory cells, the accumulator adder 402 for the first column of PEs is configured to output and the accumulator adder 402 for the second column of PEs is configured to output According to the first version, the checksum mechanism includes a buffer 404, which is configured to provide corresponding inputs to the corresponding PEs.

[0070] The buffer 404 in this example is configured to provide corresponding inputs to the respective PEs, as described for buffer 204 and PEs according to the first example.

[0071] According to an example with a memory cell having k rows and c columns, the resistance, i.e., the first PE n1 has weights w 1，1 , w 1，2 , w 1，3 ,..., w k，c / 2 . According to an example, the resistance, i.e., the second PE n2 has weights w 1，c / 2+1 , w 1，2 , w 1，3 ,..., w k，c . According to an example, the resistance, i.e., the third PE n3 has weights w 1，1 , w 1，2 , w 1，3 ,..., w k，c / 2 . According to an example, the resistance, i.e., the fourth PE n4 has weights w 1，c / 2+1 , w 1，2 , w 1，3 ,..., w k，c .

[0072] According to an example with a memory cell having k rows and c columns, the resistance, i.e., the first additional PE BCADD，1 has weights w 1，1 , w 1，2 , w 1，3 ,..., w k，c / 2 . According to an example, the resistance, i.e., the second PE BCADD，2 has weights w 1，c / 2+1 , w 1，2 , w 1，3 , …, w k，c .

[0073] The column outputs of the memory cells of the first additional PE in this example BCADD，1 correspond to the checksum O 1，n , O 2，n , O 3，n ,..., O c / 2，n . The column outputs of the memory cells of the second additional PE in this example BCADD，2 correspond to the checksum O c / 2+1，n , O c / 2+2，n , O c / 2+3，n ,..., O c，n . According to the first version, the checksum mechanism includes the input adder 406.

[0074] The input adder 404 is configured to add together the input values fed to each row of PEs, maintaining the same row index for the row in both the horizontal and vertical directions. The input adder 404 is configured to add the input values to a second vector O Iadd that has the values of the cumulative inputs corresponding to the different rows given to the PEs.

[0075] According to an example including k rows of memory cells, the input adder 404 is configured to add the n input values of an additional PE to the vector O of that additional PE Iadd : ∑ n x1, ∑ n x2, ∑ n x3,..., ∑ n x k According to the first version, the checksum mechanism includes providing the second vector O Iadd to an additional row that contains the same parameters from the same columns of the PEs: Figure 5 Depicts a first variant of a second example of a method for error detection.

[0076] The method according to the first variant of the second example includes step 502.

[0077] Step 502 includes determining, in particular using the input adder 406, the respective sum ∑ n x i .

[0078] Step 502 includes determining the respective checksums O 1，n , O 2，n , O 3，n , O 4 / 2，n , O c / 2+1，n , O c / 2+2，n , O c / 2+3，n , O c / 2+4，n .

[0079] Step 502 includes, in particular using the accumulator adder 402, determining the sum of the outputs of the same index of different PEs in the same column j of the same PE column in response to providing the respective inputs to the respective PEs

[0080] The method according to the first variant of the second example includes step 504.

[0081] Step 504 includes, for at least one column j, comparing the sum of the outputs of the same index of different PEs in the same column j of the same column PEs with the respective checksum O j，n of column j. If the sum of the outputs of column j at the same index in different PEs in the same column of PEs matches the corresponding checksum O of column j j，n then the calculation of column j has been correctly performed, otherwise the checksum O j，n or the sum contains an error. If the sum of the outputs of a column j does not match the corresponding checksum O of that column j j，n then the calculation of that column j has been incorrectly performed. If the sum matches the checksum O of column c of the memory cell j，n then the entire calculation is correct. Otherwise an error occurs.

[0082] This error detection is based on the following: According to the second version of the second example, the inputs are reused within the same row of PEs

[0083] The checksum mechanism according to the second version is configured with additional PEs as described for the first version, and the additional PEs are provided in additional columns rather than additional rows.

[0084] Figure 6 Four PEs, processing elements with additional columns, are schematically depicted. The first PE n1 , the second PE n2 and the first additional PE BCADD，1 are arranged in the same row. The third PE n2 , the fourth PE n4 and the second additional PE BCADD，2 are arranged in the same row.

[0085] Compared to the first version, the additional PEs according to the second version include resistors, i.e., weights programmed as the sum of resistors i.e., weights stored within the same column index of the crossbar that is part of the corresponding row of the PE.

[0086] This error detection is based on the same considerations as the first version, applied to the resistors, i.e., the weights of different PEs.

[0087] The resistor, i.e., the weight w, of row i and column j in the additional PE i，j is the sum of the resistors (i.e., the resistances) of the same row i and column j of n PEs, i.e., the sum of the weights: The first additional PE BCPE，1 is configured for the first row output of the PE checksum O 1，n , O 2，n , O3，n , ..., O c / 2，n . Second additional PE BCPE，2 configured to output for the second row PE checksum O 1，n , O 2，n , O 3，n , ..., O c / 2，n O 1，n , O 2，n , O 3，n , ..., O c / 2，n According to the second version, the input set from the corresponding row of the PE is fed to the corresponding PE belonging to the corresponding additional column.

[0088] According to the second version, the checksum mechanism includes corresponding output adders 602 for the rows, which are configured to add the outputs of the vertical and horizontal directions from different PEs within the same row j, maintaining the same index. The output adder 602 for row j of the PEs is configured to output a vector including the sum for row j: Figure 7 A flowchart depicting the steps of the second version including a second exemplary method for error detection is shown.

[0089] The method according to the second variant of the second example includes step 702.

[0090] Step 702 includes determining the checksum in response to providing the corresponding input to the corresponding additional PE, specifically as the output of column i of the memory cell of the additional PEj of row j O i，j .

[0091] Step 702 includes, for the corresponding row j, specifically using the corresponding output adder 602, determining the sum

[0092] The method according to the second variant of the second example includes step 704.

[0093] Step 704 includes comparing the corresponding output with the corresponding checksum O i，j .

[0094] If the corresponding output matches the corresponding checksum O i，j , the calculation is correctly performed, otherwise an error will occur in the checksum O i，j or the sum .

[0095] 3] Figure 8A flowchart including a method for error correction is schematically described. The method for error correction is based on the method for error correction according to the first example and the second example.

[0096] The method for error correction includes step 802.

[0097] Step 802 includes determining output O c and checksum O BCPE，c according to the first example of the method for error detection, and determining output O n and checksum O n，CCPE .

[0098] The method for error correction includes step 804.

[0099] Step 804 includes detecting a mismatch in the calculation of at least one horizontal or vertical column.

[0100] The method for error correction includes step 806.

[0101] Step 806 includes determining the sum of the differences between the calculation of output O c and the checksum O c of output O n，BCPE O c，BCADD = ∑(O BCPE，c - O c ) and the sum of the differences between the calculation of output O n and the checksum O n of output O n，BCPE O n，CCADD n，BCPE = ∑(O n - O c，BCADD ) .

[0102] The method for error correction includes step 808.

[0103] Step 808 includes determining whether sum O c，BCADD and sum O n，CCADD are the same. In the case where the sums match, i.e., O c，BCADD == O n，CCADD , step 810 is executed.

[0104] Otherwise, the fail-safe system is activated in step 812.

[0105] In the case where the sums match, the failure occurred during the original calculation, rather than during the calculation of one of the two checksums.

[0106] The indices of the two checksums provide coordinates to identify in which row and column or in which row and column of which PE or in which PE the fault occurs.

[0107] According to the first version of the second example of the method for error detection, the index n of O n，BCADD corresponds to the row of the matrix of PEs, and the index c of O c，BCADD corresponds to the column of the grid within the corresponding PE.

[0108] According to the second version of the second example of the method for error detection, the index n of O c，BCADD corresponds to the column of the matrix of PEs, and the index c of O c，BCADD corresponds to the column of the grid within the corresponding PE.

[0109] In step 810, it is determined whether the number of faulty rows and columns is 1. If the number of faulty rows and columns is one, step 814 is executed. Otherwise, step 816 is executed.

[0110] In step 814, the fault is corrected by adding the difference Δ. For example, for the first PE n1 the faulty output determine the corrected output of the first PE n1 the corrected output For example, for the second PE n2 the faulty output determine the corrected output of the second PE n2 the corrected output An example of determining the corrected output is: After step 814, step 818 is executed.

[0111] In step 818, the corrected output is used, for example, to determine the prediction of the neural network.

[0112] Step 816 includes determining whether the number of faulty PEs is 1. If the number of faulty PEs is one, step 820 is executed. Otherwise, step 822 is executed.

[0113] In step 820, the fault is corrected by adding the difference Δ calculated for one or more corresponding columns to the output of the row and column (one or more) within the single faulty PE. the difference Δ calculated for one or more corresponding columns of the single faulty PE.

[0114] In this case, according to the first version of the second example, the difference Δ calculated for a single column corresponds to the error that occurs within a specific PE belonging to the n-th row of the matrix of PEs.

[0115] In this case, according to the second version of the second example, the difference Δ calculated for a single column corresponds to an error occurring within a particular PE belonging to the n-th column of the matrix of PEs.

[0116] One example for determining the corrected output is: After step 820, step 818 is executed.

[0117] In step 822, the fault can be reported or corrected in different ways.

[0118] For example, the calculation can be repeated.

[0119] Optionally, step 824 can be executed. In step 824, additional redundant columns can be added.

[0120] Then the calculation can be repeated using the additional redundant columns.

[0121] The additional redundant columns can be used to replace the faulty cells within the rows and columns.

[0122] In the case of implementing both versions of the second example simultaneously, the same steps of the error correction method can be repeated to increase the fault correction coverage of the method for error correction.

[0123] The selection of the second example version can be based on the cost of the additional hardware. To obtain the best trade-off between error correction capabilities and area overhead, the selection can be made on a case-by-case basis according to the structure of the hardware accelerator.

[0124] The method for error correction is capable of handling random or accidental hardware faults. The method for error correction is capable of detecting a correct bit flip that has been maliciously introduced by an adversary.

[0125] A fault injection attack in a volatile or non-volatile memory can be induced, for example, by a large number of write processes to adjacent memory cells that generate thermal crosstalk.

[0126] According to one example, device 100 is configured to provide an output and a checksum to the controller.

[0127] According to one example, controller 112 is configured to execute the method.

[0128] Controller 112 is configured, for example, to compare the output of the set of memory cells 102 with the checksum and detect an error when the output and the checksum are different.

[0129] According to one example, controller 112 is configured to add the difference Δ to the output when an error is detected.

[0130] The input adder 406 can be a digital adder configured to add the inputs determined for the respective PEs by the controller 112 digitally. The input adder 406 can be configured to trigger the DAC of the PE including the memory cell 102 to determine the checksum to output the input voltage according to the sum of the inputs.

[0131] The output adder 602 can be a digital adder configured to receive the respective outputs digitally and add the outputs digitally.

[0132] The accumulator adder 402 can be a digital adder configured to receive the respective outputs digitally and add the outputs.

[0133] In principle, these adders can be analog adders, and the outputs of these adders can also be analog.

[0134] In the following, in the method for error detection and correction, in the scenario where an error occurs in the calculation of one of the two redundant checksums horizontally and vertically, or in the scenario where multiple errors occur simultaneously in the columns of more horizontal and vertical lines belonging to different PEs, the errors are considered.

[0135] If the values of the two redundant checksums are different, the method for error detection and correction may include stalling. During the stalling, at least one of the checksums is repeatedly determined until the values of the two checksums match. This mitigates the errors caused by transient faults.

[0136] If multiple errors are detected in the columns of more horizontal and vertical lines belonging to different PEs, the method for error detection and correction can include stalling. During the stalling, at least one output or at least one checksum that causes at least one of the multiple errors is repeatedly determined until only one error is detected or no error is detected. This allows the faulty logic that causes multiple errors to recalculate the result and mitigates the presence of errors caused by transient faults.

[0137] According to this example, the above checksum values are calculated in the original design.

[0138] The method for error detection and correction can include additional cycles for recalculating the checksum values in the following two cases.

[0139] Continuous MAC recalculation: After a fixed number of consecutive stalls are calculated in the original design, additional cycles for recalculating the checksum are introduced.

[0140] This fixed number can be preset, or the method can include determining this fixed number according to the input of the hardware designer. This allows the hardware designer to preset or select the fixed number according to the technology being tested.

[0141] Parity check: Parity check columns can be used. According to one example, a parity check column includes, for example, an additional column of memory cells programmed with a parity check code that maps Hamming weight values within the redundancy checksum and horizontally and vertically. For example, the parity check is: Figure 9 An exemplary PE with a redundant horizontal and vertical checksum adder unit 902 is schematically described. Figure 9 The first PE is depicted n1 and the second PE n2 with corresponding redundant horizontal and vertical checksum adder units 902. Figure 9 An exemplary PE with a parity check unit 904 is schematically depicted c .

[0142] In this example, the redundant horizontal and vertical checksum adder unit 902 includes the last two columns of the corresponding PE with the redundant horizontal and vertical checksum adder unit 902.

[0143] In this example, the parity check unit 904 includes the last column of the PE c .

[0144] The PEs each include 4 rows with corresponding inputs Ink1, Ink2, Ink3, Ink4. The first PE n1 and the second PE n2 each include 4 columns for linear operations (such as MAC arithmetic operations), and two columns for the checksum part. In this example, the resistance values (i.e., weights) of the memory cells in the columns of the checksum values of the corresponding PEs are the sum of the resistance values (i.e., weights) of the other memory cells of the corresponding PEs in the same row as the memory cells in the columns of the checksum.

[0145] According to one example, the weights of the first PE n1 are w b3 / n1 , w b2，n1 , w b1，n1 , w b0，n1 . According to one example, the weights of the second PE n2 are w b3 / n2 , w b2，n2 , w b1，n2 , w b0，n2 .

[0146] According to the linear operation, such as MAC arithmetic operation, the weight values are programmed, particularly the weights of the part of the neural network represented by the corresponding PE.

[0147] The output of the column corresponds to the result of a single linear operation, such as a single MAC arithmetic operation, particularly within a neuron inside a single PE.

[0148] The first PE n1 The outputs of the first to fourth columns are O b3，n1 , O b2，n1 , O b1，n1 , O b0，n1 . The first PE n1 The horizontal and vertical checksums in are O b = ∑ b w b，n1 . The second PE n2 The outputs of the first to fourth columns are O b3，n2 , O b2，n2 , O b1，n2 , O b0，n2 . The second PE n2 The horizontal and vertical checksums in are O b = ∑ b w b，n2 . According to an example, the memory cells in the PE c i.e., whose weights are ∑ n w b，n . The output of the parity check column, i.e., the parity check unit 904 in the PE c is PE c The outputs of the first to fourth columns are Figure 10 Depicts a flowchart including steps of a method for error detection and correction.

[0149] The method includes step 1002.

[0150] In step 1002, the MAC output is determined.

[0151] The method includes step 1004.

[0152] In step 1004, the checksum is determined. The checksum is determined for a predetermined MAC output. The checksum is associated with the MAC output for which it is determined.

[0153] The method includes step 1006.

[0154] In step 1006, the difference between the MAC output and the checksum associated with it is determined.

[0155] The method includes step 1008.

[0156] In step 1008, it is determined whether an error is detected. For example, an error is detected when there is a difference between the checksum and the MAC output associated with the checksum that exists or exceeds a predetermined threshold. For example, if there is no difference between the checksum and the MAC output associated with the corresponding checksum, no error is detected.

[0157] In the case where there is no error, step 1002 is performed for the new MAC output.

[0158] In the case where at least one error is detected, step 1010 is performed.

[0159] In step 1010, it is determined whether a single error is detected or more than one error is detected.

[0160] If a single error is detected, step 1012 is performed. Otherwise, step 1014 is performed.

[0161] In step 1012, parity check is performed.

[0162] In the case where the parity check is not successful, step 1004 is performed to recalculate the checksum.

[0163] Otherwise, step 1016 is performed.

[0164] In step 1016, the error is corrected.

[0165] This means that the MAC output calculation is corrected during runtime without pausing.

[0166] In step 1014, it is determined whether there are multiple errors in more rows and columns belonging to different PEs.

[0167] If there are multiple errors in one PE, step 1012 is performed.

[0168] Otherwise, step 1018 is performed.

[0169] In step 1018, it is determined whether the method has reached the number of pauses. If the method has reached the number of pauses, step 1002 is performed to recalculate the MAC output. Otherwise, step 1004 is performed to recalculate the checksum without recalculating the MAC output.

[0170] This means that if the number of pauses is reached, the method pauses for the MAC output calculation.

[0171] The number of columns used for the checksum in a PE can vary because the number of columns depends on the number of states that can be represented by a single memory cell in the horizontal and vertical directions.

[0172] According to an example, the original horizontal and vertical represent the following values of the MAC output: In the case where each memory cell can represent only 2 binary states (0 or 1), the horizontal and vertical will consist of at least 3 columns and 4 rows, with each column representing the bit validity of the value and each row representing a different weight: 1 will be mapped to => 001 4 will be mapped to => 100 7 will be mapped to => 111 3 will be mapped to => 011 Assuming that in this case all 3 columns are protected by the checksum, each row of the checksum will have to map the maximum value 3, i.e., 7 => 111 => 1 + 1 + 1 = 3 = 11, in binary.

[0173] Therefore, in this case, the checksum consists of two columns: 1 = 1 => 01 4 = 1 => 01 7 = 3 => 11 3 = 2 => 10 In the case where each memory cell represents 4 states, such as "00, 01, 10, 11", the number of columns of the checksum is exactly 1.

[0174] The parity column is actually a concept similar to the single-column checksum, but its purpose is different. The parity column is not used for correction; it is only used to further check whether the value of the checksum output is actually consistent. According to an example, the parity column represents only the least significant bit of the checksum and is just one column.

[0175] Assuming that the above values do not come from the MAC output but from the checksum, the parity column will be:

Claims

1. A device (100) for error detection, in particular error correction, in in-memory computing using a set of memory cells (102) for determining the result of a linear operation, characterized in that, Each memory cell in the set of memory cells (102) includes a respective resistor, wherein the device (100) includes the set of memory cells (102) and at least one memory cell (102), in particular at least two memory cells, for determining a checksum, which includes a resistor that is the same as or substantially the same as the sum of the respective resistors.

2. The device (100) according to claim 1, characterized in that, The device (100) includes a processing element, wherein the processing element includes the set of memory cells (102) and at least one memory cell (102) for determining a checksum.

3. The device (100) according to claim 1 or 2, characterized in that, The resistors of the memory cells (102) in the set of memory cells (102) and at least one memory cell (102) for determining a checksum are connected to a common input line on one side of the respective resistors, and wherein the other side of the respective resistors is connected to different output lines.

4. The device (100) according to claim 1, characterized in that, The device (100) includes a set of processing elements, wherein at least one memory cell (102) for determining a checksum is arranged in a processing element different from the set of memory cells (102) in the set of processing elements.

5. The device (100) according to claim 4, characterized in that, The resistors of the memory cells (102) in the set of memory cells (102) are connected to a common output line on one side of the respective resistors and to different input lines on the other side of the respective resistors.

6. The device (100) according to claim 4, characterized in that, The resistors of the memory cells (102) in the set of memory cells (102) are connected to a common output line on one side of the respective resistors and to a common input line on the other side of the respective resistors.

7. The device (100) according to one of the preceding claims, characterized in that, The device (100) includes a controller (112) configured to compare the output of the set of memory cells (102) with a checksum and to detect an error when the output and the checksum are different, wherein the device (100) is configured to provide the output and the checksum to the controller (112).

8. The device (100) according to claim 7, characterized in that, The device (100) includes a controller (112) configured to add the difference between the output and the checksum to the output when an error is detected.

9. The device (100) according to one of the preceding claims, characterized in that, The device (100) includes a processing element having a first part of a matrix including memory cells (102) and a processing element having a second part of a matrix including memory cells (102), wherein a first memory cell of the set of memory cells (102) is arranged in the first part of the matrix and a second memory cell of the set of memory cells (102) is arranged in the second part of the matrix, and wherein the device includes an output adder (602) configured to add the outputs of the first and second memory cells to the output of the set of memory cells (102).

10. The device (100) according to one of the preceding claims, characterized in that, The device (100) includes a processing element having a first aspect including memory cells (102), and a processing element having a second aspect including memory cells (102), wherein a first memory cell of the set of memory cells (102) is arranged in the first aspect, wherein a second memory cell of the set of memory cells (102) is arranged in the second aspect, and wherein the device includes an input adder (406) configured to add an aspect input to an input of a memory cell for determining a checksum and provide the input to the memory cell (102) for determining the checksum.

11. The device (100) according to one of the preceding claims, characterized in that, The set of memory cells (102) and at least one memory cell (102) for determining a checksum are arranged in an arrangement of memory cells (102) that includes a processing element and a set of processing elements that contain the set of memory cells (102) and at least one memory cell (102) for determining a checksum, and another set of memory cells (102) and at least one additional memory cell (102) for determining a checksum of the other set of memory cells (102), wherein the at least one additional memory cell is arranged in a processing element of the set of processing elements that is different from the other set of memory cells (102).

12. The device (100) according to one of the preceding claims, characterized in that, The device (100) includes memory cells for determining two redundant checksums and memory cells for parity checking of the two redundant checksums, wherein the memory cells for determining parity checking include a resistance equal to the sum of the resistances of the memory cells providing the least significant bits of the two redundant checksums.

13. A method for error detection, in particular error correction, in in-memory computing using a set of memory cells (102) for determining the result of a linear operation, wherein a respective memory cell (102) of the set of memory cells (102) comprises a respective resistor, characterized in that, Provide at least one memory cell (102), in particular at least two memory cells, for determining a checksum, which includes a resistance equal to or substantially equal to the sum of the corresponding resistances; determine the output of the set of memory cells (102) and provide an input to at least one memory cell for determining a checksum; Compare the output with the checksum; and detect an error when the output and the checksum are different.

14. The method according to claim 13, wherein The method includes: determining the respective outputs of the respective memory cells of the set of memory cells (102) and a checksum, the checksum being generated by providing the same input to the memory cells (102) of the set of memory cells (102) and at least one memory cell for determining a checksum; and adding the respective outputs of the respective memory cells (102) of the set of memory cells (102) to the output.

15. The method according to claim 13, wherein The method includes: providing respective voltages to the memory cells (102) of the set of memory cells (102) for determining the respective outputs of the respective memory cells of the set of memory cells (102); adding the respective outputs to the output; adding the respective inputs to the input of at least one memory cell (102) for determining a checksum; and providing an input to the memory cell (102) for determining a checksum.

16. The method according to any one of claims 13 to 15, characterized in that, For error correction, when an error is detected, the difference between the checksum and the output is added to the output.

17. The method according to any one of claims 13 to 16, characterized in that, The first memory cell (102) of the set of memory cells (102) is associated with a first horizontal and vertical portion in a first processing element, wherein a second memory cell (102) of the set of memory cells (102) is associated with a second horizontal and vertical portion in a second processing element, and wherein the outputs of the first memory cell (102) and the second memory cell (102) are added to the output of the set of memory cells (102).

18. The method according to any one of claims 13 to 16, characterized in that The first memory cell (102) of the set of memory cells (102) is associated with a first horizontal and vertical portion in a first processing element, wherein a second memory cell (102) of the set of memory cells (102) is associated with a second horizontal and vertical portion in a second processing element, and wherein the horizontal and vertical inputs are added to the input of at least one memory cell (102) for determining a checksum.

19. The method according to one of claims 13 to 18, characterized in that, The method includes checking (1012) the parity of memory cells for determining two redundant checksums, wherein the memory cells are used for parity checking of the two redundant checksums, and wherein the memory cells for determining the parity check include a resistance equal to the sum of the resistances of the memory cells providing the least significant bits of the two redundant checksums; recalculating (1004) the checksum in the case of a parity check failure; and otherwise correcting (1016) an error indicated by the two redundant checksums.

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