Data prefetching method and related device

Abstract

The present specification provides a data prefetch method that performs a data prefetch operation based on a target address and a prefetch offset when a first target event occurs, where the prefetch offset is determined based on offsets of a plurality of offset item records in an offset list. The offset in the offset list is determined based on a target item and a virtual address of the target data, the target item comprises an item corresponding to the target instruction in the recently accessed address table, and the target item comprises virtual addresses of a plurality of data accessed by the processor based on the target instruction. Therefore, the prefetch offset is determined based on the virtual address of each record in the recent access address table, and the data prefetch requirement during cross-page access can be met because the virtual addresses of the data used by the program are continuous, even if the prefetched data are distributed in different memory pages, the data prefetch efficiency is improved. And the prefetching operation can be realized through the continuous relationship between the virtual addresses, so that the accuracy of data prefetching during cross-page data access of the processor can be improved.

Description

Technical Field

[0001] This specification relates to the field of computer application technologies. Specifically, it relates to data prefetching technologies in the field of computer application technologies, and more specifically, to a data prefetching method and related devices. Background Art

[0002] Data prefetching is a technology used to improve the performance of computer systems. Data prefetching can predict the data that the processor may need during future execution and load this data from storage devices (such as memory, disks, etc.) into the cache or a storage area closer to the processor in advance. In this way, when the processor actually needs to use this data, it can obtain and use this data faster, thereby reducing the waiting time of the processor and improving the operating efficiency of the entire system.

[0003] However, currently, the accuracy of data prefetching technologies needs to be improved. It is necessary to improve the accuracy of data prefetching technologies to reduce the number of cache misses and improve the execution efficiency of the processor. Summary of the Invention

[0004] Embodiments of this specification provide a data prefetching method and related devices to achieve the purpose of improving the accuracy of data prefetching technologies and enhancing the execution efficiency of the processor.

[0005] To achieve the above technical objectives, the embodiments of this specification provide the following technical solutions:

[0006] In a first aspect, a data prefetching method is provided, which is applied to a processor. The data prefetching method includes:

[0007] In response to the occurrence of a first target event, perform a data prefetching operation based on a target address and a prefetch offset.

[0008] The first target event includes: the target data accessed by the processor based on a target instruction is not in the cache, or the target data is obtained through a prefetching operation; the target address includes the address of the target data.

[0009] The prefetch offset is determined based on the offsets recorded in multiple offset entries in an offset list. The offset in the offset entry is determined based on a target entry and the virtual address of the target data. The target entry includes the virtual addresses of multiple data accessed by the processor based on the target instruction.

[0010] In a second aspect, a data prefetching device is provided, which is applied to a processor. The data prefetching device includes:

[0011] A prefetch module, configured to perform a data prefetch operation based on a target address and a prefetch offset in response to the occurrence of a first target event;

[0012] The first target event includes: the target data accessed by the processor based on a target instruction is not in the cache, or the target data is obtained by a prefetch operation; the target address includes the address of the target data;

[0013] The prefetch offset is determined based on the offsets recorded in multiple offset entries in an offset list, and the offset in the offset entry is determined based on a target entry and the virtual address of the target data, and the target entry includes the virtual addresses of multiple data accessed by the processor based on the target instruction.

[0014] In a third aspect, a processor is provided, and the processor is configured to:

[0015] Perform a data prefetch operation based on a target address and a prefetch offset in response to the occurrence of a first target event;

[0016] The first target event includes: the target data accessed by the processor based on a target instruction is not in the cache, or the target data is obtained by a prefetch operation; the target address includes the address of the target data;

[0017] The prefetch offset is determined based on the offsets recorded in multiple offset entries in an offset list, and the offset in the offset entry is determined based on a target entry and the virtual address of the target data, and the target entry includes the virtual addresses of multiple data accessed by the processor based on the target instruction.

[0018] In a fourth aspect, a system-on-chip is provided, including:

[0019] A memory and a processor;

[0020] The memory is configured to store data;

[0021] The processor is configured to: perform a data prefetch operation on the data stored in the memory based on a target address and a prefetch offset in response to the occurrence of a first target event;

[0022] The first target event includes: the target data accessed by the processor based on a target instruction is not in the cache, or the target data is obtained by a prefetch operation; the target address includes the address of the target data;

[0023] The prefetch offset is determined based on the offsets recorded in multiple offset entries in an offset list, and the offset in the offset entry is determined based on a target entry and the virtual address of the target data, and the target entry includes the virtual addresses of multiple data accessed by the processor based on the target instruction.

[0024] As can be seen from the above technical solution, the data prefetching method provided by the embodiments of this specification performs a data prefetching operation based on a target address and a prefetch offset when a first target event occurs, where the prefetch offset is determined based on the offsets recorded in multiple offset entries in an offset list. The offset in the offset entry is determined based on a target entry and the virtual address of the target data. The target entry includes the entry in the recently accessed address table corresponding to the target instruction, and the target entry includes the virtual addresses of multiple data accessed by the processor based on the target instruction. In this way, determining the prefetch offset based on the virtual addresses recorded in each entry in the recently accessed address table can meet the data prefetching requirements during cross-page access, because the virtual addresses of the data used by the program are continuous. Even if the prefetch data before and after is distributed in different memory pages, the prefetch operation can be implemented through the continuous relationship between the virtual addresses, which is beneficial to improving the accuracy of data prefetching when the processor accesses data across pages and improving the data processing efficiency of the processor. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] In order to more clearly illustrate the technical solutions in the embodiments of this specification or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the drawings in the following description are only the embodiments of this specification. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on the provided drawings.

[0026] Figure 1 A schematic structural diagram of a recently accessed address table provided by the embodiments of this specification;

[0027] Figure 2 A schematic structural diagram of an offset list provided by the embodiments of this specification;

[0028] Figure 3 A schematic flowchart of a data prefetching method provided by the embodiments of this specification;

[0029] Figure 4 A schematic flowchart of the processing when a second target event is detected to occur provided by the embodiments of this specification;

[0030] Figure 5 A schematic flowchart of the processing when a first target event is detected to occur provided by the embodiments of this specification;

[0031] Figure 6 A schematic structural diagram of a computing device provided by the embodiments of this specification. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0032] Unless otherwise defined, the technical terms or scientific terms used in the embodiments of this specification shall have the ordinary meanings understood by those of ordinary skill in the art to which this specification pertains. The terms "first", "second" and similar words used in the embodiments of this specification do not denote any order, quantity or importance, but are only used to avoid confusion of components.

[0033] Unless the context otherwise requires, throughout this specification, "a plurality of" means "at least two", and "comprising" is construed in an open, inclusive sense, i.e., "including, but not limited to". In the description of this specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "examples", "specific examples" or "some examples", etc. are intended to indicate that the specific features, structures, materials or characteristics related to the embodiment or example are included in at least one embodiment or example of this specification. The schematic representations of the above terms do not necessarily refer to the same embodiment or example.

[0034] The technical solutions in the embodiments of this specification will be clearly and completely described below with reference to the accompanying drawings in the embodiments of this specification. Obviously, the described embodiments are only a part of the embodiments of this specification, rather than all of the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments in this specification without creative efforts shall fall within the scope of protection of this specification.

[0035] Overview

[0036] With the rapid development of processor technology, the operating speed of processors is getting faster and faster, while the speed of the corresponding memory (such as DRAM (Dynamic Random Access Memory)) has not been correspondingly improved. This speed difference limits the processing performance of processors. Each time a processor accesses off-chip memory (such as DRAM), the processor may need to pause for hundreds of clock cycles, significantly affecting the performance of the processor.

[0037] The cache hierarchy can improve the performance of data reference programs with good temporal and spatial locality. However, in some types of applications such as big data, due to the high cache miss rate, it is still difficult to reduce the data reference latency.

[0038] For this reason, the data prefetching technology has emerged. The data prefetching technology can be implemented based on the principle of program locality. Program locality includes temporal locality and spatial locality. Among them, temporal locality means that if a data item is being accessed, then it is very likely to be accessed again in the near future. For example, in a loop, the loop variable and the data used in the loop body are accessed in each loop iteration. Spatial locality means that if a data item is accessed, then the data items adjacent to its address are also very likely to be accessed in the near future. For example, when accessing an array element, it is very likely that the adjacent elements in the array will be accessed next. Based on the above program locality, the data prefetching technology can preload the data that the processor may use from the storage device into the cache through a certain algorithm to reduce the time required for the processor to obtain data. In the related technology, the offset-based data prefetcher (or offset prefetcher) guides subsequent data prefetching operations by statistically calculating the most frequently occurring address differences (i.e., offsets) within a period of time of the processor. However, the inventor's research found that the current data prefetcher is trained based on the physical addresses during the execution of the processor and can only identify fixed small offsets. This is because: there are certain rules for the physical addresses within the same memory page, so a prefetch offset can be determined based on this rule, and the data prefetch within the same memory page can be achieved using this prefetch offset; however, there is no statistically significant rule between the physical addresses across pages (across memory pages). Therefore, this data prefetcher cannot achieve accurate data prefetching during cross-page access. When the processor needs to use cross-page data, the data prefetching effect of the data prefetcher trained based on physical addresses is poor and the accuracy is low. Assuming that the size of a memory page is 64 cache lines, then the data prefetcher trained based on physical addresses cannot train a prefetch offset greater than 64 because adding / subtracting a number of 64 or more to the physical address of any data will necessarily cross into another memory page.

[0039] To solve this problem, the inventor designed a recently accessed address table as shown in Figure 1 and an offset list as shown in Figure 2 The recently accessed address table can include multiple items, and each item can include fields such as the instruction PC (instruction program counter value), multiple virtual addresses (in Figure 1Among them, each item contains 16 virtual addresses (virtual address 0 to virtual address 15), and the number of virtual addresses contained in each item can be determined according to actual needs), a valid bit, and a write pointer. Among them, the instruction PC can be used to indicate the virtual address of the instruction, and this instruction PC can be used to uniquely identify which instruction this item corresponds to, that is, the instruction PC can be used as an index during lookup; multiple virtual addresses can include the virtual addresses of multiple data accessed by the processor based on this instruction. The valid bit can be used to identify the valid state of this item, and the write pointer can be used to indicate the field position where the new virtual address can be written when the virtual address in this item needs to be updated; virtual address 0 to virtual address 15 can all be 0. When a new virtual address needs to be written into this item, write it into virtual address 0, and then increment the write pointer by 1 to point to virtual address 1. At this time, when a new virtual address needs to be written into this item, it can be correctly written into virtual address 1. Using the recently accessed address table can record the virtual addresses of the data accessed by each instruction within a period of time, providing basic data for the training of the prefetch offset.

[0040] In the Figure 2 shown offset list, each item (to distinguish it from the recently accessed address table, the items in the offset list can be called offset items) contains fields such as an offset, a valid bit, and a confidence level. Among them, the offset can be determined based on the recently accessed address table and each data access operation of the instruction. The valid bit can be used to indicate the valid state of this offset list, and the confidence level can be used to indicate the accuracy when the offset is used as a prefetch offset to perform a data prefetch operation. Or rather, the confidence level is positively correlated with the accuracy when the offset is used as a prefetch offset to perform a data prefetch operation. That is, if the confidence level corresponding to a certain offset is greater, the accuracy of using this offset as a prefetch offset to perform a data prefetch operation is higher.

[0041] It can be understood that Figure 1 and Figure 2 show the feasible structures of the offset list and the recently accessed address table. In other embodiments, the structures of the offset list and the recently accessed address table can be adaptively adjusted. For example, other fields except the instruction PC can be used as the index for looking up the item corresponding to the instruction, etc. This specification does not limit this, and it depends on the actual situation specifically.

[0042] Based on the above-mentioned recently accessed address table and offset list, the inventor provides a data prefetching method. When the target data accessed by the processor based on the target instruction is not in the cache, or the target data is obtained through a prefetching operation, optionally, the target data can be obtained through a historical data prefetching operation; when the target address includes the address of the target data (hereinafter simply referred to as the first target event), a data prefetching operation is performed based on the target address and the prefetch offset, where the prefetch offset is determined based on the offsets recorded in multiple offset entries in the offset list. The offset in the offset entry is determined based on the target entry and the virtual address of the target data, and the target entry includes the virtual addresses of multiple data accessed by the processor based on the target instruction. In this way, determining the prefetch offset based on the virtual addresses recorded in each entry of the recently accessed address table can meet the data prefetching requirements during cross-page access. This is because the virtual addresses of the data used by the program are continuous. Even if the prefetch data before and after is distributed in different memory pages, the prefetch operation can be achieved through the continuous relationship between the virtual addresses, which is beneficial to improving the accuracy of data prefetching when the processor accesses data across pages and improving the data processing efficiency of the processor.

[0043] In addition, since the prefetch offset is determined based on the offsets recorded in multiple offset entries in the offset list, the most reliable offset can be found from the offsets recorded in multiple offset entries in the offset list as the prefetch offset. While meeting the data prefetching requirements of any offset, it is beneficial to improve the accuracy of data prefetching, reduce cache misses, and improve processor performance.

[0044] Optionally, the target entry can be determined based on the recently accessed address table. As described above, the recently accessed address table can include multiple entries, and each entry includes the virtual addresses of multiple data accessed by the processor based on the instruction. In this way, the target entry can include the entry in the recently accessed address table corresponding to the target instruction, that is, the target entry can be the entry in the recently accessed address table that records the virtual addresses of multiple data accessed by the processor based on the target instruction.

[0045] Based on the above concept, an embodiment of this specification provides a data prefetching method. Next, the data prefetching method provided by the embodiment of this specification will be described exemplarily in conjunction with the accompanying drawings.

[0046] Exemplary Method

[0047] Taking the application to a processor as an example, an embodiment of this specification provides a data prefetching method, as Figure 3 shown, including:

[0048] S301: In response to the occurrence of the first target event, perform a data prefetching operation based on the target address and the prefetch offset;

[0049] The first target event includes: the target data accessed by the processor based on the target instruction is not in the cache, or the target data is obtained by a prefetch operation; the target address includes the address of the target data.

[0050] The prefetch offset is determined based on the offsets recorded in multiple offset entries in an offset list, and the offset in the offset entry is determined based on the target entry and the virtual address of the target data. The target entry includes the entry corresponding to the target instruction in a recently accessed address table, and the target entry includes the virtual addresses of multiple data accessed by the processor based on the target instruction.

[0051] In this embodiment, the occurrence of the first target event is used as a trigger condition for performing a data prefetch operation. This is because when the first target event occurs, it can be considered that the data that the processor needs to access during the data access process is not in the cache, and the probability of cache miss is relatively high. It is necessary to perform a data prefetch operation to reduce the cache miss rate and improve the data access performance of the processor. Specifically, in the first target event: that the target data accessed by the processor based on the target instruction is not in the cache indicates that a cache miss actually occurs; and that the target data is obtained by a prefetch operation indicates that the target data was not originally cached in the cache by the processor's pipeline, but may be prefetch-cached in the cache by a previous historical data prefetch operation. If there is no previous historical data prefetch operation, a cache miss may occur. Therefore, when the first target event occurs, a data prefetch operation can be performed based on the target address and the prefetch offset to reduce the cache miss rate. In addition, in some embodiments, the occurrence count of the first target event can also be used as a criterion for updating the prefetch offset, which will be described in detail in some of the following embodiments.

[0052] In this embodiment, the prefetch offset is determined based on the offsets recorded in multiple offset entries in the offset list. The offset in the offset entry is determined based on the target entry and the virtual address of the target data. The target entry includes the virtual addresses of multiple data accessed by the processor based on the target instruction. In this way, the virtual address of the data accessed based on the target instruction is used as the training basis for the prefetch offset, which is beneficial to determining any prefetch offset, meeting the data prefetch requirements in cases such as cross-page access, and improving the accuracy of data prefetch. Optionally, the target entry can be determined based on the recently accessed address table. As described above, the recently accessed address table can include multiple entries, and each entry includes the virtual addresses of multiple data accessed by the processor based on the instruction. In this way, the target entry can include the entry in the recently accessed address table corresponding to the target instruction, that is, the target entry can be the entry in the recently accessed address table that records the virtual addresses of multiple data accessed by the processor based on the target instruction. Of course, in some embodiments, the virtual addresses of multiple data accessed by the processor based on the target instruction recorded in the target entry can also be recorded in other ways, and this specification does not limit this, and it depends on the actual situation specifically.

[0053] In addition, since the prefetch offset is determined based on the offsets recorded in multiple offset entries in the offset list, the most reliable offset can be found from the offsets recorded in multiple offset entries in the offset list as the prefetch offset. While meeting the data prefetch requirements for any offset, it is beneficial to improve the accuracy of data prefetch, reduce cache misses, and improve processor performance.

[0054] In some embodiments, the recently accessed address table and the offset list can be updated as the processor accesses data, so as to ensure that the data recorded in the recently accessed address table and the offset list can accurately reflect the actual access situation of the processor, which is beneficial to ensuring that the prefetch offset can be determined according to real-time data and improving the accuracy of the data prefetch method.

[0055] In some of the following embodiments, some feasible ways to determine the most reliable offset from multiple offsets as the prefetch offset are given. For example, in one embodiment, the offset list further includes a confidence level corresponding to the offset;

[0056] The process of determining the prefetch offset includes:

[0057] [[ID=...]] When the update condition is satisfied, compare the confidence levels corresponding to the offsets in multiple offset entries, and use the offset with the maximum confidence level as the prefetch offset; the confidence level is used to characterize the accuracy when the corresponding offset is used as the prefetch offset;

[0058] The update conditions include: there is an offset in the offset list whose confidence level is greater than the confidence threshold, or the target count value is greater than the count threshold; the target count value is used to represent the occurrence times of the first target event.

[0059] In this embodiment, the occurrence times of the target event and the confidence level of the offset in the offset list are used as the consideration criteria for whether the prefetch offset needs to be updated. On the one hand, the prefetch offset can be updated in a timely manner when the update conditions are met, making the updated prefetch offset more conform to the data access pattern of the processor in the recent period of time and improving the accuracy of data prefetch. On the other hand, the confidence threshold and the count threshold in the update conditions can be determined comprehensively according to the processor performance and data prefetch requirements, etc., to meet the personalized setting needs of users.

[0060] In one embodiment, the confidence threshold can be set to 20, 25, 30, 31, 32, 35, etc., and the count threshold can be set to 100 times, 128 times, 150 times, 200 times, etc. This specification does not limit this, and it depends on the actual situation specifically.

[0061] In one embodiment, when the update conditions are met and the prefetch offset is determined, the target count value and the confidence level corresponding to the offset recorded in each offset item in the offset list can be set to zero to start recording the access behavior of the processor in the next cycle again.

[0062] In one embodiment, the processor further includes a first counter, and the first counter is used to record the target count value;

[0063] The data prefetch method further includes:

[0064] In response to the occurrence of the first target event, increment the count value of the first counter by 1;

[0065] Determine whether the update conditions are met. If so, execute the process of determining the prefetch offset;

[0066] If not, update the recently accessed address table by using the target instruction and the target data accessed by the target instruction.

[0067] This embodiment provides a feasible triggering condition for the determination process of the prefetch offset and the update of the recently accessed address table. In this embodiment, when the first target event occurs, in addition to performing the data prefetch operation, the determination process of the prefetch offset or the update process of the recently accessed address table can be executed according to whether the update condition is satisfied. In this way, the recently accessed address table can be updated in real time with the occurrence of the first target event, ensuring the real-time nature of the data recorded in the recently accessed address table, thereby ensuring the real-time nature of the data in the offset list, and further enabling the prefetch offset determined based on the offset in the offset list to be closer to the access behavior of the processor. In addition, it also enables the prefetch offset to be updated in a timely manner when the update condition is satisfied, which is beneficial to ensuring the accuracy of the data prefetch method.

[0068] In one embodiment, a feasible process for updating the recently accessed address table is provided. Specifically, updating the recently accessed address table using the target instruction and the target data accessed by the target instruction includes:

[0069] Query the recently accessed address table using the target instruction, and determine whether the target item corresponding to the target instruction is included in the recently accessed address table. If not, allocate an item for the target instruction in the recently accessed address table as the target item;

[0070] If so, subtract the virtual addresses recorded in the target item from the virtual address of the target data accessed by the target instruction to obtain a plurality of offsets to be updated;

[0071] Search for the offset list using the offsets to be updated. If a first target offset item including the offsets to be updated exists, increase the confidence level of the offsets to be updated in the first target offset item;

[0072] If a first target offset item including the offsets to be updated does not exist, record the offsets to be updated using a second target offset item.

[0073] In some embodiments, when querying the recently accessed address table using the target instruction, the query can be based on the instruction PC of the target instruction to determine whether there is a matching instruction PC value in the recently accessed address table, so as to determine whether the target item exists in the recently accessed address table.

[0074] When there is no target entry, an entry is allocated in the recently accessed address table for the target instruction as the target entry; when there is a target entry, the virtual address of the target data accessed by the target instruction is subtracted from the multiple virtual addresses recorded in the target entry to obtain multiple offsets to be updated; these offsets to be updated are used to sequentially search the offset list. When there is a first target offset entry including the offset to be updated, the confidence level of the offset to be updated in the first target offset entry is increased, indicating that the data prefetch accuracy is improved when the offset is used as a prefetch offset; when there is no first target offset entry including the offset to be updated, the offset to be updated is recorded using a second target offset entry.

[0075] In one embodiment, the recording the offset to be updated using the second target offset entry includes:

[0076] Check whether there is an invalid offset entry in the offset list. If so, allocate the offset to be updated to the invalid offset entry;

[0077] If not, allocate the offset to be updated to the offset entry with the minimum confidence level in the offset list.

[0078] In this embodiment, the offset list may include a valid bit field. Whether the offset entry is valid can be determined through the valid bit. When the valid bit indicates that the offset entry is invalid, this entry is called an invalid offset entry. If there is no invalid offset entry, the offset to be updated can be allocated to the offset entry with the minimum confidence level in the offset list.

[0079] In one embodiment, the increasing the confidence level of the offset to be updated in the first target offset entry includes:

[0080] The sum of the confidence level of the offset to be updated in the first target offset entry and the number of occurrences of the virtual address of the target data in the target entry is updated to the confidence level of the offset to be updated.

[0081] In this embodiment, a feasible method for increasing the confidence level of the offset to be updated in the first target offset entry is given. Specifically, comprehensively considering the number of occurrences of the virtual address of the target data in the target entry can make the confidence level of the offset more conform to the access mode of the processor, which is beneficial to improving the accuracy of the data prefetch method.

[0082] In one embodiment, the data prefetch method further includes:

[0083] In response to the occurrence of a second target event, update the recently accessed address table using the target instruction and the target data;

[0084] The second target event includes: backfilling the target data accessed by the target instruction into the cache.

[0085] In this embodiment, a feasible update timing for the virtual address in the recently accessed address table is provided. That is, when a cache miss occurs for the target data accessed by the target instruction and the target data is backfilled from the lower-level storage into the cache, it indicates that the access behavior of the processor this time may not be predicted, which has the significance of updating the prefetch offset. This access behavior can be used to update the recently accessed address table.

[0086] In one embodiment, a feasible update process is provided. Specifically, the recently accessed address table includes multiple entries, and each entry is used to record the virtual addresses of multiple data accessed by the processor based on instructions and the occurrence times corresponding to the virtual addresses.

[0087] Updating the recently accessed address table using the target instruction and the target data includes:

[0088] Query the recently accessed address table using the target instruction to determine whether there is a target entry in the recently accessed address table. If so, compare the virtual address recorded in the target entry with the virtual address of the target data. When there is a target virtual address that matches the virtual address of the target data, increment the occurrence times corresponding to the target virtual address by one; when there is no target virtual address that matches the virtual address of the target data, write the virtual address of the target data into the target entry.

[0089] If not, use a target replacement algorithm to allocate an entry in the recently accessed address table as the target entry for the target instruction.

[0090] Optionally, using the target replacement algorithm to allocate an entry in the recently accessed address table as the target entry for the target instruction includes:

[0091] Determine a replacement candidate entry among the multiple entries in the recently accessed address table according to the target replacement algorithm.

[0092] Write the virtual address of the target data into the first virtual address field of the replacement candidate entry, and set the occurrence times of the virtual address of the target data to 1.

[0093] Set the other virtual address fields and the corresponding occurrence times of the replacement candidate entry to 0.

[0094] The target replacement algorithm includes, but is not limited to, at least one of the Second Chance replacement algorithm, the Least Recently Used (LRU) replacement algorithm, and the Least Frequently Used (LFU) replacement algorithm. By using the above target replacement algorithm to determine the item to be replaced, relatively active items in the recently accessed address table can be retained, frequent replacement of frequently used items can be avoided, which is beneficial to reducing the replacement operation for items in the memory access instruction table and reducing the algorithm overhead.

[0095] The following will introduce the data prefetching method provided in this specification through a specific embodiment. Refer to Figure 4 、 Figure 5 and in combination with reference to Figure 1 、 Figure 2 For the introduction of the recently accessed address table and the offset list, reference can be made to the relevant descriptions in the previous text. In an optional embodiment, the recently accessed address table can adopt a fully associative structure, and the offset list can use the offset as an index and adopt a 2-way set associative structure. In this way, each item can be used to store two different offsets, reducing the processor overhead and improving the performance.

[0096] Figure 4 FIG. shows the feasible operation flow of the data prefetching method provided in the embodiment of this specification when detecting the occurrence of a second target event (i.e., the target data accessed by the target instruction is filled back into the cache), which specifically includes:

[0097] S1. Use the instruction PC value of the target instruction to search the recently accessed address table. If it is the same as the PC field value in a certain item in the recently accessed address table, it is considered to match this item and is determined as the target item;

[0098] S2. Compare the virtual address of the target data with the 16 virtual addresses in the matching item (taking the recently accessed address table shown in Figure 1 as an example). If it is the same as a certain virtual address in the target item, the occurrence count value corresponding to this virtual address is incremented by 1. If none of the 16 virtual addresses in the target item is the same as the virtual address of the target data, according to the write pointer value of the target item, the virtual address of the target data is written into the virtual address field pointed to by the write pointer, the occurrence count field value corresponding to it is set to 1, and the write pointer value of the target item is incremented by 1;

[0099] S3. If the PC field values of all entries in the recently accessed address table are inconsistent with the PC value of the target instruction, the second-chance replacement algorithm can be used to select an entry in the recently accessed address table and allocate it to the target instruction. Write the PC value of the target instruction into the PC field of this entry, write the virtual address of the target data into the virtual address 0 field of this entry, set the occurrence count of the corresponding virtual address 0 to 1, set the occurrence count fields of other virtual addresses and their corresponding values to 0, set the write pointer to 1, and set the valid bit to 1;

[0100] Figure 5 shows a feasible operation flow when the first target event is detected, Figure 4 and Figure 5 can be executed in parallel, Figure 5 The specific process shown includes:

[0101] S10. Perform a data prefetch operation based on the target address and the prefetch offset. Assume that the target address is A and the prefetch offset is D. Then the data prefetch operation will prefetch the corresponding data into the cache according to the virtual address A + D;

[0102] S11. Increment the value of the first counter (which can be called the execution count counter, denoted by the accessed_round counter). At the beginning of the method execution, this first counter can be pre-initialized to 0;

[0103] S12. Determine whether the first counter is greater than or equal to 128, or whether the confidence level of any item in the offset list is greater than or equal to 31 (whether the update condition is met);

[0104] S13. If the condition in S12 is met, compare the confidence levels of all valid offset items in the offset list, find the offset with the highest confidence level, and determine it as the prefetch offset. Then, the confidence level fields of all offset items in the offset list can be set to 0, and the counter value of the first counter can be set to 0;

[0105] S14. If the condition in S12 is not met, use the PC value of the target instruction to search the recently accessed address table to determine the target entry;

[0106] S15. Subtract the 16 virtual addresses recorded in the target entry from the target address to obtain 16 offsets to be updated. Use these 16 offsets to be updated to sequentially search the offset list and execute S16 and S17;

[0107] S16. If there is an offset item in the offset list that matches the offset to be updated (hereinafter referred to as the matching item), increment the value of the confidence level field of the matching item by the occurrence count value of the target address corresponding to the offset to be updated in the target entry;

[0108] S17. If there is no matching item for the to-be-updated offset in the offset list, check whether there is an invalid offset item in the offset list. If so, assign the to-be-updated offset to the invalid offset item; if not, assign the to-be-updated offset to the offset item with the lowest confidence level in the offset list.

[0109] Exemplary Device

[0110] In an exemplary embodiment of this specification, a data prefetching device is further provided, which is applied to a processor. The data prefetching device includes:

[0111] A prefetching module, configured to perform a data prefetching operation based on a target address and a prefetch offset in response to the occurrence of a first target event;

[0112] The first target event includes: the target data accessed by the processor based on a target instruction is not in the cache, or the target data is obtained by a prefetching operation; the target address includes the address of the target data;

[0113] The prefetch offset is determined based on the offsets recorded in multiple offset items in an offset list. The offset in the offset item is determined based on a target item and the virtual address of the target data. The target item includes the item corresponding to the target instruction in a recently accessed address table, and the target item includes the virtual addresses of multiple data accessed by the processor based on the target instruction.

[0114] For the specific limitations of the data prefetching device, reference can be made to the limitations of the data prefetching method in the foregoing text, which will not be elaborated here. Each module in the above data prefetching device can be implemented in whole or in part by software, hardware, and their combination. The above modules can be embedded in the processor in the computer device in hardware form or be independent of it, or be stored in the memory in the computer device in software form, so that the processor can call and execute the operations corresponding to the above modules.

[0115] Exemplary Computing Device

[0116] An embodiment of this specification further provides a processor, which is configured to:

[0117] Perform a data prefetching operation based on a target address and a prefetch offset in response to the occurrence of a first target event;

[0118] The first target event includes: the target data accessed by the processor based on a target instruction is not in the cache, or the target data is obtained by a prefetching operation; the target address includes the address of the target data;

[0119] The prefetch offset is determined based on the offsets recorded in multiple offset entries in an offset list. The offset in an offset entry is determined based on a target entry and the virtual address of the target data. The target entry includes the virtual addresses of multiple data accessed by the processor based on the target instruction.

[0120] One embodiment of this specification further provides a system-on-chip, which includes:

[0121] A memory and a processor;

[0122] The memory is configured to store data;

[0123] The processor is configured to: in response to the occurrence of a first target event, perform a data prefetch operation on the data stored in the memory based on a target address and a prefetch offset;

[0124] The first target event includes: the target data accessed by the processor based on the target instruction is not in the cache, or the target data is obtained by prefetching through a prefetch operation; the target address includes the address of the target data;

[0125] The prefetch offset is determined based on the offsets recorded in multiple offset entries in an offset list. The offset in an offset entry is determined based on a target entry and the virtual address of the target data. The target entry includes the virtual addresses of multiple data accessed by the processor based on the target instruction.

[0126] Another embodiment of this specification also proposes a computing device. Refer to Figure 6 As shown, an exemplary embodiment of this specification further provides a computing device, including: the system-on-chip as described in any of the above embodiments, and the system-on-chip includes a processor.

[0127] The internal structure of the computing device may be as Figure 6 As shown, the computing device includes a processor, a memory, a network interface, and an input device connected through a system bus. Among them, the processor of the computing device is used to provide computing and control capabilities. The memory of the computing device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and a computer program. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The network interface of the computing device is used to communicate with an external terminal through a network connection. When the computer program is executed by the processor, it provides the corresponding functions provided by the computer program.

[0128] The processor may include a main processor, and may also include a baseband chip, a modem, etc.

[0129] The memory stores a program for executing the technical solution of the present invention, and may also store an operating system and other key services. Specifically, the program may include program code, and the program code includes computer operation instructions. More specifically, the memory may include a read-only memory (ROM), other types of static storage devices that can store static information and instructions, a random access memory (RAM), other types of dynamic storage devices that can store information and instructions, a disk memory, a flash memory, and so on.

[0130] The processor may be a general-purpose processor, such as a general-purpose central processing unit (CPU), a microprocessor, etc., or may be an application-specific integrated circuit (ASIC), or one or more integrated circuits for controlling the execution of the program of the present invention. It may also be a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components.

[0131] The input device may include a device for receiving data and information input by a user, such as a keyboard, a mouse, a camera, a scanner, a light pen, a voice input device, a touch screen, a pedometer or a gravity sensor, etc.

[0132] The output device may include a device for allowing information to be output to a user, such as a display screen, a printer, a speaker, etc.

[0133] The communication interface may include a device of any transceiver type for communicating with other devices or communication networks, such as an Ethernet, a radio access network (RAN), a wireless local area network (WLAN), etc.

[0134] The processor executes the program stored in the memory and calls other devices, which can be used to implement each step of any data prefetching method provided in the above embodiments of this specification.

[0135] The computing device may further include a display component and a voice component. The display component may be a liquid crystal display screen or an electronic ink display screen. The input device of the computing device may be a touch layer covered on the display component, or may be a button, a trackball or a touchpad provided on the housing of the computing device, or may also be an external keyboard, a touchpad or a mouse, etc.

[0136] Those skilled in the art can understand, Figure 6The structure shown is only a block diagram of some of the structures related to the solution of this specification, and does not constitute a limitation on the computing device to which the solution of this specification is applied. The specific computing device may include more or fewer components than those shown in the figure, or combine certain components, or have a different component arrangement.

[0137] Those of ordinary skill in the art can understand that all or part of the processes in the above-described implementation methods can be completed by instructing relevant hardware through a computer program. The computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the implementation methods of the above various methods. Among them, any reference to a memory, storage, database, or other medium used in the various implementations provided in this specification can include non-volatile and / or volatile memories. Non-volatile memory can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or flash memory. Volatile memory can include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in various forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), Rambus direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and Rambus dynamic RAM (RDRAM), etc.

[0138] The technical features of the above embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope described in this specification.

[0139] The above-described embodiments only represent several embodiments of this specification. Their descriptions are relatively specific and detailed, but they should not be construed as limiting the scope of the solution provided by the embodiments of this specification. It should be noted that for those of ordinary skill in the art, without departing from the concept of this specification, several modifications and improvements can still be made, and these all belong to the protection scope of this specification. Therefore, the protection scope of the patent of this specification should be subject to the appended claims.

Claims

1. A data prefetching method, characterized in that, Applied to a processor, the data prefetching method includes: In response to the occurrence of a first target event, perform a data prefetching operation based on a target address and a prefetch offset; The first target event includes: the target data accessed by the processor based on a target instruction is not in the cache, or the target data is obtained by a prefetching operation; the target address includes the address of the target data; The prefetch offset is determined based on the offsets recorded in multiple offset entries in an offset list, and the offset in the offset entry is determined based on a target entry and the virtual address of the target data, and the target entry includes the virtual addresses of multiple data accessed by the processor based on the target instruction.

2. The method according to claim 1, wherein The offset list further includes a confidence level corresponding to the offset; The process of determining the prefetch offset includes: When an update condition is satisfied, compare the confidence levels corresponding to the offsets in multiple offset entries, and use the offset with the maximum confidence level as the prefetch offset; the confidence level is used to characterize the accuracy when the corresponding offset is used as the prefetch offset; The update condition includes: there is an offset in the offset list with a confidence level greater than a confidence threshold, or a target count value is greater than a count threshold; the target count value is used to characterize the occurrence times of the first target event.

3. The method according to claim 2, wherein The target entry is determined based on a recently accessed address table, and the recently accessed address table includes multiple entries, and each entry includes the virtual addresses of multiple data accessed by the processor based on an instruction; The processor further includes a first counter, and the first counter is used to record the target count value; The data prefetching method further includes: In response to the occurrence of the first target event, increment the count value of the first counter by 1; Determine whether the update condition is satisfied, and if so, perform the process of determining the prefetch offset; If not, update the recently accessed address table using the target instruction and the target data accessed by the target instruction.

4. The method according to claim 3, wherein The updating the recently accessed address table using the target instruction and the target data accessed by the target instruction includes: Use the target instruction to query the recently accessed address table, and determine whether the recently accessed address table includes the target entry corresponding to the target instruction. If not, allocate an entry in the recently accessed address table as the target entry for the target instruction; If so, subtract the virtual addresses recorded in the target entry from the virtual address of the target data accessed by the target instruction to obtain multiple offsets to be updated; Use the offsets to be updated to search the offset list. If there is a first target offset entry including the offset to be updated, increase the confidence level of the offset to be updated in the first target offset entry; If there is no first target offset entry including the offset to be updated, record the offset to be updated using a second target offset entry.

5. The method according to claim 4, wherein The recording the offset to be updated using a second target offset entry includes: Check whether there is an invalid offset entry in the offset list. If so, allocate the offset to be updated to the invalid offset entry; Otherwise, assign the to-be-updated offset to the offset entry with the lowest confidence level in the offset list.

6. The method according to claim 4, characterized in that, The increasing the confidence level of the to-be-updated offset in the first target offset entry includes: Updating the sum of the confidence level of the to-be-updated offset in the first target offset entry and the occurrence count value of the virtual address of the target data in the target entry as the confidence level of the to-be-updated offset.

7. The method according to claim 3, wherein The data prefetching method further includes: In response to the occurrence of a second target event, updating the recently accessed address table by using the target instruction and the target data; The second target event includes: the target data accessed by the target instruction is backfilled into the cache.

8. The method according to claim 7, wherein The recently accessed address table includes multiple entries, and each entry is used to record the virtual addresses of multiple data accessed by the processor based on instructions and the occurrence counts corresponding to the virtual addresses; The updating the recently accessed address table by using the target instruction and the target data includes: Querying the recently accessed address table by using the target instruction to determine whether there is a target entry in the recently accessed address table. If so, comparing the virtual address recorded in the target entry with the virtual address of the target data. When there is a target virtual address that matches the virtual address of the target data, incrementing the occurrence count corresponding to the target virtual address by one; when there is no target virtual address that matches the virtual address of the target data, writing the virtual address of the target data into the target entry; Otherwise, use a target replacement algorithm to allocate an entry in the recently accessed address table as the target entry for the target instruction.

9. The method according to claim 8, wherein The using the target replacement algorithm to allocate an entry in the recently accessed address table as the target entry for the target instruction includes: Determining a to-be-replaced entry from multiple entries in the recently accessed address table according to the target replacement algorithm; Writing the virtual address of the target data into the first virtual address field of the to-be-replaced entry, and setting the occurrence count of the virtual address of the target data to 1; Setting the other virtual address fields of the to-be-replaced entry and the corresponding occurrence counts to 0.

10. A processor, characterized in that, The processor is configured to: In response to the occurrence of a first target event, perform a data prefetching operation based on a target address and a prefetch offset; The first target event includes: the target data accessed by the processor based on a target instruction is not in the cache, or the target data is obtained through a prefetching operation; The target address includes the address of the target data; The prefetch offset is determined based on the offsets recorded in multiple offset entries in an offset list, and the offset in each offset entry is determined based on a target entry and the virtual address of the target data, and the target entry includes the virtual addresses of multiple data accessed by the processor based on the target instruction.

11. A system on a chip, characterized in that, including: a memory and a processor; The memory is configured to store data; The processor is configured to: in response to the occurrence of a first target event, perform a data prefetching operation on the data stored in the memory based on a target address and a prefetch offset; The first target event includes: the target data accessed by the processor based on the target instruction is not in the cache, or, the target data is obtained by a prefetch operation; The target address includes the address of the target data; The prefetch offset is determined based on the offsets recorded in multiple offset entries in an offset list, and the offsets in the offset entries are determined based on a target entry and the virtual address of the target data, where the target entry includes the virtual addresses of multiple data accessed by the processor based on the target instruction.

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