Data transmission method, apparatus, system, and storage medium

Abstract

The present disclosure relates to a data transmission method, device, system and storage medium. The method is used for device side DMA, the device side is connected with the host side through PCIe, and the method comprises: receiving a descriptor by DMA; obtaining target data corresponding to a source address in the descriptor by DMA, and sending the target data to PCIe, which is used for writing the target data into a destination address; sending a read data request to PCIe by DMA in the case that the target data has been sent to PCIe and the indication information of the descriptor is a preset value; and sending an interrupt information to a CPU of the host side by DMA in the case that the data corresponding to the read data request returned by PCIe is received, so that the CPU reads the data corresponding to the destination address. According to the embodiments of the present disclosure, the target data can be correctly and completely read from the destination address by the CPU through the cooperation of the software level and the hardware level, and the integrity and correctness of data transmission are ensured.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of data processing, and particularly relates to a data transmission method, device, system and storage medium. BACKGROUND

[0002] In a computer system, data transmission between a device side and a host side is usually performed through direct memory access (DMA). In the data transmission process, data is communicated through a peripheral component interconnect express (PCIe). The use of DMA can significantly improve data transmission speed and system efficiency, and meanwhile, the PCIe as an underlying transmission channel provides reliable high-speed data transmission capability. However, in a scenario where DMA writes data from the device side to the host side through the PCIe, after receiving a completion reply sent by the PCIe for a write data request, the DMA considers that the data has been transmitted and reports an interrupt to a central processing unit (CPU) of the host side, but at this time, the data may not have been written into a system memory of the host side, and thus there is a situation that the DMA reports the interrupt to the host side in advance, resulting in that the CPU of the host side cannot read correct data from the system memory. SUMMARY

[0003] In view of this, the present disclosure provides a data transmission method, device, system and storage medium.

[0004] According to an aspect of the present disclosure, a data transmission method is provided. The method is used for direct memory access (DMA) of a device side, the device side is connected with a host side through a peripheral component interconnect express (PCIe), and the method comprises the following steps.

[0005] The DMA receives a descriptor, and the descriptor comprises a source address, a destination address and indication information;

[0006] The DMA obtains target data corresponding to the source address in the descriptor, and sends the target data to the PCIe, and the PCIe is configured to write the target data into the destination address;

[0007] The DMA sends a read data request to the PCIe in a case that the target data has been sent to the PCIe and the indication information of the descriptor is a preset value;

[0008] The DMA sends interrupt information to a central processing unit (CPU) of the host side in a case that the DMA receives data corresponding to the read data request returned by the PCIe, so that the CPU reads data corresponding to the destination address.

[0009] In a possible implementation manner, the indication information is determined and configured based on the source address and the destination address.

[0010] In a possible implementation, in a case where the source address is an address of the device-side memory and the destination address is an address of the host-side system memory, the indication information in the descriptor is configured as a preset value.

[0011] In a possible implementation, in a case where the source address is not an address of the device-side memory or the destination address is not an address of the host-side system memory, the indication information in the descriptor is configured as a non-preset value or a default value.

[0012] In a possible implementation, the read data request sent by the DMA to the PCIe is used to read data corresponding to the reference address, where the reference address is determined by the DMA based on the destination address.

[0013] According to another aspect of the present disclosure, a data transmission apparatus is provided. The apparatus is used for a direct memory access (DMA) on a device side, the device side being connected to a host side through a high-speed serial bus (PCIe), and the apparatus comprises:

[0014] a receiving module configured to receive, by the DMA, a descriptor, the descriptor comprising a source address, a destination address, and indication information;

[0015] a first sending module configured to obtain, by the DMA, target data corresponding to the source address in the descriptor, and send the target data to the PCIe, the PCIe being configured to write the target data to the destination address;

[0016] a second sending module configured to send, by the DMA, a read data request to the PCIe in a case where the target data has been sent to the PCIe and the indication information in the descriptor is a preset value;

[0017] a third sending module configured to send, by the DMA, interrupt information to a central processing unit (CPU) on the host side in a case where data corresponding to the read data request returned by the PCIe is received, so that the CPU reads target data corresponding to the destination address.

[0018] In a possible implementation, the indication information is determined and configured based on the source address and the destination address.

[0019] In a possible implementation, in a case where the source address is an address of the device-side memory and the destination address is an address of the host-side system memory, the indication information in the descriptor is configured as a preset value.

[0020] In a possible implementation, in a case where the source address is not an address of the device-side memory or the destination address is not an address of the host-side system memory, the indication information in the descriptor is configured as a non-preset value or a default value.

[0021] In a possible implementation, the read data request sent by the DMA to the PCIe is used to read data corresponding to a reference address, wherein the reference address is determined by the DMA based on the destination address.

[0022] According to another aspect of the present disclosure, a data transmission system is provided. The system includes a device side and a host side, which are connected through a high-speed serial bus PCIe,

[0023] a direct memory access (DMA) on the device side, configured to:

[0024] receive a descriptor, the descriptor including a source address, a destination address, and an indication information;

[0025] obtain target data corresponding to the source address in the descriptor, and send the target data to the PCIe;

[0026] in a case where the target data has been sent to the PCIe and the indication information of the descriptor is a preset value, send a read data request to the PCIe;

[0027] in a case where data corresponding to the read data request returned by the PCIe is received, send an interrupt information to a central processing unit (CPU) on the host side;

[0028] the CPU is configured to:

[0029] read target data corresponding to the destination address in response to receiving the interrupt information;

[0030] the PCIe is configured to:

[0031] write the target data to the destination address.

[0032] In a possible implementation, the indication information is determined and configured based on the source address and the destination address.

[0033] In a possible implementation, in a case where the source address is an address of a memory on the device side and the destination address is an address of a system memory on the host side, the indication information in the descriptor is configured as a preset value.

[0034] In a possible implementation, in a case where the source address is not an address of a memory on the device side or the destination address is not an address of a system memory on the host side, the indication information in the descriptor is configured as a non-preset value or a default value.

[0035] In a possible implementation, the read data request sent by the DMA to the PCIe is used to read data corresponding to a reference address, wherein the reference address is determined by the DMA based on the destination address.

[0036] According to another aspect of the present disclosure, there is provided a data transmission apparatus comprising: a processor; a memory for storing processor-executable instructions; wherein the processor is configured to implement the above method when executing the instructions stored in the memory.

[0037] According to another aspect of the present disclosure, there is provided a non-transitory computer-readable storage medium having computer program instructions stored thereon, wherein the computer program instructions, when executed by a processor, implement the above method.

[0038] According to another aspect of the present disclosure, there is provided a computer program product comprising computer readable code, or a non-transitory computer readable storage medium carrying computer readable code, which when run in a processor of an electronic device, the processor in the electronic device implements the above method.

[0039] According to the embodiments of the present disclosure, the target data corresponding to the source address in the descriptor is acquired by the device-side DMA receiving the descriptor, and the target data is sent to the PCIe, wherein the PCIe is used to write the target data into the destination address, the descriptor comprises the source address, the destination address and the indication information, the DMA sends a read data request to the PCIe in the case that the target data has been sent to the PCIe and the indication information of the descriptor is a preset value, the DMA sends an interrupt information to the CPU on the host side in the case that the data corresponding to the read data request returned by the PCIe is received, and the CPU reads the data corresponding to the destination address, the characteristics of the PCIe are utilized, the cooperation of the software level (a field of the indication information is added in the descriptor) and the hardware level (the read data request is automatically sent by the DMA based on the added indication information field) is realized, the target data can be correctly and completely read from the destination address by the CPU on the host side, the integrity and correctness of the data transmission are ensured, and the data transmitted by the device side and the data read by the CPU on the host side have consistency.

[0040] Other features and aspects of the present disclosure will become apparent from the following detailed description of exemplary embodiments, taken in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF DRAWINGS

[0041] The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate exemplary embodiments, features, and aspects of the present disclosure and serve to explain the principles of the present disclosure.

[0042] Figure 1 A structure diagram of a data transmission system according to an embodiment of the present disclosure is shown.

[0043] Figure 2 A flowchart of a data transmission method according to an embodiment of the present disclosure is shown.

[0044] Figure 3A schematic diagram showing a descriptor according to an embodiment of the present disclosure.

[0045] Figure 4 A structural diagram of a data transmission apparatus according to an embodiment of the present disclosure is shown.

[0046] Figure 5 is a block diagram of an apparatus 1900 for data transmission according to an exemplary embodiment. DETAILED DESCRIPTION

[0047] Various exemplary embodiments, features and aspects of the present disclosure will be explained in detail below with reference to the accompanying drawings. The same reference numbers in different drawings denote the same or similar elements. Although various aspects of the embodiments are illustrated in the drawings, the drawings are not necessarily drawn to scale unless specifically indicated.

[0048] The word "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any implementation described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other implementations.

[0049] In addition, for the purpose of convenience and brevity, detailed descriptions of well-known functions and structures incorporated in the present disclosure are omitted. It will be appreciated by those skilled in the art that the present disclosure can be practiced without these specific details. In some instances, well-known methods, structures, elements, and circuits have not been described in detail in order to avoid obscuring the subject matter of the present disclosure.

[0050] In a computer system, data transmission between the device side and the host side is usually performed through direct memory access (DMA). During data transmission, data is communicated through a high-speed serial bus (PCIe). The use of DMA can significantly improve data transmission speed and system efficiency, and PCIe, as the underlying transmission channel, provides reliable high-speed data transmission capability. However, in the scenario where DMA writes data from the device side to the host side through PCIe, after receiving the completion reply sent by PCIe for the write data request, DMA considers that the data has been transmitted and reports an interrupt to the central processing unit (CPU) of the host side, but at this time the data may not have been written into the system memory of the host side, and thus there may be a situation where DMA reports an interrupt to the host side in advance, resulting in the CPU of the host side failing to read the correct data from the system memory.

[0051] In view of this, the present disclosure provides a data transmission method, device, system and storage medium. In the method of the present embodiment, the device side receives a DMA descriptor and obtains target data corresponding to the source address in the descriptor, and sends the target data to the PCIe, wherein the PCIe is used to write the target data to the destination address, the descriptor includes a source address, a destination address and an indication information, and the DMA sends a read data request to the PCIe in the case that the target data has been sent to the PCIe and the indication information of the descriptor is a preset value, and the DMA sends an interrupt information to the CPU on the host side in the case that the data corresponding to the read data request returned by the PCIe is received, so that the CPU reads the data corresponding to the destination address. By utilizing the characteristics of the PCIe, the cooperation of the software level (adding an indication information field in the descriptor) and the hardware level (the DMA automatically sends a read data request based on the added indication information field) is realized, so that the target data can be correctly and completely read by the CPU on the host side from the destination address, the integrity and correctness of data transmission are ensured, and the data transmitted by the device side and the data read by the CPU on the host side are consistent.

[0052] Figure 1 A structure diagram of a data transmission system according to an embodiment of the present disclosure is shown. The data transmission system of the present embodiment can include a device side (Device side) and a host side (Host side). As shown in the figure, Figure 1 The device side can include a DMA and a device side memory (Device Memory), and the device side memory is a memory or a buffer area of the device side; the host side can include a CPU and a system memory (System Memory), and the system memory can be used to store data and programs of a computer system. The host side and the device side can perform data transmission and communication through the PCIe.

[0053] The host side can be a terminal device or a server. The terminal device can be any one or more of a mobile phone, a foldable electronic device, a tablet computer, a desktop computer, a laptop computer, a handheld computer, a notebook computer, an ultra-mobile personal computer (UMPC), a netbook, a cellular phone, a personal digital assistant (PDA), and a vehicle-mounted device; and the server can be an entity device.

[0054] The device side can be an external device or an expansion card connected to the host, such as an image acquisition card, a network adapter, a graphics card, a storage controller, etc.

[0055] The data transmission method of the present embodiment can be applied to Figure 1 The data transmission system is shown to realize the transmission of data between the device side and the host side. The following describes the data transmission method of the present embodimentFigure 2 The data transmission method according to an embodiment of the present disclosure is introduced.

[0056] Figure 2 A flow chart of the data transmission method according to an embodiment of the present disclosure is shown. The method can be used for DMA on the device side, such as Figure 2 As shown, the method can include:

[0057] In step S201, the DMA receives a descriptor.

[0058] The descriptor can include a source address, a destination address, and indication information. The descriptor can be configured by a driver on the device side and sent to the DMA. The driver can configure the descriptor after receiving a data transmission request (such as indicating that data is to be written from the device side to the host side) from an upper layer (such as an application layer or a protocol stack).

[0059] Figure 3 A schematic diagram of the descriptor according to an embodiment of the present disclosure is shown. As shown, Figure 3 The descriptor can include a source address (such as src_address in the figure), a destination address (such as dst_address in the figure), and indication information (such as trans_dir in the figure). The DMA can generate a write data request according to the descriptor, indicating that the target data of the source address is to be read and written to the destination address.

[0060] The indication information is determined and configured based on the source address and the destination address. In the case where the source address is an address of the memory on the device side and the destination address is an address of the system memory on the host side, the indication information in the descriptor can be configured as a preset value (such as 1), indicating that the transmission direction of the target data is from the device side to the host side; in the case where the source address is not an address of the memory on the device side or the destination address is not an address of the system memory on the host side, the indication information in the descriptor can be configured as a non-preset value (such as 0) or a default value, indicating that the transmission direction of the target data is from the host side to the device side. The descriptor can also include the size of the target data (such as trans_size in the figure, for example, 1G).

[0061] In an embodiment of the present disclosure, by adding the indication information in the descriptor, the subsequent DMA can automatically generate a read data request based on the indication information after sending the target data to the PCIe based on the descriptor (without the need for the driver to configure the descriptor again), realizing the cooperation of software and hardware to ensure the consistency of data transmission and reading.

[0062] In step S202, the DMA obtains the target data corresponding to the source address in the descriptor and sends the target data to the PCIe.

[0063] The device-side DMA can take the target data from the source address according to the descriptor, and send the target data to the PCIe, which can be used to write the target data to the destination address.

[0064] In a possible implementation, the source address in the descriptor is an address of a device-side memory, the destination address is an address of a host-side system memory, the indication information is 1, and the size of the target data is 1G. The DMA can take the target data with the size of 1G from the address of the device-side memory and send the target data to the PCIe, and the PCIe can receive the target data and write the target data to the address of the host-side system memory.

[0065] After receiving the target data sent by the DMA, the PCIe will send a reply to the DMA to indicate that the target data has been received. The DMA will consider that the target data has been transmitted when receiving the reply sent by the PCIe. However, at this time, the target data can not have been written into the destination address (for example, the system memory). If the DMA considers that the data has been transmitted and reports an interrupt to the CPU on the host side, the CPU cannot read the correct data from the destination address. In order to prevent the above situation from occurring, in the embodiment of the present disclosure, the DMA can generate a read data request according to the indication information in the descriptor. If the indication information is a preset value, the DMA does not need to configure the descriptor by the driver on the device side, but generates the read data request automatically. The combination of software (adding an indication information in the descriptor) and hardware (the DMA generates a read data request when the indication information in the descriptor is the preset value) ensures that all target data has been written into the system memory on the host side before the DMA sends the interrupt information, as described below.

[0066] In step S203, the DMA sends a read data request to the PCIe when the target data has been sent to the PCIe and the indication information in the descriptor is the preset value.

[0067] The read data request sent by the DMA to the PCIe can be used to read the data corresponding to the reference address, where the reference address can be determined by the DMA based on the destination address. For example, the read data request sent by the DMA to the PCIe can be used to read the data with the same size as the target data in the destination address, or can be used to read more or less data than the target data. For example, the destination address in the descriptor is the address of the system memory on the host side, the indication information is 1, and the size of the target data is 1G. The read data request can be used to read the data with the size of 1G in the address of the system memory on the host side. At this time, the reference address is the destination address. The read data request can also be used to read only the data smaller than 1G (for example, one or more bits) in the address of the system memory on the host side. At this time, the reference address can be part of the destination address, so that the amount of data transmission in the read data process can be saved.

[0068] In the case that the DMA receives the data corresponding to the read data request returned by the PCIe, the DMA sends interrupt information to the CPU on the host side, so that the CPU reads the data corresponding to the destination address.

[0069] In the present disclosure, the characteristic of the PCIe is utilized, that is, the read data request of the PCIe waits until all write data requests before the read data request are completed. Therefore, in the present disclosure, the read data request is generated by the DMA according to the indication information in the descriptor and sent to the PCIe, when the read data request is completed (that is, when the DMA receives the data corresponding to the read data request returned by the PCIe), it indicates that all write data requests before the read data request have been completed, so that it can be guaranteed that the target data has been written into the system memory on the host side.

[0070] The interrupt information can be used to request the attention of the CPU and cause the CPU to pause the task being executed at present and process the task of the interrupt event. In the present disclosure, the task of the interrupt event can be implemented based on the target data written into the destination address, and the CPU can read the corresponding data from the destination address and execute the corresponding task after receiving the interrupt information.

[0071] The generation mode of the interrupt information can be implemented based on the prior art, and the present application does not limit this.

[0072] According to the embodiments of the present disclosure, the DMA on the device side receives the descriptor and obtains the target data corresponding to the source address in the descriptor, and sends the target data to the PCIe, wherein the PCIe is used to write the target data into the destination address, the descriptor includes the source address, the destination address and the indication information, the DMA sends a read data request to the PCIe in the case that the target data has been sent to the PCIe and the indication information of the descriptor is a preset value, the DMA sends interrupt information to the CPU on the host side in the case that the DMA receives the data corresponding to the read data request returned by the PCIe, so that the CPU reads the data corresponding to the destination address. The characteristic of the PCIe is utilized, the cooperation of the software level (the field of the indication information is added in the descriptor) and the hardware level (the read data request is automatically sent by the DMA based on the added indication information field) is realized, so that the target data can be correctly and completely read from the destination address by the CPU on the host side, the integrity and correctness of data transmission are guaranteed, and the data transmitted by the device side and the data read by the CPU on the host side have consistency.

[0073] The method can further include: in the case that the target data has been sent to the PCIe and the indication information of the descriptor is a non-pre-set value or a default value, the DMA sends interrupt information to the CPU on the host side, so that the CPU reads the data corresponding to the destination address.

[0074] At this time, the source address can not be the address of the device-side memory, or the destination address can be the address of the system memory on the host side, and the DMA can not need to generate a read data request again.

[0075] Figure 4 A structure diagram of a data transmission apparatus according to an embodiment of the present disclosure is shown. The apparatus is used for device-side direct memory access (DMA), and the device side is connected with the host side through a high-speed serial bus (PCIe). As shown in the figure, the apparatus includes: Figure 4

[0076] The receiving module 401 is configured to receive a descriptor by the DMA, and the descriptor includes a source address, a destination address, and indication information.

[0077] The first sending module 402 is configured to acquire target data corresponding to the source address in the descriptor by the DMA, and send the target data to the PCIe, which is configured to write the target data into the destination address.

[0078] The second sending module 403 is configured to send a read data request to the PCIe by the DMA in a case where the target data has been sent to the PCIe and the indication information of the descriptor is a preset value.

[0079] The third sending module 404 is configured to send interrupt information to a central processing unit (CPU) on the host side by the DMA in a case where data corresponding to the read data request returned by the PCIe is received, so that the CPU reads the target data corresponding to the destination address.

[0080] In a possible implementation, the indication information is determined and configured based on the source address and the destination address.

[0081] In a possible implementation, in a case where the source address is the address of the device-side memory and the destination address is the address of the system memory on the host side, the indication information in the descriptor is configured as a preset value.

[0082] In a possible implementation, in a case where the source address is not the address of the device-side memory or the destination address is not the address of the system memory on the host side, the indication information in the descriptor is configured as a non-pre-set value or a default value.

[0083] In a possible implementation, the read data request sent by the DMA to the PCIe is used to read data corresponding to a reference address, and the reference address is determined by the DMA based on the destination address.

[0084] ​According to the embodiment of the present disclosure, the device side receives a DMA descriptor and obtains target data corresponding to a source address in the descriptor, and sends the target data to a PCIe, wherein the PCIe is configured to write the target data into a destination address, the descriptor includes the source address, the destination address and indication information, the DMA sends a read data request to the PCIe in a case that the target data has been sent to the PCIe and the indication information of the descriptor is a preset value, the DMA sends interrupt information to a CPU on the host side in a case that data corresponding to the read data request returned by the PCIe is received, and the CPU reads data corresponding to the destination address, the characteristics of the PCIe are utilized, the cooperation of the software level (a field of the indication information is added in the descriptor) and the hardware level (the DMA automatically sends the read data request based on the added indication information field) is realized, the target data can be correctly and completely read from the destination address by the CPU on the host side, the integrity and correctness of data transmission are ensured, and the data transmitted by the device side and the data read by the CPU on the host side are consistent.

[0085] The embodiment of the present disclosure also provides a data transmission system. The system includes a device side and a host side, the device side and the host side are connected through a high-speed serial bus PCIe,

[0086] The direct memory access (DMA) on the device side is configured to:

[0087] receive a descriptor, the descriptor including a source address, a destination address and indication information;

[0088] obtain target data corresponding to the source address in the descriptor, and send the target data to the PCIe;

[0089] send a read data request to the PCIe in a case that the target data has been sent to the PCIe and the indication information of the descriptor is a preset value;

[0090] send interrupt information to a central processing unit (CPU) on the host side in a case that data corresponding to the read data request returned by the PCIe is received;

[0091] The CPU is configured to:

[0092] read target data corresponding to the destination address in response to receiving the interrupt information;

[0093] The PCIe is configured to:

[0094] write the target data into the destination address.

[0095] In a possible implementation, the indication information is determined and configured based on the source address and the destination address.

[0096] In a possible implementation, in a case where the source address is an address of the device-side memory and the destination address is an address of the host-side system memory, the indication information in the descriptor is configured as a preset value.

[0097] In a possible implementation, in a case where the source address is not an address of the device-side memory or the destination address is not an address of the host-side system memory, the indication information in the descriptor is configured as a nonpreset value or a default value.

[0098] In a possible implementation, the read data request sent by the DMA to the PCIe is used to read data corresponding to the reference address, where the reference address is determined by the DMA based on the destination address.

[0099] According to the embodiments of the present disclosure, the descriptor is received by the device-side DMA, and target data corresponding to the source address in the descriptor is obtained, and the target data is sent to the PCIe, where the PCIe is used to write the target data to the destination address, the descriptor includes the source address, the destination address, and indication information, the DMA sends a read data request to the PCIe in a case where the target data has been sent to the PCIe and the indication information of the descriptor is a preset value, the DMA sends interrupt information to a CPU on the host side in a case where data corresponding to the read data request returned by the PCIe is received, and the CPU reads data corresponding to the destination address. The embodiments of the present disclosure take advantage of the characteristics of the PCIe, realize the cooperation of the software level (a field of the newly added indication information in the descriptor) and the hardware level (the DMA automatically sends a read data request based on the newly added indication information field), and enable the target data to be correctly and completely read from the destination address by the CPU on the host side, thereby guaranteeing the integrity and correctness of data transmission and enabling the data transmitted by the device side and the data read by the CPU on the host side to be consistent.

[0100] In some embodiments, the apparatus provided by the embodiments of the present disclosure has functions or includes modules that can be used to execute the methods described in the above method embodiments, and the specific implementation can be referred to the description of the above method embodiments, which will not be described here in detail for simplicity.

[0101] The embodiments of the present disclosure also provide a computer-readable storage medium having computer program instructions stored therein, and the computer program instructions are executed by a processor to implement the above method. The computer-readable storage medium can be a volatile or nonvolatile computer-readable storage medium.

[0102] The embodiments of the present disclosure also provide a data transmission apparatus, including a processor, and a memory for storing processor-executable instructions, and the processor is configured to implement the above method when executing the instructions stored in the memory.

[0103] The embodiment of the present disclosure further provides a computer program product, comprising computer readable code or a nonvolatile computer readable storage medium carrying computer readable code, when the computer readable code is executed in a processor of an electronic device, the processor in the electronic device performs the above method.

[0104] Figure 5 is a block diagram of an apparatus 1900 for data transmission according to an exemplary embodiment. For example, the apparatus 1900 can be provided as a server or a terminal device. Referring to Figure 5 , the apparatus 1900 includes a processing component 1922, which further includes one or more processors, and a memory resource represented by a memory 1932 for storing instructions executable by the processing component 1922, such as an application program. The application program stored in the memory 1932 can include one or more than one module each corresponding to a set of instructions. In addition, the processing component 1922 is configured to execute the instructions to perform the above method.

[0105] The apparatus 1900 can also include a power supply component 1926 configured to perform power management of the apparatus 1900, a wired or wireless network interface 1950 configured to connect the apparatus 1900 to a network, and an input output interface 1958 (I / O interface). The apparatus 1900 can operate based on an operating system stored in the memory 1932, such as Windows Server TM , MacOS X TM , Unix TM , Linux TM , FreeBSD TM or the like.

[0106] In exemplary embodiments, a non-volatile computer readable storage medium, such as the memory 1932 including computer program instructions, is also provided, which can be executed by the processing component 1922 of the apparatus 1900 to complete the above method.

[0107] The present disclosure can be a system, a method, and / or a computer program product. The computer program product can include a computer readable storage medium (or media) having computer readable program instructions thereon for causing a processor to carry out aspects of the present disclosure.

[0108] Computer readable storage media can be tangible storage media which can retain and store instructions for use by an instruction execution device. Computer readable storage media can be, for example, but is not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the foregoing. More specific examples (a non-exhaustive list) of computer readable storage media include the following: a portable computer diskette, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or Flash memory), a static random access memory (SRAM), a portable compact disc read-only memory (CD-ROM), a digital versatile disk (DVD), a memory stick, a floppy disk, a mechanically encoded device such as punch-cards or raised structures in a groove having instructions recorded thereon, and any suitable combination of the foregoing. A computer readable storage medium, as used herein, is not to be construed as being transitory signals per se, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through a waveguide or other transmission media (e.g., light pulses passing through a fiber-optic cable), or electrical signals transmitted through a wire.

[0109] Computer readable program instructions described herein can be downloaded to respective computing / processing devices from a computer readable storage medium or to an external computer or external storage device via a network, for example, the Internet, a local area network, a wide area network and / or a wireless network. The network can comprise copper transmission cables, optical transmission fibers, wireless transmission, routers, firewalls, switches, gateway computers and / or edge servers. A network adapter card or network interface in each computing / processing device receives computer readable program instructions from the network and forwards the computer readable program instructions for storage in a computer readable storage medium within the respective computing / processing device.

[0110] Computer readable program instructions for carrying out operations of the present disclosure can be assembler instructions, instruction-set-architecture (ISA) instructions, machine instructions, machine dependent instructions, microcode, firmware instructions, state-setting data, or either source code or object code written in any combination of one or more programming languages, including an object oriented programming language such as Smalltalk, C++ or the like and conventional procedural programming languages, such as the "C" programming language or similar programming languages. The computer readable program instructions can execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server. In the latter scenario, the remote computer can be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or the connection can be made to an external computer (for example, through the Internet using an Internet Service Provider). In some embodiments, electronic circuitry including, for example, programmable logic circuitry, field-programmable gate array (FPGA), or programmable logic array (PLA) can execute the computer readable program instructions by utilizing state information of the computer readable program instructions to personalize the electronic circuitry, in order to perform aspects of the present disclosure.

[0111] The computer readable program instructions can also be loaded onto a computer, other programmable data processing apparatus, or other device to cause a series of operational steps to be performed on the computer, other programmable apparatus or other device to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide processes for implementing the functions / acts specified in the flowchart and / or block diagram block or blocks.

[0112] These computer readable program instructions can be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions / acts specified in the flowchart and / or block diagram block or blocks. These computer readable program instructions can also be stored in a computer readable storage medium that can include random access memory (RAM), read only memory (ROM), electrically erasable programmable read only memory (EEPROM), flash memory or other data storage device. When the computer readable program instructions are loaded into the computer and other programmable data processing apparatus, a series of operational steps are implemented that provide processes such that the computer or other programmable apparatus provide processes for implementing the functions / acts specified in the flowchart and / or block diagram block or blocks.

[0113] The computer readable program instructions can also be loaded onto a computer, other programmable data processing apparatus, or other device to cause a series of operational steps to be performed on the computer, other programmable data processing apparatus or other device to produce a computer implemented process such that the instructions which execute on the computer, other programmable data processing apparatus, or other device implement the functions / acts specified in the flowchart and / or block diagram block or blocks.

[0114] The flow diagrams and the block diagrams in the drawings are presented to illustrate the architecture, functionality, and operation of possible implementations of systems, methods and computer program products according to various embodiments of the present disclosure. In this regard, each block in the flow diagrams and the block diagrams can represent a module, segment, or portion of instructions, which comprises one or more executable instructions for implementing the specified logic functions. In some alternative implementations, the functions noted in the blocks can occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks can sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and / or flow diagrams, and combinations thereof, can be implemented by special purpose hardware-based systems that perform the specified functions or acts, or combinations of special purpose hardware and

[0115] Embodiments of the present disclosure have been described above, and the description is intended to be illustrative of the embodiments and not restrictive. Many modifications and variations of the described embodiments are possible and are within the scope of the disclosure. The selection of terms is intended to best describe the principles of the embodiments, practical application, or technical improvements in the art, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A data transmission method, characterized by, The method is used for device side direct memory access (DMA), the device side is connected with the host side through a high-speed serial bus (PCIe), and the method comprises: The DMA receives a descriptor, the descriptor comprising a source address, a destination address and indication information; The DMA obtains target data corresponding to the source address in the descriptor, and sends the target data to the PCIe, the PCIe being configured to write the target data into the destination address; The DMA sends a read data request to the PCIe in the case that the target data has been sent to the PCIe and the indication information of the descriptor is a preset value; The DMA sends interrupt information to a central processing unit (CPU) of the host side in the case that the DMA receives data corresponding to the read data request returned by the PCIe, so that the CPU reads data corresponding to the destination address.

2. The method of claim 1, wherein, The indication information is determined and configured based on the source address and the destination address.

3. The method of claim 2, wherein, In the case that the source address is an address of a device side memory and the destination address is an address of a system memory of the host side, the indication information in the descriptor is configured as the preset value.

4. The method of claim 2, wherein, In the case that the source address is not an address of a device side memory or the destination address is not an address of a system memory of the host side, the indication information in the descriptor is configured as a non-pre-set value or a default value.

5. The method of claim 2, wherein, The read data request sent by the DMA to the PCIe is used to read data corresponding to a reference address, wherein the reference address is determined by the DMA based on the destination address.

6. A data transmission apparatus characterized by comprising: The device is used for device side direct memory access (DMA), the device side is connected with the host side through a high-speed serial bus (PCIe), and the device comprises: A receiving module is configured to receive a descriptor by the DMA, the descriptor comprising a source address, a destination address and indication information; A first sending module is configured to obtain target data corresponding to the source address in the descriptor by the DMA, and send the target data to the PCIe, the PCIe being configured to write the target data into the destination address; A second sending module is configured to send a read data request to the PCIe by the DMA in the case that the target data has been sent to the PCIe and the indication information of the descriptor is a preset value; A third sending module is configured to send interrupt information to a central processing unit (CPU) of the host side by the DMA in the case that the DMA receives data corresponding to the read data request returned by the PCIe, so that the CPU reads data corresponding to the destination address.

7. A data transmission system, characterized in that The system comprises a device side and a host side, the device side and the host side being connected through a high-speed serial bus (PCIe), The device side direct memory access (DMA) is configured to: receive a descriptor, the descriptor comprising a source address, a destination address and indication information; obtain target data corresponding to the source address in the descriptor, and send the target data to the PCIe; send a read data request to the PCIe in the case that the target data has been sent to the PCIe and the indication information of the descriptor is a preset value; In a case that the read data request corresponding to the PCIe return data is received, the interrupt information is sent to the central processing unit (CPU) of the host side; The CPU is configured to: read the target data corresponding to the destination address in response to receiving the interrupt information; The PCIe is configured to: write the target data to the destination address.

8. The system of claim 7, wherein, The indication information is determined and configured based on the source address and the destination address.

9. The system of claim 8, wherein, In a case that the source address is the address of the device side memory and the destination address is the address of the system memory of the host side, the indication information in the descriptor is configured as the preset value.

10. The system of claim 8, wherein, In a case that the source address is not the address of the device side memory or the destination address is not the address of the system memory of the host side, the indication information in the descriptor is configured as a non-pre-set value or a default value.

11. A data transmission apparatus, characterized by comprising: Comprise: a processor; a memory for storing processor-executable instructions; wherein the processor is configured to implement the method of any one of claims 1 to 5 when executing the instructions stored in the memory.

12. A non-transitory computer readable storage medium having stored thereon computer program instructions, wherein, The computer program instructions are executed by the processor to implement the method of any one of claims 1 to 5.

13. A computer program product comprising a computer program or a non-transitory computer-readable storage medium bearing a computer program, characterized in that, The computer program is executed by the processor to implement the method of any one of claims 1 to 5.

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