Plug-in device and signal transmission method

Abstract

The present application provides a plug-in device and a signal transmission method, which can be applied to the field of hardware technology. The plug-in device may include a card, including at least an interconnection line and a clock line; the card can be connected to at least one storage device and is configured to transmit an interconnection signal to the storage device via the interconnection line and transmit a clock signal to the storage device via the clock line.

Description

Technical Field

[0001] The present application relates to the field of hardware technology, and in particular to a plug-in device and a signal transmission method. Background Art

[0002] The M.2 interface is a host interface solution compatible with various communication protocols, including Serial Attached Small Computer System Interface / Serial Advanced Technology Attachment (SAS / SATA) and Peripheral Component Interconnect Express (PCIe). However, the limitations of the M.2 interface have limited the development of disk redundancy technology for M.2 drives. Summary of the Invention

[0003] In view of the above problems, the present application provides a plugging and unplugging device and a signal transmission method.

[0004] According to the first aspect of the present application, a plug-in device is provided, including a board card, which includes at least an interconnection line and a clock line; the board card can be connected to at least one storage device and is configured to transmit an interconnection signal to the storage device via the interconnection line, and to transmit a clock signal to the storage device via the clock line.

[0005] A second aspect of the present application provides a signal transmission method, comprising: a board in a plug-in device transmits an interconnection signal to a storage device via an interconnection line, and transmits a clock signal to the storage device via a clock line.

[0006] According to an embodiment of the present application, the board can transmit signals to at least one storage device through at least one of the interconnection lines and the clock lines, thereby achieving compatibility with storage devices with different communication protocols, breaking through the limitations of some types of storage device interfaces (such as the M.2 interface), and improving the convenience of server maintenance. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The above contents and other objects, features and advantages of the present application will become more apparent through the following description of the embodiments of the present application with reference to the accompanying drawings, in which:

[0008] Figure 1 A schematic diagram of a plugging and unplugging device according to an embodiment of the present application is shown.

[0009] Figure 2 A schematic diagram of a board according to an embodiment of the present application is shown.

[0010] Figure 3 A schematic diagram of a board according to another embodiment of the present application is shown.

[0011] Figure 4 A schematic diagram of a board according to another embodiment of the present application is shown.

[0012] Figure 5 A schematic diagram of a board according to another embodiment of the present application is shown.

[0013] Figure 6 A schematic diagram of a board according to another embodiment of the present application is shown.

[0014] Figure 7 A schematic diagram of a board according to another embodiment of the present application is shown.

[0015] Figure 8 A schematic diagram of a board according to another embodiment of the present application is shown.

[0016] Figure 9 A schematic diagram of a board according to another embodiment of the present application is shown.

[0017] Figure 10 A schematic diagram of a board according to another embodiment of the present application is shown.

[0018] Figure 11 A schematic diagram of a carrier card according to an embodiment of the present application is shown.

[0019] Figure 12A A schematic diagram of a board according to another embodiment of the present application is shown.

[0020] Figure 12B A schematic diagram of a board according to another embodiment of the present application is shown.

[0021] Figure 13 A flow chart of a storage device hot-plugging method according to an embodiment of the present application is shown.

[0022] Figure 14 A flow chart of a method for hot-plugging a storage device according to an embodiment of the present application is shown.

[0023] Figure 15 1 and 2 show a front view and a side view of a carrier card according to another embodiment of the present application.

[0024] Figure 16 A schematic perspective view of a carrier card according to another embodiment of the present application is shown.

[0025] Figure 17 A schematic perspective view of a carrier card according to another embodiment of the present application is shown.

[0026] Figure 18A schematic perspective view of a carrier card according to another embodiment of the present application is shown.

[0027] Figure 19 A schematic diagram of a plugging and unplugging device according to another embodiment of the present application is shown.

[0028] Figure 20 A schematic diagram of a plugging and unplugging device according to another embodiment of the present application is shown.

[0029] Figure 21 A front view and a side view of a plugging device according to another embodiment of the present application are shown.

[0030] Figure 22 A schematic perspective view of a plugging device according to another embodiment of the present application is shown.

[0031] Figure 23 A schematic perspective view of a plugging device according to another embodiment of the present application is shown.

[0032] Figure 24 A flow chart of a signal transmission method according to an embodiment of the present application is shown. DETAILED DESCRIPTION

[0033] Hereinafter, embodiments of the present application will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the present application. In the detailed description below, for ease of explanation, many specific details are set forth to provide a comprehensive understanding of the embodiments of the present application. However, it is apparent that one or more embodiments may also be implemented without these specific details. In addition, in the following description, descriptions of known structures and technologies are omitted to avoid unnecessarily confusing the concepts of the present application.

[0034] The terms used herein are only for describing specific embodiments and are not intended to limit this application. The terms "comprise," "include," etc. used herein indicate the presence of the features, steps, operations, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, or components.

[0035] All terms used herein (including technical and scientific terms) have the meanings commonly understood by those skilled in the art unless otherwise defined. It should be noted that the terms used herein should be interpreted as having a meaning consistent with the context of this specification and should not be interpreted in an idealized or overly rigid manner.

[0036] When expressions such as "at least one of A, B, and C, etc." are used, they should generally be interpreted in accordance with the meaning commonly understood by those skilled in the art (for example, "a system having at least one of A, B, and C" should include but is not limited to a system having A alone, B alone, C alone, A and B, A and C, B and C, and / or A, B, C, etc.).

[0037] It should be noted that the terms "center," "longitudinal," "transverse," "length," "width," "thickness," "upper," "lower," "front," "back," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," "circumferential," and the like, indicating positions or relationships, are based on the positions or relationships shown in the accompanying drawings and are intended solely for ease of description and simplification of the present application. They are not intended to indicate or imply that the devices or components referred to must have, be constructed, or operate in a specific orientation, and therefore should not be construed as limiting the present application. The terms "mounted," "connected," and "connected" should be interpreted broadly, and may include, for example, fixed, removable, or integral connections; mechanical or electrical connections; direct or indirect connections through an intermediary; and internal communication between two components. The terms "parallel," "perpendicular," and "equal" encompass the described conditions and conditions similar to the described conditions, provided that the range of the similar conditions is within an acceptable range of deviation, as determined by a person of ordinary skill in the art taking into account the measurement in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system). For example, "parallel" includes both absolute parallelism and approximate parallelism, where the acceptable deviation range for approximate parallelism may be, for example, within 5°; "perpendicular" includes both absolute perpendicularity and approximate perpendicularity, where the acceptable deviation range for approximate perpendicularity may also be, for example, within 5°. "Equal" includes both absolute equality and approximate equality, where the acceptable deviation range for approximate equality may be, for example, that the difference between the two is less than or equal to 5% of either. Those skilled in the art will understand the specific meanings of the above terms in this application based on the specific circumstances.

[0038] In some solutions, the PCIe slots on the server motherboard can be expanded to flexibly configure Redundant Array of Independent Disks (RAID) storage cards or SATA storage cards, supporting hardware RAID. Hardware RAID can conserve server system central processing unit (CPU) and operating system resources, thereby improving server performance.

[0039] On this basis, the M.2 interface has gradually become an important choice in server configuration. For example, the system boot disk often uses an M.2 hard drive. However, the M.2 interface has some limitations. M.2 hard drives can be divided into two types: Non-Volatile Memory express (NVME) and SATA. On this basis, it is difficult for the RAID card to achieve adaptive interconnection of M.2 hard drives with different communication protocols. If the RAID card is to be interconnected with M.2 hard drives with different communication protocols, it is usually necessary to replace the hard drive backplane at the same time. In this case, the unpacking operation of the server will bring difficulties to maintenance. In view of this, the present application provides a plug-in device to support the hardware RAID function of storage devices with different communication protocols.

[0040] Figure 1 A schematic diagram of a plugging and unplugging device according to an embodiment of the present application is shown.

[0041] like Figure 1 As shown, the plug-in device of this embodiment may include a card C. Card C may include multiple circuits disposed within card C, such as traces. Thus, card C may be electrically connected to a storage device H, such as an M.2 hard drive, via multiple circuits. It should be understood that the number of components shown in the drawings is for illustrative purposes only; to achieve disk redundancy, multiple storage devices H may be used.

[0042] The multiple lines may include at least multiple interconnection lines, but are not limited thereto. In other embodiments of the present application, they may also include lines such as clock lines. Board C may be interconnected with storage device H via interconnection lines. For example, board C may perform read or write operations on storage device H via interconnection lines, thereby realizing hardware RAID functionality. Board C may also send a clock signal to storage device H via a clock line. It should be understood that the embodiments of the present application are not limited thereto. In other embodiments of the present application, board C may also include lines such as a reset line. Board C may send a reset signal to storage device H via a reset line. In another embodiment of the present application, board C may also include other interconnection lines to interconnect the server motherboard MB with storage device H, and so on. It should be understood that the present application does not limit the number of various lines in the multiple lines.

[0043] On this basis, the board C can have multiple modes. For example, the multiple modes may include but are not limited to SATA mode and NVMe mode. In different modes, the board C can transmit signals to storage devices H with different communication protocols through different lines among the multiple lines. For example, the interconnection line can be a PCIe / SAS bus. In one mode, for a storage device H that supports the SATA protocol, the board C can interconnect with the storage device H based on the signal of the corresponding protocol via the interconnection line; while for the storage device H of the NVMe protocol, another mode is required, in which the clock signal can be transmitted via the clock line, and the interconnection is based on the PCIe signal via the interconnection line. In some embodiments, the clock signal can also be transmitted to the storage device H only via the clock line.

[0044] In this way, the board C in the present application can transmit signals to at least one storage device H through at least one of the interconnection lines and the clock lines, thereby achieving compatibility with storage devices H with different communication protocols, breaking through the limitations of some types of storage device H interfaces (such as M.2 interfaces), and improving the convenience of server maintenance.

[0045] Figure 2 A schematic diagram of a board C according to an embodiment of the present application is shown.

[0046] like Figure 2 As shown, the board C in this embodiment includes a first board 100 and a second board 200 that are electrically connected. The first board 100 can be used to connect to a storage device H. The second board 200 can be used to connect to a server motherboard MB. In the solution of this application, the board implementing the disk redundancy function can be the second board 200, and the first board 100 can electrically connect the storage device H and the second board 200. In this case, multiple circuits are provided within the first board 100, allowing the second board 200 to be electrically connected to the storage device H via the multiple circuits within the first board 100. When the multiple circuits are electrically connected to the storage device H, different modes can be used to implement hardware RAID functionality for storage devices H using different communication protocols. For example, the different communication protocols include the Serial Advanced Technology Attachment (SATA) protocol and the Non-Volatile Memory Express (NVMe) protocol. The multiple modes can include a first mode (e.g., an NVMe mode) and a second mode (e.g., a SATA mode). In the first mode, the board C can transmit signals to the storage device H via interconnect circuits and clock lines. In the second mode, the disk redundancy can transmit signals to the storage device H via the interconnection line, without requiring a clock signal. For example, the interconnection line can transmit signals of different communication protocols in different modes. Specifically, in the first mode, the interconnection line can transmit PCIe signals; in the second mode, the interconnection line can transmit SATA signals.

[0047] Furthermore, according to protocol specifications, the M.2 interface struggles to support hot-swapping of storage devices H. Performing hot-swapping could pose a risk to the M.2 hard drive itself, the server's system platform, and the personnel performing the operation. Therefore, compared to storage devices H with other interface types, the maintainability of M.2 interface storage devices H is poor. However, in the present application, board C can support hot-swapping of storage devices H with different communication protocols. For example, board C can detect the communication protocols supported by storage device H and the hot-swapping process of storage device H, and then perform operations related to storage device H based on the detection results. For example, if a hot-swapping process is in progress but not completed, interconnection with storage device H may be temporarily suspended until the hot-swapping process is complete. For a hot-unplugging process, interconnection with storage device H may be suspended while the hot-unplugging process is in progress or completed. Thus, the multiple modes of board C can be used to transmit different signals to storage device H when hot-swapping storage devices H with different communication protocols are in progress.

[0048] In this way, the second board 200 in the present application can transmit signals with storage devices H of different communication protocols through different lines among the multiple lines within the first board 100 in different modes, and is compatible with hot-plugging of storage devices H of different communication protocols, breaking through the limitations of the M.2 interface and improving the maintainability of the server.

[0049] Figure 3 A schematic diagram of a board C according to another embodiment of the present application is shown.

[0050] like Figure 3As shown, the first board 100 of this embodiment may include a first interface 10 and a second interface 20. The first interface 10 is used to electrically connect multiple lines to a storage device H. The second interface 20 may be electrically connected to the first interface 10 via multiple lines. The second board 200 may include a third interface 30, which may be electrically connected to the second interface 20 of the first board 100. This allows for electrical connection between the first board 100, the second board 200, and the storage device H. For example, the first interface 10 may support hot swapping of components connected to the first interface 10. In this embodiment, the component may be the storage device H, but the present invention is not limited thereto. The component may also be a device used to support the storage device H (e.g., a carrier board described below). Specifically, the first interface 10 may be a Generic Non-Volatile Memory (GENZ) interface (e.g., a GENZ connector). Correspondingly, the interface of the device used to electrically connect to the first interface 10 may also be a GENZ interface (e.g., a GENZ gold finger). However, it should be understood that the embodiments of the present application are not limited thereto. In other embodiments of the present application, the first interface 10 may also be another interface that supports hot plugging. The present application does not impose any restrictions on the types of the second interface 20 of the first board 100 and the third interface 30 of the second board 200. Any interface that can implement the solution of the present application is sufficient.

[0051] In this way, the present application electrically connects the storage device H to the first board 100 by using the hot-swappable first interface 10, and electrically connects the first board 100 and the second board 200 through the second interface 20 of the first board 100 and the third interface 30 of the second board 200, that is, the second board is electrically connected to the interface of the M.2 hard disk that does not support hot-swappable through the first board, that is, the interface of the M.2 hard disk that does not support hot-swappable is transferred through the first board, so that the second board 200 can transmit signals with the storage device H of different communication protocols through different lines of the multiple lines in the first board 100 in different modes, and is compatible with the hot-swappable storage device H of different communication protocols, breaking through the limitations of the M.2 interface and improving the maintainability of the server.

[0052] Figure 4 A schematic diagram of a board C according to another embodiment of the present application is shown.

[0053] like Figure 4As shown, the first board 100 of this embodiment may further include a determination module 110. The determination module 110 may be electrically connected to the first interface 10 of the first board 100 and may determine whether to transmit signals to the first interface 10 for different communication protocols. Specifically, for the NVMe protocol, the determination module 110 may transmit a signal, such as a reset signal, to the first interface 10. For the SATA protocol, the determination module 110 may not transmit a reset signal to the first interface 10. In this way, the determination module 110 may provide or not provide a signal to the first interface 10 for storage devices H with different communication protocols, thereby meeting the signal requirements of storage devices H with different communication protocols. This allows compatibility with storage devices H with different communication protocols and overcomes the limitations of M.2 hard drives. Furthermore, the determination module 110 may detect the communication protocols supported by the storage device H to determine whether to transmit signals to the first interface 10. Furthermore, the determination module 110 may detect the hot-swap progress of the storage device H and indicate to the second board 200 whether the hot-swap process of the storage device H is complete. Then, the second board 200 can transmit signals to the storage device H via multiple lines only after the hot-plug process is completed. In addition, in the drawings of this application, other lines except the multiple lines are only used to illustrate the electrical connection relationship and are not used to limit the number of lines actually electrically connected between multiple devices in this application. They will not be described in detail below.

[0054] Figure 5 A schematic diagram of a board C according to another embodiment of the present application is shown.

[0055] In the present application, the judgment module may include at least one of the first isolation circuit BF1 and the second isolation circuit and the first controller CT1. For example, the first isolation circuit BF1 and the second isolation circuit may be input / output buffer circuits (‌I / O Buffer). The at least one isolation circuit is electrically connected to the first controller CT1 and the first interface 10. For example, Figure 5 As shown, the first board 100 may include a first isolation circuit BF1, which may be electrically connected to the first controller CT1 and the first interface 10. For example, the first controller CT1 may be a complex programmable logic device (CPLD).

[0056] On this basis, the first controller CT1 is electrically connected to the first interface 10 of the first board 100 and can detect the communication protocol of the storage device H and the hot plug process of the storage device H. For different communication protocols, the first controller CT1 can determine whether to transmit signals to the first interface 10 via at least one isolation circuit. For example, Figure 5As shown, the first controller CT1 can transmit signals to the first interface 10 via the first isolation circuit BF1. In one embodiment, the first controller CT1 can be electrically connected to the first terminal and the enable terminal of the first isolation circuit BF1, and the second terminal of the first isolation circuit BF1 can be electrically connected to the first interface 10. Thus, upon detecting the communication protocol of the storage device H, the first controller CT1 can first send a reset signal to the first terminal of the first isolation circuit BF1 and, through the enable terminal of the first isolation circuit BF1, control the electrical disconnection between the first terminal of the first isolation circuit BF1 and the second terminal electrically connected to the first interface 10. Subsequently, upon detecting that the hot-plug process of the storage device H is complete, the first controller CT1 can send an enable signal to the enable terminal of the first isolation circuit BF1 to control the electrical connection between the first terminal and the second terminal of the first isolation circuit BF1. This causes the reset signal to be sent to the storage device H via the first terminal of the first isolation circuit BF1, the second terminal of the first isolation circuit BF1, and the first interface 10, thereby controlling the reset of the storage device H. In this way, by providing a signal to the storage device H via the first isolation circuit BF1 , abnormal conditions of the storage device H caused by factors such as signal jitter can be avoided, thereby achieving hot swapping of the storage device H.

[0057] In this way, the communication protocol of the storage device H and the hot-swap process of the storage device H can be detected by electrically connecting the first controller CT1 to the first interface 10 of the first board 100. On this basis, the first controller CT1 is electrically connected to at least one of the first isolation circuit BF1 and the second isolation circuit, and the at least one isolation circuit is electrically connected to the first interface 10. In this way, based on the detected communication protocol of the storage device H and the hot-swap process of the storage device H, the first controller CT1 can first send a signal to the isolation circuit, and only provide a signal to the storage device H through the isolation circuit after the hot-swap process of the storage device H is completed. This avoids abnormal conditions in the storage device H due to factors such as signal jitter. This allows for hot-swapping of storage devices H compatible with different communication protocols, overcomes the limitations of the M.2 interface, and improves the maintainability of the server.

[0058] Figure 6 A schematic diagram of a board C according to another embodiment of the present application is shown.

[0059] like Figure 6As shown, the second board 200 includes a second controller CT2. The second controller CT2 is electrically connected to the third interface 30 of the second board 200 and is used to implement a disk redundancy function. For example, the second controller CT2 can be a RAID controller. The second controller CT2 can be electrically connected to multiple pins in the second interface 20 via multiple pins in the third interface 30. The multiple pins in the second interface 20 can be electrically connected to one end of multiple lines, and the other ends of the multiple lines can be electrically connected to multiple pins in the first interface 10, thereby being electrically connected to the storage device H via the multiple pins. On this basis, the second controller CT2 can remain powered on and, when the hot plug of the storage device H with different communication protocols is completed, transmit signals to the storage device H via the multiple lines to implement read and write operations for the storage device H, thereby implementing a disk redundancy function. In this way, the RAID controller is compatible with the hot plugging of M.2 hard drives with different communication protocols, breaking through the limitations of the M.2 interface and improving the maintainability of the server.

[0060] Figure 7 A schematic diagram of a board C according to another embodiment of the present application is shown.

[0061] like Figure 7 As shown, the second isolation circuit BF2 is electrically connected to the first controller CT1 and the first interface 10 and the second interface 20 of the first board 100. For example, the first controller CT1 can be electrically connected to the enable terminal of the second isolation circuit BF2. The first terminal of the second isolation circuit BF2 can be electrically connected to the first interface 10, and the second terminal can be electrically connected to the second interface 20. In this way, when the first controller CT1 controls the electrical connection between the first and second terminals of the second isolation circuit BF2, the second isolation circuit BF2 can also transmit signals between the second board 200 and the storage device H. Furthermore, when the storage device H is electrically connected to the first interface 10, the storage device H can first send a signal to the first terminal of the second isolation circuit BF2. Then, when the hot-swapping process of the storage device H is complete, the first controller CT1 controls the electrical connection between the first and second terminals of the second isolation circuit BF2, thereby transmitting the signal from the storage device H to the second board 200 via the second isolation circuit BF2, the second interface 20, and the third interface 30. In this way, the signal is sent to the first end of the second isolation circuit BF2 in advance through the storage device H, and then transmitted to the second board 200 when the first end and the second end of the second isolation circuit BF2 are electrically connected. This can avoid directly sending the signal and causing a jittered signal to be sent to the second board 200, avoiding abnormal conditions caused by factors such as signal jitter. In this way, hot-plugging of the storage device H compatible with different communication protocols can be achieved, breaking through the limitations of the M.2 interface and improving the maintainability of the server.

[0062] Figure 8 A schematic diagram of a board C according to another embodiment of the present application is shown.

[0063] like Figure 8 As shown, the second board 200 may also include a fourth interface 40. The fourth interface 40 can be electrically connected to the third interface 30 of the second board 200. For example, the fourth interface 40 and the motherboard interface of the server motherboard MB may be a PCIe gold finger and a PCIe slot, respectively. The fourth interface 40 can be used to electrically connect to the motherboard interface of the server motherboard MB. Furthermore, the second isolation circuit BF2 is electrically connected to the management controller BC of the server motherboard MB via the third interface 30, the fourth interface 40, and the motherboard interface. For example, the management controller BC may be a baseboard management controller (BMC). Thus, when the first controller CT1 controls the electrical connection between the first and second ends of the second isolation circuit BF2, the second isolation circuit BF2 can also transmit signals between the server motherboard MB and the storage device H. For example, the signal can be used to monitor the operating status of the storage device H, such as a data signal such as a log.

[0064] For example, when the storage device H is electrically connected to the first interface 10, the storage device H can first send a signal to the first end of the second isolation circuit BF2. Then, when the hot-swapping process of the storage device H is complete, the first controller CT1 controls the electrical connection between the first and second ends of the second isolation circuit BF2, thereby transmitting the signal from the storage device H to the server motherboard MB via the second isolation circuit BF2, the second interface 20, the third interface 30, the fourth interface 40, and the motherboard interface. In this way, by having the storage device H pre-send the signal to the first end of the second isolation circuit BF2 and then only transmitting the signal to the management controller BC of the server motherboard MB when the first and second ends of the second isolation circuit BF2 are electrically connected, it is possible to avoid directly sending the signal, which would result in a jittered signal being sent to the second motherboard 200. This also avoids abnormal conditions such as the management controller BC being hung due to factors such as signal jitter. This allows hot-swapping of storage devices H compatible with different communication protocols, overcomes the limitations of the M.2 interface, and improves the maintainability of the server.

[0065] Figure 9 A schematic diagram of a board C according to another embodiment of the present application is shown.

[0066] like Figure 9As shown, the plug-in device may also include a carrier card 300. The carrier card 300 may be used to carry storage devices H of various sizes. The carrier card 300 may include a fifth interface 50 and a sixth interface 60. The fifth interface 50 may be used to electrically connect to the storage device H. The sixth interface 60 may be used to electrically connect to the first interface 10 of the first board 100. In this way, the storage device H may transmit signals via the fifth interface 50, the carrier card 300 (specifically, it may be a circuit inside the carrier card 300, such as a trace), the sixth interface 60, the first interface 10, and multiple traces of the first board 100, or send signals to the first end of the second isolation circuit BF2. For example, traces for transmitting SATA protocol signals, PCIe protocol signals, reset signals, clock signals, and I2C protocol signals may be provided inside the carrier card 300, which will not be described in detail.

[0067] In addition, the determination module may further include a switching unit. For example, the switching unit may be an I2C switch. The second isolation circuit BF2 is electrically connected to the first controller CT1 and the third interface 30 via the switching unit. In this manner, the first controller CT1 may send a control signal to the enable terminal of the second isolation circuit BF2 via the switching unit to control the electrical connection or disconnection between the first terminal and the second terminal of the second isolation circuit BF2.

[0068] In this way, when the first and second ends of the second isolation circuit BF2 are electrically connected, signals sent by the storage device H can be transmitted to the management controller BC via the fifth interface 50, the sixth interface 60, the first interface 10, the second isolation circuit BF2, the switching unit, the second interface 20, the third interface 30, the fourth interface 40, and the motherboard interface. For example, the switching unit can be electrically connected to the second interface 20 and the first controller CT1 via a system management bus (SMBus). The second interface 20, the third interface 30, and the fourth interface 40 can be electrically connected via the SMBus. The management controller BC can be electrically connected to the motherboard interface via the SMBus. The second controller CT2 can also be connected to the SMBus, thereby interconnecting with other devices via the SMBus. The switching unit can also be electrically connected to the second isolation circuit BF2 via an inter-integrated circuit (I2C), and the second isolation circuit BF2 can be electrically connected to the first interface 10 via the I2C bus.

[0069] In addition, the server motherboard MB may further include a central processing unit (CPU) CP. The CPU CP may be electrically connected to the motherboard interface via a PCIe bus to transmit PCIe signals, such as a PCIe clock signal, via the motherboard interface, the fourth interface 40, and the second controller CT2. It should be understood that the aforementioned connection to the interface may specifically be connected to corresponding pins in the interface, which will not be further described.

[0070] Figure 10 A schematic diagram of a board C according to another embodiment of the present application is shown.

[0071] like Figure 10 As shown, the second board 200 may further include a clock buffer. The clock buffer may provide a clock signal to the clock line. Specifically, the second controller CT2 is electrically connected to the interconnection line via the third interface 30 of the second board 200 and the second interface 20 of the first board 100. The clock buffer is electrically connected to the second controller CT2, and is electrically connected to the clock line and the second controller CT2 via the third interface 30 of the second board 200 and the second interface 20 of the first board 100. The multiple output ends of the clock buffer may be electrically connected to multiple clock lines, respectively. In this way, when the second controller CT2 sends a clock signal to the clock buffer, the clock signal may be sent to the multiple clock lines via the multiple output ends of the clock buffer to provide a clock signal to the multiple storage devices H, so as to achieve hot-swappable compatibility with the storage devices H of the multiple NVMe protocols, break through the limitations of the M.2 interface, and improve the maintainability of the server.

[0072] Figure 11 shows a schematic diagram of a carrier card according to an embodiment of the present application, Figure 12A A schematic diagram of a board C according to another embodiment of the present application is shown.

[0073] like Figure 11 As shown, the carrier card may include a fifth interface 50 and a sixth interface 60. The sixth interface 60 includes a target pin and other pins longer than the target pin. For example, the target pin may be pin 75 of the sixth interface 60. For example, the target pin is used to provide a storage device presence signal. Specifically, the target pin of the sixth interface 60 sends a storage device presence signal to indicate whether the storage device H is in the target position to complete the hot swap process.

[0074] On this basis, the target pin can be electrically connected to the first controller CT1 in the determination module of the first board 100 via the corresponding pin in the first interface 10 of the first board 100, and can provide the first controller CT1 with a storage device presence signal. In this way, the first controller CT1 can detect the hot-plug process. For example, the target pin can be electrically connected to the ground terminal. In this way, during hot-plugging, the target pin is last connected to the first interface 10 and shorted to the ground signal at the ground terminal, causing the pin corresponding to the target pin in the first interface 10 to be at a low level, that is, the storage device presence signal is also low. In this case, the first controller CT1 can determine that the storage device H has been hot-plugged. During hot-plugging, the target pin will first be disconnected from the first interface 10, and the corresponding pin in the first interface 10 will be pulled high by the external power supply. In this case, the first controller CT1 can determine that the hot-plug process is not complete. In this way, if the target pin in the sixth interface 60 is electrically connected to the corresponding pin in the first interface 10, it can be determined that the hot-plug process of the storage device H has been completed. If other pins are electrically connected to the first interface 10 before the target pin, a storage device detection signal can be sent to the first controller CT1, allowing the first controller CT1 to detect the protocol type of the storage device H before the carrier card is in the target position. Based on the protocol type, the first controller CT1 can control the second controller CT2 to connect or stop connecting to the storage device H. This allows hot swapping of storage devices H with different communication protocols. Furthermore, when the target pin is electrically connected to the corresponding pin of the first interface 10, the voltage level of the corresponding pin of the first interface 10 is pulled down based on the ground signal at the ground terminal to send a storage device presence signal to the first interface 10. By electrically connecting the target pin to the ground terminal, the voltage level of the pin of the first board 100 can be pulled down to send a storage device presence signal to the first board 100 when the pin of the first interface 10 is electrically connected to the target pin. This allows hot swapping of storage devices H with different communication protocols.

[0075] like Figure 11 and Figure 12A As shown, the sixth interface 60 may include multiple other pins. Some of these multiple other pins can be electrically connected to multiple circuits. Based on this, the first interface 10 can transmit power signals, high-speed signals (PCIe or SATA signals), and other signals to the sixth interface 60. For example, other pins of the multiple other pins, other than the aforementioned pins, can be used to electrically connect to the first isolation circuit BF1 or the second isolation circuit BF2 in the determination module of the first board 100 via corresponding pins in the first interface 10.

[0076] On this basis, the first controller CT1 can detect the communication protocol supported by the storage device H and the hot-swap process of the carrier card. The second controller CT2 can perform corresponding storage device H-related operations on the storage device H based on the detection results of the first controller CT1. For example, the storage device H-related operations include interconnecting with the storage device H according to the detected communication protocol type. Specifically, in response to the electrical connection status indication of the first interface 10, the second controller CT2 electrically connects the sixth interface 60 of the carrier board to the first board 100 and interconnects with the storage device H according to the detected communication protocol type. In response to the electrical connection status indication of the first interface 10, the sixth interface 60 of the carrier board is electrically disconnected from the first board 100 and stops interconnecting with the storage device H. In this way, based on whether the target pin is electrically connected or disconnected from the first interface 10, it can be determined whether the storage device H is properly connected to the first board 100, thereby facilitating the hot-swapping of storage devices H with different communication protocols.

[0077] Furthermore, when other pins in the sixth interface 60 of the first controller CT1 are electrically connected to the first interface 10, the first controller CT1 can read the storage device detection signal of the storage device H via other pins (such as detection pins, etc.) of the first interface 10 and the sixth interface 60. The storage device detection signal is used to indicate the communication protocol type of the storage device H. Then, the first controller CT1 can generate a storage device status signal based on the storage device detection signal and the storage device in-place signal from the second interface 20. The storage device in-place signal is used to indicate whether the storage device H is in the target position. The storage device status signal is used to indicate whether the storage device H is in the target position and to indicate the communication protocol of the storage device H. For example, when the carrier card 300 is in the target position on the first board 100, the storage device H on the carrier card 300 is electrically connected to the first interface 10 through the target pin and other pins in the sixth interface 60. On this basis, the second controller CT2 can receive a storage device status signal from the first controller CT1. When the storage device status signal indicates that the storage device H is in the target position for hot insertion, the second controller CT2 can interconnect with the storage device H according to the communication protocol indicated by the storage device status signal. For example, interconnection can be achieved via interconnect pins connected to multiple traces. In this way, the first controller CT1 sends a storage device status signal indicating the position and protocol type of the storage device H to the second controller CT2, so that when the storage device H is in the target position, the second controller CT2 can interconnect with the storage device H according to the communication protocol. In this way, hot-swapping of storage devices H with different communication protocols can be achieved.

[0078] Furthermore, the first isolation circuit BF1 can be electrically connected to a first data pin of the first interface 10 that is connected to some of the other pins of the sixth interface 60. When the target pin of the sixth interface 60 is electrically connected to the first interface 10 and the communication protocol is the first communication protocol (e.g., NVMe), the first controller CT1 operates in a first mode to control the first isolation circuit BF1 to electrically connect the management controller BC of the server motherboard MB to the first data pin of the first interface 10. It should be understood that if the carrier card 300 directly provides data signals to the management controller BC of the server motherboard MB, factors such as data signal jitter may cause the management controller BC to experience abnormal conditions (e.g., hang). Therefore, when the carrier card 300 is in the detection position, it can send a data signal of the third communication protocol (for example, it can be an I2C protocol) to the first isolation circuit BF1, so that when the carrier card 300 is in the target position, the first controller CT1 controls the first isolation circuit BF1 to send a data signal to the management controller BC of the server motherboard MB, thereby avoiding the normal operation of the management controller BC being affected by factors such as signal jitter of the data signal, and realizing stable hot insertion of the storage device H that supports the first communication protocol.

[0079] For another example, when the target pin of the sixth interface 20 is electrically disconnected from the first interface 10 and the communication protocol is the first communication protocol, the first controller CT1 can control the first isolation circuit BF1 to electrically disconnect the management controller BC of the server motherboard MB from the first data pin of the first interface 10. In this way, when the carrier card 300 is not in the target position, the first controller CT1 controls the first isolation circuit BF1 to stop sending data signals to the management controller BC of the server motherboard MB. This prevents factors such as data signal jitter from affecting the normal operation of the management controller BC, thereby achieving stable hot swapping of the storage device H that supports the first communication protocol.

[0080] Specifically, under the control of a control signal received from the first controller CT1 via the switching unit, the first isolation circuit BF1 can electrically connect the switching unit to the first data pin of the first interface 10. In this way, the first controller CT1 sends a control signal to the first isolation circuit BF1 via the switching unit. When the carrier card 300 is in the target position, the first isolation circuit BF1 controls the first isolation circuit BF1 to send a data signal to the management controller BC via the switching unit. This prevents factors such as data signal jitter from affecting the normal operation of the management controller BC, thereby enabling stable hot insertion of a storage device H supporting the first type of communication protocol. For another example, if the first isolation circuit BF1 does not receive a control signal, the first controller CT1 can electrically disconnect the switching unit from the first interface 10. In this way, if the first isolation circuit BF1 does not receive a control signal, it disconnects the switching unit from the carrier card 300 to stop sending data signals. This prevents factors such as data signal jitter from affecting the normal operation of the management controller BC, thereby enabling stable hot insertion of a storage device H supporting the first type of communication protocol.

[0081] For example, the second isolation circuit BF2 is electrically connected to the first controller CT1 and to a second data pin of the first interface 10 that is connected to some of the other pins of the sixth interface 60. When the communication protocol is the first communication protocol, the first controller CT1 can operate in the first mode to control the second isolation circuit BF2 to be electrically connected to the reset terminal of the second controller CT2, so that the second isolation circuit BF2 receives a reset signal from the reset terminal of the second controller CT2. Then, when the target pin of the sixth interface 60 is electrically connected to the sixth interface 60, the first controller CT1 controls the second isolation circuit BF2 to electrically connect the second data pin of the sixth interface 60 to the reset terminal of the second controller CT2. In this way, when the storage device detection signal indicates the protocol type is the first type, the first controller CT1 receives the reset signal from the second controller CT2 and transmits the reset signal to the second isolation circuit BF2. Consequently, when the storage device presence signal is received, the first controller CT1 controls the second isolation circuit BF2 to send a stable reset signal to the storage device H via the carrier card 300 to reset the storage device H. This prevents unstable reset signals from affecting the storage device H, thereby achieving stable hot-swapping of the storage device H supporting the first communication protocol. For another example, the first controller CT1 may also control the second isolation circuit BF2 to electrically disconnect the second data pin of the first interface 10 from the reset terminal of the second controller CT2 when the target pin of the sixth interface 60 is electrically disconnected from the first interface 10. In this way, when the first controller CT1 does not receive a storage device presence signal, it controls the second isolation circuit BF2 to electrically disconnect from the carrier card 300 to stop sending the reset signal to the storage device H, thereby achieving stable hot removal of the storage device H that supports the first communication protocol.

[0082] For example, the second controller CT2 can transmit signals of the first communication protocol or the second communication protocol via the interconnection line. Thus, when the carrier card 300 is in the target position, the second controller CT2 is electrically connected to the carrier card 300 via the interconnection line, thereby interconnecting with the storage device H via the interconnection line based on the first communication protocol or the second communication protocol. This enables hot-swapping of storage devices H supporting different data protocols. Furthermore, when the communication protocol is the first communication protocol, the second controller CT2 can also perform a first mode of operation to provide a clock signal to the storage device H via the clock line, the first interface 10, and the sixth interface 60, and interconnect with the storage device H via the interconnection line and the sixth interface 60 based on the first communication protocol. Thus, when the carrier card 300 is in the target position, the second controller CT2 is electrically connected to the carrier card 300 via the clock line and the interconnection line. Thus, the second controller CT2 can provide a clock signal to the storage device H supporting the first communication protocol via the clock line, and interconnect with the storage device H via the interconnection line based on the first communication protocol. This enables hot-swapping of storage devices H supporting the first communication protocol.

[0083] Specifically, the second controller CT2 can be electrically connected to the clock buffer via a single line. The clock buffer is electrically connected to multiple carrier cards 300 via multiple clock lines. The second controller CT2 sends a clock signal to the clock buffer via a single line, so that the clock buffer provides clock signals to the storage devices H of the multiple carrier cards 300 via multiple clock lines based on the clock signal. In this way, the second controller CT2 controls the clock buffer to provide clock signals to the multiple carrier cards 300, thereby supporting the hot insertion of multiple storage devices H of the first communication protocol. For another example, the second controller CT2 can stop providing the clock signal to the storage device H and stop interconnecting with the storage device H when the target pin of the sixth interface 60 is electrically disconnected from the first interface 10 and the communication protocol is the first communication protocol. In this way, when the carrier card 300 is not in the target position, the second controller CT2 stops providing the clock signal to the storage device H and stops interconnecting with the storage device H, thereby achieving hot removal of the storage device H that supports the first data protocol.

[0084] On this basis, the storage device presence signal from the fifth interface 50 is transmitted to the first controller CT1 of the first board 100, which then indicates whether the storage device H is present. Furthermore, the first controller CT1 can also read the storage device detection signal from the storage device H via a pin directly connected to the first controller CT1 in the first interface 10 to determine whether the storage device H supports SATA or NVMe. When the first controller CT1 determines that the storage device H is a SATA M.2 hard drive and hot-swapping is complete, the second controller CT2 outputs a signal corresponding to the protocol to the storage device H. In addition, the first controller CT1 can also report information such as the in-place status of the storage device H to the management controller BC of the server motherboard MB through the SMbus bus; when the first controller CT1 determines that the storage device H is an NVMe M.2 hard disk, the first controller CT1 can control the first isolation circuit BF1 and the second isolation circuit BF2 (IO Buffer) to realize the reset signal of each storage device H and the on and off of the I2C bus signal of the storage device H, and the second controller CT2 outputs the NVMe signal to the storage device H, and at the same time outputs the clock signal to the M.2 hard disk, thereby realizing hot plugging of M.2 hard disks with different communication protocols.

[0085] Figure 12B A schematic diagram of a board according to another embodiment of the present application is shown.

[0086] like Figure 12B As shown, the management card corresponds to the first board. The CPLD corresponds to the first controller, the I2CSwitch corresponds to the switching unit, the IO buffer connected to the CPLD corresponds to the first isolation circuit, and the IO buffer connected to the I2CSwitch corresponds to the second isolation circuit. The main card corresponds to the second board. The RAID controller corresponds to the second controller. The clock buffer corresponds to the clock buffer.

[0087] On this basis, the carrier card's M.2 connector is connected to a SATA / NVMe M.2 hard drive, and the GENZ gold finger is connected to the management card's GENZ connector. In this case, the CPLD can detect the storage device presence signal PRSNT_N and the storage device detection signal PEDET, and generate a storage device status signal SSD_ST. For example, the storage device status signal SSD_ST can include a BP_type signal or a CT_type signal. The BP_type signal and the CT_type signal can be signals indicating the hard drive type, but are not limited to these. Furthermore, the CPLD can provide a control signal OE to the IO buffer connected to it and the IO buffer connected to the I2C switch, thereby controlling the IO buffer connected to the CPLD to provide a reset signal PERST_N to the SATA / NVMe M.2 hard drive and controlling the IO buffer connected to the I2C switch to receive I2C protocol data signals. Upon receiving the storage device status signal SSD_ST, the RAID controller can send a SATA signal or a PCIe signal to the storage device via the SAS / PCIe bus based on the communication protocol and presence status of the storage device indicated by the storage device status signal SSD_ST. And when sending PCIe signals, the clock signal PCIE_CLK is provided to the Clock Buffer, so that the Clock Buffer provides multiple clock signals PECLK to multiple SATA / NVMe M.2 hard drives. In this way, hot-swappable operations of storage devices with different communication protocols can be achieved. In addition, the RAID controller can also interact with the baseboard management controller of the server motherboard via the SMBus bus, and can receive the clock signal PCIE_CLK from the central processing unit, and can interact through the PCIE_TX / RX signals. It should be noted that Figure 12B The PCIe gold finger, daughter card connector, GENZ connector, GENZ gold finger and M.2 connector correspond to Figure 12A The various interfaces in it will not be described one by one here.

[0088] Figure 13 A flow chart of a storage device hot-plugging method according to an embodiment of the present application is shown.

[0089] like Figure 13 As shown, the method of this embodiment includes operations S1310 to S1380. For example, in this application, the storage device may be a hard disk, and the following description is based on the hard disk. Figure 13 and Figure 14 For example, the hard disk detection signal hereinafter may refer to a storage device detection signal for a hard disk, and the others are similar and will not be described in detail.

[0090] In operation S1310, when the first interface is connected to some pins in the sixth interface, the first controller reads a hard disk detection signal from the hard disk. For example, if the hard disk detection signal is low, it can be determined that the hard disk on the carrier card is a SATA M.2 hard disk; if the hard disk detection signal is high, it can be determined that the hard disk on the carrier card is an NVMe M.2 hard disk.

[0091] In operation S1320 , the first controller determines whether the hard disk has reached the target position according to the hard disk presence signal.

[0092] In operation S1330 , when the hard disk on the carrier card is a SATA M.2 hard disk, the first controller provides a hard disk status signal to the second controller.

[0093] In operation S1340, the second controller sends a signal to the sixth interface via the interconnection line to interconnect with the hard disk.

[0094] In operation S1350, when the hard disk on the carrier card is an NVMe M.2 hard disk, the first controller enables the first isolation circuit and the second isolation circuit, so that the first end and the second end of the first isolation circuit are electrically connected, and the first end and the second end of the second isolation circuit are electrically connected.

[0095] In operation S1360, in a case where the hard disk has reached the target position, the first controller provides a hard disk status signal to the second controller.

[0096] In operation S1370, the second controller sends a PCIe signal to the sixth interface via the interconnection line to interconnect with the hard disk, and sends a clock signal to the sixth interface via the clock line.

[0097] In operation S1380, the first controller reports information such as the hard disk presence status to the management controller of the mainboard via the SMBus bus.

[0098] On this basis, the management controller can monitor the hard disk presence status and access the out-of-band information of each NVMe M.2 hard disk, thereby realizing hot insertion.

[0099] Figure 14 A flow chart of a method for hot-plugging a storage device according to an embodiment of the present application is shown.

[0100] like Figure 14 As shown, the method of this embodiment may include operations S1410 to S1470.

[0101] In operation S1410 , the first controller determines, according to a hard disk presence signal, that the hard disk has not reached a target position.

[0102] In operation S1420 , when the hard disk on the carrier card is a SATA M.2 hard disk, the first controller provides a hard disk status signal to the second controller.

[0103] In operation S1430, the second controller stops sending the signal to disconnect the interconnection.

[0104] In operation S1440, when the hard disk on the carrier card is an NVMe M.2 hard disk, the first controller disables the first isolation circuit and the second isolation circuit, so that the first end and the second end of the first isolation circuit are electrically disconnected, and the first end and the second end of the second isolation circuit are electrically disconnected.

[0105] In operation S1450, the first controller provides a hard disk status signal to the second controller.

[0106] In operation S1460, the second controller stops sending the PCIe signal to stop interconnecting with the hard disk, and stops sending the clock signal.

[0107] In operation S1470, the first controller reports the hard disk not being in place status information to the management controller of the mainboard via the SMBus bus, thereby implementing hot unplugging.

[0108] Figure 15 1 and 2 show a front view and a side view of a carrier card according to another embodiment of the present application.

[0109] like Figure 15 As shown, the carrier card as a whole can have a thickness in a first direction Z and extend in a second direction X. The carrier card includes a carrier portion, and the fifth interface of the carrier card is provided at one end of the carrier portion. The sixth interface of the carrier card can also be located at the same end and next to the fifth interface. A hook can be provided at the other end of the carrier portion where no interface is provided, and the hook can be used to hook the second board card to thereby fix the relative position between the second board card and the carrier portion.

[0110] In addition, an indicator light is provided in the middle of the carrier portion, and a light guide column extending from the middle of the carrier portion to the other end, so as to guide the light signal emitted by the indicator light from the middle of the carrier portion to the observation point at the other end. For example, there can be multiple indicator lights, and they are distributed in the third direction Y. Correspondingly, there can be multiple observation points, and they are distributed in the third direction Y. For example, the light signal of the indicator light can be used, but is not limited to, to indicate states such as hot plugging. By providing an indicator light in the middle of the carrier portion of the carrier card, and guiding the light signal emitted by the indicator light to the observation hole at the other end of the carrier card through the light guide column, it is convenient to determine the position of the storage device through the light signal during the process of the carrier card driving the storage device to be plugged in and out. In this way, it is convenient to realize the hot plugging of storage devices of various sizes and various communication protocols.

[0111] Continue to refer Figure 15 The fifth interface and the sixth interface can be located at the housing of the carrier card. Next to the housing, a detachable fixing post is provided at the position for arranging the storage device to fix the relative position of the storage device and the carrier card.

[0112] M.2 drive types vary widely, including Types 1113, 1216, 1620, 1630, 2024, 2226, 2228, 2230, 2242, 2260, 2280, 2828, 3026, 3030, 3042, 22110, and 25110. These drive sizes vary, and it's crucial to consider the various M.2 drive dimensions required for connecting to hosts. Furthermore, the standard dimensions for RAID cards are 167.65mm long by 68.90mm wide, while the M.2 connector (approximately 6mm) and RAID controller (approximately 25mm long by 25mm wide) are significantly larger. Furthermore, considering the fan-out space for RAID controller wiring, heat sinks, and other necessary electronic components, as well as the limited layout design, it's difficult to achieve hot-swappable compatibility for storage devices of multiple lengths within a server's layout. Therefore, a new layout solution is needed to achieve full-size M.2 drive design. On this basis, in order to realize hot plugging of storage devices of various sizes, the present application designs a full-length carrier card. Figure 16 shows a schematic perspective view of a carrier card according to another embodiment of the present application, Figure 17 shows a schematic perspective view of a carrier card according to another embodiment of the present application, Figure 18 A schematic perspective view of a carrier card according to another embodiment of the present application is shown.

[0113] refer to Figure 16 It can be seen that, in addition to the light-guiding column and the sixth interface, a fixing column is also provided on the carrier card. Figure 17 and Figure 18 Schematic diagrams are shown showing storage devices of different sizes being arranged on a carrier card compatible with full-length storage devices of the present application. On this basis, a fixing post is provided on the carrier portion, and the distance between the fixing post and the fifth interface (or the sixth interface) is adjustable. Thus, when storage devices of various sizes are arranged on the carrier portion, the relative position between the storage device and the carrier portion can be fixed by adjusting the distance between the fixing post and the fifth interface (or the sixth interface). In this way, by providing a fixing post on the carrier card, storage devices of different sizes can be fixed on the carrier card, so that storage devices of various sizes can be electrically connected to the fifth interface. Furthermore, hot-swapping of storage devices of various sizes and various protocol types can be achieved.

[0114] Figure 19 A schematic diagram of a plugging and unplugging device according to another embodiment of the present application is shown.

[0115] like Figure 19 As shown, the second board further includes a guide rail that can extend in the second direction, so that the carrier card can be displaced in the second direction relative to the board (specifically, the second board) along the guide rail.

[0116] In principle, the board consists of two parts: the first and second boards. The second board serves as the main card, with guide rails placed on it. A carrier card, which holds the storage device, is inserted and removed along the rails. The second board connects to the motherboard's CPU via the PCIe bus and the second controller on the board via a main card interface (e.g., a PCIe slot). Furthermore, the second board connects the second controller to the second interface on the first board via a third interface. The second controller serves as the host for the storage device, managing and implementing various RAID functions using its own cache and RAID algorithm logic.

[0117] The first board is an expansion card for the second board. It is connected to the second board via a second interface and can be installed and fixed on top of the second board. Due to the limited space for component placement on the second board, the component layout space can be expanded on the first board. The first interface on the first board connects the interconnection line to the sixth interface of the carrier card, and hot-swapping of the storage device can be indirectly achieved by connecting and removing the first interface from the sixth interface on the carrier card. The first controller on the first board is used to manage the hot-swap signal management of the storage device, identify the presence of the storage device, and control the lighting of the light-emitting diode (LED) signal light.

[0118] In addition, the solution for deploying M.2 hard drives in related technologies is relatively complicated, requiring RAID cards, cables, and hard drive backplanes to be used with M.2 hard drives. Since the cables extend from the card end to the hard drive backplane side, the cables are long, which takes up chassis space and increases deployment costs. Among them, since the hard drive backplane needs to provide power supply, signal transmission, management functions and structural fixings for the M.2 hard drive, it is necessary to systematically plan the position of the hard drive backplane in the chassis. Due to the fact that the hard drive backplane may be installed in different positions in the chassis, the spatial structure and heat dissipation requirements are different, so different types of hard drive backplanes need to be designed; the cable routing design will also be different, and cables of different lengths need to be developed. In the solution of the present application, Figure 20 FIG. 1 shows a schematic diagram of a plug-in device according to another embodiment of the present application. Figure 20As shown, the board can be installed on the main card interface of the motherboard as an external device of the server. For example, the storage device can be installed on the board through a structural device that cooperates with the carrier card through a guide rail. On this basis, the storage device can be installed on the carrier card, and the carrier card is inserted or removed from the board through the guide rail. The second controller of the board is compatible with the multi-mode protocol to support storage device identification and RAID functions of NVMe or SATA protocols, and supports full-length storage devices (for example, 110 mm). It can also support hot-swappable maintenance and replacement from the RAID card without unpacking the server. In this way, the problem of cable routing is solved and space is freed up in the Figure 20 The space to the right of the board (in some solutions, this space needs to be used for wiring cables) facilitates the rational planning of the internal space of the chassis.

[0119] Figure 21 A front view and a side view of a plugging device according to another embodiment of the present application are shown.

[0120] like Figure 21 As shown, the first and second boards are stacked. For example, the first board can be inverted on top of the second board to allow for more components to be placed on the first board. It is also possible to connect the second interface of the first board to the third interface of the second board. For example, a heat sink can be provided between the stacked first and second boards to dissipate heat from the first and second boards. For example, the second controller of the second board is stacked with the first board in a first direction Z. The second controller is recessed relative to the first board in a second direction X that intersects the first direction Z. Furthermore, the sixth interface of the carrier card is electrically connected to the first interface of the first board in a second direction X, thereby creating a certain space between the carrier card and the second controller when the first and sixth interfaces are electrically connected. Thus, by stacking the first and second boards and recessing the second controller relative to the first interface in the second direction X, a certain space can be enclosed by the first interface, the sixth interface, the second board, and the first board when the first and sixth interfaces are connected. This allows for wiring and other design options within this space, thereby fully utilizing the space within the server.

[0121] In addition, a stopper is provided at one end of the guide rail of the first board away from the second controller, for limiting the movement direction of the carrier card relative to the guide rail, for example, for limiting the carrier card from deflecting in a third direction.

[0122] Figure 22 shows a schematic perspective view of a plugging device according to another embodiment of the present application, Figure 23 A schematic perspective view of a plugging device according to another embodiment of the present application is shown.

[0123] exist Figure 22 Schematic diagram of the board card is shown in FIG. 1 when the carrier card is in the target position. Figure 23 for Figure 22 A partial schematic diagram of the reference Figure 22 and Figure 23 It can be seen that a card hole is provided at the guide rail, specifically, a card hole may be provided at one end of the guide rail away from the first board. The carrier card may also include a pressing spring sheet at the other end of the carrier part, and the pressing spring sheet is provided with a hook. The hook can hook the card hole when the sixth interface of the carrier card is electrically connected to the first interface of the first board, thereby fixing the relative position between the carrier part and the guide rail. Then, when the pressing spring sheet is pressed, the pressing spring sheet can drive the hook to disengage from the card hole, thereby realizing maintenance and replacement without opening the chassis cover. In this way, the present application can realize the replacement and maintenance of the M.2 hard drive without unpacking and powering off. The solution is flexible in deployment, simple in maintenance, highly versatile, and has low design cost, and has good application value.

[0124] Figure 24 A flow chart of a signal transmission method according to an embodiment of the present application is shown.

[0125] like Figure 24 As shown, the method of this embodiment includes operation S2410.

[0126] In operation S2410 , a board in the plug-in device transmits an interconnection signal to the storage device via an interconnection line, and transmits a clock signal to the storage device via a clock line.

[0127] For example, the first controller detects the communication protocols supported by the storage device and the hot-swap process of the carrier card. The second controller performs corresponding storage device-related operations on the storage device based on the detection results of the first controller. The storage device-related operations include interconnecting with the storage device based on the detected communication protocol type.

[0128] For example, the first controller determines the hot swap process based on the electrical connection status of the first interface of the first board. The second controller, in response to the electrical connection status of the first interface, instructs the sixth interface of the carrier board to electrically connect to the first board and interconnect with the storage device according to the detected communication protocol type; and in response to the electrical connection status of the first interface, instructs the sixth interface of the carrier board to electrically disconnect from the first board and stop interconnecting with the storage device.

[0129] For example, the target pin of the sixth interface sends a storage device presence signal to indicate whether the storage device is in a target position to complete the hot swap process.

[0130] For example, when the target pin is electrically connected to the corresponding pin of the first interface, the voltage level of the corresponding pin of the first interface is pulled down based on the ground signal of the ground terminal to send a storage device presence signal to the first interface.

[0131] For example, when other pins in the sixth interface are electrically connected to the first interface, the first controller reads a storage device detection signal of the storage device via the first interface and other pins in the sixth interface. The storage device detection signal is used to indicate the communication protocol type of the storage device.

[0132] For example, when the carrier card is at a target position on the guide rail of the first board, the sixth interface is electrically connected to the first interface through the target pin and other pins.

[0133] For example, the first controller generates a storage device status signal based on the storage device detection signal and the storage device presence signal from the sixth interface. The storage device presence signal indicates whether the storage device is in the target location. The storage device status signal indicates whether the storage device is in the target location and indicates the communication protocol of the storage device. The second controller receives the storage device status signal from the first controller and, if the storage device status signal indicates that the storage device is in the target location, interconnects with the storage device according to the communication protocol indicated by the storage device status signal.

[0134] For example, when the target pin of the sixth interface is electrically connected to the first interface and the communication protocol is the first communication protocol, the first controller performs the first mode operation to control the first isolation circuit to electrically connect the management controller of the server motherboard to the first data pin of the first interface.

[0135] For example, when the target pin of the sixth interface is electrically disconnected from the first interface and the communication protocol is the first communication protocol, the first controller controls the first isolation circuit to electrically disconnect the management controller of the server motherboard from the first data pin of the first interface.

[0136] For example, the first isolation circuit electrically connects the switching unit to the first data pin of the first interface under the control of a control signal from the first controller received via the switching unit.

[0137] For example, when the first isolation circuit does not receive the control signal, the first isolation circuit disconnects the switching unit from the first interface.

[0138] For example, when the communication protocol is the first communication protocol, the first controller performs the first mode operation to control the second isolation circuit to be electrically connected to the reset end of the second controller; when the target pin of the sixth interface is electrically connected to the sixth interface, the first controller controls the second isolation circuit to electrically connect the second data pin of the sixth interface to the reset end of the second controller.

[0139] For example, when the target pin of the sixth interface is electrically disconnected from the first interface, the first controller controls the second isolation circuit to electrically disconnect the second data pin of the first interface from the reset terminal of the second controller.

[0140] For example, the second controller transmits a signal of the communication protocol through the interconnection line when the communication protocol is the first communication protocol or the second communication protocol.

[0141] For example, when the communication protocol is the first communication protocol, the second controller performs the first mode operation to provide a clock signal to the storage device via the clock line, the first interface and the sixth interface, and interconnects with the storage device based on the first communication protocol via the interconnection line and the sixth interface.

[0142] For example, the second controller sends a clock signal to the clock buffer via a single line, so that the clock buffer provides clock signals to storage devices of multiple carrier cards via multiple clock lines based on the clock signal.

[0143] For example, when the target pin of the sixth interface is electrically disconnected from the first interface and the communication protocol is the first communication protocol, the second controller stops providing the clock signal to the storage device and stops interconnecting with the storage device.

[0144] It should be understood that the signal transmission method of the embodiment of the present application is not limited to this. Please refer to the above description for details and will not be elaborated here.

[0145] The flowcharts and block diagrams in the accompanying drawings illustrate the possible implementation architecture, functions and operations of the systems, methods and computer program products according to various embodiments of the present application. In this regard, each box in the flowchart or block diagram can represent a module, program segment, or a part of code, and the above-mentioned module, program segment, or a part of code contains one or more executable instructions for realizing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the box can also occur in an order different from that marked in the accompanying drawings. For example, two boxes represented in succession can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram or flowchart, and the combination of the boxes in the block diagram or flowchart, can be implemented with a dedicated hardware-based system that performs the specified function or operation, or can be implemented with a combination of dedicated hardware and computer instructions.

[0146] Those skilled in the art will appreciate that the features described in the various embodiments of this application may be combined and / or coupled in various ways, even if such combinations or couplings are not explicitly described in this application. In particular, the features described in the various embodiments of this application may be combined and / or coupled in various ways without departing from the spirit and teachings of this application. All such combinations and / or couplings fall within the scope of this application.

[0147] The embodiments of the present application have been described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of the present application. Although each embodiment has been described separately above, this does not mean that the measures in each embodiment cannot be advantageously used in combination. Without departing from the scope of the present application, those skilled in the art may make various substitutions and modifications, and these substitutions and modifications should all fall within the scope of the present application.

Claims

1. A plug-in device, characterized in that: include: Board, including at least interconnection lines and clock lines; The board can be connected to at least one storage device and is configured to transmit an interconnection signal to the storage device via the interconnection line and transmit a clock signal to the storage device via the clock line; The board includes a first board; the first board is used to connect to the storage device; the first board includes a first interface, a second interface, at least one isolation circuit and a first controller, the first interface is electrically connected to the second interface via the interconnection line and the clock line; The at least one isolation circuit includes at least one of a first isolation circuit and a second isolation circuit; The first isolation circuit is electrically connected to the first controller and the first interface; the second isolation circuit is electrically connected to the first controller, the first interface, and the second interface.

2. The plug-in device according to claim 1, characterized in that: The board also includes a second board electrically connected to the first board; the second board is used to connect to the server mainboard.

3. The plug-in device according to claim 2, characterized in that: The interconnection circuit and the clock circuit are arranged in the first board.

4. The plug-in device according to claim 2, characterized in that: The second board includes a third interface; Wherein, the second interface is electrically connected to the third interface.

5. The plug-in device according to claim 4, characterized in that: The first interface is an interface that supports hot plugging.

6. The plug-in device according to claim 5, characterized in that: The first interface is a universal non-volatile storage interface.

7. The plugging and unplugging device according to any one of claims 2 to 6, characterized in that: The first controller is configured to determine, for different communication protocols, whether to transmit a signal to the first interface via the at least one isolation circuit.

8. The plug-in device according to claim 7, characterized in that: The first controller is electrically connected to the first interface and is configured to detect a communication protocol of the storage device and, for different communication protocols, determine whether to transmit a signal to the first interface via the at least one isolation circuit.

9. The plug-in device according to claim 7, characterized in that: The second board also includes a fourth interface for electrically connecting the third interface and the motherboard interface of the server motherboard, so that the second isolation circuit is electrically connected to the management controller of the server motherboard via the third interface, the fourth interface and the motherboard interface.

10. The plug-in device according to claim 9, characterized in that: The first board also includes a switching unit; The second isolation circuit is electrically connected to the first controller and the third interface via the switching unit.

11. The plugging and unplugging device according to any one of claims 2 to 6, characterized in that: The second board includes a second controller; the second controller is electrically connected to the interconnection line via a second interface and a third interface; the second controller is used to implement a disk redundancy function.

12. The plug-in device according to claim 11, characterized in that: The second board also includes a clock buffer for providing a clock signal to the clock line.

13. The plug-in device according to claim 12, characterized in that: The clock buffer is electrically connected to the second controller and is electrically connected to the clock line via the second interface and the third interface.

14. The plugging and unplugging device according to any one of claims 1 to 6, characterized in that: Also included is a carrier card for carrying the storage devices of various sizes; The carrier card includes a fifth interface and a sixth interface, the fifth interface is used to be electrically connected to the storage device; the sixth interface is used to be electrically connected to the board card.

15. The plug-in device according to claim 14, characterized in that: The sixth interface includes a target pin and other pins longer than the target pin.

16. The plug-in device according to claim 15, characterized in that: The target pin is configured to be electrically connected to the first controller via a corresponding pin in the first interface.

17. The plug-in device according to claim 16, characterized in that: The plurality of pins other than the target pin in the sixth interface are used to be electrically connected to the interconnection circuit and the clock circuit, the first isolation circuit and the second isolation circuit respectively via corresponding pins in the first interface.

18. The plug-in device according to claim 14, characterized in that: The first board and the second board are stacked.

19. The plug-in device according to claim 18, characterized in that: A heat dissipation layer is provided between the first board and the second board.

20. The plug-in device according to claim 19, characterized in that: The second controller of the second board is stacked with the first board in a first direction; The second controller is recessed relative to the first board in a second direction intersecting the first direction.

21. The plug-in device according to claim 20, characterized in that: The sixth interface of the carrier card is electrically connected to the first interface in the second direction; when the first interface and the sixth interface are electrically connected, there is a certain space between the carrier card and the second controller.

22. The plug-in device according to claim 14, characterized in that: The board card further includes a guide rail; the guide rail extends in the second direction so that the carrier card can be displaced along the guide rail relative to the board card in the second direction.

23. The plug-in device according to claim 22, characterized in that: The guide rail is arranged on the second board; a blocking piece is arranged at one end of the guide rail away from the second controller, for limiting the moving direction of the carrier card relative to the guide rail.

24. The plug-in device according to claim 22, characterized in that The guide rail is provided with a clamping hole; The carrier card includes a carrier portion, the fifth interface is provided at one end of the carrier portion, and the carrier card further includes a pressing spring at the other end of the carrier portion, the pressing spring being provided with a hook; The hook is capable of hooking the hook hole when the sixth interface is electrically connected to the first interface, thereby fixing the relative position between the bearing portion and the guide rail; The pressing spring can drive the hook to disengage from the locking hole when pressed.

25. The plug-in device according to claim 24, characterized in that The carrier card further includes a fixing post provided on the carrier portion; The distance between the fixing column and the fifth interface is adjustable so that when storage devices of various sizes are arranged on the carrying portion, the relative position between the storage device and the carrying portion can be fixed by adjusting the distance between the fixing column and the fifth interface.

26. The plugging and unplugging device according to any one of claims 1 to 6, characterized in that: The multiple modes of the board are respectively used to transmit different signals to the storage device when the storage device with different communication protocols performs a hot plug operation.

27. The plug-in device according to claim 26, characterized in that The multiple modes include a first mode and a second mode; wherein, in the first mode, the interconnection line transmits the interconnection signal, and the clock line transmits the clock signal; in the second mode, the interconnection line transmits the interconnection signal.

28. The plugging and unplugging device according to any one of claims 1 to 6, characterized in that: The storage device is an M.2 hard disk.

29. The plugging and unplugging device according to any one of claims 1 to 6, characterized in that: The storage device supports the Serial Advanced Technology Attachment (STA) protocol or the Non-Volatile Memory Expression (NVMEM) protocol.

30. A signal transmission method based on the plug-in device according to any one of claims 1 to 29, comprising: The board in the plug-in device transmits an interconnection signal to the storage device via an interconnection line, and transmits a clock signal to the storage device via a clock line.

31. The signal transmission method according to claim 30, wherein: The board includes a first board and a second board; the first board includes a first controller, and the second board includes a second controller; The method further comprises: The first controller detects the communication protocol supported by the storage device and the hot-swap process of the carrier card; The second controller performs corresponding storage device related operations on the storage device based on the detection result of the first controller; wherein the storage device related operations include interconnecting with the storage device according to the detected communication protocol type.

32. The signal transmission method according to claim 31, wherein: The hot swap process is determined by the first controller based on the electrical connection state of the first interface of the first board; The method also includes: the second controller electrically connects the sixth interface of the carrier board to the first board in response to the electrical connection status indication of the first interface, and interconnects with the storage device according to the detected communication protocol type; and electrically disconnects the sixth interface of the carrier board from the first board in response to the electrical connection status indication of the first interface, and stops interconnecting with the storage device.

33. The signal transmission method according to claim 32, wherein: The method further comprises: The target pin of the sixth interface sends a storage device presence signal to indicate whether the storage device is in a target position to complete the hot swap process.

34. The method according to claim 33, wherein The target pin of the sixth interface sends a storage device presence signal, including: When the target pin is electrically connected to the corresponding pin of the first interface, the target pin pulls down the level of the corresponding pin of the first interface based on the ground signal of the ground terminal, so as to send the storage device presence signal to the first interface.

35. The signal transmission method according to claim 34, wherein: The sixth interface further includes other pins except the target pin; The first controller detects the communication protocol type supported by the storage device, including: When the other pins in the sixth interface are electrically connected to the first interface, the first controller reads the storage device detection signal of the storage device via the first interface and the other pins of the sixth interface; the storage device detection signal is used to indicate the communication protocol type of the storage device.

36. The signal transmission method according to claim 35, wherein: The method further comprises: When the carrier card is located at the target position on the guide rail of the first board, the sixth interface is electrically connected to the first interface through the target pin and the other pins.

37. The signal transmission method according to claim 36, wherein: The method further comprises: The first controller generates a storage device status signal based on the storage device detection signal and the storage device presence signal from the sixth interface; the storage device presence signal is used to indicate whether the storage device is in the target position; the storage device status signal is used to indicate whether the storage device is in the target position and indicate the communication protocol of the storage device; The second controller performs corresponding storage device-related operations on the storage device based on the detection result of the first controller, including: The second controller receives the storage device status signal from the first controller, and when the storage device status signal indicates that the storage device is at the target location, interconnects with the storage device according to the communication protocol indicated by the storage device status signal.

38. The signal transmission method according to any one of claims 35 to 37, wherein: The first board further includes a first isolation circuit electrically connected to a first data pin of the first interface connected to some of the other pins of the sixth interface, and the first controller; The method further comprises: When the target pin of the sixth interface is electrically connected to the first interface and the communication protocol is the first communication protocol, the first controller performs a first mode of operation to control the first isolation circuit to electrically connect the management controller of the server motherboard to the first data pin of the first interface.

39. The signal transmission method according to claim 38, wherein: The method further comprises: When the target pin of the sixth interface is electrically disconnected from the first interface and the communication protocol is the first communication protocol, the first controller controls the first isolation circuit to electrically disconnect the management controller of the server motherboard from the first data pin of the first interface.

40. The signal transmission method according to claim 39, wherein: The first board further includes a switching unit electrically connected to the management controller and the first isolation circuit; The method further comprises: The first isolation circuit electrically connects the switching unit with the first data pin of the first interface under the control of a control signal from the first controller received via the switching unit.

41. The signal transmission method according to claim 40, wherein: The method further comprises: When the first isolation circuit does not receive the control signal, the first isolation circuit disconnects the switching unit from the first interface.

42. The signal transmission method according to any one of claims 35 to 37, wherein: The first board further includes a second isolation circuit electrically connected to the first controller and a second data pin of the first interface connected to another portion of the other pins of the sixth interface; The method further comprises: When the communication protocol is the first communication protocol, the first controller performs the operation of the first mode to control the second isolation circuit to be electrically connected to the reset end of the second controller; when the target pin of the sixth interface is electrically connected to the sixth interface, the first controller controls the second isolation circuit to electrically connect the second data pin of the sixth interface to the reset end of the second controller.

43. The signal transmission method according to claim 42, wherein: The method further comprises: When the target pin of the sixth interface is electrically disconnected from the first interface, the first controller controls the second isolation circuit to electrically disconnect the second data pin of the first interface from the reset terminal of the second controller.

44. The signal transmission method according to any one of claims 31 to 37, wherein: The second controller is electrically connected to the first interface via the interconnection line; The board in the plug-in device transmits an interconnection signal to the storage device via an interconnection line, and transmits a clock signal to the storage device via a clock line, including: The second controller transmits a signal of the communication protocol through the interconnection line when the communication protocol is the first communication protocol or the second communication protocol.

45. The signal transmission method according to claim 44, wherein: The second controller is also electrically connected to the first interface via a clock line; The method further comprises: When the communication protocol is the first communication protocol, the second controller performs a first mode of operation to provide a clock signal to the storage device via the clock line, the first interface and the sixth interface, and interconnects with the storage device based on the first communication protocol via the interconnection line and the sixth interface.

46. ​​The signal transmission method according to claim 45, wherein: There are multiple carrier cards; each of the multiple carrier cards is provided with a storage device; there are multiple clock circuits; The second board also includes a clock buffer; the second controller is electrically connected to the clock buffer via a single line; The clock buffer is electrically connected to the plurality of carrier cards via the plurality of clock lines respectively; Providing a clock signal to the storage device comprises: The second controller sends the clock signal to the clock buffer via the single line, so that the clock buffer provides the clock signals to the storage devices of the plurality of carrier cards respectively via the plurality of clock lines based on the clock signal.

47. The signal transmission method according to claim 46, wherein: The method further comprises: When the target pin of the sixth interface is electrically disconnected from the first interface and the communication protocol is the first communication protocol, the second controller stops providing a clock signal to the storage device and stops interconnecting with the storage device.

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