Task processing method and related device

Abstract

The embodiment of the specification provides a task processing method, the method is implemented based on a system-on-chip of a systolic array, the systolic array comprises a plurality of array units and a plurality of routing units, each array unit comprises at least one processing unit, the routing units are used for connecting adjacent array units, and the processing units are used for processing the systolic array. When a calculation request for a target task is received, the request is responded, a corresponding target array is distributed to the target task in a mode of configuring the routing unit, and the target array comprises at least one array unit, so that the purpose of parallel processing of multiple tasks based on a single systolic array is achieved, and the processing efficiency is improved. The problem that the utilization efficiency of the systolic array is low due to the fact that a single task occupies the whole systolic array for a long time is solved, and the use efficiency of the systolic array is effectively improved.

Description

Technical Field

[0001] This specification relates to the field of computer application technologies. Specifically, it relates to systolic array technology in the field of computer application technologies. More specifically, it relates to a task processing method and related devices. Background Art

[0002] Matrix operation is a core computing task for artificial intelligence (AI) algorithms such as machine learning and deep learning. With the wide application of AI algorithms in various applications, matrix operation has become one of the core computing tasks that various computing devices need to process. Since matrix operation requires processing a large amount of data and complex calculations, the execution time of matrix operation occupies an increasingly large proportion in the entire algorithm calculation process.

[0003] A systolic array is a hardware structure designed for parallel processing. A systolic array can make data flow in an array of processing elements (PEs) to reduce the number of memory accesses, improve the frequency and throughput rate. This feature makes the systolic array particularly effective in matrix calculation and can achieve efficient matrix calculation. However, currently, the utilization efficiency of the systolic array is relatively low, and it is necessary to improve the utilization efficiency of the systolic array. Summary of the Invention

[0004] Embodiments of this specification provide a task processing method and related devices to achieve the purpose of improving the utilization efficiency of the systolic array.

[0005] To achieve the above technical purpose, embodiments of this specification provide the following technical solutions:

[0006] In a first aspect, this specification provides a task processing method, which is applied to a system-on-chip. The system-on-chip includes a systolic array. The systolic array includes a plurality of array units and a plurality of routing units. Each of the array units includes at least one processing unit. The routing units are used to connect adjacent array units. The task processing method includes:

[0007] In response to a calculation request for a target task, determine a target array corresponding to the target task according to target parameters;

[0008] By configuring the routing units, allocate the corresponding target array for the target task. The target array includes at least one of the array units;

[0009] The target parameter is used to characterize the priority of the target task and the priority of the current task, and the target parameter is also used to characterize at least one of the resource state of the systolic array, the scale of the target task, and the scale of the current task; the current task includes the task being executed by the systolic array.

[0010] In a second aspect, this specification provides a system-on-chip, including: a systolic array and a control module, the systolic array includes a plurality of array units and a plurality of routing units, and each of the array units includes at least one processing unit, and the routing unit is used to connect adjacent array units;

[0011] The control module is configured to:

[0012] In response to a computing request for a target task, determine a target array corresponding to the target task according to the target parameter;

[0013] By configuring the routing unit, allocate the corresponding target array for the target task, and the target array includes at least one of the array units;

[0014] The target parameter is used to characterize the priority of the target task and the priority of the current task, and the target parameter is also used to characterize at least one of the resource state of the systolic array, the scale of the target task, and the scale of the current task; the current task includes the task being executed by the systolic array.

[0015] In a third aspect, an embodiment of this specification further provides a computing device, including a memory, a processor, and a computer program stored on the memory and executable on the processor, and when the processor executes the computer program, the task processing method described above is implemented.

[0016] As can be seen from the above technical solutions, the task processing method provided by the embodiments of this specification is implemented based on a systolic array on-chip system. The systolic array includes a plurality of array units and a plurality of routing units. Each of the array units includes at least one processing unit. The routing units are used to connect adjacent array units. When receiving a calculation request for a target task, in response to the request, according to the target parameters, a target array corresponding to the target task is determined, and by configuring the routing units, the corresponding target array is allocated for the target task. The target array includes at least one array unit. In this way, the purpose of implementing parallel processing of multiple tasks based on a single systolic array is achieved, avoiding the problem of low utilization efficiency of the systolic array caused by a single task occupying the entire systolic array for a long time, and effectively improving the utilization efficiency of the systolic array. In addition, this method comprehensively considers the target parameters such as the priority of the target task and the priority of the current task to determine the target array. On the one hand, it can more reasonably determine the size of the target array corresponding to the target task and the processing order of each target task. On the other hand, it can reasonably manage the execution of the current task according to the priorities of each task, and stop the execution of the current task when necessary to ensure the priority execution of high-priority tasks. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] To more clearly illustrate the technical solutions in the embodiments of this specification or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the drawings in the following description are only the embodiments of this specification. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on the provided drawings.

[0018] Figure 1 It is a schematic diagram of the architecture of a systolic array in the related art;

[0019] Figure 2 It is a schematic diagram of an application scenario of a task processing method provided by an embodiment of this specification;

[0020] Figure 3 It is a flowchart of a task processing method provided by an embodiment of this specification;

[0021] Figure 4 It is a schematic diagram of the structure of a systolic array provided by an embodiment of this specification;

[0022] Figure 5 It is a schematic diagram of the structure of another systolic array provided by an embodiment of this specification;

[0023] Figure 6 It is a flowchart of another task processing method provided by an embodiment of this specification;

[0024] Figure 7 A schematic diagram of the software and hardware architecture of a task processing method provided for an embodiment of this specification;

[0025] Figure 8 A schematic diagram of the structure of a computing device provided for an embodiment of this specification. Specific embodiments

[0026] Unless otherwise defined, the technical terms or scientific terms used in the embodiments of this specification shall have the ordinary meanings understood by those of ordinary skill in the art to which this specification pertains. The "first", "second" and similar terms used in the embodiments of this specification do not denote any order, quantity or importance, but are only used to avoid confusion of components.

[0027] Unless otherwise required by the context, throughout this specification, "a plurality" means "at least two", and "comprising" is interpreted as open and inclusive, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "examples", "specific examples" or "some examples", etc. are intended to indicate that the specific features, structures, materials or characteristics related to the embodiment or example are included in at least one embodiment or example of this specification. The schematic representations of the above terms do not necessarily refer to the same embodiment or example.

[0028] Next, the technical solutions in the embodiments of this specification will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of this specification. Obviously, the described embodiments are only a part of the embodiments of this specification, rather than all the embodiments. Based on the embodiments in this specification, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the scope of protection of this specification.

[0029] Overview

[0030] Referring to Figure 1 , Figure 1 shows a schematic diagram of the structure of a typical systolic array. Figure 1 In ij and b ij, for i = 0 to n, j = 0 to n) flow in the systolic array, and each processing unit processes the data when it flows through. The flow pattern of the data in the systolic array can be pre-determined. All necessary processing for the computing task can be completed during the process of the data flowing into and out of the processing unit array. During the processing, there is no need to repeatedly read the data, which can reduce the number of data reads and writes, and can also improve the processing speed without increasing the input and output rates.

[0031] However, through the analysis of the usage scenarios of the systolic array, it is found that as the application scenarios of the systolic array become increasingly complex, in scenarios such as cloud computing, a large number of applications run simultaneously, and there may be a situation where multiple computing tasks wait for the systolic array to process at the same time. As Figure 1 shown, the existing systolic array architectures often focus on the efficient execution of a single task and lack effective support for multi-task concurrency. This leads to the situation that when an application monopolizes the systolic array for a long time, other tasks cannot obtain computing resources in a timely manner, seriously affecting the overall performance of the system and the user experience. Especially in the cloud computing scenario, the flexibility of resource preemption and allocation directly determines the quality of service of the system. If there is no effective task preemption and concurrency mechanism, tasks that occupy computing resources for a long time will cause response delays for other tasks, and may even cause service interruptions and service losses.

[0032] Therefore, the inventors found through research that the systolic array architecture can be optimized and improved. The processing units in the systolic array are divided into multiple array units, so that each array unit includes at least one processing unit. Adjacent array units are connected through a routing unit. By configuring the routing unit, the combination and splitting of the array units can be realized. On this basis, when receiving a computing request for a target task, the target array corresponding to the target task can be allocated by configuring the routing unit, and the target array includes at least one of the array units. For example, when receiving a computing request for a certain target task, the target array that meets its computing requirements can be allocated for the target task according to the computing scale of the target task and the idle array units in the systolic array, meeting the parallel execution requirements of the target task and the tasks that have been executed in the systolic array. In this way, the purpose of realizing parallel processing of multiple tasks based on a single systolic array is achieved, avoiding the problem of low utilization efficiency of the systolic array caused by a single task occupying the entire systolic array for a long time, and effectively improving the utilization efficiency of the systolic array.

[0033] Exemplary Scenario

[0034] Refer to Figure 2 , Figure 2 shows a feasible application scenario of the task processing method provided by the embodiments of this specification, Figure 2It can be a cloud computing scenario where server 10 provides cloud computing services, and users use the corresponding services provided by server 10 through client 20. Server 10 can include a system-on-chip with a systolic array. Different users can each initiate corresponding computing tasks, and server 10 can allocate corresponding target arrays for different computing tasks in the systolic array according to the task processing method for parallel processing of multiple tasks.

[0035] Optionally, client 20 can be a computing device with network access capabilities. Specifically, for example, client 20 can be any one of a desktop computer, a tablet computer, a laptop computer, a smart phone, a digital assistant, a smart wearable device, a shopping guide terminal, a television, a smart speaker, a microphone, etc. Among them, smart wearable devices include but are not limited to smart bracelets, smart watches, smart glasses, smart helmets, smart necklaces, etc. Alternatively, client 20 can also be software that can run on the above computing devices.

[0036] Server 10 can be a computing device with certain computing and processing capabilities. It can have a network communication module, a processor, a memory, etc. The above server 10 can also be a distributed server, which can be a system with multiple processors, memories, network communication modules, etc. operating in coordination. Alternatively, server 10 can also be a server cluster formed by several servers. Or, with the development of science and technology, server 10 can also be a new technical means capable of realizing the corresponding functions of the embodiments of the specification. For example, it can be a new form of "server" based on quantum computing.

[0037] Exemplary Method

[0038] For application in Figure 3 taking the system-on-chip 30 as an example, some embodiments of this specification exemplarily illustrate the task processing method. The system-on-chip includes a systolic array, and the systolic array includes a plurality of array units and a plurality of routing units. Each of the array units includes at least one processing unit, and the routing units are used to connect adjacent array units. The task processing method includes:

[0039] S301: In response to a computing request for a target task, by configuring the routing unit, allocate a corresponding target array for the target task, and the target array includes at least one of the array units.

[0040] Referring to Figure 4 , Figure 4 shows a schematic diagram of a feasible architecture of a systolic array. In Figure 4The figure shows a systolic array comprising four array units (i.e., array units A through D). Each array unit includes 2×2 processing units (PEs). Adjacent array units are connected via routing units. The number of routing units used to connect adjacent array units can be determined based on the size of the array units. The number of processing units included in each array unit can be the same or different. For example, in some embodiments, array unit A can include 2×2 processing units, and array unit B can include 4×4 processing units. This specification does not limit this, and the specific implementation depends on the actual situation.

[0041] The routing unit may include a multiplexer mux. By configuring the input and / or output of the multiplexer mux, the purpose of merging and dividing multiple array units into a target array can be achieved. For example, Figure 5 By controlling the output of the routing unit between array unit B and array unit D, the calculation result of array unit B is given to array unit D as the input of array unit D, so that array unit B and array unit D are combined into a 4×2 matrix. When this matrix is assigned to the target task, the matrix can be called the target matrix. Figure 5 The computation results of array elements A and C are each output to the outside of the systolic array, allowing them to perform computations as separate arrays. If the 4×2 array composed of array elements B and D needs to be split into two separate arrays for task allocation, the computation results of array elements B and D can be output separately by configuring a routing unit between them.

[0042] Based on the systolic array, when a computing request for a target task is received, the target array corresponding to the target task is allocated to the target task in response to the request by configuring the routing unit. The target array includes at least one array unit. In this way, the purpose of parallel processing of multiple tasks based on a single systolic array is achieved, and the problem of low utilization efficiency of the systolic array caused by a single task occupying the entire systolic array for a long time is avoided, thereby effectively improving the utilization efficiency of the systolic array.

[0043] In order to optimize the logic of allocating a target array to a target task, to make the size of the target array allocated to the target task meet the computing requirements of the target task, or to make the target array allocated to the target task meet the resource status in the systolic array, in one embodiment, another task processing method is proposed, such as Figure 6 As shown, the task processing method is applied to a system on chip, the system on chip includes a systolic array, the systolic array includes a plurality of array units and a plurality of routing units, each of the array units includes at least one processing unit, and the routing unit is used to connect adjacent array units. The task processing method includes:

[0044] S601: In response to a computing request for a target task, determine a target array corresponding to the target task according to target parameters;

[0045] S602: Allocate the corresponding target array to the target task by configuring the routing unit, where the target array includes at least one of the array units;

[0046] The target parameters are used to characterize the priority of the target task and the priority of the current task, and the target parameters are further used to characterize at least one of the resource state of the systolic array, the scale of the target task, and the scale of the current task; the current task includes the task being executed by the systolic array.

[0047] In this embodiment, considering the target parameters to determine the target array corresponding to the target task can make the size of the target array meet the computing requirements of the target task, or make the size of the target array adapt to the resource state of the systolic array. The resource state of the systolic array may include the occupied state of the processing units of the systolic array, the number of idle processing units, etc. The scale of the target task may characterize the amount of computation required by the target task, etc. The priority of the target task may include a value assigned in advance for the target task to characterize the priority degree of the processing order. The scale and priority of the current task may refer to the scale and priority of the target task.

[0048] This method comprehensively considers the target parameters characterizing the priority of the target task and the priority of the current task, etc. to determine the target array. On the one hand, it can more reasonably determine the size of the target array corresponding to the target task and the processing order of each target task. On the other hand, it can reasonably manage the execution of the current task according to the priorities of each task, and stop the execution of the current task when necessary to ensure the priority execution of high-priority tasks.

[0049] Optionally, in one embodiment, the determining the target array corresponding to the target task according to the target parameters includes:

[0050] Based on the priority parameters, calculate the priority scores of each target task and each current task; the priority parameters include the priority of the target task, the priority of the current task, and the executed time of the current task;

[0051] Based on the priority scores and the total remaining computing resources of the systolic array, determine the target array corresponding to the target task according to the priority scores; the total remaining computing resources include unoccupied computing units.

[0052] In this embodiment, the target array is determined by integrating the total remaining computing resources of the systolic array and the priority scores of each task, so that the scale of the determined target array takes into account the resource status of the systolic array and the priorities of each task, thereby increasing the rationality of the determined target array.

[0053] In an alternative embodiment, calculating the priority scores of each target task and each current task based on the priority parameter includes:

[0054] Taking the ratio of the priority of the task to be calculated to the slack time of the task to be calculated as the priority score of the task to be calculated; the task to be calculated includes the target task or the current task, and the slack time of the task to be calculated is equal to the difference between the constraint time of the task to be calculated and the executed time of the task to be calculated; the constraint time of the task to be calculated is used to characterize the task execution duration constraint of the task to be calculated.

[0055] In this embodiment, the priority score is determined by comprehensively considering the priority of the task to be calculated and the slack time of the task to be calculated. Specifically, the higher the priority of the task to be calculated, the higher the priority score of the task to be calculated, ensuring that high-priority tasks to be calculated can be allocated more computing units or be scheduled for execution earlier.

[0056] In addition, the slack time of the task to be calculated is equal to the difference between the constraint time of the task waiting to be calculated and the executed time of the task to be calculated, that is, the slack time of the task to be calculated is positively correlated with the remaining required execution duration of the task to be calculated. The smaller the slack time of the task to be calculated, the smaller the remaining required execution time of the task to be calculated. In this embodiment, the smaller the slack time of the task to be calculated, the higher the priority score of the task to be calculated. In this way, tasks with less required execution time can be scheduled to be executed first.

[0057] In an alternative embodiment, determining the target array corresponding to the target task according to the priority score and the total remaining computing resources of the systolic array includes:

[0058] Determining the computing resources included in the corresponding target array for the target task in the total remaining computing resources of the systolic array according to the target ratio;

[0059] The target ratio is equal to the ratio of the priority score of the target task to the total priority score; the total priority score is equal to the sum of the priority score of the target task and the priority score of the current task.

[0060] In this embodiment, the ratio of the priority score of the target task to the sum of the priority scores of all tasks is used as the basis for determining the target array, so that when there are multiple target tasks waiting to be executed, there is a high probability that the multiple target tasks will all be assigned to the corresponding target arrays to execute the multiple target tasks in parallel, which is beneficial to reducing the waiting time of the target tasks.

[0061] In application scenarios such as cloud computing, the urgency levels of different tasks are usually different. For example, the tasks issued by certain user A are usually of a relatively high urgency level, while the tasks issued by another user B are of a relatively low urgency level and can be executed when the system is idle. Thus, when the idle resources of the system (i.e., idle array units) are limited, it is necessary to propose a method to release idle resources by switching the execution state of the current task to preferentially ensure the execution of target tasks with higher priorities. Specifically, in one embodiment, the determining the target array corresponding to the target task according to the target parameter includes:

[0062] Determining the target array corresponding to the target task in the target resources according to the target parameter;

[0063] The target resources include at least one of the idle array units in the systolic array and the array units occupied by the current task;

[0064] When the target resources include the array units occupied by the current task, the allocating the corresponding target array for the target task by configuring the routing unit includes:

[0065] Stopping at least one of the current tasks to release the array units occupied by the stopped current tasks;

[0066] Allocating the corresponding target array for the target task among the released array units and the original idle array units.

[0067] In this embodiment, when the idle resources are not sufficient to satisfy the execution of the target task, the array units occupied by the current task can be used as all or part of the target resources, so as to satisfy the preferential execution of the target task, thereby ensuring the preferential execution of the target task in special cases.

[0068] In an optional embodiment, a processing method is provided when the computing resources of the systolic array are not sufficient to satisfy the computing resources required by the target array. Specifically, the allocating the corresponding target array for the target task by configuring the routing unit specifically includes:

[0069] If the remaining computing resources in the systolic array are greater than or equal to the computing resources required by the target array, then by configuring the output object of the routing unit, the target array is partitioned from the first array to be allocated, and the target array is allocated to the target task; the first array to be allocated includes the idle array units in the systolic array.

[0070] If the remaining computing resources in the systolic array are less than the computing resources required by the target array, then the execution of the task to be stopped is halted, and by configuring the output object of the routing unit, the target array is partitioned from the second array to be allocated, and the target array is allocated to the target task; the second array to be allocated includes the array units corresponding to the task to be stopped and the idle array units in the systolic array.

[0071] In this embodiment, when the target array corresponding to the target task is determined, if the remaining computing resources in the systolic array are less than the computing resources required by the target array, then the execution of the task to be stopped can be halted, and the array units allocated to the task to be stopped are incorporated into the second array to be allocated and, as idle array units, are preferentially used to partition the target array for the target task.

[0072] The task to be stopped can be a task with a lower priority or a lower priority score. In an optional embodiment, the task to be stopped can be the current task with the lowest priority score among all tasks (the target task and the current task). The calculation method of the priority score can refer to the relevant limitations in the foregoing text, and this specification will not elaborate herein. In this way, the priority execution of tasks with high priority scores can be ensured.

[0073] To improve the context save and restore speed of the task to be stopped, in an optional embodiment, the halting of the execution of the task to be stopped includes:

[0074] Performing a context caching operation, where the context caching operation includes caching the context data corresponding to the task to be stopped in a target register.

[0075] When resuming the execution of the task to be stopped, performing a context restoration operation; the context restoration operation includes reading the context data corresponding to the task to be stopped from the target register;

[0076] Both the context caching operation and the context restoration operation are pipelined operations.

[0077] In this embodiment, context data is preferentially cached in the target register instead of being directly written to memory, thereby accelerating the save and restore speeds. Moreover, by decomposing the context caching operation and the context restoration operation into pipelined operations, some operations can be executed during the computing idle period, which is conducive to achieving efficient parallel management of context management.

[0078] In one embodiment, referring to Figure 7 , Figure 7 shows the software and hardware structures for cooperating with a systolic array to implement a task processing method in a system on a chip. Among them, the priority management module can calculate priority scores for the current task and the target task, and calculate the appropriate resource scale of the target array for the target task; the task scheduling module can flexibly select whether to allocate the computing units in the systolic array to the target task according to the priority scores calculated by the priority management module, the scale of the target array, and the total remaining computing resources in the systolic array. The resource allocation module can allocate the target array to the target task according to the corresponding instructions given by the task scheduling module, and save the context of the task when the task to be stopped needs to be stopped. Optionally, the priority management module, the task scheduling module, and the resource allocation module can be software modules running in the control module of the system on a chip, and the control module can include a processor or a controller. This specification does not make a limitation on this, and it depends on the actual situation specifically.

[0079] Exemplary Device

[0080] In an exemplary embodiment of this specification, a task processing device is further provided, which is applied to a system on a chip. The system on a chip includes a systolic array. The systolic array includes a plurality of array units and a plurality of routing units. Each of the array units includes at least one processing unit. The routing units are used to connect adjacent array units. The task processing device includes:

[0081] A processing module, configured to, in response to a computing request for a target task, determine a target array corresponding to the target task according to target parameters;

[0082] By configuring the routing units, allocate the corresponding target array to the target task. The target array includes at least one of the array units;

[0083] The target parameters are used to characterize the priority of the target task and the priority of the current task. The target parameters are further used to characterize at least one of the resource state of the systolic array, the scale of the target task, and the scale of the current task. The current task includes the task being executed by the systolic array.

[0084] For the specific limitations of the task processing device, reference may be made to the limitations of the task processing method in the foregoing text, which will not be elaborated herein. Each module in the above task processing device can be implemented in whole or in part by software, hardware, and their combination. The above modules can be embedded in the processor of the computer device in hardware form or independent of it, or stored in the memory of the computer device in software form, so that the processor can call and execute the operations corresponding to the above modules.

[0085] Exemplary Equipment

[0086] An embodiment of this specification also provides a system on a chip, including: a systolic array and a control module. The systolic array includes a plurality of array units and a plurality of routing units. Each of the array units includes at least one processing unit, and the routing units are used to connect adjacent array units;

[0087] The control module is configured to:

[0088] In response to a calculation request for a target task, determine a target array corresponding to the target task according to target parameters;

[0089] By configuring the routing units, allocate the corresponding target array for the target task. The target array includes at least one of the array units;

[0090] The target parameters are used to characterize the priority of the target task and the priority of the current task. The target parameters are also used to characterize at least one of the resource status of the systolic array, the scale of the target task, and the scale of the current task; the current task includes the task being executed by the systolic array.

[0091] As described above, the control module may include a processor and / or a controller in the system on a chip. For the related limitations of the control module executing the task processing method, reference may be made to the relevant descriptions in the foregoing text, which will not be elaborated in this specification.

[0092] Another embodiment of this application also proposes a computing device. Refer to Figure 8 As shown, an exemplary embodiment of this specification also provides a computing device, including: a memory and a processor. The memory stores a computer program, and when the processor executes the computer program, it executes the steps in the task processing method according to various embodiments of this specification described in the above embodiments of this specification.

[0093] The internal structure of this computing device can be as Figure 8As shown, the computing device includes a processor, a memory, a network interface, and an input device connected via a system bus. Among them, the processor of the computing device is used to provide computing and control capabilities. The memory of the computing device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and computer programs. The internal memory provides an environment for the operation of the operating system and computer programs in the non-volatile storage medium. The network interface of the computing device is used to communicate with an external terminal via a network connection. When the computer program is executed by the processor, it performs the steps in the task processing method according to various embodiments of this specification described in the above embodiments of this specification.

[0094] The processor may include a main processor and may also include a baseband chip, a modem, etc.

[0095] The memory stores a program for implementing the technical solution of the present invention and may also store an operating system and other key services. Specifically, the program may include program code, and the program code includes computer operation instructions. More specifically, the memory may include a read-only memory (ROM), other types of static storage devices that can store static information and instructions, a random access memory (RAM), other types of dynamic storage devices that can store information and instructions, a disk memory, a flash memory, etc.

[0096] The processor may be a general-purpose processor, such as a general-purpose central processing unit (CPU), a microprocessor, etc., or an application-specific integrated circuit (ASIC), or one or more integrated circuits for controlling the execution of the program of the present invention. It may also be a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components.

[0097] The input device may include a device for receiving data and information input by a user, such as a keyboard, a mouse, a camera, a scanner, a light pen, a voice input device, a touch screen, a pedometer, or a gravity sensor, etc.

[0098] The output device may include a device for allowing information to be output to a user, such as a display screen, a printer, a speaker, etc.

[0099] The communication interface may include a device using any transceiver type to communicate with other devices or communication networks, such as Ethernet, a radio access network (RAN), a wireless local area network (WLAN), etc.

[0100] The processor executes the program stored in the memory and calls other devices, which can be used to implement each step of any one of the task processing methods provided in the above embodiments of the present application.

[0101] The computing device may further include a display component and a voice component. The display component may be a liquid crystal display screen or an electronic ink display screen. The input device of the computing device may be a touch layer covered on the display component, or a button, a trackball or a touchpad provided on the housing of the computing device, or an external keyboard, touchpad or mouse, etc.

[0102] Those skilled in the art can understand that Figure 8 the structure shown in is only a block diagram of some structures related to the solution of this specification, and does not constitute a limitation on the computing device to which the solution of this specification is applied. The specific computing device may include more or fewer components than those shown in the figure, or combine some components, or have different component arrangements.

[0103] The technical features of the above embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope recorded in this specification.

[0104] The above-described embodiments only represent several implementation manners of this specification. The description is relatively specific and detailed, but it should not be understood as a limitation on the scope of the solution provided by the embodiments of this specification. It should be noted that for those of ordinary skill in the art, without departing from the concept of this specification, several modifications and improvements can still be made, and these all belong to the protection scope of this specification. Therefore, the protection scope of the patent of this specification should be subject to the appended claims.

Claims

1. A task processing method, characterized in that, Applied to a system on chip, the system on chip includes a systolic array, the systolic array includes a plurality of array units and a plurality of routing units, each of the array units includes at least one processing unit, and the routing unit is used to connect adjacent array units. The task processing method includes: In response to a computing request for a target task, determining a target array corresponding to the target task according to target parameters; By configuring the routing unit, the corresponding target array is allocated to the target task, and the target array includes at least one array unit; The target parameter is used to characterize the priority of the target task and the priority of the current task. The target parameter is also used to characterize at least one of the resource status of the systolic array, the scale of the target task, and the scale of the current task; the current task includes the task being executed by the systolic array.

2. The method according to claim 1, characterized in that, The determining, according to the target parameters, a target array corresponding to the target task comprises: Calculating the priority scores of each target task and each current task based on priority parameters; the priority parameters include the priority of the target task, the priority of the current task, and the execution time of the current task; Based on the priority score and the total remaining computing resources of the systolic array, a target array corresponding to the target task is determined according to the priority score; the total remaining computing resources include unoccupied computing units.

3. The method according to claim 2, wherein Calculating the priority scores of each target task and each current task based on the priority parameter includes: The ratio of the priority of the task to be calculated to the slack time of the task to be calculated is used as the priority score of the task to be calculated; the task to be calculated includes the target task or the current task, and the slack time of the task to be calculated is equal to the difference between the constraint time of the task to be calculated and the execution time of the task to be calculated; the constraint time of the task to be calculated is used to characterize the task execution duration constraint of the task to be calculated.

4. The method according to claim 2, wherein The determining, based on the priority score and the total remaining computing resources of the systolic array, the target array corresponding to the target task according to the priority score comprises: According to the target ratio, determining computing resources included in the target array corresponding to the target task from the total remaining computing resources of the systolic array; The target ratio is equal to the ratio of the priority score of the target task to the total priority score; the total priority score is equal to the sum of the priority score of the target task and the priority score of the current task.

5. The method according to claim 1, wherein The determining, according to the target parameters, a target array corresponding to the target task comprises: Determining a target array corresponding to the target task in the target resource according to the target parameter; The target resource includes at least one of an idle array unit in the systolic array and an array unit occupied by the current task; When the target resource includes the array unit occupied by the current task, allocating the corresponding target array to the target task by configuring the routing unit includes: Stopping at least one of the current tasks to release the array units occupied by the stopped current tasks; Among the released array units and the original idle array units, allocate the corresponding target array for the target task.

6. The method according to claim 5, wherein The step of allocating the corresponding target array for the target task by configuring the routing unit specifically includes: If the remaining computing resources in the systolic array are greater than or equal to the computing resources required by the target array, then by configuring the output object of the routing unit, divide out the target array from the first array to be allocated, and allocate the target array to the target task; the first array to be allocated includes the idle array units in the systolic array; If the remaining computing resources in the systolic array are less than the computing resources required by the target array, then stop the execution of the task to be stopped, and by configuring the output object of the routing unit, divide out the target array from the second array to be allocated, and allocate the target array to the target task; the second array to be allocated includes the array units corresponding to the task to be stopped and the idle array units in the systolic array.

7. The method according to claim 6, wherein The step of stopping the execution of the task to be stopped includes: Performing a context caching operation, and the context caching operation includes: caching the context data corresponding to the task to be stopped in a target register.

8. The method according to claim 7, wherein It further includes: When resuming the execution of the task to be stopped, performing a context restoration operation; The context restoration operation includes: reading the context data corresponding to the task to be stopped from the target register; Both the context caching operation and the context restoration operation are pipelined operations.

9. The method according to claim 6, wherein The task to be stopped includes the current task with the lowest priority score; the current task includes the tasks being executed by the systolic array.

10. A system on a chip, characterized in that, It includes: A systolic array and a control module, the systolic array includes a plurality of array units and a plurality of routing units, each of the array units includes at least one processing unit, and the routing unit is used to connect adjacent array units; The control module is configured to: In response to a computing request for a target task, determine a target array corresponding to the target task according to target parameters; By configuring the routing unit, allocate the corresponding target array for the target task, and the target array includes at least one of the array units; The target parameters are used to characterize the priority of the target task and the priority of the current task, and the target parameters are also used to characterize at least one of the resource state of the systolic array, the scale of the target task, and the scale of the current task; the current task includes the tasks being executed by the systolic array.

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