Direct memory access module verification method and device, equipment and medium

Abstract

The invention discloses a direct memory access module verification method and device, equipment and a medium, and relates to the field of integrated circuit verification. Respectively converting each data transmission parameter in the first transaction into each second transaction under an advanced high-performance bus protocol by using a bridge; executing a corresponding data transmission operation based on each second transaction through any direct memory access module, and sending an operation result to a verification component; and obtaining the first transaction and the operation result through the verification component, and verifying any direct memory access module based on the first transaction and the operation result. According to the invention, when the data transmission parameter changes, the verification of the direct memory access module can be realized only by modifying the first transaction under the advanced extensible interface protocol, so that the reusability of the verification platform is realized, and the verification difficulty and complexity are reduced.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit verification, and particularly to a method, device, equipment and medium for verifying a direct memory access module. Background Art

[0002] With the improvement of the integration level of SoC (System on Chip) and the increase of processing requirements, in order to meet the data flow characteristics and performance requirements in different application scenarios, the design of DMA (Direct Memory Access) has become more diverse and flexible. In a single SoC, multiple DMA modules may be integrated. Although there are commonalities in their configurations, each module may be differentially set and optimized according to the specific functions or performance goals it serves. For example, according to different application scenarios and data bit-width requirements, the CPU (Central Processing Unit) can adopt different strategies to issue data transfer parameters to the DMA module in different batches so that the DMA module can implement the corresponding data transfer function. At the same time, in order to optimize system performance, different numbers of channels can be instantiated at the slave ports of different DMA modules to adapt to different data transfer requirements.

[0003] Due to the complexity of DMA operations and their direct impact on system performance, the verification work has become particularly important. In current DMA designs, the AHB (Advanced High Performance Bus) protocol is generally used to configure the data transfer parameters of the DMA module. However, different DMA modules have differences in the number and order of parameter configurations, the width and number of AHB channels, etc. Moreover, each data transfer parameter corresponds to an AHB transaction in sequence, that is, the number and order of AHB transactions correspond to the data transfer parameters. At this time, when verifying the DMA module based on AHB transactions, a verification environment needs to be separately constructed for the DMA module, that is, specific logic for processing AHB transactions needs to be separately designed for the DMA module. If the number and order of parameter configurations change, the verification environment for the DMA module also needs to be reconstructed, which will greatly increase the difficulty and complexity of the verification work.

[0004] It can be seen that how to reduce the difficulty and complexity in verifying the direct memory access module is a problem that needs to be solved by those skilled in the art. Summary of the Invention

[0005] The purpose of the embodiments of the present invention is to provide a direct memory access module verification method, device, equipment and medium, which can realize the verification of the direct memory access module only by modifying the first transaction under the Advanced Extensible Interface protocol when the data transmission parameters change, realizing the reusability of the verification platform and reducing the verification difficulty and complexity. The specific scheme is as follows:

[0006] In a first aspect, the present invention provides a direct memory access module verification method, which is applied to a verification platform built based on the Unified Verification Methodology. The verification platform includes a verification component and a design under test for any direct memory access module in the system on chip. The design under test includes any direct memory access module and a bridge connected to any direct memory access module; The method includes:

[0007] After the design under test obtains the first transaction under the Advanced Extensible Interface protocol, use the bridge to convert each data transmission parameter in the first transaction into each second transaction under the Advanced High Performance Bus protocol respectively, and transmit each second transaction to any direct memory access module;

[0008] Execute corresponding data transmission operations through any direct memory access module based on each second transaction, and send the operation results to the verification component;

[0009] Obtain the first transaction and the operation results through the verification component, and verify any direct memory access module based on each data transmission parameter and the operation results in the first transaction.

[0010] Optionally, the first transaction is a transaction generated based on the constraint range of each data transmission parameter for any direct memory access module; Moreover, the constraint ranges of each data transmission parameter for different direct memory access modules are different.

[0011] Optionally, the direct memory access module verification method of the present invention further includes:

[0012] When obtaining the first transaction each time, determine the target range node corresponding to any data transmission parameter in the first transaction from each range node through the functional coverage component in the verification platform, and obtain the functional coverage for any data transmission parameter based on the proportion of the historically determined target range node and the currently determined target range node in each range node;

[0013] Wherein, each range node is a plurality of nodes obtained by dividing the constraint range of any data transmission parameter for any direct memory access module.

[0014] Optionally, when each data transmission parameter in the first transaction includes a data read / write mode, a data source address, a data destination address and a data length, executing corresponding data transmission operations through any direct memory access module based on each second transaction includes:

[0015] Parse each second transaction through any direct memory access module to obtain a data read / write mode, a data source address, a data destination address, and a data length, and perform a data transfer operation in a mode corresponding to the data read / write mode based on the data source address, the data destination address, and the data length.

[0016] Optionally, performing a data transfer operation in a mode corresponding to the data read / write mode based on the data source address, the data destination address, and the data length includes:

[0017] When the data read / write mode is a data read mode, read data from the memory of a slave device connected to the slave end of any direct memory access module based on the data source address and the data length, and transfer the read first data to the host end of any direct memory access module;

[0018] Write the first data into the memory of a master device connected to the host end based on the data destination address through the host end.

[0019] Optionally, performing a data transfer operation in a mode corresponding to the data read / write mode based on the data source address, the data destination address, and the data length includes:

[0020] When the data read / write mode is a data write mode, read data from the memory of the master device based on the data destination address and the length, and transfer the read second data to the slave end;

[0021] Write the second data into the memory of the slave device based on the data source address through the slave end.

[0022] Optionally, verify any direct memory access module based on each data transfer parameter and operation result in the first transaction, including:

[0023] Determine whether the data read / write mode is a data read mode;

[0024] If the data read / write mode is a data read mode, determine whether the data source address is the data read start address in the operation result and whether the data destination address is the data write start address in the operation result;

[0025] If the data source address is the data read start address and the data destination address is the data write start address, determine whether the first actual read data and the first actual write data in the operation result are the same; the first actual read data is the data obtained from the memory of the slave device based on the data source address and the data length; the first actual write data is the data obtained from the memory of the master device based on the data destination address and the data length;

[0026] If the first actual read data is the same as the first actual write data, it is determined that the verification of any direct memory access module passes;

[0027] If the data read / write mode is the data write mode, it is judged whether the data source address is the data write start address and whether the data destination address is the data read start address;

[0028] If the data source address is the data write start address and the data destination address is the data read start address, it is judged whether the second actual read data in the operation result is the same as the second actual write data; the second actual read data is the data obtained from the main device memory based on the data destination address and the data length; the second actual write data is the data obtained from the slave device memory based on the data source address and the data length;

[0029] If the second actual read data is the same as the second actual write data, it is determined that the verification of any direct memory access module passes.

[0030] In a second aspect, the present invention provides a direct memory access module verification device, which is applied to a verification platform built based on a unified verification methodology. The verification platform includes a verification component and a design under test for any direct memory access module in a system on a chip. The design under test includes any direct memory access module and a bridge connected to any direct memory access module; the device includes:

[0031] A transaction conversion module, configured to, after the design under test obtains a first transaction under the advanced extensible interface protocol, use the bridge to respectively convert each data transmission parameter in the first transaction into each second transaction under the advanced high-performance bus protocol, and transmit each second transaction to any direct memory access module;

[0032] An operation execution module, configured to execute corresponding data transmission operations based on each second transaction through any direct memory access module, and send the operation result to the verification component;

[0033] A verification module, configured to obtain the first transaction and the operation result through the verification component, and verify any direct memory access module based on each data transmission parameter in the first transaction and the operation result.

[0034] In a third aspect, the present invention provides an electronic device, including:

[0035] A memory, configured to store a computer program;

[0036] A processor, configured to execute the computer program to implement the steps of the foregoing direct memory access module verification method.

[0037] In a fourth aspect, the present invention provides a computer-readable storage medium having a computer program stored thereon, which implements the steps of the aforementioned direct memory access module verification method when executed by a processor.

[0038] The direct memory access module verification method of the present invention is applied to a verification platform built based on a unified verification methodology. The verification platform includes a verification component and a design to be tested for any direct memory access module in a system on chip. The design to be tested includes any direct memory access module and a bridge connected to any direct memory access module. The specific scheme includes: after the design to be tested obtains a first transaction under an advanced extensible interface protocol, using the bridge to convert each data transmission parameter in the first transaction into each second transaction under an advanced high-performance bus protocol, and transmitting each second transaction to any direct memory access module; performing a corresponding data transmission operation based on each second transaction by any direct memory access module, and sending the operation result to the verification component; obtaining the first transaction and the operation result by the verification component, and verifying any direct memory access module based on each data transmission parameter and the operation result in the first transaction.

[0039] Beneficial effects: The present invention configures the data transmission parameters of the direct memory access module by adopting the advanced extensible interface protocol. Since the advanced extensible interface protocol can put all the parameters required for a data transmission in one transaction compared to the advanced high-performance bus protocol, the direct memory access module can be verified based on a transaction under the advanced extensible interface protocol. Based on this, when the number and / or order of data transmission parameters changes, the present invention only needs to modify the parameters in the transaction under the advanced extensible interface protocol, without having to re-build the verification environment and verification platform for the direct memory access module. Moreover, the present invention can verify any direct memory access module in the system on chip through a verification platform built based on a unified verification methodology, thereby achieving the reuse of the verification platform and reducing the difficulty and complexity of the direct memory access module verification. Furthermore, since the direct memory access module has its own interface under the advanced high-performance bus protocol, without changing the hardware design of the direct memory access module, the present invention sets a bridge to convert the transaction under the advanced extensible interface protocol into the transaction under the advanced high-performance bus protocol, thereby facilitating the direct memory access module to receive and process it. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] In order to more clearly illustrate the embodiments of the present invention, the following is a brief introduction to the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0041] Figure 1 A flowchart of a method for verifying a direct memory access module provided by an embodiment of the present invention;

[0042] Figure 2 A structural diagram of a design under test provided by an embodiment of the present invention;

[0043] Figure 3 [[ID=NO=11]]A schematic diagram of the definition of a first transaction under an Advanced eXtensible Interface (AXI) protocol provided by an embodiment of the present invention;

[0044] Figure 4 A flowchart of verifying a first transaction and an operation result provided by an embodiment of the present invention;

[0045] Figure 5 A structural diagram of a verification platform provided by an embodiment of the present invention;

[0046] Figure 6 A schematic diagram of the structure of a direct memory access module verification device provided by an embodiment of the present invention;

[0047] Figure 7 A structural diagram of an electronic device provided by an embodiment of the present invention. Detailed implementation manners

[0048] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0049] The terms "including" and "having" in the specification of the present invention and any deformations related to "including" and "having" are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units is not limited to the listed steps or units, but may include steps or units not listed.

[0050] In order to enable those skilled in the art to better understand the solution of the present invention, the present invention will be further described in detail below in conjunction with the accompanying drawings and specific implementation manners.

[0051] In current DMA designs, the AHB protocol is generally used to configure the data transfer parameters of the DMA module. However, different DMA modules vary in terms of the number and order of parameter configurations, AHB channel width and quantity, etc. Moreover, each data transfer parameter corresponds to an AHB transaction in sequence, that is, the number and order of AHB transactions correspond to the data transfer parameters. At this time, when verifying the DMA module based on AHB transactions, a separate verification environment needs to be constructed for the DMA module, that is, a specific logic for processing AHB transactions needs to be designed separately for the DMA module. If the number and order of parameter configurations change, the verification environment for the DMA module needs to be rebuilt, which will greatly increase the difficulty and complexity of the verification work. For this reason, the embodiments of the present invention provide a direct memory access module verification method, which can, when the data transfer parameters change, achieve the verification of the direct memory access module only by modifying the first transaction under the advanced extensible interface protocol, realizing the reusability of the verification platform and reducing the verification difficulty and complexity.

[0052] See Figure 1 As shown, the embodiments of the present invention provide a direct memory access module verification method, which is applied to a verification platform built based on the unified verification methodology. The verification platform includes a verification component and a design under test for any direct memory access module in the system on a chip. The design under test includes any direct memory access module and a bridge connected to any direct memory access module. Among them, the direct memory access module verification method includes:

[0053] Step S11: After the design under test obtains the first transaction under the advanced extensible interface protocol, use the bridge to convert each data transfer parameter in the first transaction into each second transaction under the advanced high-performance bus protocol respectively, and transmit each second transaction to any direct memory access module.

[0054] When the embodiments of the present invention integrate multiple direct memory access modules in a single SoC chip, for any one of the multiple direct memory access modules, denoted as any direct memory access module, a bridge can be matched to any direct memory access module first, and a design under test (DUT) can be constructed based on any direct memory access module and the bridge connected to any direct memory access module. Then, a verification platform is built based on the verification component and the design under test for any direct memory access module in the system on a chip, and the verification platform is built using the unified verification methodology (UVM). Since the unified verification methodology has advantages such as standardization, reusability, and maintainability, the verification platform built by the embodiments of the present invention can achieve the verification of any direct memory access module in the system on a chip.

[0055] Considering that different direct memory access modules have different numbers of AHB interfaces, therefore, in the embodiments of the present invention, it is necessary to match a corresponding number of bridges for the direct memory access module according to the number of AHB interfaces of the direct memory access module, so that the bridges are connected to the AHB interfaces of the direct memory access module one by one.

[0056] The function of the bridge is to convert the first transaction under the Advanced eXtensible Interface (AXI) protocol into the second transaction under the Advanced High-performance Bus protocol. Since all the parameters required for a data transfer can be stored in the first transaction under the Advanced eXtensible Interface protocol, and all the parameters required for a data transfer correspond one by one to the second transaction under the Advanced High-performance Bus protocol, that is, one parameter corresponds to one second transaction under the Advanced High-performance Bus protocol. Therefore, the function of the bridge can specifically include: converting each data transfer parameter in the first transaction under the Advanced eXtensible Interface protocol into each second transaction under the Advanced High-performance Bus protocol.

[0057] As Figure 2 shown, the central processing unit transmits the first transaction under the Advanced eXtensible Interface protocol to the bridge in the design under test through the AXI bus; wherein, the first transaction includes each data transfer parameter, and the bridge can be represented as AXI2AHB bridge. After receiving the first transaction under the Advanced eXtensible Interface protocol, the bridge in the design under test converts each data transfer parameter in the first transaction under the Advanced eXtensible Interface protocol into each second transaction under the Advanced High-performance Bus protocol, that is, the data transfer parameter corresponds to the second transaction one by one, and then sequentially transmits each second transaction to the AHB interface connected to the bridge according to the configuration order of each data transfer parameter; wherein, the AHB interface is located in the slave end of the direct memory access module, and the direct memory access module is located in the design under test.

[0058] It should be noted that the slave end of the direct memory access module is also connected to the slave device memory for reading and writing data to and from the slave device memory; while the master end of the direct memory access module is connected to the master device memory for reading and writing data to and from the master device memory.

[0059] It should also be noted that since different direct memory access modules have different constraint ranges for each data transfer parameter, therefore, for any direct memory access module in the system on a chip, the first transaction under the Advanced eXtensible Interface protocol is a transaction generated based on the constraint range of each data transfer parameter of any direct memory access module.

[0060] Specifically, a value is randomly selected from within the constraint range of each data transfer parameter by any direct memory access module as the parameter value of each data transfer parameter, and then based on the parameter values of each data transfer parameter, a first transaction under the Advanced eXtensible Interface protocol is generated. Taking the data transfer parameters including the data source address, the data destination address, and the data length as an example, if the constraint range of any direct memory access module for the data source address is 0x00000001 - 0x00011111, the constraint range for the data destination address is 0x00000001 - 0x00011111, and the constraint range for the data length is 0 - 64, then the data source address can be selected as 0x00000011, the data destination address as 0x00000011, and the data length as 16. At this time, based on the selected data source address, data destination address, and data length, a first transaction under the Advanced eXtensible Interface protocol can be generated.

[0061] It should be noted that the data source address refers to the starting address for the direct memory access module to read and write data from the slave device memory, the data destination address refers to the starting address for the direct memory access module to read and write data to the master device memory, and the data length refers to the length of the data read and written.

[0062] Step S12: Through any direct memory access module, perform corresponding data transfer operations based on each second transaction, and send the operation result to the verification component.

[0063] In the embodiment of the present invention, through any direct memory access module, each second transaction transmitted by the bridge is received, corresponding data transfer operations are performed based on each second transaction, and at the same time, the operation result is sent to the verification component in the verification platform.

[0064] Specifically, when the data transfer parameters in the first transaction include the data read / write mode, the data source address, the data destination address, and the data length, through any direct memory access module, each second transaction transmitted by the bridge is received, and each second transaction is parsed to obtain the data read / write mode, the data source address, the data destination address, and the data length. Then, based on the data source address, the data destination address, and the data length, data transfer operations corresponding to the corresponding mode of the data read / write mode are performed, and at the same time, the operation result is sent to the verification component in the verification platform.

[0065] It should be noted that the data read / write mode, the data source address, the data destination address, and the data length each correspond to a second transaction. Moreover, the data read / write mode includes the data read mode and the data write mode. The data read mode means that the direct memory access module writes the data read from the slave device memory into the master device memory, and the data write mode means that the direct memory access module writes the data read from the master device memory into the slave device memory.

[0066] According to one embodiment, when the data read / write mode is the data read mode, the slave side of any direct memory access module reads data from the slave device memory connected to the slave side based on the data source address and the data length, and transmits the read first data to the master side of any direct memory access module. The master side of any direct memory access module writes the first data read from the slave device memory into the master device memory connected to the master side based on the data destination address.

[0067] According to another embodiment, when the data read / write mode is the data write mode, the master side of any direct memory access module reads data from the master device memory connected to the master side based on the data destination address and the data length, and transmits the read second data to the slave side of any direct memory access module. The slave side of any direct memory access module writes the second data read from the master device memory into the slave device memory connected to the slave side based on the data source address.

[0068] As Figure 3 shown, the embodiment of the present invention provides a definition method for the first transaction under the advanced extensible interface protocol. Among them, axi_tran.addr represents the starting address of the first transaction transmission, that is, the starting storage address of the first transaction; axi_tran.burst_length represents the number of key parameters included in the first transaction; axi_tran.data represents the data transmission parameters included in the first transaction, axi_tran.data[0] represents the data read / write mode included in the first transaction, axi_tran.data[1] represents the data source address included in the first transaction, axi_tran.data[2] represents the data destination address included in the first transaction, axi_tran.data[3] represents the data length included in the first transaction. Of course, axi_tran.data[] can also include other data transmission parameters included in the first transaction.

[0069] Step S13: Obtain the first transaction and the operation result through the verification component, and verify any direct memory access module based on each data transmission parameter in the first transaction and the operation result.

[0070] In the embodiment of the present invention, the verification component obtains the first transaction under the advanced extensible interface protocol based on the TLM (Transaction-level modeling) communication mechanism, and obtains the operation result sent by any direct memory access module based on the TLM communication mechanism. Then, based on each data transmission parameter in the first transaction and the operation result, any direct memory access module is verified, so as to realize the verification of any direct memory access module in the system on chip.

[0071] Specifically, as Figure 4 shown, after the verification component obtains the first transaction and the operation result, it first obtains the data read / write mode, data source address, data destination address, and data length from the first transaction, and determines whether the data read / write mode is the data read mode.

[0072] If the data read / write mode is the data read mode, it determines whether the data source address is the data read start address in the operation result and whether the data destination address is the data write start address in the operation result. If the data source address is the data read start address in the operation result and the data destination address is the data write start address in the operation result, it determines whether the first actual read data in the operation result is the same as the first actual write data in the operation result; where the first actual read data is the data obtained from the slave device memory based on the data source address and the data length; the first actual write data is the data obtained from the master device memory based on the data destination address and the data length. If the first actual read data in the operation result is the same as the first actual write data in the operation result, it determines that the verification of any direct memory access module passes, and prints a notification that the data comparison is correct. If the data source address is not the data read start address in the operation result or the data destination address is not the data write start address in the operation result, or the first actual read data in the operation result is not the same as the first actual write data in the operation result, it determines that the verification of any direct memory access module fails, and prints a notification that the data comparison is incorrect.

[0073] If the data read / write mode is the data write mode, it determines whether the data source address is the data write start address in the operation result and whether the data destination address is the data read start address in the operation result. If the data source address is the data write start address in the operation result and the data destination address is the data read start address in the operation result, it determines whether the second actual read data in the operation result is the same as the second actual write data in the operation result; where the second actual read data is the data obtained from the master device memory based on the data destination address and the data length; the second actual write data is the data obtained from the slave device memory based on the data source address and the data length. If the second actual read data in the operation result is the same as the second actual write data in the operation result, it determines that the verification of any direct memory access module passes, and prints a notification that the data comparison is correct. If the data source address is not the data write start address in the operation result or the data destination address is not the data read start address in the operation result, or the second actual read data in the operation result is not the same as the second actual write data in the operation result, it determines that the verification of any direct memory access module fails, and prints a notification that the data comparison is incorrect.

[0074] It should also be noted that every time the verification platform obtains a first transaction, the functional coverage component in the verification platform determines, from each range node, the target range node corresponding to any data transfer parameter in the first transaction, and obtains the functional coverage for any data transfer parameter based on the proportions of the historically determined target range node and the currently determined target range node among all range nodes. Herein, each range node is obtained after dividing the constraint range of any direct memory access module for any data transfer parameter, and both the historically determined target range node and the currently determined target range node are target range nodes corresponding to any data transfer parameter.

[0075] That is to say, the functional coverage component in the verification platform pre-divides the constraint range of any direct memory access module for each data transfer parameter to obtain each range node corresponding to each data transfer parameter respectively, that is, each data transfer parameter corresponds to multiple range nodes. Every time the verification platform obtains a first transaction, for any data transfer parameter in the first transaction, the functional coverage component in the verification platform determines the target range node corresponding to any data transfer parameter from each range node corresponding to any data transfer parameter, calculates the proportions of the historically determined target range node and the currently determined target range node corresponding to any data transfer parameter among all range nodes, and then obtains the functional coverage for any data transfer parameter according to the proportion.

[0076] Taking any data transfer parameter in the first transaction as the data length as an example, assume that the functional coverage component pre-divides the constraint range (1 - 10) of any direct memory access module for the data length into 5 range nodes, and the 5 range nodes are 1 - 2, 3 - 4, 5 - 6, 7 - 8, 9 - 10 respectively. When the verification platform obtains the first transaction this time, if the data length in the first transaction is 7, then the functional coverage component determines that the target range node corresponding to the data length is 7 - 8 from the 5 range nodes corresponding to the data length, and then calculates the proportions of the historically determined target range nodes (assumed to be 1 - 2, 3 - 4) and the currently determined target range node among all range nodes. At this time, the proportion = the total number of non-repeated target range nodes / the total number of all range nodes = 3 / 5 = 0.6. Finally, the functional coverage for the data length is obtained according to the proportion, and at this time it is 60%.

[0077] It should also be noted that since both the verification component and the functional coverage component in the verification platform process the first transaction under the Advanced eXtensible Interface (AXI) protocol to verify the direct memory access (DMA) module and calculate the functional coverage, and the first transaction under the AXI protocol can store all the parameters required for a data transfer. Even when the number and order of the parameters change, only the parameters in the first transaction need to be modified, and the processing logic of the verification component and the functional coverage component for the first transaction remains unchanged. Therefore, when the embodiments of the present invention want to verify other DMA modules, only the design under test in the verification platform needs to be replaced, and the verification component and the functional coverage component can be reused, thereby reducing the difficulty and complexity of verifying the DMA module to a certain extent.

[0078] Beneficial effects: By using the AXI protocol to configure the data transfer parameters of the DMA module, since the AXI protocol can place all the parameters required for a data transfer in one transaction compared to the Advanced High-performance Bus (AHB) protocol, based on one transaction under the AXI protocol, the verification of the DMA module can be achieved. Based on this, when the number and / or order of the data transfer parameters change, only the parameters in the transaction under the AXI protocol need to be modified, without having to rebuild the verification environment and set up the verification platform for the DMA module again. Moreover, for any DMA module in the system on a chip, the present invention can verify it through a verification platform built based on the unified verification methodology, thus realizing the reusability of the verification platform and reducing the difficulty and complexity of verifying the DMA module. Further, since the DMA module comes with an interface under the AHB protocol, without changing the hardware design of the DMA module, the present invention sets up a bridge to convert the transaction under the AXI protocol into a transaction under the AHB protocol, facilitating the reception and processing of the DMA module.

[0079] See Figure 5 As shown, the embodiments of the present invention provide a method for verifying a direct memory access module, which is applied to a verification platform built based on the unified verification methodology. The verification platform includes a verification component, a functional coverage component, and a design under test. The design under test includes a direct memory access module and a bridge connected to the direct memory access module. The specific solution is as follows:

[0080] Receive a first transaction under the Advanced Extensible Interface (AXI) protocol through a bridge in the design under test, and convert each data transfer parameter in the first transaction under the AXI protocol into a respective second transaction under the Advanced High-Performance Bus (AHB) protocol, where each data transfer parameter in the first transaction includes a data read / write mode, a data source address, a data destination address, and a data length; then, in the order of the configuration of each data transfer parameter, transmit each second transaction to a direct memory access (DMA) module connected to the bridge.

[0081] Receive each second transaction transmitted by the bridge through the DMA module, and parse each second transaction to obtain a data read / write mode, a data source address, a data destination address, and a data length, then perform a data transfer operation corresponding to the data read / write mode based on the data source address, the data destination address, and the data length, and send the operation result to a verification component.

[0082] Obtain the first transaction and the operation result through the verification component, and verify the DMA module based on each data transfer parameter in the first transaction and the operation result.

[0083] Each time the verification platform obtains the first transaction, for any data transfer parameter in the first transaction, the functional coverage component determines a target range node corresponding to any data transfer parameter from each range node corresponding to any data transfer parameter, then calculates the proportion of the historically determined target range node and the currently determined target range node corresponding to any data transfer parameter in each range node, so as to obtain the functional coverage for any data transfer parameter according to the proportion.

[0084] Beneficial effects: By using the Advanced eXtensible Interface (AXI) protocol to configure the data transfer parameters of the direct memory access (DMA) module, since the AXI protocol can place all the parameters required for a single data transfer in one transaction compared to the Advanced High-performance Bus (AHB) protocol, at this time, based on a transaction under the AXI protocol, the verification of the DMA module can be achieved. Based on this, when the quantity and / or order of the data transfer parameters change, only the parameters in the transaction under the AXI protocol need to be modified, without having to rebuild the verification environment and set up a verification platform for the DMA module again. Moreover, for any DMA module in the system-on-chip (SoC), it can be verified through a verification platform built based on the unified verification methodology, thus realizing the reusability of the verification platform and reducing the difficulty and complexity of verifying the DMA module. Further, since the DMA module has an interface under the AHB protocol by default, without changing the hardware design of the DMA module, the present invention sets up a bridge to convert the transaction under the AXI protocol into a transaction under the AHB protocol, so as to facilitate the reception and processing of the DMA module.

[0085] See Figure 6 As shown, an embodiment of the present invention provides a verification device for a direct memory access module, which is applied to a verification platform built based on the unified verification methodology. The verification platform includes a verification component and a design under test (DUT) for any direct memory access module in the system-on-chip. The DUT includes any direct memory access module and a bridge connected to any direct memory access module. Among them, the verification device for the direct memory access module includes:

[0086] A transaction conversion module 11, configured to, after the DUT obtains a first transaction under the AXI protocol, use the bridge to convert each data transfer parameter in the first transaction into each second transaction under the AHB protocol respectively, and transmit each second transaction to any direct memory access module;

[0087] An operation execution module 12, configured to execute corresponding data transfer operations through any direct memory access module based on each second transaction, and send the operation result to the verification component;

[0088] A verification module 13, configured to obtain the first transaction and the operation result through the verification component, and verify any direct memory access module based on each data transfer parameter and the operation result in the first transaction.

[0089] Since the embodiments of the device part correspond to the above-mentioned embodiments, the embodiments of the device part are described with reference to the embodiments of the above-mentioned method part and will not be elaborated here.

[0090] Advantageous effects: The present invention configures the data transfer parameters of the direct memory access module by adopting the Advanced eXtensible Interface (AXI) protocol. Since the AXI protocol can place all the parameters required for a single data transfer in one transaction compared to the Advanced High-performance Bus (AHB) protocol, based on one transaction under the AXI protocol, the verification of the direct memory access module can be achieved. Based on this, when the quantity and / or order of the data transfer parameters change, only the parameters in the transaction under the AXI protocol need to be modified, without the need to reconstruct the verification environment and build a verification platform for the direct memory access module again. Moreover, for any direct memory access module in the system-on-chip, the present invention can be verified through a verification platform built based on the unified verification methodology, thus realizing the reusability of the verification platform and reducing the difficulty and complexity of verifying the direct memory access module. Further, since the direct memory access module comes with an interface under the AHB protocol, without changing the hardware design of the direct memory access module, the present invention sets up a bridge to convert the transaction under the AXI protocol into a transaction under the AHB protocol, thus facilitating the reception and processing of the direct memory access module.

[0091] Further, the embodiment of the present application also discloses an electronic device. Figure 7 It is a structural diagram of an electronic device shown according to an exemplary embodiment. The content in the figure should not be considered as any limitation on the scope of use of the present application. The electronic device may specifically include: at least one processor 21, at least one memory 22, a power supply 23, a communication interface 24, an input / output interface 25, and a communication bus 26. Among them, the memory 22 is used to store a computer program, and the computer program is loaded and executed by the processor 21 to implement the relevant steps in the direct memory access module verification method disclosed in any of the foregoing embodiments. Additionally, the electronic device in this embodiment may specifically be an electronic computer.

[0092] In this embodiment, the power supply 23 is used to provide operating voltage for each hardware device on the electronic device; the communication interface 24 can create a data transfer channel between the electronic device and external devices, and the communication protocol it follows is any communication protocol applicable to the technical solution of the present application, and no specific limitation is imposed on it here; the input / output interface 25 is used to obtain external input data or output data to the outside, and its specific interface type can be selected according to specific application requirements, and no specific limitation is made here.

[0093] In addition, as a carrier for resource storage, the memory 22 may be a read-only memory, a random access memory, a magnetic disk, or an optical disc, etc. The resources stored thereon may include an operating system 221, a computer program 222, etc., and the storage method may be temporary storage or permanent storage.

[0094] Among them, the operating system 221 is used to manage and control each hardware device and the computer program 222 on the electronic device, and it can be Windows Server, Netware, Unix, Linux, etc. In addition to the computer program that can be used to complete the direct memory access module verification method executed by the electronic device disclosed in any of the foregoing embodiments, the computer program 222 may further include computer programs that can be used to complete other specific tasks.

[0095] Furthermore, the present application also discloses a computer-readable storage medium for storing a computer program; wherein, when the computer program is executed by a processor, the direct memory access module verification method disclosed above is implemented. For the specific steps of this method, reference can be made to the corresponding content disclosed in the foregoing embodiments, and details will not be elaborated here.

[0096] Furthermore, the present application also discloses a computer program product, including a computer program / instructions; wherein, when the computer program / instructions are executed by a processor, the direct memory access module verification method disclosed above is implemented. For the specific steps of this method, reference can be made to the corresponding content disclosed in the foregoing embodiments, and details will not be elaborated here.

[0097] In this specification, the various embodiments are described in a progressive manner. Each embodiment focuses on the differences from other embodiments. For the same or similar parts among the various embodiments, reference can be made to each other. For the devices disclosed in the embodiments, since they correspond to the methods disclosed in the embodiments, the description is relatively simple, and reference can be made to the method part for the relevant parts.

[0098] Those skilled in the art can further realize that the units and algorithm steps of the examples described in combination with the embodiments disclosed herein can be implemented by electronic hardware, computer software, or a combination of the two. To clearly illustrate the interchangeability of hardware and software, the components and steps of the examples have been generally described according to their functions in the above description. Whether these functions are executed in a hardware or software manner depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered to exceed the scope of the present application.

[0099] The steps of the methods or algorithms described in combination with the embodiments disclosed herein can be directly implemented by hardware, software modules executed by a processor, or a combination of the two. The software modules can be placed in a random access memory (RAM), internal memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, removable disk, CD-ROM, or any other form of storage medium well-known in the technical field.

[0100] Finally, it should also be noted that in this text, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device comprising a series of elements not only includes those elements, but also includes other elements not expressly listed, or further includes elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "comprising an..." does not exclude the presence of additional identical elements in the process, method, article or device comprising the element.

[0101] The technical solutions provided in this application have been introduced in detail above. Specific examples are used in this text to elaborate on the principle and implementation manner of this application. The description of the above embodiments is only used to help understand the method and its core idea of this application; at the same time, for those of ordinary skill in the art, according to the idea of this application, there will be changes in the specific implementation manner and application scope. In summary, the content of this specification should not be construed as a limitation to this application.

Claims

1. A method for verifying a direct memory access module, characterized in that Applied to a verification platform built based on the unified verification methodology, the verification platform includes verification components and a design under test for any direct memory access module in the system on a chip. The design under test includes the any direct memory access module and a bridge connected to the any direct memory access module; The method includes: After the design under test obtains a first transaction under the Advanced eXtensible Interface protocol, use the bridge to convert the respective data transfer parameters in the first transaction into respective second transactions under the Advanced High Performance Bus protocol, and transmit the respective second transactions to the any direct memory access module; Execute corresponding data transfer operations based on the respective second transactions through the any direct memory access module, and send the operation results to the verification components; Obtain the first transaction and the operation results through the verification components, and verify the any direct memory access module based on the respective data transfer parameters in the first transaction and the operation results.

2. The direct memory access module verification method according to claim 1, wherein The first transaction is a transaction generated based on the constraint ranges of the respective data transfer parameters for the any direct memory access module; moreover, the constraint ranges of the respective data transfer parameters for different direct memory access modules are different.

3. The direct memory access module verification method according to claim 2, wherein Also includes: When obtaining the first transaction each time, determine, from each range node through a functional coverage component in the verification platform, a target range node corresponding to any data transfer parameter in the first transaction, and obtain the functional coverage for any data transfer parameter based on the proportion of the historically determined target range node and the currently determined target range node in the each range node; Wherein, the each range node is a plurality of nodes obtained by dividing the constraint range of the any direct memory access module for the any data transfer parameter.

4. The direct memory access module verification method according to any one of claims 1 to 3, characterized in that When the respective data transfer parameters in the first transaction include a data read / write mode, a data source address, a data destination address, and a data length, the executing, by the any direct memory access module, corresponding data transfer operations based on the respective second transactions includes: Parse the respective second transactions through the any direct memory access module to obtain the data read / write mode, the data source address, the data destination address, and the data length, and execute data transfer operations in a mode corresponding to the data read / write mode based on the data source address, the data destination address, and the data length.

5. The direct memory access module verification method according to claim 4, wherein The executing data transfer operations in a mode corresponding to the data read / write mode based on the data source address, the data destination address, and the data length includes: When the data read / write mode is a data read mode, read data from the slave device memory connected to the slave end of the any direct memory access module based on the data source address and the data length through the slave end of the any direct memory access module, and transmit the read first data to the host end of the any direct memory access module; Write the first data into the main device memory connected to the host end based on the data destination address through the host end.

6. The direct memory access module verification method according to claim 5, characterized in that Performing a data transfer operation in a mode corresponding to the data read / write mode based on the data source address, the data destination address, and the data length, includes: When the data read / write mode is the data write mode, the host side reads data from the main device memory based on the data destination address and the data length, and transfers the read second data to the slave side; The slave side writes the second data into the slave device memory based on the data source address.

7. The direct memory access module verification method according to claim 6, characterized in that Verifying any one of the direct memory access modules based on the data transfer parameters and the operation result in the first transaction, includes: Judging whether the data read / write mode is the data read mode; If the data read / write mode is the data read mode, judging whether the data source address is the data read start address in the operation result and whether the data destination address is the data write start address in the operation result; If the data source address is the data read start address and the data destination address is the data write start address, judging whether the first actual read data and the first actual write data in the operation result are the same; the first actual read data is the data obtained from the slave device memory based on the data source address and the data length; the first actual write data is the data obtained from the main device memory based on the data destination address and the data length; If the first actual read data and the first actual write data are the same, determining that the verification of any one of the direct memory access modules is passed; If the data read / write mode is the data write mode, judging whether the data source address is the data write start address and whether the data destination address is the data read start address; If the data source address is the data write start address and the data destination address is the data read start address, judging whether the second actual read data and the second actual write data in the operation result are the same; the second actual read data is the data obtained from the main device memory based on the data destination address and the data length; the second actual write data is the data obtained from the slave device memory based on the data source address and the data length; If the second actual read data and the second actual write data are the same, determining that the verification of any one of the direct memory access modules is passed.

8. A direct memory access module verification device, characterized in that Applied to a verification platform built based on a unified verification methodology, the verification platform includes a verification component and a design under test for any one of the direct memory access modules in the system on a chip, the design under test includes any one of the direct memory access modules and a bridge connected to any one of the direct memory access modules; The device includes: A transaction conversion module, configured to, after the design under test obtains a first transaction under the advanced extensible interface protocol, use the bridge to convert the data transfer parameters in the first transaction into respective second transactions under the advanced high-performance bus protocol, and transfer the respective second transactions to any one of the direct memory access modules; An operation execution module, configured to perform corresponding data transmission operations based on the respective second transactions through any one of the direct memory access modules, and send the operation results to the verification component; A verification module, configured to obtain the first transaction and the operation results through the verification component, and verify any one of the direct memory access modules based on the respective data transmission parameters in the first transaction and the operation results.

9. An electronic device, characterized in that, Comprising: A memory, configured to store a computer program; A processor, configured to execute the computer program to implement the steps of the direct memory access module verification method according to any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that, A computer program is stored on the computer-readable storage medium, and when the computer program is executed by a processor, the steps of the direct memory access module verification method according to any one of claims 1 to 7 are implemented.

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