Data processing method, electronic equipment and computer readable medium

Abstract

The invention discloses a data processing method, electronic equipment and a computer readable medium, and belongs to the technical field of circuit design, and the method comprises the steps: building a clock tree based on the connection relation of clock pins in a circuit netlist; at least one element pair is determined according to the connection relation of the data pins of the elements in the circuit netlist, the element pair comprises a transmitting trigger and a receiving trigger, and the receiving trigger is used for receiving data sent by the corresponding transmitting trigger; combining a clock pin pair based on the clock pin of each transmitting trigger and the clock pin of the corresponding receiving trigger; traversing from a root node of the clock tree to leaf nodes, and determining a public father node of each clock pin pair; and taking the corresponding clock path from the root node to each common father node as a common clock path of each clock pin pair. The clock pins are prevented from being traversed repeatedly, the consumed time for calculating the common clock path is shortened, and then the speed and efficiency of circuit design are improved.

Description

Technical Field

[0001] This application relates to the field of circuit design technology, and more particularly, to a data processing method, an electronic device, and a computer-readable medium. Background Art

[0002] Traditional static timing analysis in circuit design calculates the worst delay case (max) of the maximum path and the best delay case (min) of the minimum path by using the delay values of circuit components under fixed process, voltage, and temperature conditions and considering on-chip variations.

[0003] For the common part of the launch clock path and the receive clock path, its delay is fixed at the same moment and will not have the situation of maximum delay and minimum delay simultaneously. However, in traditional timing analysis, in order to ensure that the circuit can work properly under various extreme conditions, the worst delay case (max) and the best delay case (min) are considered separately, which will lead to different-direction adjustments of the delay of the common path, resulting in overly pessimistic timing analysis results. For this reason, the concept of Clock Path Pessimism Removal (CPPR) is introduced. By identifying the common part in the clock path and subtracting the delay difference of this part, the overly pessimistic timing analysis results can be eliminated, making the analysis more accurate and reasonable.

[0004] The common part of the launch clock path and the receive clock path is found by traversing the maximum path and the minimum path, but as the scale of the circuit grows, the time consumption brought by this method is huge. Summary of the Invention

[0005] This application proposes a data processing method, an electronic device, and a computer-readable medium to improve the above defects.

[0006] In a first aspect, this application provides a data processing method, which is applied to a processor of an electronic device. The method includes: establishing a clock tree based on the connection relationship of clock pins in a circuit netlist; determining at least one pair of components according to the connection relationship of data pins of components in the circuit netlist, where the pair of components includes a launch flip-flop and a receive flip-flop, and the receive flip-flop is used to receive data sent by the corresponding launch flip-flop; combining the clock pins of each launch flip-flop with the clock pins of the corresponding receive flip-flop to form a pair of clock pins; traversing from the root node of the clock tree to the leaf nodes to determine the common parent node of each pair of clock pins; and taking the clock path from the root node to the corresponding clock path of each common parent node as the common clock path of each pair of clock pins.

[0007] Optionally, for a possible implementation, traversing from the root node of the clock tree to determine the common parent node of each clock pin pair includes: traversing from the root node of the clock tree towards the leaf nodes, and determining whether the current node is marked; if the current node is marked, determining whether the current node is associated with a clock pin pair; in the case where the current node is associated with a clock pin pair, determining whether both of the two clock tree nodes corresponding to the clock pin pair are marked; if both of the two clock tree nodes corresponding to the clock pin pair are marked, determining the current node as the common parent node of the clock pin pair.

[0008] Optionally, for a possible implementation, it further includes: if both of the two clock tree nodes corresponding to the clock pin pair are not marked, determining that the parent node of the current node is associated with the clock pin pair associated with the current node; taking the parent node of the current node as the current node, and returning to execute the operation steps of determining whether the current node is marked and subsequent operations until the current node is marked.

[0009] Optionally, for a possible implementation, it further includes: if the current node is not marked, and in the case where the current node is not a leaf node, taking the unmarked child node of the current node as the new current node, and returning to execute the operation steps of determining whether the current node is marked and subsequent operations until the current node is marked.

[0010] Optionally, for a possible implementation, before determining whether the current node is marked, it further includes: if the clock pin corresponding to the first node in the clock tree is the same as one of the clock pins in a clock pin pair, and the clock pin corresponding to the second node in the clock tree is the same as the other clock pin in the clock pin pair, determining that the first node or the second node is associated with the clock pin pair.

[0011] Optionally, for a possible implementation, before determining whether the current node is marked, it further includes: in the case where the current node is a leaf node, determining that the current node is marked.

[0012] Optionally, for a possible implementation, it further includes: in the case where the current node is not a leaf node, determining whether all of the child nodes of the current node are marked; if all of the child nodes of the current node are marked, determining that the current node is marked; if all of the child nodes of the current node are not marked, determining that the current node is not marked.

[0013] Optionally, for a possible implementation manner, establishing a clock tree based on the connection relationship of clock pins in a circuit netlist includes: traversing starting from the clock pin of a clock source based on the connection relationship of clock pins in the circuit netlist, and using the clock pin of the clock source as the root node of the clock tree; when the fan-out number of the current clock pin is greater than 1, determining that the current clock pin is a node of the clock tree, and using the previous-level clock pin connected to the current clock pin as the parent node of the node; when the fan-out number of the current clock pin is 0, determining that the current clock pin is a leaf node of the clock tree, and using the previous-level clock pin connected to the current clock pin as the parent node of the leaf node.

[0014] Optionally, for a possible implementation manner, after using the clock path from the root node to the corresponding common parent node of each clock pin pair as the common clock path of each clock pin pair, it further includes: obtaining the maximum delay and the minimum delay corresponding to the common clock path of each clock pin pair; determining the common pessimistic value corresponding to each clock pin pair based on the maximum delay and the minimum delay corresponding to each clock pin pair.

[0015] In a second aspect, the present application further provides an electronic device, including: one or more processors; a memory; one or more application programs, where the one or more application programs are stored in the memory, the one or more application programs are configured to be executed by the one or more processors, and the one or more application programs are configured to execute the above method.

[0016] In a third aspect, the present application further provides a computer-readable medium, where the readable storage medium stores program code executable by a processor, and when the program code is executed by the processor, the processor executes the above method.

[0017] The embodiment of the present application provides a data processing method. First, a clock tree is established based on the connection relationship of clock pins in a circuit netlist; at least one element pair is determined according to the connection relationship of data pins of elements in the circuit netlist, the element pair includes a transmitting flip-flop and a receiving flip-flop, and the receiving flip-flop is used to receive data sent by the corresponding transmitting flip-flop; secondly, a clock pin pair is formed based on the clock pin of each transmitting flip-flop and the clock pin of the corresponding receiving flip-flop; then, traversing from the root node of the clock tree to the leaf node, the common parent node of each clock pin pair is determined; finally, the clock path from the root node to the corresponding common parent node of each clock pin pair is used as the common clock path of each clock pin pair.

[0018] It can be known that each clock path is obtained by traversing from each leaf node to the root node, and then the common clock path is determined based on the clock pin pairs and each clock path obtained by traversing. Some clock nodes are traversed multiple times. When the circuit scale increases, more clock nodes will be traversed repeatedly, and this method takes a long time to calculate the common clock path. In this application, by traversing from the root node of the clock data to the leaf node, the common clock path of the clock pin pairs is obtained, avoiding repeated traversal of the clock pins, reducing the time-consuming for calculating the common clock path, and thus improving the speed and efficiency of circuit design.

[0019] Other features and advantages of this application will be described in the subsequent specification, and partly will be obvious from the specification, or will be understood by implementing this application. The objectives and other advantages of this application can be achieved and obtained through the structures specifically pointed out in the written specification, claims, and drawings. Brief Description of the Drawings

[0020] To more clearly illustrate the technical solutions in the embodiments of this application, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the following drawings are only some embodiments of this application. For those skilled in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0021] Figure 1 Shows the flowchart of the data processing method provided by the embodiment of this application;

[0022] Figure 2 Shows the schematic diagram of circuit connection provided by the embodiment of this application;

[0023] Figure 3 Shows Figure 2 the transmission schematic diagram of the clock signal;

[0024] Figure 4 Shows the structural diagram of the clock tree provided by the embodiment of this application;

[0025] Figure 5 Shows the flowchart of the data processing method provided by another embodiment of this application;

[0026] Figure 6 Shows the structural diagram of the clock tree provided by another embodiment of this application;

[0027] Figure 7 Shows the structural diagram of the clock tree provided by another embodiment of this application;

[0028] Figure 8 Shows the structural diagram of the clock tree provided by another embodiment of this application;

[0029] Figure 9 The block diagram of the electronic device provided by the embodiment of the present application is shown;

[0030] Figure 10 The block diagram of the computer-readable storage medium provided by the embodiment of the present application is shown. Specific embodiments

[0031] In order to enable those skilled in the art to better understand the solution of the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Usually, the components of the embodiments of the present application described and shown in the accompanying drawings here can be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the present application to be protected, but only represents the selected embodiments of the present application. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without creative efforts belong to the scope of protection of the present application.

[0032] It should be noted that similar reference numerals and letters indicate similar items in the following drawings. Therefore, once an item is defined in one drawing, it does not need to be further defined and explained in subsequent drawings. At the same time, in the description of the present application, the terms "first", "second", etc. are only used for distinguishing descriptions and cannot be understood as indicating or implying relative importance.

[0033] Traditional static timing analysis of circuit design uses the delay values of circuit components under fixed process, voltage, and temperature conditions, and considers on-chip variations to calculate the worst delay case (max) of the maximum path and the best delay case (min) of the minimum path.

[0034] For the common part of the transmit clock path and the receive clock path, its delay is fixed at the same moment and the maximum delay and the minimum delay do not occur simultaneously. However, in traditional timing analysis, in order to ensure that the circuit can work properly under various extreme conditions, the worst delay case (max) and the best delay case (min) are considered separately, which will cause different-direction adjustments to the delay of the common path, resulting in overly pessimistic timing analysis results. For this reason, the concept of Clock Path Pessimism Removal (CPPR) is introduced. By identifying the common part in the clock path and subtracting the delay difference of this part, the overly pessimistic timing analysis results can be eliminated, making the analysis more accurate and reasonable.

[0035] The common part of the transmission clock path and the reception clock path is found by traversing the maximum path and the minimum path. However, as the scale of the circuit grows, the time consumption brought by this method is huge.

[0036] Therefore, in the embodiments of the present application, a data processing method, an electronic device, and a computer-readable medium are provided to solve or partially solve the above problems.

[0037] Please refer to Figure 1 , which shows a flowchart of a data processing method provided by an embodiment of the present application. This method is applied to the processor of an electronic device and specifically includes steps S101 to S105.

[0038] Step S101: Establish a clock tree based on the connection relationship of clock pins in the circuit netlist.

[0039] It should be noted that the circuit netlist is a description form in circuit design, which includes various components in the circuit and the connection relationships between the components. The components include but are not limited to clock sources, flip-flops, transistors, resistors, capacitors, etc. The connection relationships between the components include the connection relationships of data pins, the connection relationships of clock pins, and the connection relationships of other pins. Among them, one pin of a component can be connected to the pins of at least one component. When a pin is simultaneously connected to the pins of multiple components, the pin will fan out multiple pins.

[0040] The clock pin represents a pin for transmitting a clock signal, and the connection relationship of the clock pins can represent the transmission path of the clock signal. The data path represents a pin for transmitting data, and the connection relationship of the data pins can represent the transmission path of the data signal.

[0041] In an alternative embodiment, establishing a clock tree based on the connection relationship of clock pins in the circuit netlist can specifically be: starting from the clock pin of the clock source and traversing based on the connection relationship of clock pins in the circuit netlist, using the clock pin of the clock source as the root node of the clock tree; when the fan-out number of the current clock pin is greater than 1, determining that the current clock pin is a node of the clock tree, and using the previous-level clock pin connected to the current clock pin as the parent node of the node; when the fan-out number of the current clock pin is 0, determining that the current clock pin is a leaf node of the clock tree, and using the previous-level clock pin connected to the current clock pin as the parent node of the leaf node.

[0042] Please refer to Figure 2, which shows a circuit corresponding to a circuit netlist. Here, Data represents the input data, Clock represents the clock signal generated by the clock source, FF1, FF2, FF3, and FF4 are all flip-flops, SET represents set. When the SET signal is triggered, the flip-flop is set, and the output Q of the flip-flop is set to 1. CLR represents clear. When the CLR signal is triggered, the flip-flop is cleared, and the output Q of the flip-flop is set to 0. The flip-flop can be a D flip-flop, JK flip-flop, T flip-flop, SR flip-flop, etc. The specific type of the flip-flop is not limited here.

[0043] Please refer to Figure 3 , which shows Figure 2 the connection relationship of the corresponding clock pins. The circles in the path of the clock transmission signal represent the clock pins. According to Figure 3 , it can be known that it includes clock pins a, b, c, d, e, f, g, h. a:0 means that clock pin a is the clock pin of the clock source, and the maximum and minimum delay difference of clock pin a is 0. (42, 50) means that the minimum delay of the clock signal of the clock source to clock pin b is 42ms, and the maximum delay of the clock signal of the clock source to clock pin b is 50ms. b:8 means that the maximum and minimum delay difference of the clock signal of the clock source to clock pin b is 8ms. (82, 93) means that the minimum delay of the clock signal of the clock source to clock pin c is 82ms, and the maximum delay of the clock signal of the clock source to clock pin c is 93ms. c:11 means that the maximum and minimum delay difference of the clock signal of the clock source to clock pin c is 11ms. Similarly, d:21 means that the maximum and minimum delay difference of the clock signal of the clock source to clock pin d is 21ms. Based on Figure 3 the connection relationship of the clock pins in, the clock tree structure obtained is as Figure 4 shown.

[0044] Exemplarily, a is the clock pin of the clock source. Taking the clock pin a of the clock source as the root node a of the clock tree, traversing to clock pin b according to the connection relationship of the clock pins, taking clock pin b as the current clock pin. From Figure 3 , it can be known that the fan-out number of clock pin b is greater than 1. Determine that clock pin b is the node b of the clock tree, and take node a as the parent node of node b. Then traverse to clock pin c, take clock pin c as the current clock pin. The fan-out number of clock pin c is greater than 1. Determine that clock pin c is the node c of the clock tree, and take node b as the parent node of node c. Then traverse to clock pin e, take clock pin e as the current clock pin. The fan-out number of clock pin e is 0. Determine that clock pin e is the leaf node e of the clock tree, and take node c as the parent node of the leaf node e. Similarly, all the clock pins in Figure 3 can be traversed to obtain Figure 4 the clock tree shown.

[0045] Step S102: Determine at least one pair of components according to the connection relationship of the data pins of the components in the circuit netlist. The pair of components includes a transmitting flip-flop and a receiving flip-flop, and the receiving flip-flop is used to receive the data sent by the corresponding transmitting flip-flop.

[0046] It should be noted that during the data transmission process, the transmitting flip-flop is used to send data, and the receiving flip-flop is used to receive the data sent by the corresponding transmitting flip-flop. At least one pair of components can be determined based on the connection relationship of the data pins of the components in the circuit netlist. It can be understood that the transmitting flip-flop needs to be triggered by a clock signal to send data, and the receiving flip-flop needs to be triggered by a clock signal to receive data. Therefore, two clock signals are required to complete the data transmission. The clock path from the clock source to the transmitting flip-flop is the trigger clock path, and the clock path from the clock source to the receiving flip-flop is the receiving clock path. The common part of the trigger clock path and the receiving clock path is the common clock path.

[0047] It can be understood that there is data transmission between multiple components in the circuit diagram corresponding to the circuit netlist. Therefore, at least one pair of components can be determined, and the receiving flip-flop in each pair of components is used to receive the data sent by the transmitting flip-flop in the pair.

[0048] Exemplarily, please refer to Figure 3 , the data output pin of FF1 is connected to the data input pin of FF2, then it is determined that FF1 and FF2 are a pair of components, where FF1 is the transmitting flip-flop and FF2 is the receiving flip-flop. Similarly, it is determined that FF1 and FF3 are a pair of components, and it is determined that FF3 and FF4 are a pair of components. Therefore, based on Figure 3 the circuit in, 3 pairs of components can be determined.

[0049] Step S103: Combine the clock pins of each transmitting flip-flop with the corresponding clock pins of the receiving flip-flop to form a pair of clock pins.

[0050] It should be noted that the transmitting flip-flop and the receiving flip-flop in each pair of components correspond to each other. The clock pin of the transmitting flip-flop represents the pin for receiving the clock signal, and the clock pin of the receiving flip-flop represents the pin for receiving the clock signal. Based on the clock pins of each transmitting flip-flop and the corresponding clock pins of the receiving flip-flop, a pair of clock pins is formed.

[0051] Exemplarily, continuing with the foregoing embodiment for introduction, FF1 and FF2 form a pair of components, FF1 and FF3 form a pair of components, and FF3 and FF4 form a pair of components. Taking FF1 and FF2 as a pair of components as an example, the clock pin e of FF1 and the clock pin f of FF2 are combined into a clock pin pair (e, f). Similarly, according to FF1 and FF3 being a pair of components, the corresponding clock pin pair (e, g) is obtained, and according to FF3 and FF4 being a pair of components, the corresponding clock pin pair (g, h) is obtained. If the clock pin pairs (e, f) and (e, g) are associated with the leaf node e, then the clock pin pairs corresponding to the leaf node e include (e, f) and (e, g), as shown in Figure 4 e in: {(e, f), (e, g)}. If the clock pin pair (g, h) is associated with the leaf node g, then the clock pin pairs corresponding to the leaf node g include (g, h), as shown in Figure 4 e in: {(g, h)}.

[0052] Step S104: Traverse from the root node of the clock tree to the leaf nodes to determine the common parent node of each of the clock pin pairs.

[0053] It should be noted that the obtained clock tree structure includes a root node, nodes, and leaf nodes. Traverse from the root node of the clock tree to the leaf nodes to determine the common parent node of each clock tree pin pair.

[0054] Specifically, traverse from the root node of the clock tree to the leaf nodes, and determine whether the current node is marked; if the current node is marked, determine whether the current node is associated with a clock pin pair; in the case where the current node is associated with a clock pin pair, determine whether both of the two clock tree nodes corresponding to the clock pin pair are marked; if both of the two clock tree nodes corresponding to the clock pin pair are marked, then determine that the current node is the common parent node of the clock pin pair. For detailed content, please refer to the subsequent embodiments.

[0055] Step S105: Use the clock path from the root node to the corresponding clock path of each common parent node as the common clock path of each clock pin pair.

[0056] It should be noted that the common parent node represents the common clock pin of the transmitting clock path and the receiving clock path, and the clock path from the clock source to the corresponding clock path of the common parent node is the common clock path of the clock pin pair.

[0057] An embodiment of the present application proposes a data processing method. First, a clock tree is established based on the connection relationship of clock pins in a circuit netlist; at least one component pair is determined according to the connection relationship of data pins of components in the circuit netlist, the component pair includes a transmitting flip-flop and a receiving flip-flop, and the receiving flip-flop is used to receive data sent by the corresponding transmitting flip-flop; secondly, based on the clock pin of each transmitting flip-flop and the clock pin of the corresponding receiving flip-flop, a clock pin pair is formed; then, starting from the root node of the clock tree, traversing towards the leaf nodes, and determining the common parent node of each clock pin pair; finally, the clock path from the root node to the corresponding common parent node of each clock pin pair is used as the common clock path of each clock pin pair.

[0058] It can be known that by traversing from each leaf node to the root node to obtain each clock path, and then determining the common clock path based on the clock pin pair and each clock path obtained by traversing, some clock nodes are traversed multiple times. When the circuit scale increases, more clock nodes will be repeatedly traversed, and this method takes more time to calculate the common clock path. In the present application, by traversing from the root node of the clock data to the leaf nodes to obtain the common clock path of the clock pin pair, the repeatedly traversed clock pins are avoided, the time consumed for calculating the common clock path is reduced, and thus the speed and efficiency of circuit design are improved.

[0059] Please refer to Figure 5 , which shows a flowchart of a data processing method provided by an embodiment of the present application. This method is applied to a processor of an electronic device and specifically includes steps S201 to S210.

[0060] Step S201: Establish a clock tree based on the connection relationship of clock pins in a circuit netlist.

[0061] Step S202: Determine at least one component pair according to the connection relationship of data pins of components in the circuit netlist, the component pair includes a transmitting flip-flop and a receiving flip-flop, and the receiving flip-flop is used to receive data sent by the corresponding transmitting flip-flop.

[0062] Step S203: Based on the clock pin of each transmitting flip-flop and the clock pin of the corresponding receiving flip-flop, form a clock pin pair.

[0063] Among them, steps S201 to S203 have been introduced in detail in the foregoing embodiments and will not be elaborated here.

[0064] Step S204: Starting from the root node of the clock tree, traverse towards the leaf nodes and determine whether the current node is marked.

[0065] It should be noted that when traversing from the root node of the clock tree to the leaf nodes, after the current node is marked, the common parent node of the clock pin pair needs to be further determined. For this purpose, it is necessary to determine whether the current node is marked.

[0066] Step S205: If the current node is marked, determine whether the current node is associated with a clock pin pair.

[0067] If the current node is marked, it means that the traversal of the current node is completed, and then it is determined whether the current node is associated with a clock pin pair.

[0068] It should be noted that a clock pin pair refers to the clock pin of the transmitting flip-flop and the clock pin of the receiving flip-flop in the component pair. Not every node is associated with a clock pin pair. Therefore, when the current node is marked, it is necessary to determine whether the current node is associated with a clock pin pair.

[0069] It should be noted that if the current node is not associated with a clock pin pair, the parent node of the current node is taken as the current node, and the operation steps of determining whether the current node is marked and subsequent operations are returned until the common parent node of each clock pin pair is determined.

[0070] In one embodiment, if the clock pin corresponding to the first node in the clock tree is the same as one of the clock pins in a clock pin pair, and the clock pin corresponding to the second node in the clock tree is the same as the other clock pin in the clock pin pair, then it is determined that the first node or the second node is associated with the clock pin pair.

[0071] Exemplarily, continuing with the previous embodiment, according to FF1 and FF2 being a component pair to obtain the corresponding clock pin pair (e, f), then it is determined that the leaf node e or the leaf node f in the clock tree is associated with the clock pin pair (e, f).

[0072] As Figure 4 shown, it means that the clock pin pair (e, f) is associated with the leaf node e, the clock pin pair (e, g) is associated with the leaf node e, and the clock pin pair (g, h) is associated with the leaf node g.

[0073] Step S206: When the current node is associated with a clock pin pair, determine whether both of the two clock tree nodes corresponding to the clock pin pair are marked.

[0074] It should be noted that the two clock tree nodes corresponding to the clock pin pair refer to the clock tree node corresponding to the clock pin of the transmitting flip-flop of the component pair and the clock tree node corresponding to the clock pin of the receiving flip-flop. If the current node is associated with a clock pin pair, it is determined whether both of the clock tree nodes corresponding to the clock pin are marked.

[0075] Step S207: If both of the two clock tree nodes corresponding to the clock pin pair are marked, determine that the current node is the common parent node of the clock pin pair.

[0076] It should be noted that both of the two clock tree nodes corresponding to the clock pin pair being marked means that the traversal of the two clock tree nodes corresponding to the clock pin pair is completed, and then determine that the current node is the common parent node of the clock pin pair.

[0077] Step S208: If the two clock tree nodes corresponding to the clock pin pair are not both marked, determine that the parent node of the current node is associated with the clock pin pair associated with the current node.

[0078] If the two clock tree nodes corresponding to the clock pin pair are not both marked, it means that the common parent node of the clock pin pair cannot be determined yet, and determine that the parent node of the current node is associated with the clock pin pair associated with the current node.

[0079] Step S209: Take the parent node of the current node as the current node, and return to execute the operation steps of judging whether the current node is marked and subsequent operations until the current node is marked.

[0080] Take the parent node of the current node as the current node, and return to execute the operation steps of judging whether the current node is marked and subsequent operations until the current node is marked.

[0081] As an alternative embodiment, if the current node is not marked and the current node is not a leaf node, then take the unmarked child node of the current node as the new current node, and return to execute the operation steps of judging whether the current node is marked and subsequent operations until the current node is marked.

[0082] It should be noted that if the current node is not marked, it means that the current node has not been fully traversed. If the current node is a leaf node, then determine that the current node is marked. If the current node is not a leaf node, it means that the child nodes of the current node have not been fully marked, so take the unmarked child node of the current node as the new current node, and return to execute the operation steps of judging whether the current node is marked and subsequent operation steps until the current node is marked.

[0083] Step S210: Take the clock path from the root node to the clock path corresponding to each common parent node as the common clock path of each clock pin pair.

[0084] Among them, Step S210 has been introduced in detail in the foregoing embodiments and will not be elaborated here.

[0085] In an alternative embodiment, before determining whether the current node is marked, steps S2041 to S2044 are further included.

[0086] Step S2041: In the case where the current node is a leaf node, it is determined that the current node is marked.

[0087] It should be noted that when traversing to the current node and the current node is a leaf node, it is determined that the current node is marked.

[0088] Step S2042: In the case where the current node is not a leaf node, it is judged whether all the child nodes of the current node are marked.

[0089] When traversing to the current node and the current node is not a leaf node, it means that the current node includes child nodes, and it is necessary to judge whether all the child nodes of the current node are marked.

[0090] Step S2043: If all the child nodes of the current node are marked, it is determined that the current node is marked.

[0091] If all the child nodes of the current node are marked, it is determined that the current node is marked.

[0092] Step S2044: If not all the child nodes of the current node are marked, it is determined that the current node is not marked.

[0093] If not all the child nodes of the current node are marked, it is determined that the current node is not marked.

[0094] An example is given. Refer to Figure 6 , if the current node is the leaf node e, it is determined that the current node is marked. If the current node is the node c, it is judged whether all the child nodes of the current node are marked. If both the leaf node e and the leaf node f are marked, it is determined that the current node is marked. If the leaf node e and the leaf node f are not both marked, it means that the child nodes of the current node have not been fully traversed, and it is determined that the current node is not marked.

[0095] In an alternative embodiment, in step S105: after using the clock paths from the root node to each corresponding common parent node as the common clock paths for each clock pin pair, steps S1051 to S1052 are further included.

[0096] Step S1051: Obtain the maximum delay and the minimum delay corresponding to the common clock path of each clock pin pair.

[0097] It should be noted that when traversing from the clock pin of the clock source to obtain the clock tree based on the connection relationship of the clock pins in the circuit netlist, the maximum delay (max) and minimum delay (min) of the clock signal sent by the clock source reaching each clock pin are recorded during this process. Therefore, the maximum delay and minimum delay corresponding to the common clock path of each clock pin pair can be obtained from the stored data.

[0098] Step S1052: Determine the common pessimistic value corresponding to each clock pin pair based on the maximum delay and minimum delay corresponding to each clock pin pair.

[0099] Subtract the minimum delay from the maximum delay corresponding to each clock pin pair to obtain the common pessimistic value corresponding to each clock pin pair.

[0100] It should be noted that in actual work, it is required that the transmitted data arrives at the receiving flip-flop before the clock signal. Therefore, the sum of the delay θ1 from the source clock signal to the transmitting flip-flop and the delay D from the transmitting flip-flop to the receiving flip-flop should be less than the delay θ2 from the source clock signal to the transmitting flip-flop. Therefore, it is necessary to determine the common clock path of the clock path of the transmitting flip-flop and the clock path of the receiving flip-flop corresponding to this data path. After determining the common pessimistic value S of the common clock path, add the common pessimistic value S to θ2 as the new delay value of the source clock signal to the transmitting flip-flop. It can eliminate overly pessimistic timing analysis results, making the analysis more accurate and reasonable. It can avoid unnecessary design margins, improve the circuit performance while ensuring the correctness of timing.

[0101] An exemplary one, please refer to Figure 5 , the initial state is that the clock pin pairs (e, f), (e, g) are associated with the leaf node e, and the clock pin pair (g, h) is associated with the leaf node g. Traverse from the root node a of the clock tree to the leaf node. Take the root node a as the current node. If it is determined that the current node is not marked, then take the child node b of the root node a as the current node. If it is determined that the current node is not marked, then take the child node c of the node b as the current node. If it is determined that the current node is not marked, then take the child node e of the node c as the current node. Since the current node is the leaf node e, it is determined that the current node is marked. The current node is associated with the clock pin pairs (e, f), (e, g). If it is determined that the 2 clock tree nodes corresponding to the clock pin pairs associated with the current node are not both marked, then set the clock pin pairs (e, f), (e, g) to be associated with the node c. Take the node c as the current node. If it is determined that the current node is not marked, then take the leaf node f as the current node. Since the current node is the leaf node f, it is determined that the current node is marked. Please refer to Figure 6, the gray nodes indicate being marked. If it is determined that the current node is not associated with the clock pin pair, then node c is taken as the current node. If it is determined that the current node is marked, then it is determined that the current node is associated with the clock pin pairs (e, f) and (e, g), and both of the two clock tree nodes corresponding to the clock pin pair (e, f) are marked, then it is determined that the current node c is the common parent node of the clock pin pair (e, f), and the clock pin pair (e, g) is set to be associated with node b. Please refer to Figure 7 , the gray nodes indicate being marked. Node b is taken as the current node. If it is determined that the current node is not marked, then node d is taken as the current node. If it is determined that the current node is not marked, then node g is taken as the current node. If it is determined that the current node is marked, and it is determined that not both of the two clock tree pins corresponding to the clock pin pair (g, h) associated with the current node g are marked, then the clock pin pair (g, h) is set to be associated with node d. Taking node d as the current node, if it is determined that the current node is not marked, then node h is taken as the current node. If it is determined that the current node is marked, and the current node is not associated with the clock pin pair, then node d is taken as the current node. If the current node is marked, then it is determined that both of the two clock tree pins corresponding to the clock pin pair (g, h) associated with the current node are marked, then it is determined that node d is the common parent node of the clock pin pair (g, h). Taking node b as the current node, if the current node is marked, and it is determined that both of the two clock tree pins corresponding to the clock pin pair (e, g) associated with the current node are marked. Please refer to Figure 8 , the gray nodes indicate being marked. It is determined that node b is the common parent node of the clock pin pair (e, g).

[0102] The data processing method of the present application traverses from the root node of the clock tree to the leaf nodes. When all the nodes of the clock tree are traversed, the common parent node of each clock pin pair can be obtained. Compared with traversing starting from the leaf nodes, some clock nodes are traversed multiple times. In the present application, each node only needs to be traversed once, which greatly reduces the time for determining the common parent node, thereby reducing the time-consuming for calculating the common clock path, and further improving the speed and efficiency of circuit design.

[0103] Please refer to Figure 9 , which shows a structural block diagram of an electronic device 700 provided by an embodiment of the present application. The electronic device 700 can be a vehicle-mounted system, and this vehicle-mounted system can be set in a vehicle. The electronic device 700 in the present application can include one or more of the following components: a processor 711, a memory 712, and one or more application programs, where the processor 711 is electrically connected to the memory 712, and one or more programs are configured to execute the methods described in the respective embodiments of the foregoing test methods.

[0104] The processor 711 may include one or more processing cores. The processor 711 connects various parts within the entire electronic device 700 using various interfaces and lines, and executes various functions of the electronic device 700 and processes data by running or executing instructions, programs, code sets, or instruction sets stored in the memory 712, and by calling data stored in the memory 712. Optionally, the processor 711 may be implemented in at least one hardware form of digital signal processing (DSP), field-programmable gate array (FPGA), or programmable logic array (PLA). The processor 711 may integrate a combination of one or more of a central processing unit (CPU), a graphics processing unit (GPU), and a modem, etc. Among them, the CPU mainly processes the operating system, user interface, computer programs, etc.; the GPU is responsible for rendering and drawing display content; the modem is used to process wireless communication. It can be understood that the above-mentioned modem may not be integrated into the processor 711 and may be implemented separately through a communication chip. Specifically, the method described in the foregoing embodiments may be executed by one or more processors 711.

[0105] For some embodiments, the memory 712 may include random access memory (RAM) and may also include read-only memory. The memory 712 can be used to store instructions, programs, code, code sets, or instruction sets. The memory 712 may include a program storage area and a data storage area. Among them, the program storage area may store instructions for implementing the operating system, instructions for implementing at least one function, instructions for implementing the following various method embodiments, etc. The data storage area may also store data created during the use of the electronic device 700.

[0106] Please refer to Figure 10 , which shows a structural block diagram of a computer-readable medium provided by an embodiment of the present application. Program code is stored in the computer-readable medium 800, and the program code can be called by the processor to execute the method described in the above method embodiments.

[0107] The computer-readable medium 800 can be an electronic memory such as a flash memory, an EEPROM (electrically erasable programmable read-only memory), an EPROM, a hard disk, or a ROM. Optionally, the computer-readable medium 800 includes a non-transitory computer-readable storage medium. The computer-readable medium 800 has a storage space for the program code 810 that executes any of the method steps in the above-described methods. These program codes can be read from or written into one or more computer program products. The program code 810 can be compressed in an appropriate form, for example.

[0108] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, and not to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements for some of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A data processing method, characterized in that A processor applied to an electronic device, the method comprising: Establishing a clock tree based on the connection relationship of clock pins in a circuit netlist; Determining at least one pair of components according to the connection relationship of data pins of components in the circuit netlist, the pair of components including a transmitting flip-flop and a receiving flip-flop, and the receiving flip-flop is used to receive data sent by the corresponding transmitting flip-flop; Combining the clock pins of each transmitting flip-flop with the clock pins of the corresponding receiving flip-flop to form a pair of clock pins; Traversing from the root node of the clock tree to the leaf nodes to determine the common parent node of each pair of clock pins; Taking the clock path from the root node to the corresponding common parent node of each pair of clock pins as the common clock path of each pair of clock pins.

2. The method according to claim 1, wherein The traversing from the root node of the clock tree to determine the common parent node of each pair of clock pins includes: Traversing from the root node of the clock tree to the leaf nodes, and determining whether the current node is marked; If the current node is marked, determining whether the current node is associated with a pair of clock pins; In the case where the current node is associated with a pair of clock pins, determining whether both of the two clock tree nodes corresponding to the pair of clock pins are marked; If both of the two clock tree nodes corresponding to the pair of clock pins are marked, determining the current node as the common parent node of the pair of clock pins.

3. The method according to claim 2, wherein Further comprising: If both of the two clock tree nodes corresponding to the pair of clock pins are not marked, determining that the parent node of the current node is associated with the pair of clock pins associated with the current node; Taking the parent node of the current node as the current node, and returning to execute the operation steps of determining whether the current node is marked and subsequent operations until the current node is marked.

4. The method according to claim 2, characterized in that Further comprising: If the current node is not marked and the current node is not a leaf node, taking the unmarked child node of the current node as the new current node, and returning to execute the operation steps of determining whether the current node is marked and subsequent operations until the current node is marked.

5. The method according to claim 2, wherein Before determining whether the current node is marked, further comprising: If the clock pin corresponding to the first node in the clock tree is the same as one of the clock pins in a pair of clock pins, and the clock pin corresponding to the second node in the clock tree is the same as the other clock pin in the pair of clock pins, determining that the first node or the second node is associated with the pair of clock pins.

6. The method according to claim 2, wherein Before determining whether the current node is marked, further comprising: In the case where the current node is a leaf node, determining that the current node is marked.

7. The method according to claim 6, characterized in that, Further comprising: In the case where the current node is not a leaf node, determining whether all child nodes of the current node are marked; If all child nodes of the current node are marked, determining that the current node is marked; If all child nodes of the current node are not marked, determining that the current node is not marked.

8. The method according to claim 1, wherein The establishing a clock tree based on the connection relationship of clock pins in a circuit netlist includes: Traversing from the clock pin of the clock source based on the connection relationship of clock pins in the circuit netlist, and taking the clock pin of the clock source as the root node of the clock tree; When the fan-out number of the current clock pin is greater than 1, determine that the current clock pin is a node of the clock tree, and use the previous-level clock pin connected to the current clock pin as the parent node of the node; When the fan-out number of the current clock pin is 0, determine that the current clock pin is a leaf node of the clock tree, and use the previous-level clock pin connected to the current clock pin as the parent node of the leaf node.

9. The method according to claim 1, wherein After using the clock paths from the root node to the corresponding common parent nodes as the common clock paths for each clock pin pair, the method further includes: Obtaining the maximum delay and the minimum delay corresponding to the common clock path of each clock pin pair; Determining the corresponding common pessimistic value for each clock pin pair based on the maximum delay and the minimum delay corresponding to each clock pin pair.

10. An electronic device, characterized in that, Comprising: One or more processors; A memory; One or more applications, wherein the one or more applications are stored in the memory, the one or more applications are configured to be executed by the one or more processors, and the one or more applications are configured to execute the method according to any one of claims 1-9.

11. A computer-readable storage medium, characterized in that, Program code is stored in the computer-readable storage medium, and the program code can be called by a processor to execute the method according to any one of claims 1-9.

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