Quantum processing unit, manufacturing method thereof and quantum computer

Abstract

The invention discloses a quantum processing unit and a manufacturing method thereof and a quantum computer, and belongs to the technical field of quantum computers, the quantum processing unit comprises a circuit board and an ion trap chip, the circuit board is provided with a chip mounting through hole, the circuit board is provided with a first circuit surface and a second circuit surface which are opposite in the thickness direction of the circuit board, the first circuit surface is provided with a first bonding terminal, the second circuit surface is provided with a second bonding terminal, the ion trap chip is provided with a first chip surface and a second chip surface which are opposite to each other in the thickness direction of the ion trap chip, the first chip surface is provided with a first electrode, the second circuit surface is provided with a second electrode, and the ion trap chip is fixedly arranged in a chip mounting through hole of the circuit board. The circuit board and the ion trap chip can realize double-sided bonding connection, so that the number of electrical connections established between the circuit board and the ion trap chip is increased, the single-sided bonding density is reduced, and the bonding difficulty of the circuit board and the ion trap chip is reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of quantum computers, and in particular, to a quantum processing unit, a manufacturing method thereof, and a quantum computer. Background Art

[0002] A quantum bit (qubit) is the basic unit of quantum computing. The increase in its quantity can significantly improve the computing power of the quantum processing unit. With the increase in the number of qubits, more requirements are put forward for the ion trap chip in the quantum processing unit. Currently, an ion trap chip with a smaller size and more extraction electrodes is needed.

[0003] However, with the increase in the number of extraction electrodes on the ion trap chip, the arrangement of the extraction electrodes will be too dense, making it difficult for the extraction electrodes of the ion trap chip to be bonded to the circuit board carrying it. Summary of the Invention

[0004] The present invention aims to at least partly solve one of the above technical problems in the prior art. To this end, the present invention provides a quantum processing unit, which can reduce the bonding difficulty between the circuit board and the ion trap chip.

[0005] The present invention also provides a manufacturing method of a quantum processing unit.

[0006] The present invention also provides a quantum computer having the above quantum processing unit.

[0007] The quantum processing unit according to an embodiment of the present invention includes: a circuit board, the circuit board is provided with a chip mounting through hole, the circuit board has a first circuit surface and a second circuit surface opposite to each other in its thickness direction, the first circuit surface has a first bonding terminal, and the second circuit surface has a second bonding terminal; an ion trap chip, the ion trap chip is fixed in the chip mounting through hole, the ion trap chip has a first chip surface and a second chip surface opposite to each other in its thickness direction, the first chip surface has a first electrode, and the second circuit surface has a second electrode; wherein, the first circuit surface and the first chip surface face the same direction, and the first electrode is bonded to the first bonding terminal, the second circuit surface and the second chip surface face the same direction, and the second electrode is bonded to the second bonding terminal.

[0008] According to the quantum processing unit of the embodiment of the present invention, the ion trap chip is fixed in the chip mounting through hole of the circuit board, and the circuit board and the ion trap chip can be bonded and connected on both sides, which is beneficial to increasing the number of electrical connections established between the circuit board and the ion trap chip, and can also disperse the electrical connections between the circuit board and the ion trap chip on different sides to reduce the bonding density on one side and reduce the bonding difficulty between the circuit board and the ion trap chip.

[0009] According to some embodiments of the present invention, in the thickness direction of the ion trap chip, the first electrode and the second electrode are arranged staggeredly, and the first bonding terminal and the second bonding terminal are arranged staggeredly.

[0010] According to some embodiments of the present invention, the number of the first electrodes and the first bonding terminals is multiple and they are bonded to each other in one-to-one correspondence, and the number of the second electrodes and the second bonding terminals is multiple and they are bonded to each other in one-to-one correspondence.

[0011] According to some embodiments of the present invention, in the width direction of the ion trap chip, at least one of the first electrodes is provided at both ends of the first chip surface, and the first bonding terminal is adjacent to the corresponding first electrode; in the length direction of the ion trap chip, at least one of the second electrodes is provided at both ends of the second chip surface, and the second bonding terminal is adjacent to the corresponding second electrode.

[0012] According to some embodiments of the present invention, the circuit board has a filter circuit and signal extraction terminals, and the first bonding terminal and the second bonding terminal are both connected to the signal extraction terminals through the filter circuit.

[0013] According to some embodiments of the present invention, a bearing protrusion is formed on the hole wall of the chip mounting through hole, and the ion trap chip is fixedly connected to the bearing protrusion through a fastener.

[0014] According to some embodiments of the present invention, the quantum processing unit further includes: a first encapsulation board opposite to the first circuit surface, the first encapsulation board is provided with a first operation through hole, and the first encapsulation board has a first support portion; a second encapsulation board opposite to the second circuit surface, the second encapsulation board is provided with a second operation through hole, and the second encapsulation board has a second support portion; wherein, in the thickness direction of the circuit board: the first encapsulation board and the second encapsulation board are clamped on both sides of the circuit board; the first operation through hole corresponds to the first bonding terminal and also corresponds to the first electrode; the second operation through hole corresponds to the second bonding terminal and also corresponds to the second electrode; the first support portion abuts against the area of the first chip surface corresponding to the second electrode, and / or, the first support portion abuts against the area of the first circuit surface corresponding to the second electrode; the second support portion abuts against the area of the second chip surface corresponding to the first electrode, and / or, the second support portion abuts against the area of the second circuit surface corresponding to the first electrode.

[0015] According to some embodiments of the present invention, the outer surfaces of the first support portion and the second support portion are both coated with an insulating buffer rubber layer.

[0016] A method for manufacturing a quantum processing unit according to another embodiment of the present invention, the quantum processing unit being the above-mentioned quantum processing unit, the method for manufacturing the quantum processing unit comprising the following steps: assembling the ion trap chip into the chip mounting through hole of the circuit board; mounting the first encapsulation board and the second encapsulation board on both sides in the thickness direction of the circuit board; bonding the first electrode to the first bonding terminal, and bonding the second electrode to the second bonding terminal.

[0017] According to the method for manufacturing a quantum processing unit of an embodiment of the present invention, the ion trap chip is fixedly arranged in the chip mounting through hole of the circuit board, and the circuit board and the ion trap chip can be connected by double-sided bonding, which is beneficial to increasing the number of electrical connections established between the circuit board and the ion trap chip. Moreover, the electrical connections between the circuit board and the ion trap chip can be dispersed on different two sides to reduce the bonding density on a single side and the bonding difficulty between the circuit board and the ion trap chip. At the same time, the first support portion and the second support portion can directly or indirectly support the ion trap chip on the upper and lower sides of the ion trap chip, avoiding damage and failure of the ion trap chip, which is beneficial to improving the yield rate of the quantum processing unit and reducing the manufacturing cost of the quantum processing unit.

[0018] A quantum computer according to yet another embodiment of the present invention includes the above-mentioned quantum processing unit.

[0019] According to the quantum computer of an embodiment of the present invention, the ion trap chip of the quantum processing unit is fixedly arranged in the chip mounting through hole of the circuit board, and the circuit board and the ion trap chip can be connected by double-sided bonding, which is beneficial to increasing the number of electrical connections established between the circuit board and the ion trap chip. Moreover, the electrical connections between the circuit board and the ion trap chip can be dispersed on different two sides to reduce the bonding density on a single side and the bonding difficulty between the circuit board and the ion trap chip, thereby being beneficial to improving the performance of the quantum computer and reducing the manufacturing cost of the quantum computer.

[0020] Additional aspects and advantages of the present invention will be given in part in the following description, become apparent in part from the following description, or be learned through the practice of the present invention. Description of the Drawings

[0021] Figure 1 is a schematic diagram of a circuit board and an ion trap chip according to an embodiment of the present invention; Figure 2 is a top view of the connection part of the circuit board and the ion trap chip according to an embodiment of the present invention; Figure 3 is a bottom view of the connection part of the circuit board and the ion trap chip according to an embodiment of the present invention; Figure 4 Schematic diagram of a quantum processing unit according to an embodiment of the present invention; Figure 5 Exploded view of a quantum processing unit according to an embodiment of the present invention; Figure 6 Another exploded view of a quantum processing unit according to an embodiment of the present invention; Figure 7 Schematic structural diagram of a quantum processing unit at an ion trap chip according to an embodiment of the present invention; Figure 8 Another schematic structural diagram of a quantum processing unit at an ion trap chip according to an embodiment of the present invention; Figure 9 Flowchart of a manufacturing method of a quantum processing unit according to an embodiment of the present invention.

[0022] Reference numerals: Circuit board 1; first circuit surface 11; first bonding terminal 111; second circuit surface 12; second bonding terminal 121; chip mounting through hole 13; bearing protrusion 131; signal lead-out terminal 14; Ion trap chip 2; first chip surface 21; first electrode 211; second chip surface 22; second electrode 221; First encapsulation board 3; first operation through hole 31; first support portion 32; Second encapsulation board 4; second operation through hole 41; second support portion 42; Avoidance groove 5; foot pad 6; Quantum processing unit 10. Detailed implementation manners

[0023] The embodiments of the present invention will be described in detail below. The examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to explain the present invention and should not be construed as limiting the present invention.

[0024] In the description of the present invention, it should be understood that the orientation or positional relationship indicated by the terms "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "inner", "outer", etc. is based on the orientation or positional relationship shown in the accompanying drawings, and is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as limiting the present invention.

[0025] In addition, the terms "first" and "second" are for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of the present invention, "a plurality of" means at least two, such as two, three, etc., unless otherwise specifically defined.

[0026] In the present invention, unless otherwise clearly specified and defined, terms such as "mounted", "connected", "coupled", "fixed", etc. should be understood in a broad sense. For example, it may be a fixed connection, a detachable connection, or integrated; it may be a mechanical connection, an electrical connection, or capable of communicating with each other; it may be directly connected, or indirectly connected through an intermediate medium, and may be the communication inside two elements or the interaction relationship between two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0027] The quantum processing unit 10 according to an embodiment of the present invention, its manufacturing method, and a quantum computer will be described in detail below with reference to the accompanying drawings.

[0028] Refer to Figures 1 - 3 As shown, the quantum processing unit 10 according to an embodiment of the present invention includes: a circuit board 1 and an ion trap chip 2. The circuit board 1 is provided with a chip mounting through hole 13. The circuit board 1 has a first circuit surface 11 and a second circuit surface 12 opposite to each other in its thickness direction. The first circuit surface 11 has a first bonding terminal 111, and the second circuit surface 12 has a second bonding terminal 121. The ion trap chip 2 is fixed in the chip mounting through hole 13. The ion trap chip 2 has a first chip surface 21 and a second chip surface 22 opposite to each other in its thickness direction. The first chip surface 21 has a first electrode 211, and the second circuit surface 12 has a second electrode 221. Among them, the first circuit surface 11 and the first chip surface 21 face the same direction, and the first electrode 211 is bonded to the first bonding terminal 111. The second circuit surface 12 and the second chip surface 22 face the same direction, and the second electrode 221 is bonded to the second bonding terminal 121.

[0029] Specifically, the circuit board 1 may be a carrier such as a ceramic substrate or a silicon substrate, which has good thermal stability and electrical insulation performance. The circuit board 1 is a double-sided circuit board and can be formed by laminating multiple board bodies. For example, the circuit board 1 is formed by laminating two or three board bodies. In the thickness direction of the circuit board 1, that is, in Figure 1In the up and down direction, the circuit board 1 has a first circuit surface 11 and a second circuit surface 12 facing in opposite directions. The first circuit surface 11 can be the upper surface of the circuit board 1, and the second circuit surface 12 can be the lower surface of the circuit board 1. The first circuit surface 11 has a first bonding terminal 111, and the second circuit surface 12 has a second bonding terminal 121. The circuit board 1 can transmit DC voltage, radio frequency (RF) signal, and microwave signal through the first bonding terminal 111 and the second bonding terminal 121. At the same time, the circuit board 1 is provided with a chip mounting through-hole 13, and the chip mounting through-hole 13 can penetrate the circuit board 1 in the thickness direction of the circuit board 1. The chip mounting through-hole 13 can be used to mount the ion trap chip 2.

[0030] The ion trap chip 2 can be used to trap ions serving as qubits and perform quantum logic gate operations. The ion trap chip 2 is a double-sided chip. In the thickness direction of the ion trap chip 2, that is, in Figure 1 the up and down direction, the ion trap chip 2 has a first chip surface 21 and a second chip surface 22 facing in opposite directions. The first chip surface 21 can be the upper surface of the ion trap chip 2, and the second chip surface 22 can be the lower surface of the ion trap chip 2. The first chip surface 21 has a first electrode 211, and the second circuit surface 12 has a second electrode 221.

[0031] The ion trap chip 2 can be fixedly connected to the chip mounting through-hole 13 on the circuit board 1 by means such as fasteners, bonding, and snap connection. The ion trap chip 2 can be at least partially embedded in the chip mounting through-hole 13, or the ion trap chip 2 can also be fixedly connected to the chip mounting through-hole 13 on one side outside the chip mounting through-hole 13. After the ion trap chip 2 is fixed to the chip mounting through-hole 13, the first chip surface 21 and the first circuit surface 11 face the same direction, so as to facilitate the bonding connection between the first electrode 211 and the first bonding terminal 111, and the second chip surface 22 and the second circuit surface 12 face the same direction, so as to facilitate the bonding connection between the second electrode 221 and the second bonding terminal 121.

[0032] It can be understood that the first electrode 211 and the first bonding terminal 111 can be bonded and connected through corresponding bonding wires, and the second electrode 221 and the second bonding terminal 121 can be bonded and connected through corresponding bonding wires. The bonding wires can be wires such as gold wires and aluminum wires, and the bonding wires can pass through the chip mounting through-hole 13 as needed to reduce the length of the bonding wires.

[0033] According to the quantum processing unit 10 of the embodiment of the present invention, the ion trap chip 2 is fixedly arranged in the chip mounting through-hole 13 of the circuit board 1, and the circuit board 1 and the ion trap chip 2 can be bonded and connected on both sides, which is beneficial to increasing the number of electrical connections established between the circuit board 1 and the ion trap chip 2, and can also disperse the electrical connections between the circuit board 1 and the ion trap chip 2 on different two sides to reduce the bonding density on a single side and reduce the bonding difficulty between the circuit board 1 and the ion trap chip 2.

[0034] In some embodiments of the present invention, with reference to Figures 1 - 3 as shown, in the thickness direction of the ion trap chip 2, the first electrode 211 and the second electrode 221 are arranged staggeredly, and the first bonding terminal 111 and the second bonding terminal 121 are arranged staggeredly.

[0035] Specifically, the thickness direction of the ion trap chip 2 is Figure 1 the up and down direction in Figure 2 and Figure 3 the direction perpendicular to the paper surface in

[0036] In this case, the first electrode 211 and the second electrode 221 are arranged staggeredly, and the first bonding terminal 111 and the second bonding terminal 121 are arranged staggeredly. That is to say, in the up and down direction, the projection of the first electrode 211 on the second chip surface 22 does not overlap with the second electrode 221 on the second chip surface 22, and the projection of the first bonding terminal 111 on the second circuit surface 12 does not overlap with the second bonding terminal 121 on the second circuit surface 12. Thus, when the wire bonder bonds the first electrode 211 and the first bonding terminal 111, the capillary of the wire bonder generates pressure on the first electrode 211 and the first bonding terminal 111 in the up and down direction, and this pressure has a relatively small impact on the second electrode 221 and the second bonding terminal 121. When the wire bonder bonds the second electrode 221 and the second bonding terminal 121, the capillary of the wire bonder generates pressure on the second electrode 221 and the second bonding terminal 121 in the up and down direction, and this pressure has a relatively small impact on the first electrode 211 and the first bonding terminal 111. Thereby, the negative impact of the stress generated during the bonding of the ion trap chip 2 and the circuit board 1 on one side on the other side is reduced, that is, the short - circuit risk caused by the failure of the wire connection after bonding is reduced, which is beneficial to improving the yield of the quantum processing unit 10.

[0037] In some embodiments of the present invention, with reference to Figure 2 and Figure 3As shown, the number of the first electrodes 211 and the first bonding terminals 111 are both multiple and are bonded to each other in a one-to-one correspondence. The number of the second electrodes 221 and the second bonding terminals 121 are both multiple and are bonded to each other in a one-to-one correspondence. Thus, the number of electrical connections between the circuit board 1 and the ion trap chip 2 is increased, so that the quantum processing unit 10 has a finer electric field regulation ability, and the quantum processing unit 10 has a higher-scale and higher-fidelity quantum operation ability.

[0038] In some embodiments of the present invention, the ion trap chip 2 may be a chip on an alumina ceramic carrier. The ion trap chip 2 realizes the arrangement of multiple first electrodes 211 and multiple second electrodes 221 on both the first chip surface 21 and the second chip surface 22, which can increase the total number of the first electrodes 211 and the second electrodes 221, so as to improve the computing ability of the quantum processing unit 10. At the same time, the volume of the ion trap chip 2 can be reduced, and the risk of the ion trap chip 2 being broken can be reduced.

[0039] In some embodiments of the present invention, referring to Figures 1 - 3 As shown, in the width direction of the ion trap chip 2, at least one first electrode 211 is provided at both ends of the first chip surface 21, and the first bonding terminal 111 is arranged adjacent to the corresponding first electrode 211. In the length direction of the ion trap chip 2, at least one second electrode 221 is provided at both ends of the second chip surface 22, and the second bonding terminal 121 is arranged adjacent to the corresponding second electrode 221.

[0040] Specifically, the width direction of the ion trap chip 2 is Figures 1 - 3 the left-right direction in

[0041] The length direction of the ion trap chip 2 is Figures 1 - 3In the front-rear direction, one or more second electrodes 221 may be arranged at the front end of the second chip surface 22, and one or more second electrodes 221 may be arranged at the rear end of the second chip surface 22. Second bonding terminals 121 adjacent to the second electrodes 221 are correspondingly arranged on the front and rear sides of the chip mounting through hole 13 on the second circuit surface 12. The second electrode 221 at the front end of the second chip surface 22 may be bonded to the second bonding terminal 121 corresponding to the front side of the chip mounting through hole 13 on the second circuit surface 12, and the second electrode 221 at the rear end of the second chip surface 22 may be bonded to the second bonding terminal 121 corresponding to the rear side of the chip mounting through hole 13 on the second circuit surface 12. This can reduce the lead length for connecting the second electrode 221 and the second bonding terminal 121, thereby facilitating cost reduction and improving the reliability of bonding. At the same time, compared with the centralized arrangement of multiple second electrodes 221, in the embodiment of the present invention, multiple second electrodes 221 are arranged at opposite front and rear ends of the second chip surface 22, which can avoid excessive density of the second electrodes 221 on the second chip surface 22, facilitating the bonding operation of the wire bonder.

[0042] In some embodiments of the present invention, referring to Figures 1 - 3 as shown, the circuit board 1 has a filtering circuit and signal extraction terminals 14, and both the first bonding terminal 111 and the second bonding terminal 121 are connected to the signal extraction terminals 14 through the filtering circuit.

[0043] Specifically, power or a signal can be connected to the signal extraction terminals 14. When the power or the signal is transmitted to the ion trap chip 2 through the circuit board 1, it needs to be filtered by the filtering circuit to reduce the interference of external noise on the ion trap chip 2 and improve the stability and control accuracy of the ion trap chip 2. At the same time, the electrodes and circuits inside the ion trap chip 2 will generate thermal noise and 1 / f noise, etc. These noises will interfere with the motion mode of the ions and affect the transmission of quantum information and the fidelity of quantum control. The filtering circuit can suppress these internal noises and ensure the purity of the ion motion mode. In addition, the motion mode of the ions is the carrier of quantum information transmission. Some Raman quantum controls are coupled with the motion mode of the ions. The non-ideal change in the ion motion state will greatly affect the fidelity of quantum operations and cause a decoherence effect. The filtering circuit can provide a pure electrical signal, reduce the non-ideal change in the ion motion state, and thus improve the fidelity of quantum control.

[0044] In some embodiments, the total number of pins in all signal lead terminals 14 is N, the filtering circuit may include N filtering sub - circuits, and at least one filtering capacitor is integrated on each filtering sub - circuit. The total number of the first bonding terminals 111 and the second bonding terminals 121 is N, where N≥2 and N is an integer. That is to say, each first bonding terminal 111 is electrically connected to a pin of a corresponding signal lead terminal 14 through a corresponding filtering sub - circuit, and each second bonding terminal 121 is electrically connected to a pin of a corresponding signal lead terminal 14 through a corresponding filtering sub - circuit. Thus, the signal crosstalk between different electrodes can be reduced through the filtering sub - circuits, ensuring the purity of the electrical signals applied to each first electrode 211 and each second electrode 221 of the ion trap chip 2, and improving the manipulation accuracy of the ion trap chip 2 for ions.

[0045] Referring to Figure 1 As shown, the number of signal lead terminals 14 is two. In the direction perpendicular to the thickness of the circuit board 1, the two signal lead terminals 14 are located at both ends of the circuit board 1, and the chip mounting through - hole 13 is located between the two signal lead terminals 14. For example, the chip mounting through - hole 13 is located at the center of the circuit board 1, one signal lead terminal 14 is located at the left end of the circuit board 1, and the other signal lead terminal 14 is located at the right end of the circuit board 1, so as to leave enough layout space for the filtering circuit, enable the filtering sub - circuits in the filtering circuit to be evenly arranged separately, reduce the manufacturing difficulty of the circuit board 1, avoid the over - concentration of the filtering sub - circuits, and reduce the risk of signal crosstalk.

[0046] In some embodiments of the present invention, referring to Figure 1 and Figure 3 As shown, a bearing protrusion 131 is formed on the hole wall of the chip mounting through - hole 13, and the ion trap chip 2 is fixedly connected to the bearing protrusion 131 through a fastener.

[0047] In some embodiments, the fastener can be a screw, and the screw passes through the ion trap chip 2 and is in threaded cooperation with the bearing protrusion 131. In other embodiments, the fastener can be a buckle, and the buckle passes through the ion trap chip 2 and is in snap - fit with the bearing protrusion 131. The bearing protrusion 131 can increase the contact area between the ion trap chip 2 and the circuit board 1, thereby facilitating the increase of the connection stability and reliability between the ion trap chip 2 and the circuit board 1.

[0048] Optionally, the number of the bearing protrusions 131 and the fasteners can be multiple, and the ion trap chip 2 is connected to the bearing protrusion 131 through multiple fasteners to further improve the connection stability and reliability between the ion trap chip 2 and the circuit board 1.

[0049] In some embodiments of the present invention, referring to Figures 4 - 8As shown, the quantum processing unit 10 further includes: a first encapsulation board 3 and a second encapsulation board 4. The first encapsulation board 3 faces the first circuit surface 11. The first encapsulation board 3 is provided with a first operation through hole 31 and has a first support portion 32. The second encapsulation board 4 faces the second circuit surface 12. The second encapsulation board 4 is provided with a second operation through hole 41 and has a second support portion 42. Wherein, in the thickness direction of the circuit board 1: the first encapsulation board 3 and the second encapsulation board 4 are clamped on both sides of the circuit board 1. The first operation through hole 31 corresponds to the first bonding terminal 111, and the first operation through hole 31 also corresponds to the first electrode 211. The second operation through hole 41 corresponds to the second bonding terminal 121, and the second operation through hole 41 also corresponds to the second electrode 221. The first support portion 32 abuts against the area of the first chip surface 21 corresponding to the second electrode 221, and / or the first support portion 32 abuts against the area of the first circuit surface 11 corresponding to the second electrode 221. The second support portion 42 abuts against the area of the second chip surface 22 corresponding to the first electrode 211, and / or the second support portion 42 abuts against the area of the second circuit surface 12 corresponding to the first electrode 211.

[0050] Wherein, the first encapsulation board 3 and the second encapsulation board 4 can fix and protect the circuit board 1 on the upper and lower sides of the circuit board 1. The first encapsulation board 3 and the second encapsulation board 4 can also correspondingly support at least one of the ion trap chip 2 and the circuit board 1 on the back of the bonding area to reduce the deformation amount of the ion trap chip 2 and the circuit board 1 during bonding.

[0051] In addition, the first encapsulation board 3 and the second encapsulation board 4 can be metal plates. The first encapsulation board 3 and the second encapsulation board 4 can shield external interference and the influence of stray electric fields on the ion trap chip 2 and the circuit board 1. At the same time, the first encapsulation board 3 and the second encapsulation board 4 can also conduct the heat of the ion trap chip 2 to improve the heat dissipation capacity of the ion trap chip 2 and improve the service performance of the ion trap chip 2.

[0052] Specifically, in the thickness direction of the circuit board 1, that is Figures 4 - 8 in the up and down direction in, the first encapsulation board 3 and the second encapsulation board 4 are clamped on both sides of the circuit board 1 to fix and support the circuit board 1. The first encapsulation board 3, the circuit board 1 and the second encapsulation board 4 can be connected by multiple fasteners such as screws and rivets.

[0053] The first encapsulation board 3 is provided with a first operation through hole 31. In the up-and-down direction, the first encapsulation board 3 faces the first circuit surface 11, and the first operation through hole 31 corresponds to the first bonding terminal 111 and also corresponds to the first electrode 211. When the first bonding terminal 111 is bonded to the first electrode 211, the press head of the wire bonding machine can extend into the first operation through hole 31 to bond the first bonding terminal 111 and the first electrode 211 through a wire, so as to avoid interference between the first encapsulation board 3 and the wire bonding machine.

[0054] The second encapsulation board 4 has a second support portion 42. In the up-and-down direction, the second support portion 42 abuts against the area of the second chip surface 22 corresponding to the first electrode 211, and / or the second support portion 42 abuts against the area of the second circuit surface 12 corresponding to the first electrode 211. That is to say, in the up-and-down direction, in the area of the second chip surface 22 corresponding to the first electrode 211 and the area of the second circuit surface 12 corresponding to the first electrode 211, the second support portion 42 abuts against at least one area. Thus, when the first bonding terminal 111 is bonded to the first electrode 211, the second support portion 42 is located on the back surface of the first electrode 211, and the second support portion 42 can support the ion trap chip 2 corresponding to the pressed area, so as to reduce the deformation amount of the ion trap chip 2 when the first bonding terminal 111 is bonded to the first electrode 211, and avoid cracks or breakage of the ion trap chip 2 during bonding, thereby being beneficial to improving the yield rate of the quantum processing unit 10.

[0055] Referring to Figures 4 - 8 the embodiment shown, the number of the second support portions 42 is two, and the two second support portions 42 respectively abut against the areas of the second circuit surface 12 corresponding to the first electrode 211, that is, the two second support portions 42 respectively abut against the corresponding two bearing protrusions 131.

[0056] It should be noted that if in the up-and-down direction, there is no area of the second circuit surface 12 corresponding to the first electrode 211, that is, the projection of the first electrode 211 on the second circuit surface 12 in the up-and-down direction is located outside the second circuit surface 12, then the second support portion 42 can only abut against the area of the second chip surface 22 corresponding to the first electrode 211 (not shown in the figure).

[0057] If in the up-and-down direction, only a part of the second circuit surface 12 corresponds to the first electrode 211, that is, a part of the projection of the first electrode 211 on the second circuit surface 12 in the up-and-down direction is located inside the second circuit surface 12, then the second support portion 42 can abut against the area of the second circuit surface 12 corresponding to a part of the first electrode 211, and the second support portion 42 also abuts against the area of the second chip surface 22 corresponding to the other part of the first electrode 211 (not shown in the figure).

[0058] If, in the up-down direction, the entire area of the second circuit surface 12 corresponds to the first electrode 211, that is, the projection of the first electrode 211 onto the second circuit surface 12 in the up-down direction is entirely within the second circuit surface 12, then the second support portion 42 can abut only against the area of the second circuit surface 12 corresponding to the first electrode 211 (i.e., Figures 1 - 8 the embodiment shown).

[0059] The second encapsulation board 4 is provided with a second operation through hole 41. In the up-down direction, the second encapsulation board 4 faces the second circuit surface 12, and the second operation through hole 41 corresponds to the second bonding terminal 121 and also corresponds to the second electrode 221. When the second bonding terminal 121 and the second electrode 221 are bonded, the indenter of the wire bonder can extend into the second operation through hole 41 to bond the second bonding terminal 121 and the second electrode 221 through a wire, so as to avoid interference between the second encapsulation board 4 and the wire bonder.

[0060] The first encapsulation board 3 has a first support portion 32. In the up-down direction, the first support portion 32 abuts against the area of the first chip surface 21 corresponding to the second electrode 221, and / or the first support portion 32 abuts against the area of the first circuit surface 11 corresponding to the second electrode 221. That is to say, in the up-down direction, among the area of the first chip surface 21 corresponding to the second electrode 221 and the area of the first circuit surface 11 corresponding to the second electrode 221, the first support portion 32 abuts against at least one area. Thus, when the second bonding terminal 121 and the second electrode 221 are bonded, the first support portion 32 is located on the back of the second electrode 221, and the first support portion 32 can support the ion trap chip 2 corresponding to the pressed area, so as to reduce the deformation amount of the ion trap chip 2 when the second bonding terminal 121 and the second electrode 221 are bonded, and avoid cracks or breakage of the ion trap chip 2 during bonding, thereby facilitating the improvement of the yield rate of the quantum processing unit 10.

[0061] Referring to Figures 4 - 8 the embodiment shown, the number of the first support portions 32 is two, and the two first support portions 32 respectively abut against the front and rear ends of the first chip surface 21.

[0062] It should be noted that if, in the up-down direction, there is no area of the first circuit surface 11 corresponding to the second electrode 221, that is, the projection of the second electrode 221 onto the first circuit surface 11 in the up-down direction is outside the first circuit surface 11, then the first support portion 32 can abut only against the area of the first chip surface 21 corresponding to the second electrode 221 (i.e., Figures 1 - 8 the embodiment shown).

[0063] If, in the vertical direction, the first circuit surface 11 only corresponds to a part of the second electrode 221, that is, a part of the projection of the second electrode 221 in the vertical direction onto the first circuit surface 11 is located inside the first circuit surface 11, the first support portion 32 can abut against the area of the first circuit surface 11 corresponding to a part of the second electrode 221, and the first support portion 32 also abuts against the area of the first chip surface 21 corresponding to another part of the second electrode 221 (not shown in the figure).

[0064] If, in the vertical direction, the first circuit surface 11 corresponds to the entire area of the second electrode 221, that is, the entire projection of the second electrode 221 in the vertical direction onto the first circuit surface 11 is located inside the first circuit surface 11, the first support portion 32 can only abut against the area of the first circuit surface 11 corresponding to the second electrode 221 (not shown in the figure).

[0065] In addition, due to the provision of the first operation through-hole 31 and the second operation through-hole 41, the problem of the optical path passing through can be solved, and light and signals can directly reach the ion trap chip 2 through the first operation through-hole 31 or the second operation through-hole 41.

[0066] In some embodiments of the present invention, the outer surfaces of the first support portion 32 and the second support portion 42 are both coated with an insulating buffer glue layer, which can endow the first support portion 32 and the second support portion 42 with good electrical insulation performance, and avoid the problem of short circuit caused by the first support portion 32 and the second support portion 42 to the ion trap chip 2, the circuit board 1 and the leads.

[0067] At the same time, the insulating buffer glue layer also has a buffering effect. When the quantum processing unit 10 operates at ultra-low temperature, the materials of various parts of the quantum processing unit 10 will produce corresponding micro-deformations under the influence of low temperature, and the insulating buffer glue layer also plays the role of a buffer.

[0068] Refer to Figures 4 - 6 As shown, the first encapsulation board 3 and the second encapsulation board 4 are also provided with avoidance grooves 5 corresponding to the signal lead-out terminals 14, so that the signal lead-out terminals 14 are exposed outside the first encapsulation board 3 and the second encapsulation board 4, facilitating the subsequent lower-level connection of the signal lead-out terminals 14.

[0069] A plurality of feet 6 can be provided on both the first encapsulation board 3 and the second encapsulation board 4. The plurality of feet 6 can be distributed around the periphery and in the middle of the side of the first encapsulation board 3 and the second encapsulation board 4 facing the circuit board 1. The first encapsulation board 3 and the second encapsulation board 4 abut against the circuit board 1 through the corresponding feet 6. Due to the height of the feet 6, a sandwich space capable of accommodating filter capacitors can be formed between the first encapsulation board 3 and the second encapsulation board 4 and the circuit board 1 to avoid damaging electronic components. In addition, the feet 6 can also be coated with an insulating buffer glue layer to form an insulating and buffering effect.

[0070] For the quantum processing unit 10 according to an embodiment of the present invention, both the ion trap chip 2 and the circuit board 1 adopt a double-sided expansion structure, reducing the overall size of the ion trap chip 2 and the circuit board 1 and enabling a larger number of electrical connections between the ion trap chip 2 and the circuit board 1. The first encapsulation board 3 and the second encapsulation board 4 have functions such as heat conduction, heat dissipation, support, shielding, fixing, and protection. Moreover, the first operation through-hole 31 and the second operation through-hole 41 can directly manipulate the ion trap chip 2 and also facilitate the manipulation of the optical path.

[0071] Refer to Figures 1 - 9 As shown, for the manufacturing method of the quantum processing unit according to another embodiment of the present invention, the quantum processing unit is the quantum processing unit of the above embodiment, and the manufacturing method of the quantum processing unit includes the following steps: Step S1: Assemble the ion trap chip into the chip installation through-hole.

[0072] Among them, the ion trap chip 2 can be installed on the bearing protrusion 131 of the chip installation through-hole 13 by a fastener, and the circuit board 1 is integrated with a filtering circuit.

[0073] Step S2: Install the first encapsulation board and the second encapsulation board on both sides of the circuit board in the thickness direction.

[0074] Among them, the first encapsulation board 3 and the second encapsulation board 4 can be installed on the upper and lower sides of the circuit board 1 by fasteners, and the first support portion 32 and the second support portion 42 can directly or indirectly support the ion trap chip 2 on the upper and lower sides of the ion trap chip 2.

[0075] Step S3: Bond the first electrode to the first bonding terminal and bond the second electrode to the second bonding terminal.

[0076] Among them, a wire bonder can be used to extend into the first operation through-hole 31 and bond the first electrode 211 to the first bonding terminal 111 using a wire. Then, the quantum processing unit 10 is flipped, and the wire bonder extends into the second operation through-hole 41 and bonds the second electrode 221 to the second bonding terminal 121 using a wire.

[0077] According to the manufacturing method of the quantum processing unit 10 according to an embodiment of the present invention, the ion trap chip 2 is fixedly arranged in the chip mounting through hole 13 of the circuit board 1. The circuit board 1 and the ion trap chip 2 can be connected by double-sided bonding, which is beneficial to increasing the number of electrical connections established between the circuit board 1 and the ion trap chip 2. Moreover, the electrical connections between the circuit board 1 and the ion trap chip 2 can be dispersed on different sides, so as to reduce the bonding density on a single side and the bonding difficulty between the circuit board 1 and the ion trap chip 2. At the same time, the first support portion 32 and the second support portion 42 can directly or indirectly support the ion trap chip 2 on the upper and lower sides of the ion trap chip 2, avoiding damage and failure of the ion trap chip 2, which is beneficial to improving the yield rate of the quantum processing unit 10 and reducing the manufacturing cost of the quantum processing unit 10.

[0078] The quantum computer according to another embodiment of the present invention includes the quantum processing unit 10 of the above embodiment.

[0079] In the quantum computer according to an embodiment of the present invention, the ion trap chip 2 of the quantum processing unit 10 is fixedly arranged in the chip mounting through hole 13 of the circuit board 1. The circuit board 1 and the ion trap chip 2 can be connected by double-sided bonding, which is beneficial to increasing the number of electrical connections established between the circuit board 1 and the ion trap chip 2. Moreover, the electrical connections between the circuit board 1 and the ion trap chip 2 can be dispersed on different sides, so as to reduce the bonding density on a single side and the bonding difficulty between the circuit board 1 and the ion trap chip 2, and further beneficial to improving the performance of the quantum computer and reducing the manufacturing cost of the quantum computer.

[0080] In the description of this specification, the descriptions with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples", etc. mean that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described can be combined in a suitable manner in any one or more embodiments or examples. In addition, those skilled in the art can combine and combine the different embodiments or examples described in this specification.

[0081] Although the embodiments of the present invention have been shown and described above, it can be understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Those of ordinary skill in the art can make changes, modifications, substitutions, and variations to the above embodiments within the scope of the present invention.

Claims

1. A quantum processing unit, characterized in that, Comprising: A circuit board (1), the circuit board (1) is provided with a chip mounting through hole (13), the circuit board (1) has a first circuit surface (11) and a second circuit surface (12) facing away from each other in its thickness direction, the first circuit surface (11) has a first bonding terminal (111), and the second circuit surface (12) has a second bonding terminal (121); An ion trap chip (2), the ion trap chip (2) is fixed in the chip mounting through hole (13), the ion trap chip (2) has a first chip surface (21) and a second chip surface (22) facing away from each other in its thickness direction, the first chip surface (21) has a first electrode (211), and the second circuit surface (12) has a second electrode (221); Wherein, the first circuit surface (11) and the first chip surface (21) face the same direction, and the first electrode (211) is bonded and connected to the first bonding terminal (111), the second circuit surface (12) and the second chip surface (22) face the same direction, and the second electrode (221) is bonded and connected to the second bonding terminal (121).

2. The quantum processing unit according to claim 1, wherein In the thickness direction of the ion trap chip (2), the first electrode (211) and the second electrode (221) are arranged staggeredly, and the first bonding terminal (111) and the second bonding terminal (121) are arranged staggeredly.

3. The quantum processing unit according to claim 2, characterized in that, The number of the first electrodes (211) and the first bonding terminals (111) is multiple and they are bonded and connected in one-to-one correspondence, and the number of the second electrodes (221) and the second bonding terminals (121) is multiple and they are bonded and connected in one-to-one correspondence.

4. The quantum processing unit according to claim 3, wherein In the width direction of the ion trap chip (2), at least one of the first electrodes (211) is provided at both ends of the first chip surface (21), and the first bonding terminal (111) is adjacent to the corresponding first electrode (211); In the length direction of the ion trap chip (2), at least one of the second electrodes (221) is provided at both ends of the second chip surface (22), and the second bonding terminal (121) is adjacent to the corresponding second electrode (221).

5. The quantum processing unit according to claim 1, characterized in that The circuit board (1) has a filtering circuit and a signal lead-out terminal (14), and the first bonding terminal (111) and the second bonding terminal (121) are both connected to the signal lead-out terminal (14) through the filtering circuit.

6. The quantum processing unit according to claim 1, wherein A bearing protrusion (131) is formed on the hole wall of the chip mounting through hole (13), and the ion trap chip (2) is fixedly connected to the bearing protrusion (131) through a fastener.

7. The quantum processing unit according to any one of claims 1-6, characterized in that, The quantum processing unit further comprises: A first encapsulation board (3), the first encapsulation board (3) is opposite to the first circuit surface (11), the first encapsulation board (3) is provided with a first operation through hole (31), and the first encapsulation board (3) has a first support portion (32); A second encapsulation board (4), the second encapsulation board (4) being opposite to the second circuit surface (12), the second encapsulation board (4) being provided with a second operation through hole (41), and the second encapsulation board (4) having a second support portion (42); Wherein, in the thickness direction of the circuit board (1): The first encapsulation board (3) and the second encapsulation board (4) are clamped on both sides of the circuit board (1); The first operation through hole (31) corresponds to the first bonding terminal (111), and the first operation through hole (31) also corresponds to the first electrode (211); The second operation through hole (41) corresponds to the second bonding terminal (121), and the second operation through hole (41) also corresponds to the second electrode (221); The first support portion (32) abuts against the area of the first chip surface (21) corresponding to the second electrode (221), and / or, the first support portion (32) abuts against the area of the first circuit surface (11) corresponding to the second electrode (221); The second support portion (42) abuts against the area of the second chip surface (22) corresponding to the first electrode (211), and / or, the second support portion (42) abuts against the area of the second circuit surface (12) corresponding to the first electrode (211).

8. The quantum processing unit according to claim 7, characterized in that, Insulating buffer glue layers are coated on the outer surfaces of the first support portion (32) and the second support portion (42).

9. A manufacturing method of a quantum processing unit, characterized in that, The quantum processing unit is the quantum processing unit according to claim 7 or 8, and the manufacturing method of the quantum processing unit includes the following steps: Assembling the ion trap chip into the chip installation through hole; Installing the first encapsulation board and the second encapsulation board on both sides in the thickness direction of the circuit board; Bonding the first electrode to the first bonding terminal, and bonding the second electrode to the second bonding terminal.

10. A quantum computer, characterized in that, Including the quantum processing unit according to any one of claims 1-8.

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