Power management circuit and display device

Abstract

The invention provides a power management circuit and a display device. The power management circuit comprises a chip main body and an inductor assembly, the chip main body comprises a DC-DC conversion module, a level conversion module and a gamma voltage module, and the inductor assembly is arranged on the chip main body and electrically connected with the chip main body. The inductor assembly comprises a plurality of unit inductors and a plurality of transistors, and the unit inductors are connected into the inductor assembly with the adjustable inductance value through the transistors. And heat-conducting glue is arranged between the chip main body and the inductor assembly. The power management circuit further comprises a register which is used for controlling the on or off state of the transistor so as to adjust the inductance value of the inductance component. According to the power management circuit, the high-integration design is realized, the heat dissipation effect is improved, and the flexibility of power management is improved through the adjustable inductance assembly.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a power management circuit and a display device. Background Art

[0002] A traditional PMIC (power management circuit) includes multiple modules. For at least one of these modules, a traditional PMIC needs to configure an inductor component separately on the periphery, resulting in a large space occupied on the PCB layout.

[0003] In addition, since the inductor element is configured separately as a peripheral component, different inductors need to be replaced for testing under different load conditions, which makes adjustments more cumbersome and less flexible.

[0004] At the same time, traditional PMICs have poor heat dissipation and are prone to overheating in high-power application scenarios, affecting the stability and service life of the PMIC.

[0005] Therefore, it is necessary to propose a new technical solution to solve the above technical problems. Summary of the Invention

[0006] The purpose of the embodiments of the present application is to provide a power management circuit and a display device, aiming to improve the heat dissipation effect of the power management circuit.

[0007] An embodiment of the present application provides a power management circuit, which includes: a chip body, the chip body including a DC-DC conversion module, a level conversion module and a gamma voltage module; and an inductor component, the inductor component is arranged on the chip body and electrically connected to the chip body.

[0008] In the above power management circuit, thermal conductive glue is provided between the chip body and the inductor component.

[0009] In the above power management circuit, the inductor component includes multiple unit inductors, multiple control signal lines and multiple transistors. The multiple unit inductors are electrically connected to the multiple transistors, and the gates of the multiple transistors are respectively electrically connected to the multiple control signal lines.

[0010] In the above power management circuit, a plurality of the unit inductors are arranged in an array.

[0011] In the above power management circuit, the multiple unit inductors include a first unit inductor to a K-th unit inductor, each unit inductor includes a first pad and a second pad which are oppositely arranged, the multiple transistors include a first transistor to a (2K - 1)-th transistor, where K is an integer greater than 1; the multiple control signal lines include a first control signal line to a (2K - 1)-th control signal line; the gate of the (2i - 2)-th transistor is electrically connected to the (2i - 2)-th control signal line, the first pad of the i-th unit inductor is electrically connected to the drain of the (2i - 2)-th transistor, the source of the (2i - 2)-th transistor is electrically connected to the second pad of the (i - 1)-th unit inductor, the gate of the (2i - 1)-th transistor is electrically connected to the (2i - 1)-th control signal line, the second pad of the i-th unit inductor is electrically connected to the source of the (2i - 1)-th transistor, the drain of the (2i - 1)-th transistor is electrically connected to the output terminal of the inductor assembly, where i is greater than or equal to 2 and less than or equal to K; the first pad of the first unit inductor is electrically connected to the input terminal of the inductor assembly, the second pad of the first unit inductor is electrically connected to the sources of the first transistor and the second transistor, the gate of the first transistor is electrically connected to the first control signal line, the drain of the first transistor is electrically connected to the output terminal of the inductor assembly, the gate of the second transistor is electrically connected to the second control signal line, and the drain of the second transistor is electrically connected to the first pad of the second unit inductor.

[0012] In the above power management circuit, the power management circuit further includes a register, the register is electrically connected to the first control signal line to the (2K - 1)-th control signal line, and the register is used to control the first transistor to the (2K - 1)-th transistor to adjust the inductance value of the inductor assembly.

[0013] In the above power management circuit, the register is an adjustable register having 2 to 6 binary control bits, and the register is used to adjust the inductance value of the inductor assembly to a plurality of predetermined values within a predetermined range.

[0014] In the above power management circuit, the predetermined range is from 1 μH to 16 μH.

[0015] In the above power management circuit, the register is used to control the on or off states of the first transistor to the (2K - 1)-th transistor by outputting high-level or low-level signals to the first control signal line to the (2K - 1)-th control signal line.

[0016] An embodiment of the present application further provides a display device, including a display panel and the above power management circuit, and the power management circuit is electrically connected to the display panel.

[0017] The power management circuit provided by this application realizes the high integration of the power management circuit by arranging the inductance component on the chip body and electrically connecting it to the chip body, while significantly improving the heat dissipation effect. Specifically, the inductance component includes a plurality of unit inductors and a plurality of transistors. The plurality of unit inductors are connected into an inductance component with an adjustable inductance value through the plurality of transistors, so that the inductance value can be flexibly adjusted according to actual needs without replacing external inductance elements. When the power management circuit operates under different load conditions, the connection mode of the unit inductors can be changed by controlling the on or off state of the transistors, thereby adjusting the total inductance value of the inductance component. Therefore, the power management circuit can adapt to various working conditions, improve the power conversion efficiency, and reduce energy loss.

[0018] In addition, a thermal conductive adhesive is provided between the chip body and the inductance component, which improves the heat conduction efficiency. The inductance component itself has a good thermal conductivity coefficient. By arranging it above the chip body, it acts as a heat dissipation device for the chip body, increasing the heat dissipation surface area. Heat can be efficiently transferred from the chip body to the inductance component through the thermal conductive adhesive and then dissipated into the environment. This technical solution solves the problem that traditional power management circuits are prone to overheating in high-power application scenarios, and improves the stability and service life of the power management circuit.

[0019] In addition, the plurality of unit inductors are arranged in an array form, which not only makes the structure more compact, but also enables heat to be more evenly dispersed, avoiding local overheating.

[0020] In addition, the power management circuit further includes a register, which is electrically connected to the control signal line and is used to control the on or off state of the transistors. The register is an adjustable register with 2 to 6 binary control bits, and can adjust the inductance value of the inductance component to a plurality of predetermined values within a predetermined range, enabling the power management circuit to automatically optimize the inductance value according to the actual working state, and improving the response speed and energy efficiency.

[0021] In summary, the power management circuit provided by this application realizes the organic combination of high integration, good heat dissipation and flexible adjustability, and solves the technical problems of traditional power management circuits in terms of large space occupation, poor heat dissipation effect and weak flexibility. Description of the Drawings

[0022] Figure 1 is a schematic diagram of a display device provided by an embodiment of this application.

[0023] Figure 2 is a block diagram of a power management circuit provided by an embodiment of this application.

[0024] Figure 3 is Figure 2 a schematic diagram of the power management circuit shown.

[0025] Figure 4 is Figure 2 A schematic diagram of the arrangement of multiple unit inductances of an inductor component in the power management circuit shown.

[0026] Figure 5 is Figure 2 A circuit diagram of the inductor component in the power management circuit shown.

[0027] Figure 6 is Figure 2 A circuit diagram of the first part of the peripheral circuit corresponding to the boost unit of the DC-DC conversion module in the power management circuit shown.

[0028] Figure 7 is Figure 2 A circuit diagram of the second part of the peripheral circuit corresponding to the buck unit of the DC-DC conversion module in the power management circuit shown.

[0029] Figure 8 is Figure 2 A circuit diagram of the third part of the peripheral circuit corresponding to the buck-boost unit of the DC-DC conversion module in the power management circuit shown. Detailed implementation manners

[0030] The following will describe in detail the specific implementation manners of the present application with reference to the accompanying drawings.

[0031] Terms such as "first", "second" and similar words do not denote any order, quantity or importance, but are only used to distinguish different technical features. The term "a plurality of" and similar words mean two or more, unless otherwise clearly defined.

[0032] The embodiments of the present application can be combined with each other.

[0033] The display device provided by the embodiments of the present application can be, for example, an LCD display device, an OLED display device, a Mini-LED display device, a Micro-LED display device. The embodiments of the present application will be described by taking the LCD display device as an example.

[0034] As Figure 1 shown, the display device provided by the embodiments of the present application includes a display panel, a timing controller, a source driver circuit, and a power management circuit (the power management circuit can be integrated with the timing controller into the same chip).

[0035] The display panel includes a display area and a non-display area. The display area is provided with M×N pixels arranged in an array, where M and N are integers greater than 1. The non-display area is located around the display area and is used to arrange the driving circuit and various signal lines. The display panel also includes a plurality of gate lines, a plurality of data lines, and a gate driving circuit. The plurality of gate lines extend in a first direction and are arranged in a second direction, and the plurality of data lines extend in the second direction and are arranged in the first direction, and the first direction is perpendicular to the second direction. The gate driving circuit is disposed in the non-display area and is electrically connected to the plurality of gate lines. The source driving circuit is electrically connected to the plurality of data lines through a flexible circuit board. The timing controller is electrically connected to the gate driving circuit and the source driving circuit respectively.

[0036] The display panel includes a thin-film transistor array substrate, a counter substrate, and a liquid crystal layer disposed between the two substrates. The thin-film transistor array substrate includes a glass substrate, a first metal layer disposed on the glass substrate, a gate insulating layer disposed on the first metal layer, a semiconductor layer disposed on the gate insulating layer, a second metal layer disposed on the semiconductor layer, a passivation layer disposed on the second metal layer, and a pixel electrode disposed on the passivation layer. The first metal layer includes gate lines, gate electrodes, etc. The second metal layer includes data lines, source electrodes, drain electrodes, etc. The counter substrate includes a glass substrate, a black matrix disposed on the glass substrate, a color filter layer disposed on the black matrix, and a common electrode disposed on the color filter layer.

[0037] Each pixel includes at least one thin-film transistor and a pixel electrode. The gate of the thin-film transistor is electrically connected to the corresponding gate line, the source is electrically connected to the corresponding data line, and the drain is electrically connected to the corresponding pixel electrode. When the gate line outputs a high-level scan signal, the thin-film transistor is turned on, and the data signal on the data line is transmitted to the pixel electrode through the thin-film transistor; when the gate line outputs a low-level scan signal, the thin-film transistor is turned off, and the pixel electrode maintains the voltage corresponding to the data signal.

[0038] The gate driving circuit includes N cascaded gate driving sub-circuits, and each gate driving sub-circuit is electrically connected to a gate line. The gate driving sub-circuit sequentially outputs scan signals under the control of the timing controller to scan each row of pixels in the display area row by row. The source driving circuit generates and outputs data signals according to the image data under the control of the timing controller. The timing controller is used to receive and process externally input image data and timing signals, generate control signals, and transmit the image data to the source driving circuit. The power management circuit is used to provide operating voltages for various parts of the display device, including providing a common voltage for the common electrode of the liquid crystal display panel, providing a gate driving voltage for the gate driving circuit, providing a gamma voltage for the source driving circuit, etc.

[0039] An embodiment of the present application provides a power management circuit. This power management circuit adopts a four-in-one architecture, including a chip body 101 (wafer part) and a peripheral circuit 102. The peripheral circuit 102 includes an inductor component 1021, as Figure 2 , Figure 3 , Figures 6 to 8 shown. The chip body 101 includes a DC-DC conversion module, a level conversion module, and a gamma voltage module. As Figure 3 shown, the chip body 101 is disposed on a printed circuit board including at least a part of the peripheral circuit 102. At least a part of the peripheral circuit 102 other than the inductor component 1021 is disposed on the printed circuit board. The inductor component 1021 is disposed on the chip body 101 and electrically connected to the chip body 101, constituting a power management circuit with a four-in-one architecture.

[0040] As Figure 2 and Figure 3 shown, the chip body 101 is composed of a DC-DC conversion module, a level conversion module, and a gamma voltage module. These three modules are integrated in the chip body 101. The inductor component 1021 is disposed on the chip body 101 (top surface) and electrically connected to the chip body 101 through a conductive material. A thermal conductive adhesive is disposed between the chip body 101 and the inductor component 1021 to improve the heat conduction efficiency and ensure that the heat generated by the chip body 101 can be effectively transferred to the inductor component 1021.

[0041] The DC-DC conversion module includes a boost unit, a buck unit, and a buck-boost unit. The boost unit is used to increase the input voltage to obtain a high voltage. For example, it can increase the input voltage of 5V to 12V. The buck unit is used to decrease the input voltage to obtain a low voltage. For example, it can decrease the input voltage of 5V to 3.3V. The buck-boost unit can increase or decrease the input voltage as needed to obtain a negative voltage. For example, it can convert the input voltage of 5V to -5V.

[0042] The level conversion module is used to achieve voltage level conversion. For example, it can convert the input voltage of 0V to 3.3V to -10V to 28V to meet the requirements of different electronic components for the operating voltage, enabling the power management circuit to adapt to the driving requirements of various display devices.

[0043] The gamma voltage module divides the input voltage into multiple groups of gamma tap voltages, such as 4 groups or 14 groups of gamma tap voltages, by means of voltage division, to provide an accurate driving voltage for the display device.

[0044] As Figures 6 to 8As shown, the first part of the peripheral circuit 102 corresponding to the boost unit of the DC-DC conversion module of the power management circuit includes a first inductor component 10211 with an inductance value of 6.8 μH. The second part of the peripheral circuit 102 corresponding to the buck unit of the DC-DC conversion module of the power management circuit includes a second inductor component 10212 with an inductance value of 10 μH. The third part of the peripheral circuit 102 corresponding to the buck-boost unit of the DC-DC conversion module of the power management circuit includes a third inductor component 10213 with an inductance value of 10 μH.

[0045] In an embodiment of the present application, the inductor component 1021 (including the first inductor component 10211, the second inductor component 10212, and the third inductor component 10213) adopts a modular design and includes a plurality of unit inductors C, a plurality of control signal lines, and a plurality of transistors. As Figure 4 and Figure 5 shown, the plurality of unit inductors C are arranged in an array and are connected into an inductor component 1021 with an adjustable inductance value through a plurality of transistors and a plurality of control signal lines. Each unit inductor C includes a first pad P1 and a second pad P2 arranged oppositely for electrically connecting with other electronic components.

[0046] Each unit inductor C may have the same inductance value, such as 1 μH or 2 μH. Of course, the inductance value of the unit inductor C is not limited thereto and can be set to other appropriate values according to actual requirements. The plurality of unit inductors C are connected in series.

[0047] The gates of the plurality of transistors are respectively electrically connected to the plurality of control signal lines. Through these control signal lines, the on or off state of the transistors can be controlled, thereby changing the connection mode of the unit inductors C and adjusting the inductance value of the inductor component 1021.

[0048] In an embodiment of the present application, as Figure 5 shown, the inductor component 1021 includes a first unit inductor C1 to a Kth unit inductor C(K), and a first transistor T1 to a (2K - 1)th transistor T(2K - 1), where K is an integer greater than 1. The inductor component 1021 further includes a first control signal line L1 to a (2K - 1)th control signal line L(2K - 1) for controlling the corresponding transistors. The first unit inductor C1 to the Kth unit inductor C(K) are connected in series.

[0049] The first pad P1(1) of the first unit inductor C1 is electrically connected to the input terminal S1 of the inductor component 1021. The second pad P2(1) of the first unit inductor C1 is electrically connected to the source electrodes of the first transistor T1 and the second transistor T2. The gate of the first transistor T1 is electrically connected to the first control signal line L1, and the drain of the first transistor T1 is electrically connected to the output terminal S2 of the inductor component 1021. The gate of the second transistor T2 is electrically connected to the second control signal line L2, and the drain of the second transistor T2 is electrically connected to the first pad P1(2) of the second unit inductor C2.

[0050] The second pad P2(2) of the second unit inductor C2 is electrically connected to the source electrode of the third transistor T3. The gate of the third transistor T3 is electrically connected to the third control signal line L3, and the drain of the third transistor T3 is electrically connected to the output terminal S2 of the inductor component 1021. This technical solution enables the second unit inductor C2 to be included in the circuit or bypassed as needed.

[0051] For the i-th unit inductor C (where i is greater than or equal to 2 and less than or equal to K), its first pad P1 is electrically connected to the drain of the (2i - 2)-th transistor T(2i - 2). The gate of the (2i - 2)-th transistor T(2i - 2) is electrically connected to the (2i - 2)-th control signal line L(2i - 2), and the source of the (2i - 2)-th transistor T(2i - 2) is electrically connected to the second pad P2 of the (i - 1)-th unit inductor C. The second pad P2 of the i-th unit inductor C is electrically connected to the source of the (2i - 1)-th transistor T(2i - 1). The gate of the (2i - 1)-th transistor T(2i - 1) is electrically connected to the (2i - 1)-th control signal line L(2i - 1), and the drain of the (2i - 1)-th transistor T(2i - 1) is electrically connected to the output terminal S2 of the inductor component 1021.

[0052] In the embodiments of the present application, the first transistor T1 to the (2K - 1)-th transistor T(2K - 1) are all N-type transistors. Of course, they can also be P-type transistors. Taking the first transistor T1 to the (2K - 1)-th transistor T(2K - 1) being all N-type transistors as an example, when the first control signal line L1 outputs a high-level signal and the second control signal line L2 outputs a low-level signal, the first transistor T1 conducts and the second transistor T2 cuts off. The current can flow directly from the first unit inductor C1 to the output terminal S2 of the inductor component 1021. At this time, the inductance value of the inductor component 1021 is equal to the inductance value of the first unit inductor C1. When the first control signal line L1 outputs a low-level signal, the second control signal line L2 outputs a high-level signal, and the third control signal line L3 outputs a high-level signal, the second transistor T2 and the third transistor T3 conduct. The current can flow from the first unit inductor C1 to the second unit inductor C2, and so on. By controlling different control signal lines, different current paths can be achieved, thereby obtaining different combinations of inductance values.

[0053] In an embodiment of the present application, the power management circuit further includes a register, which is electrically connected to the first control signal line L1 to the (2K - 1)th control signal line L(2K - 1). The register is used to control the first transistor T1 to the (2K - 1)th transistor T(2K - 1) through the first control signal line L1 to the (2K - 1)th control signal line L(2K - 1), so as to adjust the inductance value of the inductor component 1021. The register controls the on or off state of the first transistor T1 to the (2K - 1)th transistor T(2K - 1) by outputting high - level or low - level signals to the first control signal line L1 to the (2K - 1)th control signal line L(2K - 1), so as to change the connection mode of multiple unit inductors C.

[0054] Taking an adjustable register with 3 - bit binary control bits as an example for illustration. The register is used to adjust the inductance value of the inductor component 1021 to multiple predetermined values within a predetermined range. When the inductance value of each unit inductor C is 2 μH, the predetermined range is 2 μH to 16 μH, as shown in Table 1. Specifically, when the value of the register is 000, the inductance value is 2 μH; when the value of the register is 001, the inductance value is 4 μH; when the value of the register is 010, the inductance value is 6 μH; when the value of the register is 011, the inductance value is 8 μH; when the value of the register is 100, the inductance value is 10 μH; when the value of the register is 101, the inductance value is 12 μH; when the value of the register is 110, the inductance value is 14 μH; when the value of the register is 111, the inductance value is 16 μH.

[0055]

[0056]

[0057] Table 1

[0058] Taking an adjustable register with 4 - bit binary control bits as an example for illustration. As Figure 4 shown, the inductor component 1021 is arranged in a 3×3 array manner, and the inductor component 1021 includes 9 unit inductors C. When the inductance value of each unit inductor C is 1 μH, the predetermined range is 1 μH to 9 μH, as shown in Table 2.

[0059]

[0060] Table 2

[0061] Through the control of the register, the inductance value of the inductance component 1021 can be flexibly adjusted according to different load conditions, so as to realize the optimized adjustment of the power supply working condition. When the display panel displays a light load image, a smaller inductance value is used to improve the response speed; when the display panel displays a heavy load image, a larger inductance value is used to reduce the ripple and improve the efficiency. The technical solution of the present application can enable the power management circuit to adapt to various working conditions and improve the overall performance.

[0062] In the embodiment of the present application, the inductance component 1021 is arranged above the chip body 101, and a thermal conductive adhesive is arranged between the chip body 101 and the inductance component 1021. The inductance includes a coil. By utilizing the characteristic that the inductance has a good thermal conductivity coefficient, the inductance component 1021 is arranged on the chip body 101 to act as a heat dissipation device for the chip body 101, which can increase the heat dissipation surface area and improve the heat dissipation effect of the chip body 101.

[0063] As Figure 3 and Figure 4 shown, the inductance component 1021 is arranged above the chip body 101 (including a DC-DC conversion module, a level conversion module, and a gamma voltage module), achieving a better heat dissipation effect. The heat generated by the chip body 101 is transferred to the inductance component 1021 through the thermal conductive adhesive, and then the inductance component 1021 dissipates the heat into the environment. Since the inductance component 1021 adopts a design of multiple unit inductors C, the heat can be more evenly dispersed, avoiding local overheating and improving the heat dissipation efficiency.

[0064] In addition, the whole composed of the chip body 101, the thermal conductive adhesive, and the inductance component 1021 is not encapsulated with a plastic encapsulation material, further improving the heat dissipation efficiency. Compared with the traditional plastic encapsulation structure, the heat dissipation effect in the embodiment of the present application is better, and it can support working at a higher power density. This non-plastic encapsulation design also reduces the thermal resistance, enabling the heat to be transferred from the chip body 101 to the environment faster.

[0065] The embodiment of the present application also provides a display device, including a display panel and the above-mentioned power management circuit, and the power management circuit is electrically connected to the display panel. The power management circuit provides various voltages required for the display panel to ensure the normal operation of the display panel. Since the power management circuit has high integration, good heat dissipation, and adjustable properties, the display device can maintain stable performance under various working conditions.

[0066] In the power management circuit, the inductor component 1021 is directly located above the chip body 101. When the transistor switches at high frequency, the rapidly changing magnetic field in the inductor generates electromagnetic radiation. These radiations may interfere with the sensitive circuits in the chip body 101, especially the gamma voltage module and the level conversion module, resulting in flickering, streaks or color distortion in the display panel. In a high-resolution display panel, even a tiny voltage fluctuation may cause visible display defects.

[0067] To solve the above technical problems, the power management circuit includes an electromagnetic shielding layer for reducing the electromagnetic interference generated by the inductor component 1021. The electromagnetic shielding layer is disposed between the inductor component 1021 and the chip body 101. The electromagnetic shielding layer is made of a permalloy material. The electromagnetic shielding layer includes a magnetic conductive layer in the middle and conductive layers on both sides. The magnetic conductive layer is used to guide the magnetic lines of force to prevent them from penetrating into the chip body 101, and the conductive layer is used to shield the electric field interference. The electromagnetic shielding layer adopts a grid-like structure, which can not only ensure sufficient shielding effect but also maintain good heat conduction performance. A thermally conductive insulating material is filled between the electromagnetic shielding layer and the chip body 101 to ensure that heat can be effectively transferred. The edge of the electromagnetic shielding layer extends 2 mm beyond the edge of the chip body 101, and through a multi-point grounding design, the induced current is guided to the ground plane to further reduce the electromagnetic interference. This electromagnetic shielding layer can reduce the electromagnetic radiation intensity and effectively protect the sensitive circuits from interference.

[0068] Furthermore, the inductor component 1021 of the power management circuit provided by the embodiments of the present application adopts a special inductor arrangement structure for reducing electromagnetic radiation. In this inductor component 1021, adjacent unit inductors C adopt opposite winding directions so that the magnetic fields cancel each other out. The unit inductors C in the inductor component 1021 are arranged in a checkerboard pattern. In a 3×3 inductor array, the unit inductors C at positions (1,1), (1,3), (2,2), (3,1) and (3,3) are wound clockwise, while the unit inductors C at positions (1,2), (2,1), (2,3) and (3,2) are wound counterclockwise. When all the unit inductors C work simultaneously, the magnetic field directions generated by adjacent unit inductors C are opposite, and magnetic field cancellation is achieved in the far-field region. The connection path of the unit inductor C adopts a symmetric layout, so that the current path forms a closed loop, reducing the radiation loop area. A magnetic shielding ring is disposed around the inductor component 1021 and is made of a high magnetic permeability material for constraining the leakage magnetic field to prevent it from spreading to the sensitive area. This inductor arrangement structure combined with the magnetic shielding ring can reduce the electromagnetic radiation of the inductor component 1021, effectively solve the electromagnetic interference problem, and ensure that the image quality of the display panel is not affected.

[0069] When using a power management circuit in a high-temperature environment, the on-resistance of a transistor increases with the increase in temperature, and the inductance value and saturation current of an inductor also change. For example, when a display device operates in an outdoor high-temperature environment (above 50°C), the increase in the on-resistance of the transistor leads to an increase in power loss and a decrease in circuit efficiency, further exacerbating the heat dissipation problem. At the same time, the temperature coefficient of the inductance value also causes the originally set inductance value to shift, affecting the output accuracy of the power management circuit.

[0070] To solve the above technical problems, the power management circuit further includes a temperature compensation module. The temperature compensation module is used to adjust the register value according to the real-time temperature to ensure that the power management circuit can obtain the expected inductance value at different temperatures. The temperature compensation module includes a temperature sensor, a non-volatile memory, and a temperature compensation control unit. The temperature sensor is arranged at a predetermined position of the chip body 101 and the inductor component 1021 for real-time temperature monitoring. The temperature sensor is electrically connected to a bandgap reference voltage source. The non-volatile memory stores a temperature-inductance value correspondence table, which contains the actual inductance value change data of each unit inductor C at different temperatures at intervals of 5°C within the temperature range of -20°C to 85°C. The temperature compensation control unit is electrically connected to the temperature sensor and the non-volatile memory, and is used to read the corresponding temperature compensation coefficient from the non-volatile memory according to the temperature data collected by the temperature sensor and adjust the register value accordingly. The temperature compensation control unit reads the temperature data from the temperature sensor every predetermined time (for example, 100 milliseconds) and calculates the offset of the inductance value according to the current temperature. When the temperature rises from 25°C to 60°C, the temperature compensation control unit automatically increases the register value to activate additional unit inductors C to compensate for the decrease in the inductance value caused by the increase in temperature. The temperature compensation control unit is also used to analyze the temperature change trend and adjust the inductor configuration in advance when the temperature changes rapidly to avoid fluctuations in the output of the power management circuit.

[0071] The power management circuit provided by this application realizes the high integration of the power management circuit and significantly improves the heat dissipation effect by arranging the inductor component 1021 on the chip body 101 and electrically connecting it to the chip body 101. Specifically, the inductor component 1021 includes a plurality of unit inductors C and a plurality of transistors. The plurality of unit inductors C are connected into an inductor component 1021 with an adjustable inductance value through the plurality of transistors, so that the inductance value can be flexibly adjusted according to actual needs without replacing external inductor components. When the power management circuit operates under different load conditions, the connection mode of the unit inductors C can be changed by controlling the on or off state of the transistors, thereby adjusting the total inductance value of the inductor component 1021. Therefore, the power management circuit can adapt to various working conditions, improve the power conversion efficiency, and reduce energy loss.

[0072] In addition, a thermal conductive adhesive is provided between the chip body 101 and the inductor component 1021, which improves the heat conduction efficiency. The inductor component 1021 itself has a good thermal conductivity coefficient. By arranging it above the chip body 101, it acts as a heat dissipation device for the chip body 101, increasing the heat dissipation surface area. Heat can be efficiently transferred from the chip body 101 to the inductor component 1021 through the thermal conductive adhesive and then dissipated into the environment. This technical solution solves the problem that traditional power management circuits are prone to overheating in high-power application scenarios, improving the stability and service life of the power management circuit.

[0073] In addition, multiple unit inductors C are arranged in an array form, which not only makes the structure more compact but also enables heat to be more evenly dispersed, avoiding local overheating.

[0074] In addition, the power management circuit further includes a register, which is electrically connected to the control signal line and is used to control the on or off state of the transistor. The register is an adjustable register with 2 to 6 binary control bits, which can adjust the inductance value of the inductor component 1021 to multiple predetermined values within a predetermined range, enabling the power management circuit to automatically optimize the inductance value according to the actual working state, improving the response speed and energy efficiency.

[0075] In summary, the power management circuit provided in this application realizes an organic combination of high integration, good heat dissipation performance, and flexible adjustability, solving the technical problems of traditional power management circuits in terms of large space occupation, poor heat dissipation effect, and weak flexibility.

[0076] The above has introduced the embodiments of this application in detail. The content of this specification should not be construed as a limitation on the protection scope of this application.

Claims

1. A power management circuit, characterized in that, The power management circuit includes: a chip body, the chip body including a DC-DC conversion module, a level conversion module, and a gamma voltage module; and an inductor assembly, the inductor assembly being disposed on the chip body and electrically connected to the chip body.

2. The power management circuit according to claim 1, characterized in that There is a thermal conductive adhesive provided between the chip body and the inductor assembly.

3. The power management circuit according to claim 1, wherein The inductor assembly includes a plurality of unit inductors, a plurality of control signal lines, and a plurality of transistors. The plurality of unit inductors are electrically connected to the plurality of transistors, and the gates of the plurality of transistors are electrically connected to the plurality of control signal lines respectively.

4. The power management circuit according to claim 3, wherein The plurality of unit inductors are arranged in an array form.

5. The power management circuit according to claim 3, wherein, The plurality of unit inductors include a first unit inductor to a Kth unit inductor. Each unit inductor includes a first pad and a second pad arranged opposite to each other. The plurality of transistors include a first transistor to a (2K - 1)th transistor, where K is an integer greater than 1; The plurality of control signal lines include a first control signal line to a (2K - 1)th control signal line; The gate of the (2i - 2)th transistor is electrically connected to the (2i - 2)th control signal line. The first pad of the ith unit inductor is electrically connected to the drain of the (2i - 2)th transistor. The source of the (2i - 2)th transistor is electrically connected to the second pad of the (i - 1)th unit inductor. The gate of the (2i - 1)th transistor is electrically connected to the (2i - 1)th control signal line. The second pad of the ith unit inductor is electrically connected to the source of the (2i - 1)th transistor. The drain of the (2i - 1)th transistor is electrically connected to the output terminal of the inductor assembly, where i is greater than or equal to 2 and less than or equal to K; The first pad of the first unit inductor is electrically connected to the input terminal of the inductor assembly. The second pad of the first unit inductor is electrically connected to the sources of the first transistor and the second transistor. The gate of the first transistor is electrically connected to the first control signal line. The drain of the first transistor is electrically connected to the output terminal of the inductor assembly. The gate of the second transistor is electrically connected to the second control signal line. The drain of the second transistor is electrically connected to the first pad of the second unit inductor.

6. The power management circuit according to claim 5, wherein The power management circuit further includes a register, the register being electrically connected to the first control signal line to the (2K - 1)th control signal line. The register is used to control the first transistor to the (2K - 1)th transistor to adjust the inductance value of the inductor assembly.

7. The power management circuit according to claim 6, characterized in that, The register is an adjustable register having 2 to 6 binary control bits. The register is used to adjust the inductance value of the inductor assembly to a plurality of predetermined values within a predetermined range.

8. The power management circuit according to claim 7, wherein The predetermined range is 1 μH to 16 μH.

9. The power management circuit according to claim 6, wherein The register is used to control the on or off states of the first transistor to the (2K - 1)th transistor by outputting high-level or low-level signals to the first control signal line to the (2K - 1)th control signal line.

10. A display device, characterized in that, including: a display panel; and the power management circuit according to any one of claims 1 to 9, the power management circuit being electrically connected to the display panel.

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